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3075 Commits

Author SHA1 Message Date
Matthias Koefferlein cef96902ad Boundary for circuits, reverted automatic generation of global pins 
- global pins have been generated for device cells too and lead
  to implicit pins which may not be desired. The original problem
  was how to make abstract circuits comparable. This has to be
  solved differently.
- Circuit boundaries are good for displaying the boxes for
  abstract circuits
 2019-07-09 19:55:48 +02:00
Matthias Koefferlein 0c6ead6f90 WIP: introduced boundary into L2N format so we have something to display for abstracts. 2019-07-09 01:18:23 +02:00
Matthias Koefferlein c9e08c4500 WIP: propagate global nets to parent hierarchy even if there is no shape inside the cell. 2019-07-08 23:11:35 +02:00
Matthias Koefferlein bdb8a7bcc2 WIP: reverted modifications on SPICE reader. 2019-07-08 21:51:59 +02:00
Matthias Koefferlein 9625caea65 WIP: added full LVS test. 2019-07-08 21:43:06 +02:00
Matthias Koefferlein b48453633f WIP: some fixes and small enhancements. New tests. 2019-07-08 00:09:10 +02:00
Matthias Koefferlein bc2d9448d6 Providing LVS tests. 2019-07-07 21:33:28 +02:00
Matthias Koefferlein 95a1e38fe3 WIP: better reproducablility for .lvsdb layer names, updated tests. 2019-07-07 19:39:00 +02:00
Matthias Koefferlein 993ef78575 WIP: some cleanup/enhancement 
General topic: abstracts and swappable pins.
Issue: we work bottom up and assign pins. This is the
basis for net graph building. But swappable means those
pins can change. The compare works fine, but debugging
output is strange: as the pin assigned is fixed, the nets
found to be attached to a circuit might not fit any
proposed pin pair (which does not contain swapping).

The problem gets worse with abstracts.

The enhancements are
- Such cases generate only warnings in the browser
  and the message says swapping might be the case
- Floating nets are treated differently. This should
  lead to a better performance for abstracts/black boxes,
  but in case of disconnected pins (due to wire errors),
  floating nets happen to create mismatches in the nets above.
- Net graph building does not consider swappable nets. In
  case of two swappable pins this wouldn't be an issue, but
  for more than two this would create ambiguities and
  prevent topological matching.

Plus: Debug output option for net graph

Tests updated
 2019-07-07 18:17:14 +02:00
Matthias Koefferlein ace0788f85 WIP: Spice reader reads pin names from nets 2019-07-07 00:05:22 +02:00
Matthias Koefferlein 0e5ecdc36b Attempt to make LVS compare output a little more predictable with boundary cases 
- For unattached subcircuit pins no error should be reported
- For abstract nets, graph propagation through subcircuit pins isn't attempted.
  Abstract nets are only dummy-associated currently.
 2019-07-06 23:40:49 +02:00
Matthias Koefferlein 903b1f7505 WIP: fixed 'equivalent_pins' 2019-07-06 21:47:25 +02:00
Matthias Koefferlein 5ce8dd2684 WIP: added circuit blankout. 2019-07-06 19:50:20 +02:00
Matthias Koefferlein fb8a64b0e1 WIP: updated LVS doc. 2019-07-06 09:37:54 +02:00
Matthias Koefferlein 24a0c3dd00 LVS template for macros. Enhancement: 'schematic' statement can now be anywhere in LVS script. 2019-07-06 09:35:51 +02:00
Matthias Koefferlein a179705a03 WIP: more refactoring. 2019-07-06 09:15:33 +02:00
Matthias Koefferlein 0595ec2e0f WIP: one more test for LVS 2019-07-06 09:08:32 +02:00
Matthias Koefferlein 2f6aae7204 WIP: refactoring, added first tests for LVS 2019-07-06 08:52:40 +02:00
Matthias Koefferlein 15022709b4 WIP: doc update, robustness of LVS browser model (xref) 2019-07-05 23:35:14 +02:00
Matthias Koefferlein a6a0d9946c Updated documentation 2019-07-05 21:45:50 +02:00
Matthias Koefferlein fade779238 WIP: doc update. 2019-07-05 17:48:23 +02:00
Matthias Koefferlein 153bfa9c52 Updated doc. 2019-07-04 23:56:04 +02:00
Matthias Koefferlein 68f98d9f0d Some typos fixed, connect_implicit now can be used multiple times (but without glob pattern) 2019-07-04 23:55:46 +02:00
Matthias Koefferlein 71777670de Fixed unit tests. 2019-07-04 01:24:19 +02:00
Matthias Koefferlein 5e70f4fa03 Fixed an edit bug. 2019-07-04 01:18:25 +02:00
Matthias Koefferlein bd5fbc065a WIP: updated doc. 2019-07-04 01:16:08 +02:00
Matthias Koefferlein 07ae488652 WIP: bugfix - don't uppercase file names in SPICE .include, typos fixed. 2019-07-04 00:57:52 +02:00
Matthias Koefferlein 20c8c6bdaa WIP: more LVS doc. 2019-07-04 00:57:04 +02:00
Matthias Koefferlein 437ead7699 WIP: updated doc. 2019-07-03 01:48:55 +02:00
Matthias Koefferlein 0399b07ff3 WIP: Added sample / xs for vertical BJT 2019-07-03 01:25:26 +02:00
Matthias Koefferlein d913d2352c WIP: doc updated, small typos fixed. 2019-07-03 00:45:11 +02:00
Matthias Koefferlein 66a9fa41e7 WIP: added more docs, confine BJT combination to emitter parameters. 2019-07-02 21:09:32 +02:00
Matthias Koefferlein 8aa6f4edcf WIP: added more test data, doc links 2019-07-02 02:03:58 +02:00
Matthias Koefferlein 87ca28a83f WIP: updated LVS doc. 2019-07-02 01:49:56 +02:00
Matthias Koefferlein ae71356052 Added reference circuit 2019-07-02 00:30:50 +02:00
Matthias Koefferlein 5bfed544b7 Added inverter test layout 2019-07-02 00:27:05 +02:00
Matthias Koefferlein 9f26553d4b Added inverter test layout 2019-07-02 00:25:31 +02:00
Matthias Koefferlein 3c4c1b9c4f WIP: bugfixes 
1.) Don't error out in batch mode (without view)
2.) Don't add nets to connectivity when they just
    serve for device recognition
 2019-07-02 00:07:50 +02:00
Matthias Koefferlein f931b6a1c1 Bugfix: avoid an assertion in the netlist browser 
Reason: when a circuit does not have pins and is top level,
but the reference has pins, the reference pins are regarded
to match against (nil). This case has to be reported properly,
otherwise the model can't be built consistently.
 2019-07-02 00:01:11 +02:00
Matthias Koefferlein 1e49338fe9 WIP: doc. 2019-06-30 23:36:51 +02:00
Matthias Koefferlein 2f66f3ee3b WIP: Extraction of DRC and LVS doc, added doc to classes 2019-06-28 18:44:36 +02:00
Matthias Koefferlein ef1441e546 WIP: fixed unit tests. 2019-06-28 17:08:04 +02:00
Matthias Koefferlein 6ed3838baf WIP: fixed an edit failure 2019-06-28 14:43:52 +02:00
Matthias Koefferlein ed41af9b4b WIP: added documentation to LVS script. 2019-06-28 12:50:55 +02:00
Matthias Koefferlein a8f8ca0d7d WIP: fixed a display issue and a segfault in the netlist browser. 2019-06-28 11:45:58 +02:00
Matthias Koefferlein 80d86cc425 WIP: netlist browser - allow switching between L2N and LVSDB view 2019-06-28 11:27:43 +02:00
Matthias Koefferlein 910a36b83d WIP: better matching of subcircuits - attempt to map them even if not identical. This hopefully makes solving subcircuit connection problems easier. 2019-06-28 11:05:43 +02:00
Matthias Koefferlein 3310d34cf3 WIP: better tooltips and comments for LVS browser. 2019-06-27 00:14:18 +02:00
Matthias Koefferlein 955d21a656 WIP: case insensitive compare of netlists (after reading Spice, the names are caseless) 2019-06-26 20:58:42 +02:00
Matthias Koefferlein 0cbfa698f0 WIP: debugging, development 
- LVS DSL debugging, enhancements
- Allow polygons with holes in L2N
- Spice Reader: was creating too many class objects
- Device class categorizer: allow associating A->C,B-C
- ...
 2019-06-26 20:41:49 +02:00