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iverilog/ivtest/vvp_tests
Cary R. 00325f3efb Merge pull request #1348 from jotego/interface-ports
Support SystemVerilog interface-typed module ports
2026-05-16 15:33:56 -07:00
..
2026-04-29 20:59:19 -07:00
2026-02-19 23:46:15 -08:00

This directory contains configurations for thet tests that test the iverilog
compiler with the vvp simulation engine. Eash test file is actually a JSON
file that calls out the test type, names the source file, the gold file, any
command argument flags.

{
    "type"   : "normal",
    "source" : "macro_str_esc.v",
    "gold"   : "macro_str_esc"
}