Commit Graph

450 Commits

Author SHA1 Message Date
Nick Gasson 64e85304b5 VHDL translation for timescale
This patch generates delays with the correct VHDL units. Taking
into account the source module's timescale and precision.
2009-02-23 16:23:56 -08:00
Nick Gasson 5660e67b8b Support IVL_EX_DELAY in VHDL target
This patch adds a translation of 64-bit delay expressions to
vhdl_const_time objects.
2009-02-23 15:30:51 -08:00
Nick Gasson a931eaa586 Fix another case where VHDL input may be driven
This fixes another corner case where the VHDL code generator
would incorrectly generate code that drives an input with an
output.
2009-02-09 13:44:43 -08:00
Nick Gasson 2115e87f78 Fix VHDL naming collisions with modules
This fixes a bug where the renaming rules for modules
would generate entity names that collided with already
existing module names.
2009-02-05 14:40:47 -08:00
Stephen Williams 99a5d4ca9e Update mkinstalldirs to handle paths with spaces.
The newer mkinstalldirs can handle paths that have spaces in them.
While I'm at it, I also updated the Makefiles so that installation
can also work to DESTDIR directories that have spaces.
2009-02-04 08:44:22 -08:00
Nick Gasson f89f3dcbaf More VHDL naming fixes
This handles the cases where:
    * Instance names contain leading/trailing underscores
    * Instance names contain consecutive underscores
    * Module names contain consecutive underscores
    * Module names contain leading/trailing underscores
	* Ports may be inconsistently renamed
2009-02-02 19:41:50 -08:00
Nick Gasson 501106dc92 Support named blocks with local variables in VHDL target
This patch adds code to generate process-local variables
for scopes of type IVL_SCT_BLOCK. This also handles using
the correct assignment operator (:=) for the local VHDL
variables.
2009-02-01 07:08:55 -08:00
Nick Gasson 3dadedf9b5 Fix VHDL bug where constant is assigned to input
This fixes a bug where the VHDL target would not
map ports in cases where the port was driven by
a constant.
2009-01-28 17:45:24 -08:00
Nick Gasson babc9c1352 Various signal naming fixes for VHDL target
This avoids generating invalid VHDL signal names in the
following cases:
	- The name begins or ends with an underscore
	- The name contains two consecutive underscores
	- The name is the same as a component declaration
	- The name differs from another only in case
2009-01-28 17:44:14 -08:00
Nick Gasson 497e095277 Avoid multiple declaration of VHDL temporaries
This fixes a bug where temporary variables could be declared
more than once.

It also takes out a debugging print statement I accidentally
left in the last patch.
2009-01-25 08:03:43 -08:00
Nick Gasson 308688f190 VHDL fix concatenation of std_logics
This fixes an assertion failure when taking a slice of
the result of concatenating several single-element vectors.
2009-01-25 07:59:06 -08:00
Nick Gasson 2107125545 Handle %m in VHDL $display code
Just prints a warning that it's not supported.
2009-01-25 07:55:20 -08:00
Nick Gasson ee5302cf33 Fix some more errors when reading from VHDL outputs
I forgot to modify the LPM generating code with the
last patch. This *should* now always ensure a signal
is readable before code is generated to read from it.
2009-01-25 07:50:03 -08:00
Nick Gasson 69e91e4065 Fix various problems with VHDL `buffer' port generation
This patch corrects several bugs with the generation of
VHDL `buffer' ports. The code generator should now
generate a buffer only if the port needs to be read inside
the architecture, otherwise it will stay `out'.

This also correct a bug where an output port is connected
directly to the output of an instantiated component. Generating
`buffer's would work here, but a more idiomatic VHDL approach is
to declare an intermediate signal which both outputs are connected
to. This is implemented in the patch (fixes the regression of
readout.v in the testsuite).
2009-01-25 07:49:54 -08:00
Nick Gasson e5ce88304e Fix mapping of VHDL expressions to function arguments
Noticed this as part of the test case for pr2516774b. Under some
circumstances the input arguments would be cast to the wrong type.
This patch ensures that all the arguments have the correct type.
2009-01-22 17:39:50 -08:00
Nick Gasson 3cc2018346 Emit VHDL hex constants for some unsigned bits strings
This patch changes the output of VHDL unsigned bit strings
which are 4, 8, 16, 32, or 64 bits to use VHDL hex string
constants.

So the following:
  "00000001"
Becomes
  X"01"

Which is much easier to read
2009-01-22 17:39:41 -08:00
Nick Gasson c787e1acd8 Fix VHDL bug where input may be driven by input
This is a fix for pr2527366 where draw_nexus would sometimes
generate code to drive an input from in an input (where they
should have been left unconnected)
2009-01-22 17:38:38 -08:00
Nick Gasson ba8688c0d1 Fix regression of always3.1.8A with VHDL target
The patch for pr2516774 exposed a bug which caused
always3.1.8A to fail. This patch corrects that.

The test to decide when to use a sensitivity list
rather than an explicit wait statement wasn't tight enough.
2009-01-19 19:54:56 -08:00
Nick Gasson 78bc4b5d47 Fix assignment to VHDL function arguments
This patch is a fix for pr2516774.

The idea is to generate a local variable inside
a function whenever an argument is assigned to. The
variable has an initial value of the argument value
and is used in its place for the remainder of the
function. This patch also handles the case where the
argument is assigned to inside a while loop.
2009-01-19 19:50:48 -08:00
Nick Gasson e6846ea3a7 Improve memory management in VHDL target
Previously the VHDL code generator managed memory for
the AST objects by requiring that each AST element be
responsible for deleting its children. The disadvantages
of this are that it's quite easy to accidentally leak
memory by forgetting to delete a child, and no AST pointers
may be shared by multiple parents (or we'd end up with
double-deletes) -- this results in unnecessary copies of
objects being made.

There's no real need for fine-grained memory management of
AST objects since once they're allocated they tend to
persist until the code generator is about to terminate, when
they should all be freed.

This patch provides a custom new/delete operator for
vhdl_element which logs the vhdl_element objects allocated
in a std::vector (after calling the default operator new).
Once the code generator is finished a single free_all_objects
call deletes all the AST objects in one go. The custom delete
operator is required so that we can still explicitly deallocate
vhdl_element objects before the code generator completes.

There are also some allocation statistics printed at the end
when -pdebug=1 is specified.
2009-01-18 16:42:10 -08:00
Nick Gasson f9448b9dd7 Clean up VHDL debug messages
This won't produce so many useless messages, and the messages
produced should be more relevant.
2009-01-17 09:19:58 -08:00
Nick Gasson f1f9274bb9 Move VHDL global state management to a single file
The new state.cc/hh file now manages all the global
state that we maintain while generating VHDL. This
should make the code a bit tidier.
2009-01-17 09:19:58 -08:00
Nick Gasson 8043629231 Fix some cases where VHDL `buffer' ports were generated incorrectly
This actually removes generation of `buffer' for now.
2009-01-17 09:19:58 -08:00
Nick Gasson ede6acca77 Store only a single VHDL entity for each Verilog module 2009-01-17 09:19:57 -08:00
Nick Gasson 3c2080e502 Start improving performace of VHDL hierarchy generation
This should prune a large amount of the visits to scopes
in the hierarchy. In particular, only one instance of each
scope type should be visited.
2009-01-17 09:19:57 -08:00
Nick Gasson 50f11390b2 Fix VHDL value of undriven net
This ensures an undriven net has the correct value in
the generated VHDL (either '1', '0', or 'Z').

This is a fix for pr2489116.
2009-01-06 20:36:33 -08:00
Nick Gasson 02b58f6ae8 Remove some redundant code from draw_synthesisable_wait
The default draw_wait now produces code for FFs with sync
waits that should synthesise OK.
2009-01-06 20:33:34 -08:00
Nick Gasson 6047eab005 Try to generate VHDL sensitivity lists whereever possible
This patch generates VHDL sensitivity lists for sequential
as well as combinatorial processes which do not contain
a wait statement. Otherwise it falls back on the original
wait-on/until behaviour.

This should make the generated VHDL more acceptable to
synthesisers.
2009-01-06 20:33:21 -08:00
Nick Gasson 19720a0f9d Prefer sensitivity list for VHDL combinatorial processes
This patch generates a sensitivity list for combinatorial
VHDL processes if they don't contain a wait statement, and
a wait-on statement if they do contain another wait statement.

This should help synthesisers correctly identifier
level-sensitive latches.
2009-01-06 20:33:08 -08:00
Nick Gasson a0489e9208 Generate more idiomatic VHDL for some Verilog templates
In particular this improves the code generated for flip-flops
so the output can be synthesised with certain tools (e.g. Synopsis).

See the comments above draw_synthesisable_wait for more details.
2009-01-06 20:32:54 -08:00
Stephen Williams 90a4ddebba Keep source code version information in version files.
Rather then spread VERSION= defines throughout all the makefiles, put
the base version in version_base.in. Use that to generate a version.h
that includes the base version as well as the detailed version.
2009-01-05 21:43:21 -08:00
Stephen Williams ea938b7907 Revert "Enable -Wshadow by default"
This reverts commit 31d67fcd3e.
The concensus has been that this causes too many build problems in
the general case and what is needed instead is a way to turn on the
extra warnings for developers only.
2009-01-01 08:33:26 -08:00
Larry Doolittle 31d67fcd3e Enable -Wshadow by default
The code base is almost shadow-free now, so this won't add much noise to the compiles.
Problems I know about:
 lxt{,2}_write.c:  patch sent upstream
 cflexor.c:  exposes gray area of name space boundary
2008-12-29 16:03:16 -08:00
Larry Doolittle b76c14e452 Shadow reduction part 6
Finish cleaning up shadowed variables, flagged by turning on -Wshadow.
No intended change in functionality.  Patch looks right, and is tested
to compile and run on my machine.  No regressions in the test suite.

This is the end of the simple, coordination-free patches.
The remaining shadows are special cases that will need extra attention.
2008-12-29 16:00:03 -08:00
Cary R a3a3485c85 Make casex/z conditional x/z aware.
Previously only the X/Z state of the label expression was
considered to be a don't care. This patch adds that
functionality to the conditional expression as well.
2008-12-18 16:32:08 -08:00
Cary R 26ee14c7dd Clean up Makefile.in files.
This patch cleans up the Makefile.in files.

We only need to delete config.log in the lower directories.

We reference the *.in files at $(srcdir)/

We need to make distclean for the tgt-(fpga,pal,verilog) directories.
This is to cleanup the Makefile.

Add some missing "rm -r f dep"
2008-12-16 19:42:53 -08:00
Cary R eea7693539 VHDL: Add initial support for non-constant casex/z label expressions.
This patch adds support for concatenation/repetition, signals and
part and bit select of signals for casez/x expression labels.
These along with the original constants can be mixed in almost any
order. Only constant selects are currently supported.
2008-12-16 19:20:04 -08:00
Nick Gasson 4f4191ecdd Add VHDL flag to specify maximum module depth
Specifying -pdepth=N only outputs entities that correspond
to Verilog modules found at depth < N in the hierarchy.

Setting -pdepth=0 (the default) outputs all entities.

This is for feature request 2391457
2008-12-16 09:05:33 -08:00
Stephen Williams 6b45f8899e Flatten the tree of configure scripts.
Collapse all the configure checks to a single configure script in
the root of the source tree. This makes the configure process run
a lot faster, expecially on Windows systems that are slower in general.
2008-12-13 21:42:55 -08:00
Nick Gasson b6c4560fdc Avoid assertion failure in VHDL translate_select
This avoids triggering an assertion failure by trying to
select bits from a std_logic (which isn't a vector type).
2008-12-12 20:52:50 -08:00
Nick Gasson 651d208451 Remove some uneccessary zero-time waits from VHDL outputs
This patch optimises away straight line sequences like:

wait for 0 ns;
wait for X ns;

to:

wait for X ns;

This tidies up the output a bit.

It also has the effect of removing all code from initial
processes where the assignments have been extracted as
VHDL signal intialisers. (c.f. pr2391337)
2008-12-07 16:53:47 -08:00
Nick Gasson 712e08ebe8 Emit useful error message for pr2362211
This prints out an error message rather than crashing out with
an assertion failure when a function assigns to a non-local
variable, which cannot be done in VHDL.
2008-12-07 16:50:07 -08:00
Nick Gasson d689c93879 Rework VHDL assignment statement generation
This changes the assignment statement generator so that
each VHDL declaration "knows" which type of assignment
statement can/should be used on (i.e. signals must be
assigned with <=). This will help us catch cases when
we try to use, for example, := with signals. This occurs
in pr2362211 where we try to assign to a signal within
a function (where only := can be used).
2008-12-07 16:49:57 -08:00
Nick Gasson c06c49c992 Fix assignment of constant to input
If a module's input was connected to a nexus that contained
a constant driver. That constant would be incorrectly generated
as an assignment to the input *inside* the child module (instead
of an assignment inside the instantiating module).
2008-12-07 16:45:05 -08:00
Larry Doolittle 4948875230 Allow building with gcc-4.4
With this small patch, building succeeds with Debian's current gcc-snapshot,
gcc (Debian 20081130-1) 4.4.0 20081130 (experimental) [trunk revision 142292]

That gcc also warns about the remaining #idents in
  vvp/concat.cc
  vvp/dff.h

The resulting build shows some regressions in the test suite, that
I am still investigating.  The patch does not break building, or show
test suite regressions, with gcc-4.3.
2008-12-05 20:48:25 -08:00
Nick Gasson 1cc5586c4d Add debugging output to VHDL target
Prints progress when -pdebug=1 specified.

Adds a new debug_msg function to print progress messages.
2008-11-29 20:16:09 -08:00
Nick Gasson 4263f791f6 Fix part select of width-1 vector
Signals of width 1 are declared in VHDL as std_logic, as this
is the usual way to represent them. Unfortunately, we cannot
distinguish between

reg [0:0] a;

and

reg a;

This patch avoids trying to slice a std_logic so a[0] is equivalent to a.
2008-11-26 13:14:27 -08:00
Cary R 4c28af4c36 Update Makefile.in to have current version by default.
This patch removes the CVS ident information from the Makefile.in
files it also puts in the current version 0.9.devel for the default
VERSION definition. This is normally passed down, but a local make
will use the value from the local Makefile. This will eventually be
replaced with a file based version to give us just one place to
reliably modify the version.
2008-11-25 16:42:32 -08:00
Larry Doolittle fcd39fd0a1 Restore pristine builds
Commit 24827c4b42 broke
pristine builds.  Touch up CPPFLAGS so tgt-vvp/vvp.c
and tgt-vhdl/vhdl.c can find version.h when building
out-of-tree.
2008-11-24 22:07:51 -08:00
Stephen Williams 27f4ba2e38 Remove the unused CVS ident support in the configure scripts. 2008-11-19 21:07:34 -08:00