Explicit imports should always conflict with local declarations using
the same name. Wildcard imports only conflict if they are referenced
before a local declaration with the same name.
This also unifies the detection of identifier conflicts.
As reported on iverilog-devel on 2018-10-12, a dimension size of zero
could case the compiler to go into an infinite loop. Further tests
showed that unsized or queue dimensions entered as packed dimensions
would cause the compiler to crash.
- make primitive redefinition a warning, not an error
- make edge-sensitive ifnone a warning, not an error
This allows Icarus to be used to simulate designs using third-party
cell libraries that contain such things.
In traditional Verilog, each task_port_item must have an explicit port
direction.
In SystemVerilog, if the port direction is not specified, it should be
inherited from the preceding task_port_item for that task/function, and
only the first task_port_item should infer the direction to be 'input'.
This implements and enforces the full set of rules for determining
timescales in SystemVerilog. The previous relaxation of the rules
that allowed timescales to be redefined within the compilation unit
scope has been removed. Time unit and precision redeclarations are
now recognised after a nested module declaration.
(* my_fancy_attribute *)
foobar1 foobar (clk(clk), rst(rst) ...);
- Modifies PGModule to hold the attribute map (can be verified with pform_dump)
- pform_make_modgate(s) bind the attributes from the parser to the above map
- The attributes from PGModule are inserted into the NetScope of that module
PGModule::elaborate_scope_mod_instances_
- Currently these attributes automatically make it into netlist
- These attributes are accessible via ivl_scope_attr_cnt and ivl_scope_attr_val
from ivl_target.h
Replace explicit comparisons against generation_flag with calls to
the gn_system_verilog helper function, both for code clarity and
to fix a couple of bugs. Also simplify the implementation of the
function, as we already rely on the generation_flag enumeration
being an ordered list.
This just enables the compiler to parse path declarations that
contain part selects. As for bit selects, the part select is
discarded, and if elaboration of specify blocks is enabled,
the path declaration will be applied to the entire vector. If
elaboration is enabled, a warning message will now be output
when a bit or part select is discarded.
If a static variable declared in a task, function, or block has an
initialisation expression, SystemVerilog requires the declaration to
have an explicit static lifetime. This is supposed to be a compile
error, but for now just output a warning.
Implementing this required adding support in the parser for explicit
lifetimes in variable declarations. For now, just output an error if
the user asks for a lifetime that isn't the default for that scope.
This is syntax permitted in 1364-2001 but removed in 1364-2005.
Also update the iverilog man page to document the anachronisms warning
class that warns about use of this feature when a later generation is
selected.
The compiler was emitting a "sorry" message and aborting compilation when
it encountered attributes on a wire declaration/assignment. Change this
to a warning, as most attributes are ignored anyway.
Get rid of the data_type, signed_flag, and range arguments to the
pform_module_define_port because they add no value within the
parse.y parser. Cleaning these out will hopefully ease the addition
of new functionality.
This can be handled entirely in the parser, where we rewrite the
syntax to me a begin/end block that contains the index variable
declaration and the for loop.
The verinum arithmetic operators now observe the standard Verilog
rules for calculating the result width if all operands are sized.
If any operand is unsized, the result is lossless, as before.
They also now all observe the standard rules for handling partially
undefined operands (if any operand bit is 'x', the entire result is
'x').
I've also added the unary '-' operator, and renamed v_not() to be
the unary '~' operator. This has allowed some simplification in
other parts of the compiler.
This implementation works by detecting assignments
to constant properties in elaboration. Allow initializer
assignments to assign to the constant, error all other
assignments, and otherwise treat the constant like any
other property.
Class constructors are the "new" method in a class description.
Elaborate the constructor as an ordinary method, but the only
way to access this method is to implicitly call it. The elaborator
will take the constructor call and generate a naked "new" expression
and implicit constructor method call with the object itself as the
return value.
Rework lexical support for PACKAGE_IDENTIFIER so that the lexor
can help with package scoped identifiers.
Pform package types and package functions up to elaboration.
This patch adds support for bool/bit vector types on the LHS of
a parameter declaration and ensures implicit casts in parameter
declarations are performed where necessary.
A package can have parameters, but it does not have specparams or
keep the order the parameters are defined. This patch skips these
items if the scope is not a Module.
This was temporarily implemented to just copy definitions to the
local scope, but the better method is to create a PEIdent that has
the package attached to it.
The parser does not distinguish between module and UDP instances, so
a UDP delay is handled by the rules used for parsing module parameter
overrides. Although these rules had been relaxed to accept the case of
a simple decimal value (e.g. #10), they did not allow a simple real
value (e.g. #0.1).
Implement through the ivl core to the ivl_target.h API.
Also draft implementation of creating and storing arrays
in the vvp runtime and code generator.
In vvp, create the .var/str variable for representing strings, and
handle strings in the $display system task.
Add to vvp threads the concept of a stack of strings. This is going to
be how complex objects are to me handled in the future: forth-like
operation stacks. Also add the first two instructions to minimally get
strings to work.
In the parser, handle the variable declaration and make it available
to the ivl_target.h code generator. The vvp code generator can use this
information to generate the code for new vvp support.
The parser had been changed to support null statements in sequential
and parallel blocks (a feature introduced in SystemVerilog), but was
not supported in elaboration, leading to a compiler crash. This patch
fixes this by discarding the null statements during parsing.
Making the scope type NESTED_MODULE was just plain wrong, because
it didn't really encapsulate the meaning of program blocks OR
nested modules. So instead create nested_module() and program_block()
flags and use those to test scope constraints.
An important advantage of program blocks is its ability to nest
within a module. This winds up also allowing modules to nest, which
is legal but presumably less used feature.
This patch extends the compiler to support all specparam declarations
allowed by the 1364-2005 standard. For compatibility with other
simulators, it allows specparam values to be used in any constant
expression, but outputs a warning message and disables run-time
annotation of a specparam if it is used in an expression that must
be evaluated at compile time.
This is a cleanup in preparation for better support of range lists.
(cherry picked from commit 8f7cf3255acad55841f8b3725e3786ef49daad68)
Conflicts:
PTask.h
elab_scope.cc
elab_sig.cc
parse.y
pform.cc
pform.h
pform_types.h
Signed-off-by: Stephen Williams <steve@icarus.com>
The SystemVerilog unbased literals (e.g. '0, '1, etc.) are expected to be
used standalone and cannot take a size. This patch modifies the parsing
code to give a good error message when this is done.
Class methods belong in a class scope, not the containing module.
So create a lexical scope that carries tasks and functions and
create a PClass to represent classes.
Tasks call arguments may be dropped in favor of default values.
Allow for that in the syntax. This requires a little handling
of the non-SystemVerilog case during elaboration.
Class names can be declared early, before definitions, so that the
name can be used as a type name. This thus allows class definitions
to be separate from the declaration. This creates some complexity in
the parser, since the lexor knows about the class names.
This adds the vector_type_t and real_type_t types to handle
vector and real types in tf_port items. This cleans up a lot
of the parsing for these items.
During parse/pform processing, convert increment statements to
the equivalent compressed assignment statement. This is less weird
for elaboration processing and better expresses what is going on.
This gets me to the point where the parser stashes a defined type,
and the lexical analyzer uses the type names to differentiate
IDENTIFIER and TYPE_IDENTIFIER.
Parse typedefs with structs and enums, but give a sorry message,
because they are not yet supported. Rearrange some of the parse
rules for variables in order to increase comonality with the
typedef rules.
Martin Whitaker
Maciej Kurc
Stefan Biereigel
Cary R
Vamsi Vytla
Stephen Williams
Henry Wong
Maciej Suminski
Martin Whitaker
Larry Doolittle
Todd Strader (todd.strader@gmail.com)
Arun Persaud