fe72d02cf6
Major rework of the ternary operator elaboration code.
...
This patch reworks much of the ternary code to short circuit when
possible and supports real values better. It adds a blend operator
for real values that returns 0.0 when the values differ and the value
when they match. This deviates slightly from the standard which
specifies that the value for reals is always 0.0 when the conditional
is 'bx. There are also a couple bug fixes.
These fixes have not been ported to continuous assignments yet.
Ternary operators used at compile time and in procedural assignments
should be complete (short circuit and support real values).
2008-03-08 19:45:13 -08:00
692caca9dc
Connect module instance arrays MSB to MSB.
...
When a bit port of a module instance is connected to a vector
argument, the MSB module instance should be connected to the MSB
of the vector argument. This matters only in the rare case that
the %m is used. It also makes wave dumps come out right.
2008-03-06 20:37:08 -08:00
8d3febff2b
Keep processes in proper lexical scope
...
Normally processes are found in the lexical scope of a module, but
there are special cases where processes (other then task/function
definitions) are in other lexical scopes. The most likely case is
initilizations that are in the lexical scope where the assigned
variable is declared.
In the process, the behaviors list is kept in the base PScope class
instead of the Module or any other derived lexical scope class.
2008-03-03 20:49:52 -08:00
52ac96ca15
elaborate_sig for generated case items
...
Handle elaborate_sig for scopes that are within a case-generated
scheme.
2008-02-27 20:54:47 -08:00
11a33a0907
Merge branch 'pscope'
2008-02-24 19:45:21 -08:00
8e704cbf93
Rework handling of lexical scope
...
Move the storage of wires (signals) out of the Module class into
the PScope base class, and instead of putting the PWires all into
the Module object, distribute them into the various lexical scopes
(derived from PScope) so that the wire names do not need to carry
scope information.
This required some rewiring of elaboration of signals, and rewriting
of lexical scope handling.
2008-02-24 19:40:54 -08:00
b0e4a6884a
Objects of lexical scope use PScope base class.
...
All the pform objects that represent lexical scope now are derived
from the PScope class, and are kept in a lexical_scope table so that
the scope can be managed.
2008-02-15 21:20:24 -08:00
2b5560957a
Force the L-value and R-value to match for real values.
...
Check that if either the L-value or the R-value are real then both
must be real. This prevents a runtime crash.
2008-02-13 20:44:16 -08:00
bc1d3eb7cd
Add support for generate case
...
Generate case is a complex generate scheme where the items are
sub-schemes of the case generate itself. The parser handles them
something like nested generate statements, but storing the case
guards as the test expression. Then the elaborator notes the
case scheme and reaches into the case item schemes inside to make
up tests, select the generate item, and elaborate.
2008-02-09 22:19:42 -08:00
f1f2806e3c
Get delays of signed extended continuous assignments right.
...
Padding and continuous assignment caused problems if the continuous
assignment includes a delay. The problem is that the padding was
not necessarily included in the delay. Rework the elaboration to
make sure the padding is indeed included in the delay.
2008-02-01 20:13:23 -08:00
d9ac146b8f
Spelling fixes
...
only comments and documentation
some punctuation and capitalization for good measure
Changelogs are purposefully untouched
2008-01-29 20:24:24 -08:00
47d65034db
Spelling fixes
...
mostly comments, but includes some identifiers and message text
2008-01-27 18:18:13 -08:00
731f1df70b
Hook up input port part select properly.
...
The input part select that is used to match a module port to a short
vector connected to it was wired incorrectly.
2008-01-10 20:47:06 -08:00
9d0cdc8ae9
Hook up output port part select properly.
...
The output part select that is used to match a module port to a long
vector connected to it was wired incorrectly.
2008-01-10 18:20:21 -08:00
f8d410e2d4
remove lint flagged by gcc-4.3
...
watch for possible behavior changes in
elaborate.cc:3409
vvp/vvp_net.cc:600
2008-01-07 18:39:10 -08:00
8ea3b6b0b8
header includes for gcc-4.3 compatibility
...
minimal changes required to build without error
tested with gcc-4.3 (Debian 4.3-20071130-1) 4.3.0 20071130 (experimental)
2008-01-04 16:14:44 -08:00
58d3d2f265
Better track signals marked local.
2007-12-27 16:47:01 -07:00
1db19b8703
Make statement file lineno available to targets.
...
Make the Verilog file/lineno of statements available to loadable
code generators. Make sure the information is properly set for
system task calls.
2007-12-22 09:31:24 -05:00
7975e14b5c
LineInfo uses perm_string for path.
...
Rework the handling of file names to use a perm_string heap to hold
the file names, instead of the custom file name heap in the lexor.
Also rename the get_line to get_fileline to reflect its real duties.
This latter chage touched a lot of files.
2007-12-20 12:31:01 -05:00
dd56dd1635
Correct naming of unnamed generate blocks.
...
This patch causes unnamed generate blocks to be automatically named
using the naming scheme defined in the Verilog-2005 standard. This
is a fix for the problem discussed in pr1821610.
2007-11-18 21:01:35 -08:00
05a6e69d2d
Support nested generate schemes.
...
This patch adds support for nested loops and if-else decisions in generate
statements.
2007-11-07 21:27:00 -08:00
e26b9e72a2
More array fixes and down indexed part selects can be a lval.
...
Here are some more array fixes. They are mostly better error messages
instead of just asserting and some code cleanup. The one new thing
that probably should have been a separate submission is that down
indexed part select [base -: width] can now be a lvalue.
2007-11-07 20:53:27 -08:00
2ea6692833
Make patch for pr1792108 synth aware.
...
This patch makes the behavior selection fro pr1792108 depend on the
synth* functors.
2007-11-07 20:00:51 -08:00
221c99c5f4
Only remove output nets for synthesis backends.
...
During elaboration only remove output nets for synthesis backends.
2007-11-07 20:00:33 -08:00
dbce0cb05a
Fix @* to correctly handle non-input nets.
...
@* was only expanding to input nets. nex_input() for blocks was removing
any output net that was also an input. There was also a bug in how output
nets were removed. Only outputs currently defined were removed from the
input list.
always @(*) begin
y = a;
z = y;
end
would report "a" as an input. While
always @(*) begin
z = y;
y = a;
end
would report both "a" and "y" as inputs.
To fix this all nex_inputs now take a flag that when true (the default)
correctly removes any output from the input list. Both the above cases
will now return "a". If the flag is false outputs which are also inputs
will be included in the input list. This is what the @* elaboration code
uses to get the correct sensitivity list.
2007-11-07 20:00:05 -08:00
9c99b002ba
Resize vectors to mismatched ports
...
It is legal in Verilog to bind expressions to ports that do not
match the port width. Icarus Verilog needs to create the necessary
part selects to get the connections right.
Signed-off-by: Stephen Williams <steve@icarus.com>
2007-09-09 21:14:52 -07:00
d43cda3def
Add port checks for primitives.
...
This patch adds functionality to verify that primitives are given
an appropriate number of ports. For multiple output gates (but,
not, pulldown, pullup) it also reports that Icarus currently does
not support multiple outputs when more than one is given.
2007-09-06 18:50:02 -07:00
7c852aa075
Add cmos/rcmos primitives.
...
This patch adds the cmos and rcmos primitives.
2007-09-06 18:46:22 -07:00
7bf4b64c0a
Check that logic gates are not given null ports.
...
Logic gates do not handle null ports so check for this and
issue an error message when it happens.
2007-09-04 16:13:46 -07:00
4f6b47b345
Check that functions do not call invalid statements.
...
This patch adds checks to verify that functions do not invoke
statements that are invalid for them (#, @, wait, enable/call
tasks and non blocking assignment). For reference see section
10.3.4 of 1364-2001.
2007-08-30 20:41:45 -07:00
845e74c30e
Evaluate parameter expressions losslessly
...
Make sure parameter expressions are evaluated losslessly, as if
the l-value is unsigned and thus virtually infinite.
2007-06-27 22:05:36 -07:00
396ffd1cdd
Add support for conditional generate. In the process, fix bugs
...
related to generate used multiple times by multiple scopes causing
spurious generation results.
Signed-off-by: Stephen Williams <steve@icarus.com>
2007-06-21 19:04:48 -07:00
b631268f56
Error resiliency (ldoolitt)
2007-06-05 21:35:51 +00:00
129a064e1a
Handle bit/part select of array words in nets.
2007-06-04 02:19:07 +00:00
c7d97f4146
Properly evaluate scope path expressions.
2007-06-02 03:42:12 +00:00
ddd36ecb6c
Rework the heirarchical identifier parse syntax and pform
...
to handle more general combinations of heirarch and bit selects.
2007-05-24 04:07:11 +00:00
36471e9f96
Properly ignore unsupported ifnone.
2007-04-16 01:10:07 +00:00
79fdb2b243
Attach line number information to task calls.
2007-04-15 20:45:40 +00:00
f621448ced
Parse edge sensitive paths without edge specifier.
2007-04-13 02:34:35 +00:00
af913e7eb1
Allow implicit wires in assign l-value.
2007-04-05 03:09:50 +00:00
bd1b00ca29
Improve port mismatch error message.
2007-04-01 23:01:10 +00:00
611d2c81b3
Spelling fixes from Larry
2007-03-22 16:08:14 +00:00
d9efe3312e
Limit the calculated widths of constants.
2007-03-08 05:30:02 +00:00
e6fa72c318
Handle processes within generate loops.
2007-03-05 05:59:10 +00:00
606751dbfd
Check that path source/destination are ports.
2007-03-03 05:56:55 +00:00
fc9a90c9e0
Add support for edge sensitive spec paths.
2007-03-02 06:13:22 +00:00
243cf94165
Add support for conditional specify delay paths.
2007-03-01 06:19:38 +00:00
c1c2381261
Parse all specify paths to pform.
2007-02-12 01:52:21 +00:00
a623502ece
More generous handling of errors in blocks.
2007-02-01 05:52:24 +00:00
f77d803aeb
Clean up elaboration of for-loop increment expression.
2007-01-21 04:26:36 +00:00
ca9da51a79
Precalculate constant power expressions, and constant function arguments.
2007-01-19 05:42:40 +00:00
91d84e7dc7
Major rework of array handling. Memories are replaced with the
...
more general concept of arrays. The NetMemory and NetEMemory
classes are removed from the ivl core program, and the IVL_LPM_RAM
lpm type is removed from the ivl_target API.
2007-01-16 05:44:14 +00:00
2c7d2effd1
Fix an uninitialized variable warning.
2006-12-09 01:59:35 +00:00
2eeea7003e
@* without inputs is an error.
2006-12-08 04:09:41 +00:00
48029ed8e5
Fix crash handling constant true conditional.
2006-11-27 02:01:07 +00:00
94f07d16e3
Fix compile time eval of condition expresion to do reduction OR of vectors.
2006-11-26 07:10:30 +00:00
041091cfac
Fix nexus widths for direct link assign and ternary nets.
2006-11-26 06:29:16 +00:00
c339dc4bbc
Remove last bits of relax_width methods, and use test_width
...
to calculate the width of an r-value expression that may
contain unsized numbers.
2006-11-04 06:19:24 +00:00
2302693201
Expression widths with unsized literals are pseudo-infinite width.
2006-10-30 05:44:49 +00:00
4af28e2b77
no-specify turns of specparam elaboration.
2006-10-03 15:33:49 +00:00
69cd007a71
Support real valued specify delays, properly scaled.
2006-10-03 05:06:00 +00:00
d6be82f748
Support selective control of specify and xtypes features.
2006-09-28 04:35:18 +00:00
b658a3b41f
Missing PSpec.cc file.
2006-09-26 19:48:40 +00:00
0edb5a7547
Basic support for specify timing.
2006-09-23 04:57:19 +00:00
0e2c6544b9
Proper error message when logic array pi count is bad.
2006-09-22 22:14:27 +00:00
fc0695beb6
Handle 64bit delay constants.
2006-08-08 05:11:37 +00:00
71faebd6df
Make elaborate_expr methods aware of the width that the context
...
requires of it. In the process, fix sizing of the width of unary
minus is context determined sizes.
2006-06-02 04:48:49 +00:00
a8b86ea3bb
More explicit datatype setup.
2006-05-01 20:47:58 +00:00
0c9fb766b6
Get the data type of part select results right.
2006-04-30 05:17:48 +00:00
4493e3f928
Chop down assign r-values that elaborate too wide.
2006-04-26 04:43:50 +00:00
f001d0001a
Add support for generate loops w/ wires and gates.
2006-04-10 00:37:42 +00:00
e8efa6df53
Fix instance arrays indexed by overridden parameters.
2006-03-30 01:49:07 +00:00
368c27c9e4
Handle complex net node delays.
2006-01-03 05:22:14 +00:00
58f182a159
Node delays can be more general expressions in structural contexts.
2006-01-02 05:33:19 +00:00
0e044d6684
More precise about r-value width of constants.
2005-11-26 00:35:42 +00:00
c02b3b8ac6
Reorganize signal part select handling, and add support for
...
indexed part selects.
Expand expression constant propagation to eliminate extra
sums in certain cases.
2005-11-10 13:28:11 +00:00
16dc3ab4d4
Error message for invalid for-loop index variable.
2005-09-27 04:51:37 +00:00
9fd16575d9
Support bool expressions and compares handle them optimally.
2005-09-14 02:53:13 +00:00
4a8be3db9c
Implement bi-directional part selects.
2005-08-06 17:58:16 +00:00
bc9f286954
More debug information.
2005-07-15 00:41:09 +00:00
b9799cf6ec
Remove NetVariable and ivl_variable_t structures.
2005-07-11 16:56:50 +00:00
657ac8168e
Debug messages.
2005-06-17 05:06:47 +00:00
739a1839ed
Do sign extension of structuran nets.
2005-05-24 01:44:27 +00:00
7796c8bcfb
Parameters cannot have their width changed.
2005-05-17 20:56:55 +00:00
adbe734b6c
Some debug messages.
2005-05-13 05:12:39 +00:00
365cfedd55
Update DFF support to new data flow.
2005-04-24 23:44:01 +00:00
4ccbb4f0b2
Get rval width right for arguments into task calls.
2005-03-05 05:38:33 +00:00
257e1f9516
Support shifts and divide.
2005-02-19 02:43:38 +00:00
55b5bf9d39
distinguish between single port namy instances, and single instances many sub-ports.
2005-02-10 04:56:58 +00:00
ee5bb5fcaf
Add the NetRepeat node, and code generator support.
2005-02-08 00:12:36 +00:00
c23a35a033
Debug messages for PGAssign elaboration.
2005-01-30 01:42:05 +00:00
25de448d34
Remove obsolete NetSubnet class.
2005-01-22 18:16:00 +00:00
4d139b58aa
Properly pad vector widths in pgassign.
2005-01-12 03:17:36 +00:00
9e94afe399
Use PartSelect/PV and VP to handle part selects through ports.
2005-01-09 20:16:00 +00:00
8f2d679c8a
Unify elaboration of l-values for all proceedural assignments,
...
including assing, cassign and force.
Generate NetConcat devices for gate outputs that feed into a
vector results. Use this to hande gate arrays. Also let gate
arrays handle vectors of gates when the outputs allow for it.
2004-12-29 23:55:43 +00:00
3947d7dd33
Force r-value padded to width.
2004-12-15 17:09:11 +00:00
d19e76a193
Fix r-value width of continuous assign.
2004-12-12 18:13:39 +00:00
65e9b6be12
Rework of internals to carry vectors through nexus instead
...
of single bits. Make the ivl, tgt-vvp and vvp initial changes
down this path.
2004-12-11 02:31:25 +00:00
e4ae832153
Clean up spurious trailing white space.
2004-10-04 01:10:51 +00:00
c10e572091
Support degenerat wait statements.
2004-09-05 21:07:26 +00:00
9de786fc44
Add support for module instance arrays.
2004-09-05 17:44:41 +00:00
8bf434754f
Propagate source line number in synthetic delay statements.
2004-06-30 15:32:02 +00:00
76c0fe459c
Only pad the width of vector r-values.
2004-06-20 15:59:06 +00:00
9949040285
Add support for the default_nettype directive.
2004-06-13 04:56:53 +00:00
5472b27e1f
Rewire/generalize parsing an elaboration of
...
function return values to allow for better
speed and more type support.
2004-05-31 23:34:36 +00:00
55ba131997
Handle wait with constant-false expression.
2004-05-25 03:42:58 +00:00
c6453a0854
primitive ports can bind bi name.
2004-03-08 00:47:44 +00:00
413932e406
Verilog2001 new style port declartions for primitives.
2004-03-08 00:10:29 +00:00
9531920685
MOre thorough use of elab_and_eval function.
2004-03-07 20:04:10 +00:00
177b6ffb6a
Addtrbute keys are perm_strings.
2004-02-20 18:53:33 +00:00
27af95d402
Use perm_strings for named langiage items.
2004-02-18 17:11:54 +00:00
6a02613fca
Get rid of useless warning.
2004-01-21 04:35:03 +00:00
e617e4a98c
Handle wide expressions in wait condition.
2004-01-13 03:42:49 +00:00
ee172bdccf
Attach line number information to for loop parts.
2003-10-26 04:49:51 +00:00
39b2928ad8
Summary list of missing modules.
2003-09-25 00:25:14 +00:00
6abe797963
Evaluate nb-assign r-values using elab_and_eval.
2003-09-20 06:08:53 +00:00
94a71fdee8
Evaluate gate array index constants using elab_and_eval.
2003-09-20 06:00:37 +00:00
1f0c274e82
Obsolete find_symbol and find_event from the Design class.
2003-09-20 01:05:35 +00:00
178847fc53
Spelling fixes.
2003-09-13 01:01:51 +00:00
cee34f8a8a
Support time0 resolution of combinational threads.
2003-09-04 20:28:05 +00:00
7c1401a2ba
Spelling patch.
2003-08-28 04:11:17 +00:00
c96598a429
Primitive outputs have same limitations as continuous assignment.
2003-08-05 03:01:58 +00:00
004ecd08dd
Elide empty begin-end in conditionals.
2003-07-02 04:19:16 +00:00
61195c5daa
Harmless fixup of warnings.
2003-06-21 01:21:42 +00:00
b43c543455
Handle assign of real to vector.
2003-06-13 19:10:20 +00:00
17e93b7cbe
Implement the wait statement behaviorally instead of as nets.
2003-05-19 02:50:58 +00:00
d958fd2c36
Fix truncation of signed constant in constant addition.
2003-05-04 20:04:08 +00:00
5b726e09af
Include port name in port assignment error message.
2003-04-24 05:25:55 +00:00
d18934d444
Sign extend NetMult inputs if result is signed.
2003-03-29 05:51:25 +00:00
4e182ebf67
Some better internal error messages.
2003-03-26 06:16:38 +00:00
badad63ab4
All NetObj objects have lex_string base names.
2003-03-06 00:28:41 +00:00
4c67de5ca7
Add the lex_strings string handler, and put
...
scope names and system task/function names
into this table. Also, permallocate event
names from the beginning.
2003-03-01 06:25:30 +00:00
cd572a74ce
Add the portbind warning.
2003-02-22 04:12:49 +00:00
e571dd90d8
Calculate delay statement delays using elaborated
...
expressions instead of pre-elaborated expression
trees.
Remove the eval_pexpr methods from PExpr.
2003-02-08 19:49:21 +00:00
55af069fe8
Rewrite delay statement elaboration of handle real expressions.
2003-02-07 02:49:24 +00:00
e941e7e805
Spelling fixes.
2003-01-30 16:23:07 +00:00
8f0c02c0fa
Spelling fixes.
2003-01-27 05:09:17 +00:00
46253ed873
Rework expression parsing and elaboration to
...
accommodate real/realtime values and expressions.
2003-01-26 21:15:58 +00:00
f56d763411
Move strstream to ostringstream for compatibility.
2003-01-14 21:16:18 +00:00
dedae73761
Account for local units in calculated delays.
2002-12-21 19:42:17 +00:00
b89e138404
precalculate r-values of nb assignments and task arguments.
2002-12-05 04:15:14 +00:00
807a758f7c
Do not set width if width is already OK.
2002-11-26 03:35:13 +00:00
cfd8cbf850
Port expressions for output ports are lnets, not nets.
2002-11-09 19:20:48 +00:00
3fca25181a
Evaluate nonblocking assign r-values.
2002-08-28 18:54:36 +00:00
c0046e845e
Handle special case of empty system task argument list.
2002-08-15 02:11:54 +00:00
d4eaede435
Do not elide named blocks.
2002-08-13 05:35:00 +00:00
52bf4e613f
conditional ident string using autoconfig.
2002-08-12 01:34:58 +00:00
37331d1c1b
Add port name to pin size error message.
2002-07-31 23:55:38 +00:00
843e1f9c44
Save event matching for nodangle.
2002-07-24 16:22:59 +00:00
15becdaee4
Need driver for sure in assign feedback and other cases.
2002-07-18 02:06:37 +00:00
Cary R
Stephen Williams
Larry Doolittle
Martin Whitaker
steve