bd5cc96956
Correct vector sizes for bit select
2008-07-08 00:20:31 +01:00
4777966b4c
Bit select bug fixes
2008-07-07 21:19:59 +01:00
6b73cc39a5
Add Active_High support func and fix LPM part select
2008-07-07 16:17:54 +01:00
b0de1a8d7e
Implement part select for LHS of assignment
2008-07-07 16:11:45 +01:00
c33600bcc3
Add concatenation operator
2008-07-06 18:21:34 +01:00
1410c339de
Make sure any calls to numeric_std Resize have correct type
...
The signed/unsigned-ness of an expression needs to be
preserved over any call to Resize. Also add a sanity
check to make sure non-vector types are not resized.
2008-07-04 11:36:11 +01:00
88816e150a
Properly parenthesise unary operators
2008-07-04 11:17:24 +01:00
c54b36c902
Add logical AND operator
2008-07-04 11:10:20 +01:00
19cbab78b2
Tidy up code to generate default branch of case
2008-07-03 20:04:47 +01:00
050aa277ae
Make vhdl_element::emit a little more generic
2008-07-01 10:37:22 +01:00
500442e5c5
Working function calls
2008-06-25 22:15:57 +01:00
d997397c38
Generate function calls with parameters
2008-06-25 21:49:22 +01:00
7773000c36
Generate function declarations
2008-06-25 21:40:35 +01:00
43c671cb5c
Emit VHDL for function declarations
2008-06-25 18:00:48 +01:00
a3df37b851
Initial code to generate function calls
...
Also catch a few null-pointer issues
2008-06-25 17:29:09 +01:00
12b448ef01
Merge branch 'vhdl' of git@github.com:nickg/iverilog into vhdl
...
Conflicts:
tgt-vhdl/vhdl_syntax.cc
2008-06-24 19:42:35 +01:00
e77bb0157e
Remove redundant methods from vhdl_arch
2008-06-24 19:39:05 +01:00
75631bd8f1
Move is_inital code out of vhdl_process into vhdl_scope
...
Part of tidy up before implementing functions
2008-06-24 19:06:06 +01:00
63b1887ff2
Refactor code to use the new vhdl_scope class
2008-06-24 18:52:25 +01:00
ba36e47575
Add new vhdl_scope class and refactor
2008-06-24 18:12:00 +01:00
3866c4526e
Simplify code to emit operators
2008-06-24 14:58:58 +01:00
cb08f02de1
Resize signed/unsigned bit vectors correctly
2008-06-24 10:58:21 +01:00
4188fbecee
Add XOR operator and catch default case branch
2008-06-24 10:55:45 +01:00
88dc9b6b63
Remove debugging information from the output
2008-06-23 15:02:26 +01:00
632a265e14
Fix casting/resizing order bug
2008-06-23 15:00:55 +01:00
449cd0a76e
Correctly generate signed/unsigned types
2008-06-23 14:28:27 +01:00
e5ef0d97bd
Fix signed/unsigned resizing
2008-06-23 13:04:28 +01:00
d06f5c7c54
Emit loop statements with the correct indent
2008-06-23 12:27:30 +01:00
9911939576
Simplify casting code
2008-06-23 12:21:10 +01:00
c9ace14c40
Shift operators working correctly
2008-06-23 12:14:12 +01:00
75f7c9ae0c
Only move constant assignments into initialisation
2008-06-21 16:40:18 +01:00
5cfe7ea0aa
Tidy up output
2008-06-21 16:28:07 +01:00
c70fb4ba08
Simple implementation of IVL_EX_SELECT
2008-06-21 16:17:44 +01:00
7cba9f3cb2
Shift left/right
2008-06-21 15:19:33 +01:00
d6acb8d059
Less than / greater than
2008-06-21 15:16:22 +01:00
ec23b70bb7
While loops
2008-06-21 15:13:44 +01:00
0caf4fd9d0
Add case statement
2008-06-21 15:03:36 +01:00
d7bb5658f2
Translate IVL_ST_DELAYX statements
2008-06-19 12:16:19 +01:00
254ccb9ccb
First passing at blocking assignment
2008-06-18 13:06:27 +01:00
d2bebee9d9
Refactor before adding blocking assignment
2008-06-18 12:51:11 +01:00
af8c08e6a7
Allow optional VHPI $finish implementation
2008-06-17 20:16:16 +01:00
ae0b09dd3a
Don't bother emitting else part if it's empty
2008-06-16 19:53:42 +01:00
8d0afa632d
Subtraction and multiplication LPM devices
2008-06-16 19:49:24 +01:00
ce72eb4eb4
Fix Valgrind warnings
2008-06-16 14:26:38 +01:00
7cde5f247e
Add translation for not-equals operator
2008-06-16 12:47:41 +01:00
2fb57805ea
Use signed rather than std_logic_vector
...
Arithmetic operators now working correctly
2008-06-14 18:03:25 +01:00
919c1d695c
Adding binary +
2008-06-14 17:09:31 +01:00
9fbb449e06
Optimise away empty (VHDL) processes
2008-06-13 14:17:24 +01:00
be3c4cf268
Generate signal initial values from `initial' processes
2008-06-13 14:10:28 +01:00
b8c1f9ab67
A system for linking ivl_signal_t to entities
2008-06-12 20:26:23 +01:00
0df3eabe26
Convert `if (foo) ..' to `if foo = '1' then ..'
2008-06-12 11:36:21 +01:00
8fe2211e2b
Generate `after' modifier instead of `wait' statements
2008-06-12 11:24:43 +01:00
d6f1162547
Generate correct VHDL signal values
2008-06-12 10:50:46 +01:00
46991aa65c
Generate process bodies in the right place
2008-06-12 10:47:52 +01:00
a7cfdc3a87
Add VHDL if statement to AST types
2008-06-11 14:11:37 +01:00
b010b8e3ca
Use `assert false' as initial translation of $finish
2008-06-11 13:37:21 +01:00
5a7cfd8c02
Clean up vhdl_comp_inst
2008-06-10 14:00:15 +01:00
babe694366
Generate port mappings
2008-06-10 13:58:41 +01:00
f6753a9013
Add ports to component declarations
2008-06-10 11:24:16 +01:00
1fb01d4d98
Emit port declarations
2008-06-09 16:37:05 +01:00
3106fe0ed6
Generate port declarations for entities.
...
But doesn't emit them yet!
2008-06-09 16:27:04 +01:00
e29954e03f
Generate concurrent assignments from logic gates
2008-06-09 15:05:32 +01:00
3b5d56e087
Allow n-ary expressions
2008-06-09 14:53:50 +01:00
aa91186119
Add AST elements for unary/binary expressions to model logic gates
2008-06-09 14:39:58 +01:00
d08f5af9c6
Add concurrent assignments
2008-06-09 14:21:55 +01:00
b96e471fa2
Stub code for handling logic gates
2008-06-09 14:08:27 +01:00
7120ab7b13
Expression type might be null in some cases
2008-06-09 12:54:21 +01:00
120b5dc80e
Add constant integers
2008-06-09 12:46:55 +01:00
d762253f74
Wait statements
2008-06-09 12:40:59 +01:00
1d28b935e8
Split vhdl_element.cc into multiple files
2008-06-08 13:27:48 +01:00
Nick Gasson