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iverilog/pform.cc

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Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
/*
Support dynamic array initialisation in variable declarations.
2019-09-16 21:35:27 +02:00
* Copyright (c) 1998-2019 Stephen Williams (steve@icarus.com)
Update some copyright notices.
2013-04-09 03:35:37 +02:00
* Copyright CERN 2013 / Stephen Williams (steve@icarus.com)
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
updated FSF-address
2012-08-29 03:41:23 +02:00
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
*/
Create a config.h.in file to hold all the config junk, and support gcc 3.0. (Stephan Boettcher)
2001-07-25 05:10:48 +02:00
# include "config.h"
Add parse and elaboration of non-blocking assignments, Replace list<PCase::Item*> with an svector version, Add integer support.
1999-06-06 22:45:38 +02:00
# include "compiler.h"
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
# include "pform.h"
# include "parse_misc.h"
Add automatic module libraries.
2001-10-21 01:02:39 +02:00
# include "parse_api.h"
Get the scope of class methods right Class methods belong in a class scope, not the containing module. So create a lexical scope that carries tasks and functions and create a PClass to represent classes.
2012-03-11 21:18:24 +01:00
# include "PClass.h"
Named events as far as the pform.
2000-04-01 21:31:57 +02:00
# include "PEvent.h"
Parse (with sorry message) package declarations.
2012-10-21 20:42:19 +02:00
# include "PPackage.h"
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
# include "PUdp.h"
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
# include "PGenerate.h"
Added parser support for SV modport declarations.
2015-01-10 12:09:42 +01:00
# include "PModport.h"
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
# include "PSpec.h"
Parse disciplines and contribution statements Parse discipline declarations, net discipline declarations, and analog contribution statements. Don't yet do anything useful with these, just give a sorry message where they are encountered.
2008-05-11 21:00:11 +02:00
# include "discipline.h"
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
# include <list>
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
# include <map>
Remove malloc.h support and for C++ files use <c...> include files. The functions (malloc, free, etc.) that used to be provided in malloc.h are now provided in cstdlib for C++ files and stdlib.h for C files. Since we require a C99 compliant compiler it makes sense that malloc.h is no longer needed. This patch also modifies all the C++ files to use the <c...> version of the standard C header files (e.g. <cstdlib> vs <stdlib.h>). Some of the files used the C++ version and others did not. There are still a few other header changes that could be done, but this takes care of much of it.
2010-05-31 22:12:06 +02:00
# include <cassert>
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
# include <stack>
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
# include <typeinfo>
Move strstream to ostringstream for compatibility.
2003-01-14 22:16:18 +01:00
# include <sstream>
header includes for gcc-4.3 compatibility minimal changes required to build without error tested with gcc-4.3 (Debian 4.3-20071130-1) 4.3.0 20071130 (experimental)
2008-01-05 00:23:47 +01:00
# include <cstring>
# include <cstdlib>
Improved error checking for defparam values supplied on the command line. Fixes GitHub issue #139 plus various assertion failures when invalid values are specified.
2017-01-29 21:13:01 +01:00
# include <cctype>
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
Data type handling of module ports. Fix data type handling of module ports. When ports are declared as ports and given data types in different statements, the parser incorrectly (and silently) dropped the intended data type for the default LOGIC type.
2008-01-04 05:13:56 +01:00
# include "ivl_assert.h"
Make ivl_alloc.h the last include so it doesn't effect any system includes. In ivl_alloc.h we redefine malloc(), realloc() and calloc() to have standard error checking. We don't want to do this for anything that comes from the standard headers. This specifically doesn't work if a C++ header files does std::malloc, etc. Also change to -W instead of -Wextra since that is more portable. I plan to add a check from -Wextra and use it when available since it is more descriptive.
2010-10-24 00:52:56 +02:00
# include "ivl_alloc.h"
Data type handling of module ports. Fix data type handling of module ports. When ports are declared as ports and given data types in different statements, the parser incorrectly (and silently) dropped the intended data type for the default LOGIC type.
2008-01-04 05:13:56 +01:00
Add support for synthesis translate meta-comments.
2014-07-16 03:03:40 +02:00
/*
* The "// synthesis translate_on/off" meta-comments cause this flag
* to be turned off or on. The pform_make_behavior and similar
* functions look at this flag and may choose to add implicit ivl
* synthesis flags.
*/
static bool pform_mc_translate_flag = true;
void pform_mc_translate_on(bool flag) { pform_mc_translate_flag = flag; }
Allow modules (and program blocks in particular) to nest. An important advantage of program blocks is its ability to nest within a module. This winds up also allowing modules to nest, which is legal but presumably less used feature.
2012-05-10 04:35:11 +02:00
/*
* The pform_modules is a map of the modules that have been defined in
* the top level. This should not contain nested modules/programs.
Handle typedefs in $root scope.
2013-12-15 05:07:31 +01:00
* pform_primitives is similar, but for UDP primitives.
Allow modules (and program blocks in particular) to nest. An important advantage of program blocks is its ability to nest within a module. This winds up also allowing modules to nest, which is legal but presumably less used feature.
2012-05-10 04:35:11 +02:00
*/
Use perm_strings for named langiage items.
2004-02-18 18:11:54 +01:00
map<perm_string,Module*> pform_modules;
map<perm_string,PUdp*> pform_primitives;
Add automatic module libraries.
2001-10-21 01:02:39 +02:00
Handle typedefs in $root scope.
2013-12-15 05:07:31 +01:00
/*
Support separate compilation units in SystemVerilog. The compilation unit scope is now treated as a specialised form of package (with an automatically generated name). All items declared outside a design element are added to the current compilation unit package. Apart from when searching for a symbol, once we get into elaboration we can treat these just like any other package.
2017-10-21 16:04:25 +02:00
* The pform_units is a list of the SystemVerilog compilation unit scopes.
* The current compilation unit is the last element in the list. All items
* declared or defined at the top level (outside any design element) are
* added to the current compilation unit scope.
Handle typedefs in $root scope.
2013-12-15 05:07:31 +01:00
*/
Support separate compilation units in SystemVerilog. The compilation unit scope is now treated as a specialised form of package (with an automatically generated name). All items declared outside a design element are added to the current compilation unit package. Apart from when searching for a symbol, once we get into elaboration we can treat these just like any other package.
2017-10-21 16:04:25 +02:00
vector<PPackage*> pform_units;
Add function to define parameter from command line This patch is based on one from "bruce <bruce1914@gmail.com>". I've applied all but the elaboration code, which I rewrote to properly work with the elaboration work queue. I also constrained the implementation so that the parameter name must have exactly two components: the root scope name and the parameter name. This is necessary to keep the defparm processing sane. The comments from bruce's original patch are as follows: -- This patch would provide function to define parameter from command line. This serves the same functionality as 'defparam' in Verilog source code, but provide much more ease for using. Parameter definition can be write in command file, with following syntax: +parameter+<scope>.<parameter>=<val> *Do not apply any space between them* The scope name should be full hierachical name with root name at the begining. The following example would override test.T1 with new value 2'b01: +parameter+test.T1=2'b01 'test' here is the root module name. The parameter value here should be constant. Parameter definition can also be write in the command line: iverilog -Ptest.T1=2'b01 This serves the same functionality with the previous example. If we define the same parameter in command file and command line, the one in command line would over-write all others.
2009-08-06 23:42:13 +02:00
Support separate compilation units in SystemVerilog. The compilation unit scope is now treated as a specialised form of package (with an automatically generated name). All items declared outside a design element are added to the current compilation unit package. Apart from when searching for a symbol, once we get into elaboration we can treat these just like any other package.
2017-10-21 16:04:25 +02:00
static bool is_compilation_unit(LexicalScope*scope)
{
// A compilation unit is the only scope that doesn't have a parent.
Rework handling of timescales in parser. This implements and enforces the full set of rules for determining timescales in SystemVerilog. The previous relaxation of the rules that allowed timescales to be redefined within the compilation unit scope has been removed. Time unit and precision redeclarations are now recognised after a nested module declaration.
2017-11-05 18:50:05 +01:00
assert(scope);
Support separate compilation units in SystemVerilog. The compilation unit scope is now treated as a specialised form of package (with an automatically generated name). All items declared outside a design element are added to the current compilation unit package. Apart from when searching for a symbol, once we get into elaboration we can treat these just like any other package.
2017-10-21 16:04:25 +02:00
return scope->parent_scope() == 0;
}
Elaborate root tasks/functions.
2014-10-01 01:06:32 +02:00
Rework port input and inout to use data_type_or_implicit rule for types.
2012-04-13 05:20:37 +02:00
std::string vlltype::get_fileline() const
{
ostringstream buf;
buf << (text? text : "") << ":" << first_line;
string res = buf.str();
return res;
}
Improved error checking for defparam values supplied on the command line. Fixes GitHub issue #139 plus various assertion failures when invalid values are specified.
2017-01-29 21:13:01 +01:00
static bool is_hex_digit_str(const char *str)
{
while (*str) {
if (!isxdigit(*str)) return false;
str++;
}
return true;
}
static bool is_dec_digit_str(const char *str)
{
while (*str) {
if (!isdigit(*str)) return false;
str++;
}
return true;
}
static bool is_oct_digit_str(const char *str)
{
while (*str) {
if (*str < '0' || *str > '7') return false;
str++;
}
return true;
}
static bool is_bin_digit_str(const char *str)
{
while (*str) {
if (*str != '0' && *str != '1') return false;
str++;
}
return true;
}
Add function to define parameter from command line This patch is based on one from "bruce <bruce1914@gmail.com>". I've applied all but the elaboration code, which I rewrote to properly work with the elaboration work queue. I also constrained the implementation so that the parameter name must have exactly two components: the root scope name and the parameter name. This is necessary to keep the defparm processing sane. The comments from bruce's original patch are as follows: -- This patch would provide function to define parameter from command line. This serves the same functionality as 'defparam' in Verilog source code, but provide much more ease for using. Parameter definition can be write in command file, with following syntax: +parameter+<scope>.<parameter>=<val> *Do not apply any space between them* The scope name should be full hierachical name with root name at the begining. The following example would override test.T1 with new value 2'b01: +parameter+test.T1=2'b01 'test' here is the root module name. The parameter value here should be constant. Parameter definition can also be write in the command line: iverilog -Ptest.T1=2'b01 This serves the same functionality with the previous example. If we define the same parameter in command file and command line, the one in command line would over-write all others.
2009-08-06 23:42:13 +02:00
/*
* Parse configuration file with format <key>=<value>, where key
* is the hierarchical name of a valid parameter name, and value
* is the value user wants to assign to. The value should be constant.
*/
void parm_to_defparam_list(const string&param)
{
Fix memory leak and gcc4.4 compilation. There was a small memory leak in parm_to_defparam_list where space for "key" and "value" was being allocated via strdup and never freed. This was fixed by freeing them at each return point. In that function, key and value were defined to be const char* but were later mutated. gcc4.4 is more strict with const-ness in some functions than previous versions (see http://gcc.gnu.org/gcc-4.4/porting_to.html section "Strict null-terminated sequence utilities"), so this caused compilation to fail. Fixed by removing the const modifier in the declaration of those two variables and related nkey variable. This also necessitated malloc'ing room for value in one path through the code, which made memory management easier as well.
2009-08-22 04:28:19 +02:00
char* key;
char* value;
Add function to define parameter from command line This patch is based on one from "bruce <bruce1914@gmail.com>". I've applied all but the elaboration code, which I rewrote to properly work with the elaboration work queue. I also constrained the implementation so that the parameter name must have exactly two components: the root scope name and the parameter name. This is necessary to keep the defparm processing sane. The comments from bruce's original patch are as follows: -- This patch would provide function to define parameter from command line. This serves the same functionality as 'defparam' in Verilog source code, but provide much more ease for using. Parameter definition can be write in command file, with following syntax: +parameter+<scope>.<parameter>=<val> *Do not apply any space between them* The scope name should be full hierachical name with root name at the begining. The following example would override test.T1 with new value 2'b01: +parameter+test.T1=2'b01 'test' here is the root module name. The parameter value here should be constant. Parameter definition can also be write in the command line: iverilog -Ptest.T1=2'b01 This serves the same functionality with the previous example. If we define the same parameter in command file and command line, the one in command line would over-write all others.
2009-08-06 23:42:13 +02:00
unsigned off = param.find('=');
if (off > param.size()) {
key = strdup(param.c_str());
Fix memory leak and gcc4.4 compilation. There was a small memory leak in parm_to_defparam_list where space for "key" and "value" was being allocated via strdup and never freed. This was fixed by freeing them at each return point. In that function, key and value were defined to be const char* but were later mutated. gcc4.4 is more strict with const-ness in some functions than previous versions (see http://gcc.gnu.org/gcc-4.4/porting_to.html section "Strict null-terminated sequence utilities"), so this caused compilation to fail. Fixed by removing the const modifier in the declaration of those two variables and related nkey variable. This also necessitated malloc'ing room for value in one path through the code, which made memory management easier as well.
2009-08-22 04:28:19 +02:00
value = (char*)malloc(1);
*value = '\0';
Add function to define parameter from command line This patch is based on one from "bruce <bruce1914@gmail.com>". I've applied all but the elaboration code, which I rewrote to properly work with the elaboration work queue. I also constrained the implementation so that the parameter name must have exactly two components: the root scope name and the parameter name. This is necessary to keep the defparm processing sane. The comments from bruce's original patch are as follows: -- This patch would provide function to define parameter from command line. This serves the same functionality as 'defparam' in Verilog source code, but provide much more ease for using. Parameter definition can be write in command file, with following syntax: +parameter+<scope>.<parameter>=<val> *Do not apply any space between them* The scope name should be full hierachical name with root name at the begining. The following example would override test.T1 with new value 2'b01: +parameter+test.T1=2'b01 'test' here is the root module name. The parameter value here should be constant. Parameter definition can also be write in the command line: iverilog -Ptest.T1=2'b01 This serves the same functionality with the previous example. If we define the same parameter in command file and command line, the one in command line would over-write all others.
2009-08-06 23:42:13 +02:00
} else {
key = strdup(param.substr(0, off).c_str());
Fix memory leak and gcc4.4 compilation. There was a small memory leak in parm_to_defparam_list where space for "key" and "value" was being allocated via strdup and never freed. This was fixed by freeing them at each return point. In that function, key and value were defined to be const char* but were later mutated. gcc4.4 is more strict with const-ness in some functions than previous versions (see http://gcc.gnu.org/gcc-4.4/porting_to.html section "Strict null-terminated sequence utilities"), so this caused compilation to fail. Fixed by removing the const modifier in the declaration of those two variables and related nkey variable. This also necessitated malloc'ing room for value in one path through the code, which made memory management easier as well.
2009-08-22 04:28:19 +02:00
value = strdup(param.substr(off+1).c_str());
Add function to define parameter from command line This patch is based on one from "bruce <bruce1914@gmail.com>". I've applied all but the elaboration code, which I rewrote to properly work with the elaboration work queue. I also constrained the implementation so that the parameter name must have exactly two components: the root scope name and the parameter name. This is necessary to keep the defparm processing sane. The comments from bruce's original patch are as follows: -- This patch would provide function to define parameter from command line. This serves the same functionality as 'defparam' in Verilog source code, but provide much more ease for using. Parameter definition can be write in command file, with following syntax: +parameter+<scope>.<parameter>=<val> *Do not apply any space between them* The scope name should be full hierachical name with root name at the begining. The following example would override test.T1 with new value 2'b01: +parameter+test.T1=2'b01 'test' here is the root module name. The parameter value here should be constant. Parameter definition can also be write in the command line: iverilog -Ptest.T1=2'b01 This serves the same functionality with the previous example. If we define the same parameter in command file and command line, the one in command line would over-write all others.
2009-08-06 23:42:13 +02:00
}
Revert bad merge from vhdl branch
2010-10-02 20:02:27 +02:00
Add function to define parameter from command line This patch is based on one from "bruce <bruce1914@gmail.com>". I've applied all but the elaboration code, which I rewrote to properly work with the elaboration work queue. I also constrained the implementation so that the parameter name must have exactly two components: the root scope name and the parameter name. This is necessary to keep the defparm processing sane. The comments from bruce's original patch are as follows: -- This patch would provide function to define parameter from command line. This serves the same functionality as 'defparam' in Verilog source code, but provide much more ease for using. Parameter definition can be write in command file, with following syntax: +parameter+<scope>.<parameter>=<val> *Do not apply any space between them* The scope name should be full hierachical name with root name at the begining. The following example would override test.T1 with new value 2'b01: +parameter+test.T1=2'b01 'test' here is the root module name. The parameter value here should be constant. Parameter definition can also be write in the command line: iverilog -Ptest.T1=2'b01 This serves the same functionality with the previous example. If we define the same parameter in command file and command line, the one in command line would over-write all others.
2009-08-06 23:42:13 +02:00
// Resolve hierarchical name for defparam. Remember
// to deal with bit select for generate scopes. Bit
Revert bad merge from vhdl branch
2010-10-02 20:02:27 +02:00
// select expression should be constant integer.
Add function to define parameter from command line This patch is based on one from "bruce <bruce1914@gmail.com>". I've applied all but the elaboration code, which I rewrote to properly work with the elaboration work queue. I also constrained the implementation so that the parameter name must have exactly two components: the root scope name and the parameter name. This is necessary to keep the defparm processing sane. The comments from bruce's original patch are as follows: -- This patch would provide function to define parameter from command line. This serves the same functionality as 'defparam' in Verilog source code, but provide much more ease for using. Parameter definition can be write in command file, with following syntax: +parameter+<scope>.<parameter>=<val> *Do not apply any space between them* The scope name should be full hierachical name with root name at the begining. The following example would override test.T1 with new value 2'b01: +parameter+test.T1=2'b01 'test' here is the root module name. The parameter value here should be constant. Parameter definition can also be write in the command line: iverilog -Ptest.T1=2'b01 This serves the same functionality with the previous example. If we define the same parameter in command file and command line, the one in command line would over-write all others.
2009-08-06 23:42:13 +02:00
pform_name_t name;
Fix memory leak and gcc4.4 compilation. There was a small memory leak in parm_to_defparam_list where space for "key" and "value" was being allocated via strdup and never freed. This was fixed by freeing them at each return point. In that function, key and value were defined to be const char* but were later mutated. gcc4.4 is more strict with const-ness in some functions than previous versions (see http://gcc.gnu.org/gcc-4.4/porting_to.html section "Strict null-terminated sequence utilities"), so this caused compilation to fail. Fixed by removing the const modifier in the declaration of those two variables and related nkey variable. This also necessitated malloc'ing room for value in one path through the code, which made memory management easier as well.
2009-08-22 04:28:19 +02:00
char *nkey = key;
Add function to define parameter from command line This patch is based on one from "bruce <bruce1914@gmail.com>". I've applied all but the elaboration code, which I rewrote to properly work with the elaboration work queue. I also constrained the implementation so that the parameter name must have exactly two components: the root scope name and the parameter name. This is necessary to keep the defparm processing sane. The comments from bruce's original patch are as follows: -- This patch would provide function to define parameter from command line. This serves the same functionality as 'defparam' in Verilog source code, but provide much more ease for using. Parameter definition can be write in command file, with following syntax: +parameter+<scope>.<parameter>=<val> *Do not apply any space between them* The scope name should be full hierachical name with root name at the begining. The following example would override test.T1 with new value 2'b01: +parameter+test.T1=2'b01 'test' here is the root module name. The parameter value here should be constant. Parameter definition can also be write in the command line: iverilog -Ptest.T1=2'b01 This serves the same functionality with the previous example. If we define the same parameter in command file and command line, the one in command line would over-write all others.
2009-08-06 23:42:13 +02:00
char *ptr = strchr(key, '.');
while (ptr != 0) {
*ptr++ = '\0';
// Find if bit select is applied, this would be something
// like - scope[2].param = 10
char *bit_l = strchr(nkey, '[');
if (bit_l !=0) {
*bit_l++ = '\0';
char *bit_r = strchr(bit_l, ']');
if (bit_r == 0) {
cerr << "<command line>: error: missing ']' for defparam: " << nkey << endl;
Fix memory leak and gcc4.4 compilation. There was a small memory leak in parm_to_defparam_list where space for "key" and "value" was being allocated via strdup and never freed. This was fixed by freeing them at each return point. In that function, key and value were defined to be const char* but were later mutated. gcc4.4 is more strict with const-ness in some functions than previous versions (see http://gcc.gnu.org/gcc-4.4/porting_to.html section "Strict null-terminated sequence utilities"), so this caused compilation to fail. Fixed by removing the const modifier in the declaration of those two variables and related nkey variable. This also necessitated malloc'ing room for value in one path through the code, which made memory management easier as well.
2009-08-22 04:28:19 +02:00
free(key);
free(value);
Add function to define parameter from command line This patch is based on one from "bruce <bruce1914@gmail.com>". I've applied all but the elaboration code, which I rewrote to properly work with the elaboration work queue. I also constrained the implementation so that the parameter name must have exactly two components: the root scope name and the parameter name. This is necessary to keep the defparm processing sane. The comments from bruce's original patch are as follows: -- This patch would provide function to define parameter from command line. This serves the same functionality as 'defparam' in Verilog source code, but provide much more ease for using. Parameter definition can be write in command file, with following syntax: +parameter+<scope>.<parameter>=<val> *Do not apply any space between them* The scope name should be full hierachical name with root name at the begining. The following example would override test.T1 with new value 2'b01: +parameter+test.T1=2'b01 'test' here is the root module name. The parameter value here should be constant. Parameter definition can also be write in the command line: iverilog -Ptest.T1=2'b01 This serves the same functionality with the previous example. If we define the same parameter in command file and command line, the one in command line would over-write all others.
2009-08-06 23:42:13 +02:00
return;
}
*bit_r = '\0';
int i = 0;
while (*(bit_l+i) != '\0')
if (!isdigit(*(bit_l+i++))) {
cerr << "<command line>: error: scope index expression is not constant: " << nkey << endl;
Fix memory leak and gcc4.4 compilation. There was a small memory leak in parm_to_defparam_list where space for "key" and "value" was being allocated via strdup and never freed. This was fixed by freeing them at each return point. In that function, key and value were defined to be const char* but were later mutated. gcc4.4 is more strict with const-ness in some functions than previous versions (see http://gcc.gnu.org/gcc-4.4/porting_to.html section "Strict null-terminated sequence utilities"), so this caused compilation to fail. Fixed by removing the const modifier in the declaration of those two variables and related nkey variable. This also necessitated malloc'ing room for value in one path through the code, which made memory management easier as well.
2009-08-22 04:28:19 +02:00
free(key);
free(value);
Add function to define parameter from command line This patch is based on one from "bruce <bruce1914@gmail.com>". I've applied all but the elaboration code, which I rewrote to properly work with the elaboration work queue. I also constrained the implementation so that the parameter name must have exactly two components: the root scope name and the parameter name. This is necessary to keep the defparm processing sane. The comments from bruce's original patch are as follows: -- This patch would provide function to define parameter from command line. This serves the same functionality as 'defparam' in Verilog source code, but provide much more ease for using. Parameter definition can be write in command file, with following syntax: +parameter+<scope>.<parameter>=<val> *Do not apply any space between them* The scope name should be full hierachical name with root name at the begining. The following example would override test.T1 with new value 2'b01: +parameter+test.T1=2'b01 'test' here is the root module name. The parameter value here should be constant. Parameter definition can also be write in the command line: iverilog -Ptest.T1=2'b01 This serves the same functionality with the previous example. If we define the same parameter in command file and command line, the one in command line would over-write all others.
2009-08-06 23:42:13 +02:00
return;
}
name_component_t tmp(lex_strings.make(nkey));
index_component_t index;
index.sel = index_component_t::SEL_BIT;
verinum *seln = new verinum(atoi(bit_l));
PENumber *sel = new PENumber(seln);
index.msb = sel;
index.lsb = sel;
tmp.index.push_back(index);
name.push_back(tmp);
}
else // no bit select
name.push_back(name_component_t(lex_strings.make(nkey)));
nkey = ptr;
ptr = strchr(nkey, '.');
}
name.push_back(name_component_t(lex_strings.make(nkey)));
Improved error checking for defparam values supplied on the command line. Fixes GitHub issue #139 plus various assertion failures when invalid values are specified.
2017-01-29 21:13:01 +01:00
free(key);
Revert bad merge from vhdl branch
2010-10-02 20:02:27 +02:00
Add function to define parameter from command line This patch is based on one from "bruce <bruce1914@gmail.com>". I've applied all but the elaboration code, which I rewrote to properly work with the elaboration work queue. I also constrained the implementation so that the parameter name must have exactly two components: the root scope name and the parameter name. This is necessary to keep the defparm processing sane. The comments from bruce's original patch are as follows: -- This patch would provide function to define parameter from command line. This serves the same functionality as 'defparam' in Verilog source code, but provide much more ease for using. Parameter definition can be write in command file, with following syntax: +parameter+<scope>.<parameter>=<val> *Do not apply any space between them* The scope name should be full hierachical name with root name at the begining. The following example would override test.T1 with new value 2'b01: +parameter+test.T1=2'b01 'test' here is the root module name. The parameter value here should be constant. Parameter definition can also be write in the command line: iverilog -Ptest.T1=2'b01 This serves the same functionality with the previous example. If we define the same parameter in command file and command line, the one in command line would over-write all others.
2009-08-06 23:42:13 +02:00
// Resolve value to PExpr class. Should support all kind of constant
// format including based number, dec number, real number and string.
Revert bad merge from vhdl branch
2010-10-02 20:02:27 +02:00
Improved error checking for defparam values supplied on the command line. Fixes GitHub issue #139 plus various assertion failures when invalid values are specified.
2017-01-29 21:13:01 +01:00
// Is it a string?
if (*value == '"') {
char *buf = strdup (value);
char *buf_ptr = buf+1;
// Parse until another '"' or '\0'
while (*buf_ptr != '"' && *buf_ptr != '\0') {
buf_ptr++;
// Check for escape, especially '\"', which does not mean the
// end of string.
if (*buf_ptr == '\\' && *(buf_ptr+1) != '\0')
buf_ptr += 2;
}
if (*buf_ptr == '\0') // String end without '"'
cerr << "<command line>: error: missing close quote of string for defparam: " << name << endl;
else if (*(buf_ptr+1) != 0) { // '"' appears within string with no escape
cerr << buf_ptr << endl;
cerr << "<command line>: error: \'\"\' appears within string value for defparam: " << name
<< ". Ignore characters after \'\"\'" << endl;
}
*buf_ptr = '\0';
buf_ptr = buf+1;
// Remember to use 'new' to allocate string for PEString
// because 'delete' is used by its destructor.
char *nchar = strcpy(new char [strlen(buf_ptr)+1], buf_ptr);
PExpr* ndec = new PEString(nchar);
Add function to define parameter from command line This patch is based on one from "bruce <bruce1914@gmail.com>". I've applied all but the elaboration code, which I rewrote to properly work with the elaboration work queue. I also constrained the implementation so that the parameter name must have exactly two components: the root scope name and the parameter name. This is necessary to keep the defparm processing sane. The comments from bruce's original patch are as follows: -- This patch would provide function to define parameter from command line. This serves the same functionality as 'defparam' in Verilog source code, but provide much more ease for using. Parameter definition can be write in command file, with following syntax: +parameter+<scope>.<parameter>=<val> *Do not apply any space between them* The scope name should be full hierachical name with root name at the begining. The following example would override test.T1 with new value 2'b01: +parameter+test.T1=2'b01 'test' here is the root module name. The parameter value here should be constant. Parameter definition can also be write in the command line: iverilog -Ptest.T1=2'b01 This serves the same functionality with the previous example. If we define the same parameter in command file and command line, the one in command line would over-write all others.
2009-08-06 23:42:13 +02:00
Module::user_defparms.push_back( make_pair(name, ndec) );
Improved error checking for defparam values supplied on the command line. Fixes GitHub issue #139 plus various assertion failures when invalid values are specified.
2017-01-29 21:13:01 +01:00
free(buf);
free(value);
return;
Add function to define parameter from command line This patch is based on one from "bruce <bruce1914@gmail.com>". I've applied all but the elaboration code, which I rewrote to properly work with the elaboration work queue. I also constrained the implementation so that the parameter name must have exactly two components: the root scope name and the parameter name. This is necessary to keep the defparm processing sane. The comments from bruce's original patch are as follows: -- This patch would provide function to define parameter from command line. This serves the same functionality as 'defparam' in Verilog source code, but provide much more ease for using. Parameter definition can be write in command file, with following syntax: +parameter+<scope>.<parameter>=<val> *Do not apply any space between them* The scope name should be full hierachical name with root name at the begining. The following example would override test.T1 with new value 2'b01: +parameter+test.T1=2'b01 'test' here is the root module name. The parameter value here should be constant. Parameter definition can also be write in the command line: iverilog -Ptest.T1=2'b01 This serves the same functionality with the previous example. If we define the same parameter in command file and command line, the one in command line would over-write all others.
2009-08-06 23:42:13 +02:00
}
Revert bad merge from vhdl branch
2010-10-02 20:02:27 +02:00
Improved error checking for defparam values supplied on the command line. Fixes GitHub issue #139 plus various assertion failures when invalid values are specified.
2017-01-29 21:13:01 +01:00
// Is it a based number?
char *num = strchr(value, '\'');
if (num != 0) {
verinum *val;
const char *base = num + 1;
if (*base == 's' || *base == 'S')
base++;
switch (*base) {
case 'h':
case 'H':
if (is_hex_digit_str(base+1)) {
val = make_unsized_hex(num);
} else {
cerr << "<command line>: error: invalid digit in hex value specified for defparam: " << name << endl;
free(value);
return;
}
break;
case 'd':
case 'D':
if (is_dec_digit_str(base+1)) {
val = make_unsized_dec(num);
} else {
cerr << "<command line>: error: invalid digit in decimal value specified for defparam: " << name << endl;
free(value);
return;
}
break;
case 'o':
case 'O':
if (is_oct_digit_str(base+1)) {
val = make_unsized_octal(num);
} else {
cerr << "<command line>: error: invalid digit in octal value specified for defparam: " << name << endl;
free(value);
return;
}
break;
case 'b':
case 'B':
if (is_bin_digit_str(base+1)) {
val = make_unsized_binary(num);
} else {
cerr << "<command line>: error: invalid digit in binary value specified for defparam: " << name << endl;
free(value);
return;
}
break;
default:
cerr << "<command line>: error: invalid numeric base specified for defparam: " << name << endl;
free(value);
return;
}
if (num != value) { // based number with size
*num = 0;
if (is_dec_digit_str(value)) {
verinum *siz = make_unsized_dec(value);
val = pform_verinum_with_size(siz, val, "<command line>", 0);
} else {
cerr << "<command line>: error: invalid size for value specified for defparam: " << name << endl;
free(value);
return;
}
}
PExpr* ndec = new PENumber(val);
Module::user_defparms.push_back( make_pair(name, ndec) );
free(value);
return;
}
Revert bad merge from vhdl branch
2010-10-02 20:02:27 +02:00
Improved error checking for defparam values supplied on the command line. Fixes GitHub issue #139 plus various assertion failures when invalid values are specified.
2017-01-29 21:13:01 +01:00
// Is it a decimal number?
num = (value[0] == '-') ? value + 1 : value;
if (is_dec_digit_str(num)) {
verinum *val = make_unsized_dec(num);
if (value[0] == '-') *val = -(*val);
PExpr* ndec = new PENumber(val);
Module::user_defparms.push_back( make_pair(name, ndec) );
free(value);
return;
}
Revert bad merge from vhdl branch
2010-10-02 20:02:27 +02:00
Improved error checking for defparam values supplied on the command line. Fixes GitHub issue #139 plus various assertion failures when invalid values are specified.
2017-01-29 21:13:01 +01:00
// Is it a real number?
char *end = 0;
double rval = strtod(value, &end);
if (end != value && *end == 0) {
verireal *val = new verireal(rval);
PExpr* nreal = new PEFNumber(val);
Module::user_defparms.push_back( make_pair(name, nreal) );
free(value);
return;
Add function to define parameter from command line This patch is based on one from "bruce <bruce1914@gmail.com>". I've applied all but the elaboration code, which I rewrote to properly work with the elaboration work queue. I also constrained the implementation so that the parameter name must have exactly two components: the root scope name and the parameter name. This is necessary to keep the defparm processing sane. The comments from bruce's original patch are as follows: -- This patch would provide function to define parameter from command line. This serves the same functionality as 'defparam' in Verilog source code, but provide much more ease for using. Parameter definition can be write in command file, with following syntax: +parameter+<scope>.<parameter>=<val> *Do not apply any space between them* The scope name should be full hierachical name with root name at the begining. The following example would override test.T1 with new value 2'b01: +parameter+test.T1=2'b01 'test' here is the root module name. The parameter value here should be constant. Parameter definition can also be write in the command line: iverilog -Ptest.T1=2'b01 This serves the same functionality with the previous example. If we define the same parameter in command file and command line, the one in command line would over-write all others.
2009-08-06 23:42:13 +02:00
}
Improved error checking for defparam values supplied on the command line. Fixes GitHub issue #139 plus various assertion failures when invalid values are specified.
2017-01-29 21:13:01 +01:00
// None of the above.
cerr << "<command line>: error: invalid value specified for defparam: " << name << endl;
Fix memory leak and gcc4.4 compilation. There was a small memory leak in parm_to_defparam_list where space for "key" and "value" was being allocated via strdup and never freed. This was fixed by freeing them at each return point. In that function, key and value were defined to be const char* but were later mutated. gcc4.4 is more strict with const-ness in some functions than previous versions (see http://gcc.gnu.org/gcc-4.4/porting_to.html section "Strict null-terminated sequence utilities"), so this caused compilation to fail. Fixed by removing the const modifier in the declaration of those two variables and related nkey variable. This also necessitated malloc'ing room for value in one path through the code, which made memory management easier as well.
2009-08-22 04:28:19 +02:00
free(value);
Add function to define parameter from command line This patch is based on one from "bruce <bruce1914@gmail.com>". I've applied all but the elaboration code, which I rewrote to properly work with the elaboration work queue. I also constrained the implementation so that the parameter name must have exactly two components: the root scope name and the parameter name. This is necessary to keep the defparm processing sane. The comments from bruce's original patch are as follows: -- This patch would provide function to define parameter from command line. This serves the same functionality as 'defparam' in Verilog source code, but provide much more ease for using. Parameter definition can be write in command file, with following syntax: +parameter+<scope>.<parameter>=<val> *Do not apply any space between them* The scope name should be full hierachical name with root name at the begining. The following example would override test.T1 with new value 2'b01: +parameter+test.T1=2'b01 'test' here is the root module name. The parameter value here should be constant. Parameter definition can also be write in the command line: iverilog -Ptest.T1=2'b01 This serves the same functionality with the previous example. If we define the same parameter in command file and command line, the one in command line would over-write all others.
2009-08-06 23:42:13 +02:00
}
Support the include directive.
1998-12-09 05:02:47 +01:00
/*
* The lexor accesses the vl_* variables.
*/
string vl_file = "";
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
extern int VLparse();
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
/* This tracks the current module being processed. There can only be
Spelling fixes only comments and documentation some punctuation and capitalization for good measure Changelogs are purposefully untouched
2008-01-29 21:19:59 +01:00
exactly one module currently being parsed, since Verilog does not
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
allow nested module definitions. */
Allow modules (and program blocks in particular) to nest. An important advantage of program blocks is its ability to nest within a module. This winds up also allowing modules to nest, which is legal but presumably less used feature.
2012-05-10 04:35:11 +02:00
static list<Module*>pform_cur_module;
Add support for -v flag in command file.
2007-04-19 04:52:53 +02:00
bool pform_library_flag = false;
SV: Add support for var decls in unnamed begin/end blocks. SystemVerilog allows variables to be declared in unnamed begin/end blocks. This patch adds support for this functionality.
2014-07-23 03:55:24 +02:00
/*
* Give each unnamed block that has a variable declaration a unique name.
*/
static unsigned scope_unnamed_block_with_decl = 1;
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
/* increment this for generate schemes within a module, and set it
to zero when a new module starts. */
static unsigned scope_generate_counter = 1;
/* This tracks the current generate scheme being processed. This is
always within a module. */
static PGenerate*pform_cur_generate = 0;
Timescale warnings.
2002-04-15 02:04:22 +02:00
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
/* Blocks within the same conditional generate construct may have
the same name. Here we collect the set of names used in each
construct, so they can be added to the local scope without
conflicting with each other. Generate constructs may nest, so
we need a stack. */
static list<set<perm_string>> conditional_block_names;
Added parser support for SV modport declarations.
2015-01-10 12:09:42 +01:00
/* This tracks the current modport list being processed. This is
always within an interface. */
static PModport*pform_cur_modport = 0;
Add support for the default_nettype directive.
2004-06-13 06:56:53 +02:00
static NetNet::Type pform_default_nettype = NetNet::WIRE;
Timescale warnings.
2002-04-15 02:04:22 +02:00
/*
Rework handling of timescales in parser. This implements and enforces the full set of rules for determining timescales in SystemVerilog. The previous relaxation of the rules that allowed timescales to be redefined within the compilation unit scope has been removed. Time unit and precision redeclarations are now recognised after a nested module declaration.
2017-11-05 18:50:05 +01:00
* These variables track the time scale set by the most recent `timescale
* directive. Time scales set by SystemVerilog timeunit and timeprecision
* declarations are stored directly in the current lexical scope.
Timescale warnings.
2002-04-15 02:04:22 +02:00
*/
Add support for `resetall and other directive changes. This patch adds support for the `resetall directive. It also changes `celldefine, `endcelldefine and `resetall to no longer grab text following them. These directives do not take an argument so they should not be grabbing any text and silently discarding it. The `timescale processing was reworked to handle being reset and hooks were added to easily change the default time units and precision when we add that feature request.
2009-05-22 20:03:36 +02:00
static int pform_time_unit;
static int pform_time_prec;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
System Verilog timeunit and timeprecision addition This patch adds timeunit and timeprecision keywords.Use -gsystem-verilog generation flag to use this feature
2009-06-20 05:58:46 +02:00
/*
Rework handling of timescales in parser. This implements and enforces the full set of rules for determining timescales in SystemVerilog. The previous relaxation of the rules that allowed timescales to be redefined within the compilation unit scope has been removed. Time unit and precision redeclarations are now recognised after a nested module declaration.
2017-11-05 18:50:05 +01:00
* These variables track where the most recent `timescale directive
* occurred. This allows us to warn about time scales that are inherited
* from another file.
System Verilog timeunit and timeprecision addition This patch adds timeunit and timeprecision keywords.Use -gsystem-verilog generation flag to use this feature
2009-06-20 05:58:46 +02:00
*/
Timescale warnings.
2002-04-15 02:04:22 +02:00
static char*pform_timescale_file = 0;
Add support for `resetall and other directive changes. This patch adds support for the `resetall directive. It also changes `celldefine, `endcelldefine and `resetall to no longer grab text following them. These directives do not take an argument so they should not be grabbing any text and silently discarding it. The `timescale processing was reworked to handle being reset and hooks were added to easily change the default time units and precision when we add that feature request.
2009-05-22 20:03:36 +02:00
static unsigned pform_timescale_line;
Timescale warnings.
2002-04-15 02:04:22 +02:00
Rework handling of timescales in parser. This implements and enforces the full set of rules for determining timescales in SystemVerilog. The previous relaxation of the rules that allowed timescales to be redefined within the compilation unit scope has been removed. Time unit and precision redeclarations are now recognised after a nested module declaration.
2017-11-05 18:50:05 +01:00
/*
* These variables track whether we can accept new timeunits declarations.
*/
bool allow_timeunit_decl = true;
bool allow_timeprec_decl = true;
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
static inline void FILE_NAME(LineInfo*obj, const char*file, unsigned lineno)
{
obj->set_lineno(lineno);
obj->set_file(filename_strings.make(file));
}
Handle expression widths for EEE and NEE operators, add named blocks and scope handling, add registers declared in named blocks.
1999-06-24 06:24:18 +02:00
/*
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
* The lexical_scope keeps track of the current lexical scope that is
* being parsed. The lexical scope may stack, so the current scope may
* have a parent, that is restored when the current scope ends.
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
*
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
* Items that have scoped names are put in the lexical_scope object.
Handle expression widths for EEE and NEE operators, add named blocks and scope handling, add registers declared in named blocks.
1999-06-24 06:24:18 +02:00
*/
Rework of lexical scope handling in parser. This patch modifies the parser to use a single stack to track lexical scopes, rather than starting a new stack for each generate construct.
2010-01-08 23:49:48 +01:00
static LexicalScope* lexical_scope = 0;
Parse and elaborate timescale to scopes.
2000-07-23 00:09:03 +02:00
Added support for default subroutine lifetimes (SystemVerilog).
2016-03-19 18:27:27 +01:00
LexicalScope* pform_peek_scope(void)
{
assert(lexical_scope);
return lexical_scope;
}
Handle expression widths for EEE and NEE operators, add named blocks and scope handling, add registers declared in named blocks.
1999-06-24 06:24:18 +02:00
void pform_pop_scope()
{
On error there is no need to pop the scope. The error routines for task and function definitions were incorrectly popping the scope. This should not be done since no scope was pushed. Also assert that the current_task/function is 0 to catch that kind of error like the other definition rules.
2010-06-13 20:41:24 +02:00
assert(lexical_scope);
Rework of lexical scope handling in parser. This patch modifies the parser to use a single stack to track lexical scopes, rather than starting a new stack for each generate construct.
2010-01-08 23:49:48 +01:00
lexical_scope = lexical_scope->parent_scope();
Support separate compilation units in SystemVerilog. The compilation unit scope is now treated as a specialised form of package (with an automatically generated name). All items declared outside a design element are added to the current compilation unit package. Apart from when searching for a symbol, once we get into elaboration we can treat these just like any other package.
2017-10-21 16:04:25 +02:00
assert(lexical_scope);
Handle expression widths for EEE and NEE operators, add named blocks and scope handling, add registers declared in named blocks.
1999-06-24 06:24:18 +02:00
}
Added support for default subroutine lifetimes (SystemVerilog).
2016-03-19 18:27:27 +01:00
static LexicalScope::lifetime_t find_lifetime(LexicalScope::lifetime_t lifetime)
{
if (lifetime != LexicalScope::INHERITED)
return lifetime;
Support separate compilation units in SystemVerilog. The compilation unit scope is now treated as a specialised form of package (with an automatically generated name). All items declared outside a design element are added to the current compilation unit package. Apart from when searching for a symbol, once we get into elaboration we can treat these just like any other package.
2017-10-21 16:04:25 +02:00
return lexical_scope->default_lifetime;
Added support for default subroutine lifetimes (SystemVerilog).
2016-03-19 18:27:27 +01:00
}
Elaborate class_new and (null) expressions This gets the types right for class_new and null expressions, and elaborate them down to the ivl_target.h API.
2012-11-12 02:42:31 +01:00
static PScopeExtra* find_nearest_scopex(LexicalScope*scope)
{
PScopeExtra*scopex = dynamic_cast<PScopeExtra*> (scope);
while (scope && !scopex) {
scope = scope->parent_scope();
scopex = dynamic_cast<PScopeExtra*> (scope);
}
return scopex;
}
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
static void add_local_symbol(LexicalScope*scope, perm_string name, PNamedItem*item)
{
assert(scope);
// Check for conflict with another local symbol.
map<perm_string,PNamedItem*>::const_iterator cur_sym
= scope->local_symbols.find(name);
if (cur_sym != scope->local_symbols.end()) {
cerr << item->get_fileline() << ": error: "
"'" << name << "' has already been declared "
"in this scope." << endl;
cerr << cur_sym->second->get_fileline() << ": : "
"It was declared here as "
<< cur_sym->second->symbol_type() << "." << endl;
error_count += 1;
return;
}
// Check for conflict with an explicit import.
map<perm_string,PPackage*>::const_iterator cur_pkg
= scope->explicit_imports.find(name);
if (cur_pkg != scope->explicit_imports.end()) {
cerr << item->get_fileline() << ": error: "
"'" << name << "' has already been "
"imported into this scope from package '"
<< cur_pkg->second->pscope_name() << "'." << endl;
error_count += 1;
return;
}
scope->local_symbols[name] = item;
}
static PPackage*find_potential_import(const struct vlltype&loc, LexicalScope*scope,
perm_string name, PNamedItem::SymbolType st)
{
assert(scope);
PPackage*found_pkg = 0;
for (set<PPackage*>::const_iterator cur_pkg = scope->potential_imports.begin();
cur_pkg != scope->potential_imports.end(); ++cur_pkg) {
PPackage*search_pkg = *cur_pkg;
map<perm_string,PNamedItem*>::const_iterator cur_sym
= search_pkg->local_symbols.find(name);
if (cur_sym != search_pkg->local_symbols.end()) {
if (st != PNamedItem::ANY && st != cur_sym->second->symbol_type())
continue;
if (found_pkg) {
cerr << loc.get_fileline() << ": error: "
"Ambiguous use of '" << name << "'. "
"It is exported by both '"
<< found_pkg->pscope_name()
<< "' and by '"
<< search_pkg->pscope_name()
<< "'." << endl;
error_count += 1;
} else {
found_pkg = search_pkg;
scope->explicit_imports[name] = found_pkg;
}
}
}
return found_pkg;
}
static void check_potential_imports(const struct vlltype&loc, perm_string name)
{
LexicalScope*scope = lexical_scope;
while (scope) {
if (scope->local_symbols.find(name) != scope->local_symbols.end())
return;
if (scope->explicit_imports.find(name) != scope->explicit_imports.end())
return;
if (find_potential_import(loc, scope, name, PNamedItem::ANY))
return;
scope = scope->parent_scope();
}
}
Support timescales in design units that aren't inside a module. SystemVerilog allows tasks, functions, and classes to be defined at the root level or inside packages, so we can't rely on an enclosing module being present to provide the timescale.
2016-07-22 23:48:20 +02:00
/*
Rework handling of timescales in parser. This implements and enforces the full set of rules for determining timescales in SystemVerilog. The previous relaxation of the rules that allowed timescales to be redefined within the compilation unit scope has been removed. Time unit and precision redeclarations are now recognised after a nested module declaration.
2017-11-05 18:50:05 +01:00
* Set the local time unit/precision. This version is used for setting
* the time scale for design elements (modules, packages, etc.) and is
* called after any initial timeunit and timeprecision declarations
* have been parsed.
Support timescales in design units that aren't inside a module. SystemVerilog allows tasks, functions, and classes to be defined at the root level or inside packages, so we can't rely on an enclosing module being present to provide the timescale.
2016-07-22 23:48:20 +02:00
*/
Rework handling of timescales in parser. This implements and enforces the full set of rules for determining timescales in SystemVerilog. The previous relaxation of the rules that allowed timescales to be redefined within the compilation unit scope has been removed. Time unit and precision redeclarations are now recognised after a nested module declaration.
2017-11-05 18:50:05 +01:00
void pform_set_scope_timescale(const struct vlltype&loc)
{
PScopeExtra*scope = dynamic_cast<PScopeExtra*>(lexical_scope);
assert(scope);
PScopeExtra*parent = find_nearest_scopex(scope->parent_scope());
bool used_global_timescale = false;
if (scope->time_unit_is_default) {
if (is_compilation_unit(scope)) {
scope->time_unit = def_ts_units;
} else if (!is_compilation_unit(parent)) {
scope->time_unit = parent->time_unit;
scope->time_unit_is_default = parent->time_unit_is_default;
} else if (pform_timescale_file != 0) {
scope->time_unit = pform_time_unit;
scope->time_unit_is_default = false;
used_global_timescale = true;
} else /* parent is compilation unit */ {
scope->time_unit = parent->time_unit;
scope->time_unit_is_default = parent->time_unit_is_default;
}
}
if (scope->time_prec_is_default) {
if (is_compilation_unit(scope)) {
scope->time_precision = def_ts_prec;
} else if (!is_compilation_unit(parent)) {
scope->time_precision = parent->time_precision;
scope->time_prec_is_default = parent->time_prec_is_default;
} else if (pform_timescale_file != 0) {
scope->time_precision = pform_time_prec;
scope->time_prec_is_default = false;
used_global_timescale = true;
} else {
scope->time_precision = parent->time_precision;
scope->time_prec_is_default = parent->time_prec_is_default;
}
}
if (gn_system_verilog() && (scope->time_unit < scope->time_precision)) {
Fix a couple of minor bugs in the timescale parsing rework.
2017-11-06 01:37:56 +01:00
if (scope->time_unit_is_local || scope->time_prec_is_local) {
VLerror("error: a timeprecision is missing or is too large!");
}
Rework handling of timescales in parser. This implements and enforces the full set of rules for determining timescales in SystemVerilog. The previous relaxation of the rules that allowed timescales to be redefined within the compilation unit scope has been removed. Time unit and precision redeclarations are now recognised after a nested module declaration.
2017-11-05 18:50:05 +01:00
} else {
assert(scope->time_unit >= scope->time_precision);
}
Support timescales in design units that aren't inside a module. SystemVerilog allows tasks, functions, and classes to be defined at the root level or inside packages, so we can't rely on an enclosing module being present to provide the timescale.
2016-07-22 23:48:20 +02:00
Rework handling of timescales in parser. This implements and enforces the full set of rules for determining timescales in SystemVerilog. The previous relaxation of the rules that allowed timescales to be redefined within the compilation unit scope has been removed. Time unit and precision redeclarations are now recognised after a nested module declaration.
2017-11-05 18:50:05 +01:00
if (warn_timescale && used_global_timescale
Support timescales in design units that aren't inside a module. SystemVerilog allows tasks, functions, and classes to be defined at the root level or inside packages, so we can't rely on an enclosing module being present to provide the timescale.
2016-07-22 23:48:20 +02:00
&& (strcmp(pform_timescale_file, loc.text) != 0)) {
cerr << loc.get_fileline() << ": warning: "
<< "timescale for " << scope->pscope_name()
<< " inherited from another file." << endl;
cerr << pform_timescale_file << ":" << pform_timescale_line
<< ": ...: The inherited timescale is here." << endl;
}
Rework handling of timescales in parser. This implements and enforces the full set of rules for determining timescales in SystemVerilog. The previous relaxation of the rules that allowed timescales to be redefined within the compilation unit scope has been removed. Time unit and precision redeclarations are now recognised after a nested module declaration.
2017-11-05 18:50:05 +01:00
allow_timeunit_decl = false;
allow_timeprec_decl = false;
}
/*
* Set the local time unit/precision. This version is used for setting
* the time scale for subsidiary items (classes, subroutines, etc.),
* which simply inherit their time scale from their parent scope.
*/
static void pform_set_scope_timescale(PScope*scope, const PScope*parent)
{
scope->time_unit = parent->time_unit;
scope->time_precision = parent->time_precision;
scope->time_unit_is_default = parent->time_unit_is_default;
scope->time_prec_is_default = parent->time_prec_is_default;
Support timescales in design units that aren't inside a module. SystemVerilog allows tasks, functions, and classes to be defined at the root level or inside packages, so we can't rely on an enclosing module being present to provide the timescale.
2016-07-22 23:48:20 +02:00
}
Added support for default subroutine lifetimes (SystemVerilog).
2016-03-19 18:27:27 +01:00
PClass* pform_push_class_scope(const struct vlltype&loc, perm_string name,
LexicalScope::lifetime_t lifetime)
Get the scope of class methods right Class methods belong in a class scope, not the containing module. So create a lexical scope that carries tasks and functions and create a PClass to represent classes.
2012-03-11 21:18:24 +01:00
{
PClass*class_scope = new PClass(name, lexical_scope);
Added support for default subroutine lifetimes (SystemVerilog).
2016-03-19 18:27:27 +01:00
class_scope->default_lifetime = find_lifetime(lifetime);
Get the scope of class methods right Class methods belong in a class scope, not the containing module. So create a lexical scope that carries tasks and functions and create a PClass to represent classes.
2012-03-11 21:18:24 +01:00
FILE_NAME(class_scope, loc);
Elaborate class_new and (null) expressions This gets the types right for class_new and null expressions, and elaborate them down to the ivl_target.h API.
2012-11-12 02:42:31 +01:00
PScopeExtra*scopex = find_nearest_scopex(lexical_scope);
Support separate compilation units in SystemVerilog. The compilation unit scope is now treated as a specialised form of package (with an automatically generated name). All items declared outside a design element are added to the current compilation unit package. Apart from when searching for a symbol, once we get into elaboration we can treat these just like any other package.
2017-10-21 16:04:25 +02:00
assert(scopex);
Elaborate class_new and (null) expressions This gets the types right for class_new and null expressions, and elaborate them down to the ivl_target.h API.
2012-11-12 02:42:31 +01:00
assert(!pform_cur_generate);
Rework handling of timescales in parser. This implements and enforces the full set of rules for determining timescales in SystemVerilog. The previous relaxation of the rules that allowed timescales to be redefined within the compilation unit scope has been removed. Time unit and precision redeclarations are now recognised after a nested module declaration.
2017-11-05 18:50:05 +01:00
pform_set_scope_timescale(class_scope, scopex);
Elaborate class_new and (null) expressions This gets the types right for class_new and null expressions, and elaborate them down to the ivl_target.h API.
2012-11-12 02:42:31 +01:00
scopex->classes[name] = class_scope;
Elaborate classes in lexical order so that mutual references work.
2013-04-29 01:28:24 +02:00
scopex->classes_lexical .push_back(class_scope);
Elaborate class_new and (null) expressions This gets the types right for class_new and null expressions, and elaborate them down to the ivl_target.h API.
2012-11-12 02:42:31 +01:00
Get the scope of class methods right Class methods belong in a class scope, not the containing module. So create a lexical scope that carries tasks and functions and create a PClass to represent classes.
2012-03-11 21:18:24 +01:00
lexical_scope = class_scope;
return class_scope;
}
Added support for default subroutine lifetimes (SystemVerilog).
2016-03-19 18:27:27 +01:00
PPackage* pform_push_package_scope(const struct vlltype&loc, perm_string name,
LexicalScope::lifetime_t lifetime)
Parse (with sorry message) package declarations.
2012-10-21 20:42:19 +02:00
{
PPackage*pkg_scope = new PPackage(name, lexical_scope);
Added support for default subroutine lifetimes (SystemVerilog).
2016-03-19 18:27:27 +01:00
pkg_scope->default_lifetime = find_lifetime(lifetime);
Parse (with sorry message) package declarations.
2012-10-21 20:42:19 +02:00
FILE_NAME(pkg_scope, loc);
Rework handling of timescales in parser. This implements and enforces the full set of rules for determining timescales in SystemVerilog. The previous relaxation of the rules that allowed timescales to be redefined within the compilation unit scope has been removed. Time unit and precision redeclarations are now recognised after a nested module declaration.
2017-11-05 18:50:05 +01:00
allow_timeunit_decl = true;
allow_timeprec_decl = true;
Support timescales in design units that aren't inside a module. SystemVerilog allows tasks, functions, and classes to be defined at the root level or inside packages, so we can't rely on an enclosing module being present to provide the timescale.
2016-07-22 23:48:20 +02:00
Parse (with sorry message) package declarations.
2012-10-21 20:42:19 +02:00
lexical_scope = pkg_scope;
return pkg_scope;
}
Added support for default subroutine lifetimes (SystemVerilog).
2016-03-19 18:27:27 +01:00
PTask* pform_push_task_scope(const struct vlltype&loc, char*name,
LexicalScope::lifetime_t lifetime)
Objects of lexical scope use PScope base class. All the pform objects that represent lexical scope now are derived from the PScope class, and are kept in a lexical_scope table so that the scope can be managed.
2008-02-16 06:20:24 +01:00
{
perm_string task_name = lex_strings.make(name);
Added support for default subroutine lifetimes (SystemVerilog).
2016-03-19 18:27:27 +01:00
LexicalScope::lifetime_t default_lifetime = find_lifetime(lifetime);
bool is_auto = default_lifetime == LexicalScope::AUTOMATIC;
Rework of lexical scope handling in parser. This patch modifies the parser to use a single stack to track lexical scopes, rather than starting a new stack for each generate construct.
2010-01-08 23:49:48 +01:00
PTask*task = new PTask(task_name, lexical_scope, is_auto);
Added support for default subroutine lifetimes (SystemVerilog).
2016-03-19 18:27:27 +01:00
task->default_lifetime = default_lifetime;
Rework of lexical scope handling in parser. This patch modifies the parser to use a single stack to track lexical scopes, rather than starting a new stack for each generate construct.
2010-01-08 23:49:48 +01:00
FILE_NAME(task, loc);
Get the scope of class methods right Class methods belong in a class scope, not the containing module. So create a lexical scope that carries tasks and functions and create a PClass to represent classes.
2012-03-11 21:18:24 +01:00
Elaborate class_new and (null) expressions This gets the types right for class_new and null expressions, and elaborate them down to the ivl_target.h API.
2012-11-12 02:42:31 +01:00
PScopeExtra*scopex = find_nearest_scopex(lexical_scope);
Support separate compilation units in SystemVerilog. The compilation unit scope is now treated as a specialised form of package (with an automatically generated name). All items declared outside a design element are added to the current compilation unit package. Apart from when searching for a symbol, once we get into elaboration we can treat these just like any other package.
2017-10-21 16:04:25 +02:00
assert(scopex);
if (is_compilation_unit(scopex) && !gn_system_verilog()) {
Fix for GitHub issue 25 - compiler crash when function declared outside module. This is an error in traditional Verilog and a unsupported feature in SystemVerilog. Fail gracefully with a suitable error/sorry message. Do the same for task declarations.
2014-05-23 22:55:46 +02:00
cerr << task->get_fileline() << ": error: task declarations "
"must be contained within a module." << endl;
error_count += 1;
}
Get the scope of class methods right Class methods belong in a class scope, not the containing module. So create a lexical scope that carries tasks and functions and create a PClass to represent classes.
2012-03-11 21:18:24 +01:00
Rework handling of timescales in parser. This implements and enforces the full set of rules for determining timescales in SystemVerilog. The previous relaxation of the rules that allowed timescales to be redefined within the compilation unit scope has been removed. Time unit and precision redeclarations are now recognised after a nested module declaration.
2017-11-05 18:50:05 +01:00
pform_set_scope_timescale(task, scopex);
Better handle nesting of scopes inside generate blocks. Within generate schemes it is possible to have nested scopes, even more liberally then outside generate blocks. So see to it that the scopes properly stack with the generate blocks, and that wires and behaviors are put in the right scopes.
2008-06-20 06:31:53 +02:00
if (pform_cur_generate) {
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
add_local_symbol(pform_cur_generate, task_name, task);
pform_cur_generate->tasks[task_name] = task;
Support separate compilation units in SystemVerilog. The compilation unit scope is now treated as a specialised form of package (with an automatically generated name). All items declared outside a design element are added to the current compilation unit package. Apart from when searching for a symbol, once we get into elaboration we can treat these just like any other package.
2017-10-21 16:04:25 +02:00
} else {
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
add_local_symbol(scopex, task_name, task);
scopex->tasks[task_name] = task;
Better handle nesting of scopes inside generate blocks. Within generate schemes it is possible to have nested scopes, even more liberally then outside generate blocks. So see to it that the scopes properly stack with the generate blocks, and that wires and behaviors are put in the right scopes.
2008-06-20 06:31:53 +02:00
}
Get the scope of class methods right Class methods belong in a class scope, not the containing module. So create a lexical scope that carries tasks and functions and create a PClass to represent classes.
2012-03-11 21:18:24 +01:00
Rework of lexical scope handling in parser. This patch modifies the parser to use a single stack to track lexical scopes, rather than starting a new stack for each generate construct.
2010-01-08 23:49:48 +01:00
lexical_scope = task;
Allow generate schemes to generate task/function definitions. Generating task/function definitions involves getting the functions to put themselves into the generate scheme instead of the module, and getting elaboration to elaborate those definitions in the generate scheme.
2008-06-19 06:54:58 +02:00
Objects of lexical scope use PScope base class. All the pform objects that represent lexical scope now are derived from the PScope class, and are kept in a lexical_scope table so that the scope can be managed.
2008-02-16 06:20:24 +01:00
return task;
}
Generalize user defined function return type handling. I'm gonna need functions to return class objects, so generalize the output types of user defined functions.
2013-04-15 03:03:21 +02:00
PFunction* pform_push_function_scope(const struct vlltype&loc, const char*name,
Added support for default subroutine lifetimes (SystemVerilog).
2016-03-19 18:27:27 +01:00
LexicalScope::lifetime_t lifetime)
Objects of lexical scope use PScope base class. All the pform objects that represent lexical scope now are derived from the PScope class, and are kept in a lexical_scope table so that the scope can be managed.
2008-02-16 06:20:24 +01:00
{
perm_string func_name = lex_strings.make(name);
Added support for default subroutine lifetimes (SystemVerilog).
2016-03-19 18:27:27 +01:00
LexicalScope::lifetime_t default_lifetime = find_lifetime(lifetime);
bool is_auto = default_lifetime == LexicalScope::AUTOMATIC;
Rework of lexical scope handling in parser. This patch modifies the parser to use a single stack to track lexical scopes, rather than starting a new stack for each generate construct.
2010-01-08 23:49:48 +01:00
PFunction*func = new PFunction(func_name, lexical_scope, is_auto);
Added support for default subroutine lifetimes (SystemVerilog).
2016-03-19 18:27:27 +01:00
func->default_lifetime = default_lifetime;
Rework of lexical scope handling in parser. This patch modifies the parser to use a single stack to track lexical scopes, rather than starting a new stack for each generate construct.
2010-01-08 23:49:48 +01:00
FILE_NAME(func, loc);
Get the scope of class methods right Class methods belong in a class scope, not the containing module. So create a lexical scope that carries tasks and functions and create a PClass to represent classes.
2012-03-11 21:18:24 +01:00
Fix for GitHub issue 25 - compiler crash when function declared outside module. This is an error in traditional Verilog and a unsupported feature in SystemVerilog. Fail gracefully with a suitable error/sorry message. Do the same for task declarations.
2014-05-23 22:55:46 +02:00
PScopeExtra*scopex = find_nearest_scopex(lexical_scope);
Support separate compilation units in SystemVerilog. The compilation unit scope is now treated as a specialised form of package (with an automatically generated name). All items declared outside a design element are added to the current compilation unit package. Apart from when searching for a symbol, once we get into elaboration we can treat these just like any other package.
2017-10-21 16:04:25 +02:00
assert(scopex);
if (is_compilation_unit(scopex) && !gn_system_verilog()) {
Fix for GitHub issue 25 - compiler crash when function declared outside module. This is an error in traditional Verilog and a unsupported feature in SystemVerilog. Fail gracefully with a suitable error/sorry message. Do the same for task declarations.
2014-05-23 22:55:46 +02:00
cerr << func->get_fileline() << ": error: function declarations "
"must be contained within a module." << endl;
error_count += 1;
}
Get the scope of class methods right Class methods belong in a class scope, not the containing module. So create a lexical scope that carries tasks and functions and create a PClass to represent classes.
2012-03-11 21:18:24 +01:00
Rework handling of timescales in parser. This implements and enforces the full set of rules for determining timescales in SystemVerilog. The previous relaxation of the rules that allowed timescales to be redefined within the compilation unit scope has been removed. Time unit and precision redeclarations are now recognised after a nested module declaration.
2017-11-05 18:50:05 +01:00
pform_set_scope_timescale(func, scopex);
Better handle nesting of scopes inside generate blocks. Within generate schemes it is possible to have nested scopes, even more liberally then outside generate blocks. So see to it that the scopes properly stack with the generate blocks, and that wires and behaviors are put in the right scopes.
2008-06-20 06:31:53 +02:00
if (pform_cur_generate) {
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
add_local_symbol(pform_cur_generate, func_name, func);
pform_cur_generate->funcs[func_name] = func;
Handle functions in $root scope.
2014-10-03 00:04:14 +02:00
Support separate compilation units in SystemVerilog. The compilation unit scope is now treated as a specialised form of package (with an automatically generated name). All items declared outside a design element are added to the current compilation unit package. Apart from when searching for a symbol, once we get into elaboration we can treat these just like any other package.
2017-10-21 16:04:25 +02:00
} else {
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
add_local_symbol(scopex, func_name, func);
scopex->funcs[func_name] = func;
Better handle nesting of scopes inside generate blocks. Within generate schemes it is possible to have nested scopes, even more liberally then outside generate blocks. So see to it that the scopes properly stack with the generate blocks, and that wires and behaviors are put in the right scopes.
2008-06-20 06:31:53 +02:00
}
Handle functions in $root scope.
2014-10-03 00:04:14 +02:00
Rework of lexical scope handling in parser. This patch modifies the parser to use a single stack to track lexical scopes, rather than starting a new stack for each generate construct.
2010-01-08 23:49:48 +01:00
lexical_scope = func;
Allow generate schemes to generate task/function definitions. Generating task/function definitions involves getting the functions to put themselves into the generate scheme instead of the module, and getting elaboration to elaborate those definitions in the generate scheme.
2008-06-19 06:54:58 +02:00
Objects of lexical scope use PScope base class. All the pform objects that represent lexical scope now are derived from the PScope class, and are kept in a lexical_scope table so that the scope can be managed.
2008-02-16 06:20:24 +01:00
return func;
}
PBlock* pform_push_block_scope(char*name, PBlock::BL_TYPE bt)
{
SV: Add support for var decls in unnamed begin/end blocks. SystemVerilog allows variables to be declared in unnamed begin/end blocks. This patch adds support for this functionality.
2014-07-23 03:55:24 +02:00
perm_string block_name;
if (name) block_name = lex_strings.make(name);
else {
// Create a unique name for this unnamed block.
char tmp[32];
snprintf(tmp, sizeof tmp, "$unm_blk_%u",
scope_unnamed_block_with_decl);
block_name = lex_strings.make(tmp);
scope_unnamed_block_with_decl += 1;
}
Objects of lexical scope use PScope base class. All the pform objects that represent lexical scope now are derived from the PScope class, and are kept in a lexical_scope table so that the scope can be managed.
2008-02-16 06:20:24 +01:00
Rework of lexical scope handling in parser. This patch modifies the parser to use a single stack to track lexical scopes, rather than starting a new stack for each generate construct.
2010-01-08 23:49:48 +01:00
PBlock*block = new PBlock(block_name, lexical_scope, bt);
Add check for explicit lifetime when initialising static variables. If a static variable declared in a task, function, or block has an initialisation expression, SystemVerilog requires the declaration to have an explicit static lifetime. This is supposed to be a compile error, but for now just output a warning. Implementing this required adding support in the parser for explicit lifetimes in variable declarations. For now, just output an error if the user asks for a lifetime that isn't the default for that scope.
2016-03-19 21:39:54 +01:00
block->default_lifetime = find_lifetime(LexicalScope::INHERITED);
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
if (name) add_local_symbol(lexical_scope, block_name, block);
Rework of lexical scope handling in parser. This patch modifies the parser to use a single stack to track lexical scopes, rather than starting a new stack for each generate construct.
2010-01-08 23:49:48 +01:00
lexical_scope = block;
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
Objects of lexical scope use PScope base class. All the pform objects that represent lexical scope now are derived from the PScope class, and are kept in a lexical_scope table so that the scope can be managed.
2008-02-16 06:20:24 +01:00
return block;
}
Properly implement import <pkg>::<name> This was temporarily implemented to just copy definitions to the local scope, but the better method is to create a PEIdent that has the package attached to it.
2013-02-18 01:22:24 +01:00
/*
Remove redundant checks for package imports during parsing. The find_* and symbol_search functions now handle this.
2019-09-22 10:16:10 +02:00
* Create a new identifier.
Properly implement import <pkg>::<name> This was temporarily implemented to just copy definitions to the local scope, but the better method is to create a PEIdent that has the package attached to it.
2013-02-18 01:22:24 +01:00
*/
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
PEIdent* pform_new_ident(const struct vlltype&loc, const pform_name_t&name)
Properly implement import <pkg>::<name> This was temporarily implemented to just copy definitions to the local scope, but the better method is to create a PEIdent that has the package attached to it.
2013-02-18 01:22:24 +01:00
{
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
if (gn_system_verilog() && name.size() == 1)
check_potential_imports(loc, name.back().name);
Remove redundant checks for package imports during parsing. The find_* and symbol_search functions now handle this.
2019-09-22 10:16:10 +02:00
return new PEIdent(name);
Properly implement import <pkg>::<name> This was temporarily implemented to just copy definitions to the local scope, but the better method is to create a PEIdent that has the package attached to it.
2013-02-18 01:22:24 +01:00
}
Detect generate regions within generate schemes. Generate schemes may nest freely, but generate regions (an anachronistic concept from 1364-2001) cannot nest, not within schemes or other regions. Have the parser detect the nesting and print an error message.
2010-03-12 01:06:02 +01:00
PGenerate* pform_parent_generate(void)
{
return pform_cur_generate;
}
Parse attributes on statements within event statements. Statements can have attributes attached to them. Handle a few cases in the parser where attributes may be attached to statements, and get them as far as the pform.
2008-09-05 06:27:21 +02:00
void pform_bind_attributes(map<perm_string,PExpr*>&attributes,
Enumeration element values can be expressions Allow more complex enumeration expressions, which means putting off the evaluation of the expression values until elaboration.
2010-11-13 03:47:06 +01:00
list<named_pexpr_t>*attr, bool keep_attrs)
Parse attributes on statements within event statements. Statements can have attributes attached to them. Handle a few cases in the parser where attributes may be attached to statements, and get them as far as the pform.
2008-09-05 06:27:21 +02:00
{
if (attr == 0)
return;
Some more cppcheck cleanup. This patch cleans up most of the warnings in the main (ivl) directory.
2011-04-19 03:17:16 +02:00
while (! attr->empty()) {
Enumeration element values can be expressions Allow more complex enumeration expressions, which means putting off the evaluation of the expression values until elaboration.
2010-11-13 03:47:06 +01:00
named_pexpr_t tmp = attr->front();
attr->pop_front();
attributes[tmp.name] = tmp.parm;
Parse attributes on statements within event statements. Statements can have attributes attached to them. Handle a few cases in the parser where attributes may be attached to statements, and get them as far as the pform.
2008-09-05 06:27:21 +02:00
}
Enumeration element values can be expressions Allow more complex enumeration expressions, which means putting off the evaluation of the expression values until elaboration.
2010-11-13 03:47:06 +01:00
if (!keep_attrs)
delete attr;
Parse attributes on statements within event statements. Statements can have attributes attached to them. Handle a few cases in the parser where attributes may be attached to statements, and get them as far as the pform.
2008-09-05 06:27:21 +02:00
}
Prevent non-blocking assignment in program blocks.
2012-05-06 19:21:51 +02:00
bool pform_in_program_block()
{
Fix some cppcheck warnings in the main directory
2012-08-08 20:26:46 +02:00
if (pform_cur_module.empty())
Prevent non-blocking assignment in program blocks.
2012-05-06 19:21:51 +02:00
return false;
Allow modules (and program blocks in particular) to nest. An important advantage of program blocks is its ability to nest within a module. This winds up also allowing modules to nest, which is legal but presumably less used feature.
2012-05-10 04:35:11 +02:00
if (pform_cur_module.front()->program_block)
Prevent non-blocking assignment in program blocks.
2012-05-06 19:21:51 +02:00
return true;
return false;
}
Added support for interface declaration and instantiation. modport and extern tf declarations are not yet supported.
2014-12-20 00:10:14 +01:00
bool pform_in_interface()
{
if (pform_cur_module.empty())
return false;
if (pform_cur_module.front()->is_interface)
return true;
return false;
}
Rework of automatic task/function support. This patch splits any VVP net functor that needs to access both statically and automatically allocated state into two sub-classes, one for handling operations on statically allocated state, the other for handling operations on automatically allocated state. This undoes the increase in run-time memory use introduced when automatic task/function support was first introduced. This patch also fixes various issues with event handling in automatic scopes. Event expressions in automatic scopes may now reference either statically or automatically allocated variables or arrays, or part selects or word selects thereof. More complex expressions (e.g. containing arithmetic or logical operators, function calls, etc.) are not currently supported. This patch introduces some error checking for language constructs that may not reference automatically allocated variables. Further error checking will follow in a subsequent patch.
2008-10-28 18:52:39 +01:00
static bool pform_at_module_level()
{
Allow modules (and program blocks in particular) to nest. An important advantage of program blocks is its ability to nest within a module. This winds up also allowing modules to nest, which is legal but presumably less used feature.
2012-05-10 04:35:11 +02:00
return (lexical_scope == pform_cur_module.front())
Rework of lexical scope handling in parser. This patch modifies the parser to use a single stack to track lexical scopes, rather than starting a new stack for each generate construct.
2010-01-08 23:49:48 +01:00
|| (lexical_scope == pform_cur_generate);
Rework of automatic task/function support. This patch splits any VVP net functor that needs to access both statically and automatically allocated state into two sub-classes, one for handling operations on statically allocated state, the other for handling operations on automatically allocated state. This undoes the increase in run-time memory use introduced when automatic task/function support was first introduced. This patch also fixes various issues with event handling in automatic scopes. Event expressions in automatic scopes may now reference either statically or automatically allocated variables or arrays, or part selects or word selects thereof. More complex expressions (e.g. containing arithmetic or logical operators, function calls, etc.) are not currently supported. This patch introduces some error checking for language constructs that may not reference automatically allocated variables. Further error checking will follow in a subsequent patch.
2008-10-28 18:52:39 +01:00
}
Attach disciplines to wires Allow discipline declaration of nets that attaches the discipline to a new wire or a wire that is already declared.
2008-05-12 02:30:33 +02:00
PWire*pform_get_wire_in_scope(perm_string name)
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
{
Rework of lexical scope handling in parser. This patch modifies the parser to use a single stack to track lexical scopes, rather than starting a new stack for each generate construct.
2010-01-08 23:49:48 +01:00
return lexical_scope->wires_find(name);
Better handle nesting of scopes inside generate blocks. Within generate schemes it is possible to have nested scopes, even more liberally then outside generate blocks. So see to it that the scopes properly stack with the generate blocks, and that wires and behaviors are put in the right scopes.
2008-06-20 06:31:53 +02:00
}
static void pform_put_wire_in_scope(perm_string name, PWire*net)
{
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
add_local_symbol(lexical_scope, name, net);
Rework of lexical scope handling in parser. This patch modifies the parser to use a single stack to track lexical scopes, rather than starting a new stack for each generate construct.
2010-01-08 23:49:48 +01:00
lexical_scope->wires[name] = net;
Better handle nesting of scopes inside generate blocks. Within generate schemes it is possible to have nested scopes, even more liberally then outside generate blocks. So see to it that the scopes properly stack with the generate blocks, and that wires and behaviors are put in the right scopes.
2008-06-20 06:31:53 +02:00
}
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
Get the netenum_t base type data from the pform. The pform propagates the parsed enum base type information to the elaborator so that the base type can be fully elaborated. This is necessary to get the types of the enumeration literals correct.
2010-11-04 04:11:19 +01:00
static void pform_put_enum_type_in_scope(enum_type_t*enum_set)
Enum names in r-value expressions When enum names are used as r-values in expressions, use their values. Treat the enum names similar to (but not exactly as) localparams so that they fit into the rest of the elaboration flow naturally.
2010-10-31 19:26:09 +01:00
{
Support separate compilation units in SystemVerilog. The compilation unit scope is now treated as a specialised form of package (with an automatically generated name). All items declared outside a design element are added to the current compilation unit package. Apart from when searching for a symbol, once we get into elaboration we can treat these just like any other package.
2017-10-21 16:04:25 +02:00
lexical_scope->enum_sets.insert(enum_set);
Enum names in r-value expressions When enum names are used as r-values in expressions, use their values. Treat the enum names similar to (but not exactly as) localparams so that they fit into the rest of the elaboration flow naturally.
2010-10-31 19:26:09 +01:00
}
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
PWire*pform_get_make_wire_in_scope(const struct vlltype&, perm_string name,
Output an error message when a SV variable declaration reuses a name. Assertion failures are not the right way to handle user code errors.
2018-02-18 18:51:56 +01:00
NetNet::Type net_type, NetNet::PortType port_type,
ivl_variable_type_t vt_type)
Enum names in r-value expressions When enum names are used as r-values in expressions, use their values. Treat the enum names similar to (but not exactly as) localparams so that they fit into the rest of the elaboration flow naturally.
2010-10-31 19:26:09 +01:00
{
PWire*cur = pform_get_wire_in_scope(name);
Output an error message when a SV variable declaration reuses a name. Assertion failures are not the right way to handle user code errors.
2018-02-18 18:51:56 +01:00
// If the wire already exists and is fully defined, this
// must be a redeclaration. Start again with a new wire.
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
// The error will be reported when we add the new wire
// to the scope. Do not delete the old wire - it will
// remain in the local symbol map.
if (cur && cur->get_data_type() != IVL_VT_NO_TYPE)
Output an error message when a SV variable declaration reuses a name. Assertion failures are not the right way to handle user code errors.
2018-02-18 18:51:56 +01:00
cur = 0;
Enum names in r-value expressions When enum names are used as r-values in expressions, use their values. Treat the enum names similar to (but not exactly as) localparams so that they fit into the rest of the elaboration flow naturally.
2010-10-31 19:26:09 +01:00
if (cur == 0) {
cur = new PWire(name, net_type, port_type, vt_type);
pform_put_wire_in_scope(name, cur);
} else {
bool rc = cur->set_wire_type(net_type);
assert(rc);
rc = cur->set_data_type(vt_type);
assert(rc);
}
return cur;
}
ivl: Typedefs may use unpacked arrays.
2014-12-15 11:25:35 +01:00
void pform_set_typedef(perm_string name, data_type_t*data_type, std::list<pform_range_t>*unp_ranges)
Implement simple typedefs, and parse type identifiers. This gets me to the point where the parser stashes a defined type, and the lexical analyzer uses the type names to differentiate IDENTIFIER and TYPE_IDENTIFIER.
2012-01-09 02:51:18 +01:00
{
ivl: Typedefs may use unpacked arrays.
2014-12-15 11:25:35 +01:00
if(unp_ranges)
data_type = new uarray_type_t(data_type, unp_ranges);
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
add_local_symbol(lexical_scope, name, data_type);
Support separate compilation units in SystemVerilog. The compilation unit scope is now treated as a specialised form of package (with an automatically generated name). All items declared outside a design element are added to the current compilation unit package. Apart from when searching for a symbol, once we get into elaboration we can treat these just like any other package.
2017-10-21 16:04:25 +02:00
data_type_t*&ref = lexical_scope->typedefs[name];
Handle typedefs in $root scope.
2013-12-15 05:07:31 +01:00
Implement simple typedefs, and parse type identifiers. This gets me to the point where the parser stashes a defined type, and the lexical analyzer uses the type names to differentiate IDENTIFIER and TYPE_IDENTIFIER.
2012-01-09 02:51:18 +01:00
ivl_assert(*data_type, ref == 0);
ref = data_type;
Handle enumerations as packed struct/union members. There were also some subtleties related to using enumerations from typedefs and using them in multiple places. Fix various bugs related to those issues.
2013-12-05 00:25:14 +01:00
if (enum_type_t*enum_type = dynamic_cast<enum_type_t*>(data_type)) {
pform_put_enum_type_in_scope(enum_type);
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
list<named_pexpr_t>::const_iterator cur;
for (cur = enum_type->names->begin(); cur != enum_type->names->end(); ++cur)
add_local_symbol(lexical_scope, cur->name, enum_type);
Handle enumerations as packed struct/union members. There were also some subtleties related to using enumerations from typedefs and using them in multiple places. Fix various bugs related to those issues.
2013-12-05 00:25:14 +01:00
}
Implement simple typedefs, and parse type identifiers. This gets me to the point where the parser stashes a defined type, and the lexical analyzer uses the type names to differentiate IDENTIFIER and TYPE_IDENTIFIER.
2012-01-09 02:51:18 +01:00
}
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
data_type_t* pform_test_type_identifier(const struct vlltype&loc, const char*txt)
Handle typedefs in $root scope.
2013-12-15 05:07:31 +01:00
{
Implement simple typedefs, and parse type identifiers. This gets me to the point where the parser stashes a defined type, and the lexical analyzer uses the type names to differentiate IDENTIFIER and TYPE_IDENTIFIER.
2012-01-09 02:51:18 +01:00
perm_string name = lex_strings.make(txt);
Parse more package items Rework lexical support for PACKAGE_IDENTIFIER so that the lexor can help with package scoped identifiers. Pform package types and package functions up to elaboration.
2013-04-01 00:46:36 +02:00
Miscellaneous SystemVerilog syntax. ... and sorry messages.
2012-03-05 04:33:16 +01:00
LexicalScope*cur_scope = lexical_scope;
do {
Parse more package items Rework lexical support for PACKAGE_IDENTIFIER so that the lexor can help with package scoped identifiers. Pform package types and package functions up to elaboration.
2013-04-01 00:46:36 +02:00
map<perm_string,data_type_t*>::iterator cur;
// First look to see if this identifier is imported from
// a package. If it is, see if it is a type in that
// package. If it is, then great. If imported as
Spelling fixes Mostly comments. One user-visible string ("Evalutated to ") changed in the debug_eval_tree case.
2014-01-29 00:50:27 +01:00
// something other than a type, then give up now because
Parse more package items Rework lexical support for PACKAGE_IDENTIFIER so that the lexor can help with package scoped identifiers. Pform package types and package functions up to elaboration.
2013-04-01 00:46:36 +02:00
// the name has at least shadowed any other possible
// meaning for this name.
map<perm_string,PPackage*>::iterator cur_pkg;
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
cur_pkg = cur_scope->explicit_imports.find(name);
if (cur_pkg != cur_scope->explicit_imports.end()) {
Parse more package items Rework lexical support for PACKAGE_IDENTIFIER so that the lexor can help with package scoped identifiers. Pform package types and package functions up to elaboration.
2013-04-01 00:46:36 +02:00
PPackage*pkg = cur_pkg->second;
cur = pkg->typedefs.find(name);
if (cur != pkg->typedefs.end())
return cur->second;
// Not a type. Give up.
return 0;
}
Miscellaneous SystemVerilog syntax. ... and sorry messages.
2012-03-05 04:33:16 +01:00
cur = cur_scope->typedefs.find(name);
if (cur != cur_scope->typedefs.end())
return cur->second;
Fix space errors in various files
2012-08-16 20:06:20 +02:00
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
PPackage*pkg = find_potential_import(loc, cur_scope, name, PNamedItem::TYPE);
if (pkg) {
cur = pkg->typedefs.find(name);
if (cur != cur_scope->typedefs.end())
return cur->second;
}
Miscellaneous SystemVerilog syntax. ... and sorry messages.
2012-03-05 04:33:16 +01:00
cur_scope = cur_scope->parent_scope();
} while (cur_scope);
Parse more package items Rework lexical support for PACKAGE_IDENTIFIER so that the lexor can help with package scoped identifiers. Pform package types and package functions up to elaboration.
2013-04-01 00:46:36 +02:00
Miscellaneous SystemVerilog syntax. ... and sorry messages.
2012-03-05 04:33:16 +01:00
return 0;
Implement simple typedefs, and parse type identifiers. This gets me to the point where the parser stashes a defined type, and the lexical analyzer uses the type names to differentiate IDENTIFIER and TYPE_IDENTIFIER.
2012-01-09 02:51:18 +01:00
}
Allow typedefs to override inherited type names.
2014-02-22 05:48:34 +01:00
/*
* The parser uses this function to test if the name is a typedef in
* the current scope. We use this to know if we can override the
* definition because it shadows a containing scope.
*/
bool pform_test_type_identifier_local(perm_string name)
{
LexicalScope*cur_scope = lexical_scope;
map<perm_string,data_type_t*>::iterator cur;
cur = cur_scope->typedefs.find(name);
if (cur != cur_scope->typedefs.end())
return true;
return false;
}
Parse more package items Rework lexical support for PACKAGE_IDENTIFIER so that the lexor can help with package scoped identifiers. Pform package types and package functions up to elaboration.
2013-04-01 00:46:36 +02:00
PECallFunction* pform_make_call_function(const struct vlltype&loc,
const pform_name_t&name,
const list<PExpr*>&parms)
{
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
if (gn_system_verilog() && name.size() == 1)
check_potential_imports(loc, name.back().name);
Remove redundant checks for package imports during parsing. The find_* and symbol_search functions now handle this.
2019-09-22 10:16:10 +02:00
PECallFunction*tmp = new PECallFunction(name, parms);
Parse more package items Rework lexical support for PACKAGE_IDENTIFIER so that the lexor can help with package scoped identifiers. Pform package types and package functions up to elaboration.
2013-04-01 00:46:36 +02:00
FILE_NAME(tmp, loc);
return tmp;
}
Handle tasks in packages.
2013-04-09 03:12:54 +02:00
PCallTask* pform_make_call_task(const struct vlltype&loc,
const pform_name_t&name,
const list<PExpr*>&parms)
{
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
if (gn_system_verilog() && name.size() == 1)
check_potential_imports(loc, name.back().name);
Remove redundant checks for package imports during parsing. The find_* and symbol_search functions now handle this.
2019-09-22 10:16:10 +02:00
PCallTask*tmp = new PCallTask(name, parms);
Handle tasks in packages.
2013-04-09 03:12:54 +02:00
FILE_NAME(tmp, loc);
return tmp;
}
Elaborate foreach loops as synthetic for loops. Create an implicit scope to hold the index variable, and generate a for loop to perform the functionality of the foreach.
2014-08-22 00:47:46 +02:00
void pform_make_foreach_declarations(const struct vlltype&loc,
std::list<perm_string>*loop_vars)
{
static const struct str_pair_t str = { IVL_DR_STRONG, IVL_DR_STRONG };
list<decl_assignment_t*>assign_list;
for (list<perm_string>::const_iterator cur = loop_vars->begin()
; cur != loop_vars->end() ; ++ cur) {
decl_assignment_t*tmp_assign = new decl_assignment_t;
tmp_assign->name = lex_strings.make(*cur);
assign_list.push_back(tmp_assign);
}
pform_makewire(loc, 0, str, &assign_list, NetNet::REG, &size_type);
}
PForeach* pform_make_foreach(const struct vlltype&loc,
char*name,
list<perm_string>*loop_vars,
Statement*stmt)
{
perm_string use_name = lex_strings.make(name);
delete[]name;
foreach multiple indices through the pform.
2014-08-25 23:58:57 +02:00
if (loop_vars==0 || loop_vars->empty()) {
cerr << loc.get_fileline() << ": error: "
<< "No loop variables at all in foreach index." << endl;
Sorry message for multi-dimension foreach loop indices.
2014-08-22 05:34:55 +02:00
error_count += 1;
}
Elaborate foreach loops as synthetic for loops. Create an implicit scope to hold the index variable, and generate a for loop to perform the functionality of the foreach.
2014-08-22 00:47:46 +02:00
foreach multiple indices through the pform.
2014-08-25 23:58:57 +02:00
ivl_assert(loc, loop_vars);
PForeach*fe = new PForeach(use_name, *loop_vars, stmt);
Elaborate foreach loops as synthetic for loops. Create an implicit scope to hold the index variable, and generate a for loop to perform the functionality of the foreach.
2014-08-22 00:47:46 +02:00
FILE_NAME(fe, loc);
foreach multiple indices through the pform.
2014-08-25 23:58:57 +02:00
delete loop_vars;
Elaborate foreach loops as synthetic for loops. Create an implicit scope to hold the index variable, and generate a for loop to perform the functionality of the foreach.
2014-08-22 00:47:46 +02:00
return fe;
}
Better handle nesting of scopes inside generate blocks. Within generate schemes it is possible to have nested scopes, even more liberally then outside generate blocks. So see to it that the scopes properly stack with the generate blocks, and that wires and behaviors are put in the right scopes.
2008-06-20 06:31:53 +02:00
static void pform_put_behavior_in_scope(PProcess*pp)
{
Rework of lexical scope handling in parser. This patch modifies the parser to use a single stack to track lexical scopes, rather than starting a new stack for each generate construct.
2010-01-08 23:49:48 +01:00
lexical_scope->behaviors.push_back(pp);
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
}
Infrastructure for parsing analog process statements. Organize the parsing infrastructure for parsing analog processes, including holding them in scopes, and collecting analog statements.
2008-07-27 21:02:09 +02:00
void pform_put_behavior_in_scope(AProcess*pp)
{
Rework of lexical scope handling in parser. This patch modifies the parser to use a single stack to track lexical scopes, rather than starting a new stack for each generate construct.
2010-01-08 23:49:48 +01:00
lexical_scope->analog_behaviors.push_back(pp);
Infrastructure for parsing analog process statements. Organize the parsing infrastructure for parsing analog processes, including holding them in scopes, and collecting analog statements.
2008-07-27 21:02:09 +02:00
}
Add support for the default_nettype directive.
2004-06-13 06:56:53 +02:00
void pform_set_default_nettype(NetNet::Type type,
const char*file, unsigned lineno)
{
pform_default_nettype = type;
Fix some cppcheck warnings in the main directory
2012-08-08 20:26:46 +02:00
if (! pform_cur_module.empty()) {
Add support for the default_nettype directive.
2004-06-13 06:56:53 +02:00
cerr << file<<":"<<lineno << ": error: "
<< "`default_nettype directives must appear" << endl;
cerr << file<<":"<<lineno << ": : "
<< "outside module definitions. The containing" << endl;
cerr << file<<":"<<lineno << ": : "
Allow modules (and program blocks in particular) to nest. An important advantage of program blocks is its ability to nest within a module. This winds up also allowing modules to nest, which is legal but presumably less used feature.
2012-05-10 04:35:11 +02:00
<< "module " << pform_cur_module.back()->mod_name()
Add support for the default_nettype directive.
2004-06-13 06:56:53 +02:00
<< " starts on line "
Allow modules (and program blocks in particular) to nest. An important advantage of program blocks is its ability to nest within a module. This winds up also allowing modules to nest, which is legal but presumably less used feature.
2012-05-10 04:35:11 +02:00
<< pform_cur_module.back()->get_fileline() << "." << endl;
Add support for the default_nettype directive.
2004-06-13 06:56:53 +02:00
error_count += 1;
}
}
Fix for pr2924354. Creation of implicit nets requires knowledge of whether an identifier has been declared before it is used. Currently implicit nets are created during elaboration, but by this stage the order of declaration and use is not known. This patch moves the creation of implicit nets into the parser stage.
2010-01-12 21:11:01 +01:00
static void pform_declare_implicit_nets(PExpr*expr)
{
/* If implicit net creation is turned off, then stop now. */
if (pform_default_nettype == NetNet::NONE)
return;
if (expr)
expr->declare_implicit_nets(lexical_scope, pform_default_nettype);
}
Timescale warnings.
2002-04-15 02:04:22 +02:00
/*
* The lexor calls this function to set the active timescale when it
* detects a `timescale directive. The function saves the directive
Rework handling of timescales in parser. This implements and enforces the full set of rules for determining timescales in SystemVerilog. The previous relaxation of the rules that allowed timescales to be redefined within the compilation unit scope has been removed. Time unit and precision redeclarations are now recognised after a nested module declaration.
2017-11-05 18:50:05 +01:00
* values (for use by subsequent design elements) and if warnings are
* enabled checks to see if some design elements have no timescale.
Timescale warnings.
2002-04-15 02:04:22 +02:00
*/
void pform_set_timescale(int unit, int prec,
const char*file, unsigned lineno)
Parser and pform use hierarchical names as hname_t objects instead of encoded strings.
2001-12-03 05:47:14 +01:00
{
assert(unit >= prec);
pform_time_unit = unit;
pform_time_prec = prec;
Timescale warnings.
2002-04-15 02:04:22 +02:00
Fix first_file test for timescale warning.
2002-04-18 20:38:37 +02:00
if (pform_timescale_file) {
Timescale warnings.
2002-04-15 02:04:22 +02:00
free(pform_timescale_file);
Fix first_file test for timescale warning.
2002-04-18 20:38:37 +02:00
}
Timescale warnings.
2002-04-15 02:04:22 +02:00
Add support for `resetall and other directive changes. This patch adds support for the `resetall directive. It also changes `celldefine, `endcelldefine and `resetall to no longer grab text following them. These directives do not take an argument so they should not be grabbing any text and silently discarding it. The `timescale processing was reworked to handle being reset and hooks were added to easily change the default time units and precision when we add that feature request.
2009-05-22 20:03:36 +02:00
if (file) pform_timescale_file = strdup(file);
else pform_timescale_file = 0;
Timescale warnings.
2002-04-15 02:04:22 +02:00
pform_timescale_line = lineno;
Parser and pform use hierarchical names as hname_t objects instead of encoded strings.
2001-12-03 05:47:14 +01:00
}
Add support for SystemVerilog style time literals SystemVerilog has support for time literals. The time literal for example #10ns, adds a delay of 10ns no matter the time unit currently in effect. For more details please refer to http://iverilog.wikia.com/wiki/Projects#SystemVerilog_Style_Time_Literals Tested-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com> Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
2011-07-05 19:11:56 +02:00
bool get_time_unit(const char*cp, int &unit)
{
const char *c;
bool rc = true;
if (strchr(cp, '_')) {
VLerror(yylloc, "Invalid timeunit constant ('_' is not "
"supported).");
return false;
}
c = strpbrk(cp, "munpfs");
if (!c)
return false;
if (*c == 's')
unit = 0;
else if (!strncmp(c, "ms", 2))
unit = -3;
else if (!strncmp(c, "us", 2))
unit = -6;
else if (!strncmp(c, "ns", 2))
unit = -9;
else if (!strncmp(c, "ps", 2))
unit = -12;
else if (!strncmp(c, "fs", 2))
unit = -15;
else {
rc = false;
ostringstream msg;
msg << "Invalid timeunit scale '" << cp << "'.";
VLerror(msg.str().c_str());
}
return rc;
}
Fix up original SV timeunit/timeprecision patch. This patch modifies the original SystemVerilog timeunit/timeprecision patch in the following way: Removed trailing space. Reworked some code to use standard spacing rules. Added some comments. Combined some code. Major rework of local/global timeunit/timeprecision logic. Major rework of timeunit/timeprecision declaration/check code. This was needed to remove the shift/reduce warnings. Add a number of checks for invalid combinations.
2009-07-11 03:19:59 +02:00
/*
* Get a timeunit or timeprecision value from a string. This is
* similar to the code in lexor.lex for the `timescale directive.
*/
static bool get_time_unit_prec(const char*cp, int &res, bool is_unit)
System Verilog timeunit and timeprecision addition This patch adds timeunit and timeprecision keywords.Use -gsystem-verilog generation flag to use this feature
2009-06-20 05:58:46 +02:00
{
Fix up original SV timeunit/timeprecision patch. This patch modifies the original SystemVerilog timeunit/timeprecision patch in the following way: Removed trailing space. Reworked some code to use standard spacing rules. Added some comments. Combined some code. Major rework of local/global timeunit/timeprecision logic. Major rework of timeunit/timeprecision declaration/check code. This was needed to remove the shift/reduce warnings. Add a number of checks for invalid combinations.
2009-07-11 03:19:59 +02:00
/* We do not support a '_' in these time constants. */
if (strchr(cp, '_')) {
if (is_unit) {
VLerror(yylloc, "Invalid timeunit constant ('_' is not "
"supported).");
} else {
VLerror(yylloc, "Invalid timeprecision constant ('_' is not "
"supported).");
}
return true;
System Verilog timeunit and timeprecision addition This patch adds timeunit and timeprecision keywords.Use -gsystem-verilog generation flag to use this feature
2009-06-20 05:58:46 +02:00
}
Fix up original SV timeunit/timeprecision patch. This patch modifies the original SystemVerilog timeunit/timeprecision patch in the following way: Removed trailing space. Reworked some code to use standard spacing rules. Added some comments. Combined some code. Major rework of local/global timeunit/timeprecision logic. Major rework of timeunit/timeprecision declaration/check code. This was needed to remove the shift/reduce warnings. Add a number of checks for invalid combinations.
2009-07-11 03:19:59 +02:00
/* Check for the 1 digit. */
if (*cp != '1') {
if (is_unit) {
VLerror(yylloc, "Invalid timeunit constant (1st digit).");
} else {
VLerror(yylloc, "Invalid timeprecision constant (1st digit).");
}
return true;
System Verilog timeunit and timeprecision addition This patch adds timeunit and timeprecision keywords.Use -gsystem-verilog generation flag to use this feature
2009-06-20 05:58:46 +02:00
}
Fix up original SV timeunit/timeprecision patch. This patch modifies the original SystemVerilog timeunit/timeprecision patch in the following way: Removed trailing space. Reworked some code to use standard spacing rules. Added some comments. Combined some code. Major rework of local/global timeunit/timeprecision logic. Major rework of timeunit/timeprecision declaration/check code. This was needed to remove the shift/reduce warnings. Add a number of checks for invalid combinations.
2009-07-11 03:19:59 +02:00
cp += 1;
/* Check the number of zeros after the 1. */
res = strspn(cp, "0");
if (res > 2) {
if (is_unit) {
VLerror(yylloc, "Invalid timeunit constant (number of "
"zeros).");
} else {
VLerror(yylloc, "Invalid timeprecision constant (number of "
"zeros).");
}
return true;
System Verilog timeunit and timeprecision addition This patch adds timeunit and timeprecision keywords.Use -gsystem-verilog generation flag to use this feature
2009-06-20 05:58:46 +02:00
}
Fix up original SV timeunit/timeprecision patch. This patch modifies the original SystemVerilog timeunit/timeprecision patch in the following way: Removed trailing space. Reworked some code to use standard spacing rules. Added some comments. Combined some code. Major rework of local/global timeunit/timeprecision logic. Major rework of timeunit/timeprecision declaration/check code. This was needed to remove the shift/reduce warnings. Add a number of checks for invalid combinations.
2009-07-11 03:19:59 +02:00
cp += res;
System Verilog timeunit and timeprecision addition This patch adds timeunit and timeprecision keywords.Use -gsystem-verilog generation flag to use this feature
2009-06-20 05:58:46 +02:00
Fix up original SV timeunit/timeprecision patch. This patch modifies the original SystemVerilog timeunit/timeprecision patch in the following way: Removed trailing space. Reworked some code to use standard spacing rules. Added some comments. Combined some code. Major rework of local/global timeunit/timeprecision logic. Major rework of timeunit/timeprecision declaration/check code. This was needed to remove the shift/reduce warnings. Add a number of checks for invalid combinations.
2009-07-11 03:19:59 +02:00
/* Now process the scaling string. */
if (strncmp("s", cp, 1) == 0) {
res -= 0;
return false;
System Verilog timeunit and timeprecision addition This patch adds timeunit and timeprecision keywords.Use -gsystem-verilog generation flag to use this feature
2009-06-20 05:58:46 +02:00
Fix up original SV timeunit/timeprecision patch. This patch modifies the original SystemVerilog timeunit/timeprecision patch in the following way: Removed trailing space. Reworked some code to use standard spacing rules. Added some comments. Combined some code. Major rework of local/global timeunit/timeprecision logic. Major rework of timeunit/timeprecision declaration/check code. This was needed to remove the shift/reduce warnings. Add a number of checks for invalid combinations.
2009-07-11 03:19:59 +02:00
} else if (strncmp("ms", cp, 2) == 0) {
res -= 3;
return false;
System Verilog timeunit and timeprecision addition This patch adds timeunit and timeprecision keywords.Use -gsystem-verilog generation flag to use this feature
2009-06-20 05:58:46 +02:00
Fix up original SV timeunit/timeprecision patch. This patch modifies the original SystemVerilog timeunit/timeprecision patch in the following way: Removed trailing space. Reworked some code to use standard spacing rules. Added some comments. Combined some code. Major rework of local/global timeunit/timeprecision logic. Major rework of timeunit/timeprecision declaration/check code. This was needed to remove the shift/reduce warnings. Add a number of checks for invalid combinations.
2009-07-11 03:19:59 +02:00
} else if (strncmp("us", cp, 2) == 0) {
res -= 6;
return false;
System Verilog timeunit and timeprecision addition This patch adds timeunit and timeprecision keywords.Use -gsystem-verilog generation flag to use this feature
2009-06-20 05:58:46 +02:00
Fix up original SV timeunit/timeprecision patch. This patch modifies the original SystemVerilog timeunit/timeprecision patch in the following way: Removed trailing space. Reworked some code to use standard spacing rules. Added some comments. Combined some code. Major rework of local/global timeunit/timeprecision logic. Major rework of timeunit/timeprecision declaration/check code. This was needed to remove the shift/reduce warnings. Add a number of checks for invalid combinations.
2009-07-11 03:19:59 +02:00
} else if (strncmp("ns", cp, 2) == 0) {
res -= 9;
return false;
System Verilog timeunit and timeprecision addition This patch adds timeunit and timeprecision keywords.Use -gsystem-verilog generation flag to use this feature
2009-06-20 05:58:46 +02:00
Fix up original SV timeunit/timeprecision patch. This patch modifies the original SystemVerilog timeunit/timeprecision patch in the following way: Removed trailing space. Reworked some code to use standard spacing rules. Added some comments. Combined some code. Major rework of local/global timeunit/timeprecision logic. Major rework of timeunit/timeprecision declaration/check code. This was needed to remove the shift/reduce warnings. Add a number of checks for invalid combinations.
2009-07-11 03:19:59 +02:00
} else if (strncmp("ps", cp, 2) == 0) {
res -= 12;
return false;
System Verilog timeunit and timeprecision addition This patch adds timeunit and timeprecision keywords.Use -gsystem-verilog generation flag to use this feature
2009-06-20 05:58:46 +02:00
Fix up original SV timeunit/timeprecision patch. This patch modifies the original SystemVerilog timeunit/timeprecision patch in the following way: Removed trailing space. Reworked some code to use standard spacing rules. Added some comments. Combined some code. Major rework of local/global timeunit/timeprecision logic. Major rework of timeunit/timeprecision declaration/check code. This was needed to remove the shift/reduce warnings. Add a number of checks for invalid combinations.
2009-07-11 03:19:59 +02:00
} else if (strncmp("fs", cp, 2) == 0) {
res -= 15;
return false;
System Verilog timeunit and timeprecision addition This patch adds timeunit and timeprecision keywords.Use -gsystem-verilog generation flag to use this feature
2009-06-20 05:58:46 +02:00
}
Fix up original SV timeunit/timeprecision patch. This patch modifies the original SystemVerilog timeunit/timeprecision patch in the following way: Removed trailing space. Reworked some code to use standard spacing rules. Added some comments. Combined some code. Major rework of local/global timeunit/timeprecision logic. Major rework of timeunit/timeprecision declaration/check code. This was needed to remove the shift/reduce warnings. Add a number of checks for invalid combinations.
2009-07-11 03:19:59 +02:00
ostringstream msg;
msg << "Invalid ";
if (is_unit) msg << "timeunit";
else msg << "timeprecision";
msg << " scale '" << cp << "'.";
VLerror(msg.str().c_str());
return true;
System Verilog timeunit and timeprecision addition This patch adds timeunit and timeprecision keywords.Use -gsystem-verilog generation flag to use this feature
2009-06-20 05:58:46 +02:00
}
Fix a couple of minor bugs in the timescale parsing rework.
2017-11-06 01:37:56 +01:00
void pform_set_timeunit(const char*txt, bool initial_decl)
System Verilog timeunit and timeprecision addition This patch adds timeunit and timeprecision keywords.Use -gsystem-verilog generation flag to use this feature
2009-06-20 05:58:46 +02:00
{
Fix up original SV timeunit/timeprecision patch. This patch modifies the original SystemVerilog timeunit/timeprecision patch in the following way: Removed trailing space. Reworked some code to use standard spacing rules. Added some comments. Combined some code. Major rework of local/global timeunit/timeprecision logic. Major rework of timeunit/timeprecision declaration/check code. This was needed to remove the shift/reduce warnings. Add a number of checks for invalid combinations.
2009-07-11 03:19:59 +02:00
int val;
if (get_time_unit_prec(txt, val, true)) return;
Rework handling of timescales in parser. This implements and enforces the full set of rules for determining timescales in SystemVerilog. The previous relaxation of the rules that allowed timescales to be redefined within the compilation unit scope has been removed. Time unit and precision redeclarations are now recognised after a nested module declaration.
2017-11-05 18:50:05 +01:00
PScopeExtra*scope = dynamic_cast<PScopeExtra*>(lexical_scope);
assert(scope);
Fix a couple of minor bugs in the timescale parsing rework.
2017-11-06 01:37:56 +01:00
if (initial_decl) {
Rework handling of timescales in parser. This implements and enforces the full set of rules for determining timescales in SystemVerilog. The previous relaxation of the rules that allowed timescales to be redefined within the compilation unit scope has been removed. Time unit and precision redeclarations are now recognised after a nested module declaration.
2017-11-05 18:50:05 +01:00
scope->time_unit = val;
scope->time_unit_is_local = true;
scope->time_unit_is_default = false;
allow_timeunit_decl = false;
} else if (!scope->time_unit_is_local) {
VLerror(yylloc, "error: repeat timeunit found and the initial "
"timeunit for this scope is missing.");
} else if (scope->time_unit != val) {
VLerror(yylloc, "error: repeat timeunit does not match the "
"initial timeunit for this scope.");
System Verilog timeunit and timeprecision addition This patch adds timeunit and timeprecision keywords.Use -gsystem-verilog generation flag to use this feature
2009-06-20 05:58:46 +02:00
}
Fix up original SV timeunit/timeprecision patch. This patch modifies the original SystemVerilog timeunit/timeprecision patch in the following way: Removed trailing space. Reworked some code to use standard spacing rules. Added some comments. Combined some code. Major rework of local/global timeunit/timeprecision logic. Major rework of timeunit/timeprecision declaration/check code. This was needed to remove the shift/reduce warnings. Add a number of checks for invalid combinations.
2009-07-11 03:19:59 +02:00
}
System Verilog timeunit and timeprecision addition This patch adds timeunit and timeprecision keywords.Use -gsystem-verilog generation flag to use this feature
2009-06-20 05:58:46 +02:00
Add support for SystemVerilog style time literals SystemVerilog has support for time literals. The time literal for example #10ns, adds a delay of 10ns no matter the time unit currently in effect. For more details please refer to http://iverilog.wikia.com/wiki/Projects#SystemVerilog_Style_Time_Literals Tested-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com> Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
2011-07-05 19:11:56 +02:00
int pform_get_timeunit()
{
Rework handling of timescales in parser. This implements and enforces the full set of rules for determining timescales in SystemVerilog. The previous relaxation of the rules that allowed timescales to be redefined within the compilation unit scope has been removed. Time unit and precision redeclarations are now recognised after a nested module declaration.
2017-11-05 18:50:05 +01:00
PScopeExtra*scopex = find_nearest_scopex(lexical_scope);
assert(scopex);
return scopex->time_unit;
Add support for SystemVerilog style time literals SystemVerilog has support for time literals. The time literal for example #10ns, adds a delay of 10ns no matter the time unit currently in effect. For more details please refer to http://iverilog.wikia.com/wiki/Projects#SystemVerilog_Style_Time_Literals Tested-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com> Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
2011-07-05 19:11:56 +02:00
}
Fix a couple of minor bugs in the timescale parsing rework.
2017-11-06 01:37:56 +01:00
void pform_set_timeprec(const char*txt, bool initial_decl)
Fix up original SV timeunit/timeprecision patch. This patch modifies the original SystemVerilog timeunit/timeprecision patch in the following way: Removed trailing space. Reworked some code to use standard spacing rules. Added some comments. Combined some code. Major rework of local/global timeunit/timeprecision logic. Major rework of timeunit/timeprecision declaration/check code. This was needed to remove the shift/reduce warnings. Add a number of checks for invalid combinations.
2009-07-11 03:19:59 +02:00
{
int val;
if (get_time_unit_prec(txt, val, false)) return;
Rework handling of timescales in parser. This implements and enforces the full set of rules for determining timescales in SystemVerilog. The previous relaxation of the rules that allowed timescales to be redefined within the compilation unit scope has been removed. Time unit and precision redeclarations are now recognised after a nested module declaration.
2017-11-05 18:50:05 +01:00
PScopeExtra*scope = dynamic_cast<PScopeExtra*>(lexical_scope);
assert(scope);
Fix a couple of minor bugs in the timescale parsing rework.
2017-11-06 01:37:56 +01:00
if (initial_decl) {
Rework handling of timescales in parser. This implements and enforces the full set of rules for determining timescales in SystemVerilog. The previous relaxation of the rules that allowed timescales to be redefined within the compilation unit scope has been removed. Time unit and precision redeclarations are now recognised after a nested module declaration.
2017-11-05 18:50:05 +01:00
scope->time_precision = val;
scope->time_prec_is_local = true;
scope->time_prec_is_default = false;
allow_timeprec_decl = false;
} else if (!scope->time_prec_is_local) {
VLerror(yylloc, "error: repeat timeprecision found and the initial "
"timeprecision for this scope is missing.");
} else if (scope->time_precision != val) {
VLerror(yylloc, "error: repeat timeprecision does not match the "
"initial timeprecision for this scope.");
System Verilog timeunit and timeprecision addition This patch adds timeunit and timeprecision keywords.Use -gsystem-verilog generation flag to use this feature
2009-06-20 05:58:46 +02:00
}
}
Parser and pform use hierarchical names as hname_t objects instead of encoded strings.
2001-12-03 05:47:14 +01:00
Break sized constants into a size token and a based numeric constant.
2003-04-14 05:37:47 +02:00
verinum* pform_verinum_with_size(verinum*siz, verinum*val,
const char*file, unsigned lineno)
{
assert(siz->is_defined());
unsigned long size = siz->as_ulong();
Fix for GitHub issue #60 (part 1) - reject numeric constant with zero size.
2015-04-26 12:04:02 +02:00
if (size == 0) {
cerr << file << ":" << lineno << ": error: Sized numeric constant "
"must have a size greater than zero." << endl;
error_count += 1;
}
Break sized constants into a size token and a based numeric constant.
2003-04-14 05:37:47 +02:00
verinum::V pad;
Handle numeric literals with no digits.
2015-09-23 01:15:41 +02:00
if (val->len() == 0) {
Break sized constants into a size token and a based numeric constant.
2003-04-14 05:37:47 +02:00
pad = verinum::Vx;
Handle numeric literals with no digits.
2015-09-23 01:15:41 +02:00
} else {
switch (val->get(val->len()-1)) {
case verinum::Vz:
pad = verinum::Vz;
break;
case verinum::Vx:
pad = verinum::Vx;
break;
default:
pad = verinum::V0;
break;
}
Break sized constants into a size token and a based numeric constant.
2003-04-14 05:37:47 +02:00
}
Fix padding of x when literal is sized and unsigned.
2007-01-27 06:36:11 +01:00
verinum*res = new verinum(pad, size, true);
Break sized constants into a size token and a based numeric constant.
2003-04-14 05:37:47 +02:00
unsigned copy = val->len();
if (res->len() < copy)
copy = res->len();
for (unsigned idx = 0 ; idx < copy ; idx += 1) {
res->set(idx, val->get(idx));
}
res->has_sign(val->has_sign());
bool trunc_flag = false;
for (unsigned idx = copy ; idx < val->len() ; idx += 1) {
if (val->get(idx) != pad) {
trunc_flag = true;
break;
}
}
if (trunc_flag) {
cerr << file << ":" << lineno << ": warning: Numeric constant "
<< "truncated to " << copy << " bits." << endl;
}
delete siz;
delete val;
return res;
}
Basic support for program blocks.
2012-05-01 06:12:59 +02:00
void pform_startmodule(const struct vlltype&loc, const char*name,
Added support for interface declaration and instantiation. modport and extern tf declarations are not yet supported.
2014-12-20 00:10:14 +01:00
bool program_block, bool is_interface,
Added support for default subroutine lifetimes (SystemVerilog).
2016-03-19 18:27:27 +01:00
LexicalScope::lifetime_t lifetime,
Added support for interface declaration and instantiation. modport and extern tf declarations are not yet supported.
2014-12-20 00:10:14 +01:00
list<named_pexpr_t>*attr)
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
{
Fix some cppcheck warnings in the main directory
2012-08-08 20:26:46 +02:00
if (! pform_cur_module.empty() && !gn_system_verilog()) {
Allow modules (and program blocks in particular) to nest. An important advantage of program blocks is its ability to nest within a module. This winds up also allowing modules to nest, which is legal but presumably less used feature.
2012-05-10 04:35:11 +02:00
cerr << loc << ": error: Module definition " << name
<< " cannot nest into module " << pform_cur_module.front()->mod_name() << "." << endl;
error_count += 1;
}
Added support for default subroutine lifetimes (SystemVerilog).
2016-03-19 18:27:27 +01:00
if (lifetime != LexicalScope::INHERITED && !gn_system_verilog()) {
cerr << loc << ": error: Default subroutine lifetimes "
"require SystemVerilog." << endl;
error_count += 1;
}
Added support for interface declaration and instantiation. modport and extern tf declarations are not yet supported.
2014-12-20 00:10:14 +01:00
if (gn_system_verilog() && ! pform_cur_module.empty()) {
if (pform_cur_module.front()->program_block) {
cerr << loc << ": error: module, program, or interface "
"declarations are not allowed in program "
"blocks." << endl;
error_count += 1;
}
if (pform_cur_module.front()->is_interface
&& !(program_block || is_interface)) {
cerr << loc << ": error: module declarations are not "
"allowed in interfaces." << endl;
error_count += 1;
}
Disallow modules/gates in program blocks.
2012-05-15 04:13:57 +02:00
}
Handle unconnected module ports.
1999-09-17 04:06:25 +02:00
Use perm_strings for named langiage items.
2004-02-18 18:11:54 +01:00
perm_string lex_name = lex_strings.make(name);
Allow modules (and program blocks in particular) to nest. An important advantage of program blocks is its ability to nest within a module. This winds up also allowing modules to nest, which is legal but presumably less used feature.
2012-05-10 04:35:11 +02:00
Module*cur_module = new Module(lexical_scope, lex_name);
cur_module->program_block = program_block;
Added support for interface declaration and instantiation. modport and extern tf declarations are not yet supported.
2014-12-20 00:10:14 +01:00
cur_module->is_interface = is_interface;
Added support for default subroutine lifetimes (SystemVerilog).
2016-03-19 18:27:27 +01:00
cur_module->default_lifetime = find_lifetime(lifetime);
Support timescales in design units that aren't inside a module. SystemVerilog allows tasks, functions, and classes to be defined at the root level or inside packages, so we can't rely on an enclosing module being present to provide the timescale.
2016-07-22 23:48:20 +02:00
FILE_NAME(cur_module, loc);
Allow modules (and program blocks in particular) to nest. An important advantage of program blocks is its ability to nest within a module. This winds up also allowing modules to nest, which is legal but presumably less used feature.
2012-05-10 04:35:11 +02:00
cur_module->library_flag = pform_library_flag;
detect module ports not declared within the module.
2001-10-31 04:11:15 +01:00
Allow modules (and program blocks in particular) to nest. An important advantage of program blocks is its ability to nest within a module. This winds up also allowing modules to nest, which is legal but presumably less used feature.
2012-05-10 04:35:11 +02:00
pform_cur_module.push_front(cur_module);
Rework handling of timescales in parser. This implements and enforces the full set of rules for determining timescales in SystemVerilog. The previous relaxation of the rules that allowed timescales to be redefined within the compilation unit scope has been removed. Time unit and precision redeclarations are now recognised after a nested module declaration.
2017-11-05 18:50:05 +01:00
allow_timeunit_decl = true;
allow_timeprec_decl = true;
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
add_local_symbol(lexical_scope, lex_name, cur_module);
Allow modules (and program blocks in particular) to nest. An important advantage of program blocks is its ability to nest within a module. This winds up also allowing modules to nest, which is legal but presumably less used feature.
2012-05-10 04:35:11 +02:00
lexical_scope = cur_module;
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
/* The generate scheme numbering starts with *1*, not
zero. That's just the way it is, thanks to the standard. */
scope_generate_counter = 1;
Allow modules (and program blocks in particular) to nest. An important advantage of program blocks is its ability to nest within a module. This winds up also allowing modules to nest, which is legal but presumably less used feature.
2012-05-10 04:35:11 +02:00
pform_bind_attributes(cur_module->attributes, attr);
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
Parse port_declaration_lists from the 2001 Standard.
2002-05-20 01:37:28 +02:00
/*
* This function is called by the parser to make a simple port
* reference. This is a name without a .X(...), so the internal name
* should be generated to be the same as the X.
*/
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
Module::port_t* pform_module_port_reference(perm_string name,
Parse port_declaration_lists from the 2001 Standard.
2002-05-20 01:37:28 +02:00
const char*file,
unsigned lineno)
{
Module::port_t*ptmp = new Module::port_t;
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
PEIdent*tmp = new PEIdent(name);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, file, lineno);
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
ptmp->name = name;
Remove svector class from Module.h The goal is to completely remove the svector class because the standard vector class works perfectly well. This removes the uses in the Module.h header file.
2008-11-03 05:08:38 +01:00
ptmp->expr.push_back(tmp);
Parse port_declaration_lists from the 2001 Standard.
2002-05-20 01:37:28 +02:00
return ptmp;
}
Remove svector class from Module.h The goal is to completely remove the svector class because the standard vector class works perfectly well. This removes the uses in the Module.h header file.
2008-11-03 05:08:38 +01:00
void pform_module_set_ports(vector<Module::port_t*>*ports)
Parse port_declaration_lists from the 2001 Standard.
2002-05-20 01:37:28 +02:00
{
Fix some cppcheck warnings in the main directory
2012-08-08 20:26:46 +02:00
assert(! pform_cur_module.empty());
Parse port_declaration_lists from the 2001 Standard.
2002-05-20 01:37:28 +02:00
/* The parser parses ``module foo()'' as having one
unconnected port, but it is really a module with no
ports. Fix it up here. */
Remove svector class from Module.h The goal is to completely remove the svector class because the standard vector class works perfectly well. This removes the uses in the Module.h header file.
2008-11-03 05:08:38 +01:00
if (ports && (ports->size() == 1) && ((*ports)[0] == 0)) {
Parse port_declaration_lists from the 2001 Standard.
2002-05-20 01:37:28 +02:00
delete ports;
ports = 0;
}
if (ports != 0) {
Allow modules (and program blocks in particular) to nest. An important advantage of program blocks is its ability to nest within a module. This winds up also allowing modules to nest, which is legal but presumably less used feature.
2012-05-10 04:35:11 +02:00
pform_cur_module.front()->ports = *ports;
Parse port_declaration_lists from the 2001 Standard.
2002-05-20 01:37:28 +02:00
delete ports;
}
}
Fix new shadow issues and add -Wshadow to gcc compile. Some new shadow issues have crept in. This patch fixes these new issues and adds -Wshadow to the normal warning flags to keep any new occurrences from happening.
2010-05-13 03:53:56 +02:00
void pform_endmodule(const char*name, bool inside_celldefine,
Module::UCDriveType uc_drive_def)
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
{
Fix some cppcheck warnings in the main directory
2012-08-08 20:26:46 +02:00
assert(! pform_cur_module.empty());
Allow modules (and program blocks in particular) to nest. An important advantage of program blocks is its ability to nest within a module. This winds up also allowing modules to nest, which is legal but presumably less used feature.
2012-05-10 04:35:11 +02:00
Module*cur_module = pform_cur_module.front();
pform_cur_module.pop_front();
perm_string mod_name = cur_module->mod_name();
Use perm_strings for named langiage items.
2004-02-18 18:11:54 +01:00
assert(strcmp(name, mod_name) == 0);
Allow modules (and program blocks in particular) to nest. An important advantage of program blocks is its ability to nest within a module. This winds up also allowing modules to nest, which is legal but presumably less used feature.
2012-05-10 04:35:11 +02:00
cur_module->is_cell = inside_celldefine;
cur_module->uc_drive = uc_drive_def;
// If this is a root module, then there is no parent module
// and we try to put this newly defined module into the global
// root list of modules. Otherwise, this is a nested module
// and we put it into the parent module scope to be elaborated
// if needed.
Fix some cppcheck warnings in the main directory
2012-08-08 20:26:46 +02:00
map<perm_string,Module*>&use_module_map = (pform_cur_module.empty())
Allow modules (and program blocks in particular) to nest. An important advantage of program blocks is its ability to nest within a module. This winds up also allowing modules to nest, which is legal but presumably less used feature.
2012-05-10 04:35:11 +02:00
? pform_modules
: pform_cur_module.front()->nested_modules;
Use perm_strings for named langiage items.
2004-02-18 18:11:54 +01:00
Clean up spurious trailing white space.
2004-10-04 03:10:51 +02:00
map<perm_string,Module*>::const_iterator test =
Allow modules (and program blocks in particular) to nest. An important advantage of program blocks is its ability to nest within a module. This winds up also allowing modules to nest, which is legal but presumably less used feature.
2012-05-10 04:35:11 +02:00
use_module_map.find(mod_name);
Detect duplicate module declarations.
2003-01-16 22:44:19 +01:00
Allow modules (and program blocks in particular) to nest. An important advantage of program blocks is its ability to nest within a module. This winds up also allowing modules to nest, which is legal but presumably less used feature.
2012-05-10 04:35:11 +02:00
if (test != use_module_map.end()) {
Detect duplicate module declarations.
2003-01-16 22:44:19 +01:00
ostringstream msg;
msg << "Module " << name << " was already declared here: "
Allow modules (and program blocks in particular) to nest. An important advantage of program blocks is its ability to nest within a module. This winds up also allowing modules to nest, which is legal but presumably less used feature.
2012-05-10 04:35:11 +02:00
<< test->second->get_fileline() << endl;
Detect duplicate module declarations.
2003-01-16 22:44:19 +01:00
VLerror(msg.str().c_str());
Don't crash on duplicate module Fix for pr1938138, pform.cc:278: failed assertion lexical_scope == 0
2008-04-10 06:09:55 +02:00
} else {
Allow modules (and program blocks in particular) to nest. An important advantage of program blocks is its ability to nest within a module. This winds up also allowing modules to nest, which is legal but presumably less used feature.
2012-05-10 04:35:11 +02:00
use_module_map[mod_name] = cur_module;
Detect duplicate module declarations.
2003-01-16 22:44:19 +01:00
}
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
Support separate compilation units in SystemVerilog. The compilation unit scope is now treated as a specialised form of package (with an automatically generated name). All items declared outside a design element are added to the current compilation unit package. Apart from when searching for a symbol, once we get into elaboration we can treat these just like any other package.
2017-10-21 16:04:25 +02:00
// The current lexical scope should be this module by now.
Allow modules (and program blocks in particular) to nest. An important advantage of program blocks is its ability to nest within a module. This winds up also allowing modules to nest, which is legal but presumably less used feature.
2012-05-10 04:35:11 +02:00
ivl_assert(*cur_module, lexical_scope == cur_module);
Rework of lexical scope handling in parser. This patch modifies the parser to use a single stack to track lexical scopes, rather than starting a new stack for each generate construct.
2010-01-08 23:49:48 +01:00
pform_pop_scope();
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
Add file and line information for parameters, etc. This patch adds file and line information for parameters and local parameters. It also adds file/line stubs for signals in the tgt-* files. It adds the pform code needed to eventually do genvar checks and passing of genvar file/line information. It verifies that a genvar does not have the same name as a parameter/local parameter.
2008-05-06 04:46:30 +02:00
void pform_genvars(const struct vlltype&li, list<perm_string>*names)
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
{
list<perm_string>::const_iterator cur;
for (cur = names->begin(); cur != names->end() ; *cur++) {
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
PGenvar*genvar = new PGenvar();
FILE_NAME(genvar, li);
if (pform_cur_generate) {
add_local_symbol(pform_cur_generate, *cur, genvar);
pform_cur_generate->genvars[*cur] = genvar;
} else {
add_local_symbol(pform_cur_module.front(), *cur, genvar);
pform_cur_module.front()->genvars[*cur] = genvar;
}
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
}
delete names;
}
void pform_start_generate_for(const struct vlltype&li,
char*ident1, PExpr*init,
PExpr*test,
char*ident2, PExpr*next)
{
Rework of lexical scope handling in parser. This patch modifies the parser to use a single stack to track lexical scopes, rather than starting a new stack for each generate construct.
2010-01-08 23:49:48 +01:00
PGenerate*gen = new PGenerate(lexical_scope, scope_generate_counter++);
lexical_scope = gen;
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(gen, li);
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
pform_cur_generate = gen;
pform_cur_generate->scheme_type = PGenerate::GS_LOOP;
pform_cur_generate->loop_index = lex_strings.make(ident1);
pform_cur_generate->loop_init = init;
pform_cur_generate->loop_test = test;
pform_cur_generate->loop_step = next;
delete[]ident1;
delete[]ident2;
}
Add support for conditional generate. In the process, fix bugs related to generate used multiple times by multiple scopes causing spurious generation results. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-06-22 04:04:48 +02:00
void pform_start_generate_if(const struct vlltype&li, PExpr*test)
{
Rework of lexical scope handling in parser. This patch modifies the parser to use a single stack to track lexical scopes, rather than starting a new stack for each generate construct.
2010-01-08 23:49:48 +01:00
PGenerate*gen = new PGenerate(lexical_scope, scope_generate_counter++);
lexical_scope = gen;
Add support for conditional generate. In the process, fix bugs related to generate used multiple times by multiple scopes causing spurious generation results. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-06-22 04:04:48 +02:00
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(gen, li);
Add support for conditional generate. In the process, fix bugs related to generate used multiple times by multiple scopes causing spurious generation results. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-06-22 04:04:48 +02:00
pform_cur_generate = gen;
pform_cur_generate->scheme_type = PGenerate::GS_CONDIT;
pform_cur_generate->loop_init = 0;
pform_cur_generate->loop_test = test;
pform_cur_generate->loop_step = 0;
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
conditional_block_names.push_front(set<perm_string>());
Add support for conditional generate. In the process, fix bugs related to generate used multiple times by multiple scopes causing spurious generation results. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-06-22 04:04:48 +02:00
}
void pform_start_generate_else(const struct vlltype&li)
{
assert(pform_cur_generate);
assert(pform_cur_generate->scheme_type == PGenerate::GS_CONDIT);
PGenerate*cur = pform_cur_generate;
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
pform_endgenerate(false);
Add support for conditional generate. In the process, fix bugs related to generate used multiple times by multiple scopes causing spurious generation results. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-06-22 04:04:48 +02:00
Rework of lexical scope handling in parser. This patch modifies the parser to use a single stack to track lexical scopes, rather than starting a new stack for each generate construct.
2010-01-08 23:49:48 +01:00
PGenerate*gen = new PGenerate(lexical_scope, scope_generate_counter++);
lexical_scope = gen;
Add support for conditional generate. In the process, fix bugs related to generate used multiple times by multiple scopes causing spurious generation results. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-06-22 04:04:48 +02:00
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(gen, li);
Add support for conditional generate. In the process, fix bugs related to generate used multiple times by multiple scopes causing spurious generation results. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-06-22 04:04:48 +02:00
pform_cur_generate = gen;
pform_cur_generate->scheme_type = PGenerate::GS_ELSE;
pform_cur_generate->loop_init = 0;
pform_cur_generate->loop_test = cur->loop_test;
pform_cur_generate->loop_step = 0;
}
Add support for generate case Generate case is a complex generate scheme where the items are sub-schemes of the case generate itself. The parser handles them something like nested generate statements, but storing the case guards as the test expression. Then the elaborator notes the case scheme and reaches into the case item schemes inside to make up tests, select the generate item, and elaborate.
2008-02-10 07:19:42 +01:00
/*
* The GS_CASE version of the PGenerate contains only case items. The
* items in turn contain the generated items themselves.
*/
void pform_start_generate_case(const struct vlltype&li, PExpr*expr)
{
Rework of lexical scope handling in parser. This patch modifies the parser to use a single stack to track lexical scopes, rather than starting a new stack for each generate construct.
2010-01-08 23:49:48 +01:00
PGenerate*gen = new PGenerate(lexical_scope, scope_generate_counter++);
lexical_scope = gen;
Add support for generate case Generate case is a complex generate scheme where the items are sub-schemes of the case generate itself. The parser handles them something like nested generate statements, but storing the case guards as the test expression. Then the elaborator notes the case scheme and reaches into the case item schemes inside to make up tests, select the generate item, and elaborate.
2008-02-10 07:19:42 +01:00
FILE_NAME(gen, li);
pform_cur_generate = gen;
pform_cur_generate->scheme_type = PGenerate::GS_CASE;
pform_cur_generate->loop_init = 0;
pform_cur_generate->loop_test = expr;
pform_cur_generate->loop_step = 0;
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
conditional_block_names.push_front(set<perm_string>());
Add support for generate case Generate case is a complex generate scheme where the items are sub-schemes of the case generate itself. The parser handles them something like nested generate statements, but storing the case guards as the test expression. Then the elaborator notes the case scheme and reaches into the case item schemes inside to make up tests, select the generate item, and elaborate.
2008-02-10 07:19:42 +01:00
}
Add support for the 1364-2001 generate of a named block. This is obsolete in 1364-2005, but is supported 1364-2001. Icarus already supported generate with unnamed block.
2008-11-15 03:35:39 +01:00
/*
* The named block generate case.
*/
void pform_start_generate_nblock(const struct vlltype&li, char*name)
{
Rework of lexical scope handling in parser. This patch modifies the parser to use a single stack to track lexical scopes, rather than starting a new stack for each generate construct.
2010-01-08 23:49:48 +01:00
PGenerate*gen = new PGenerate(lexical_scope, scope_generate_counter++);
lexical_scope = gen;
Add support for the 1364-2001 generate of a named block. This is obsolete in 1364-2005, but is supported 1364-2001. Icarus already supported generate with unnamed block.
2008-11-15 03:35:39 +01:00
FILE_NAME(gen, li);
pform_cur_generate = gen;
pform_cur_generate->scheme_type = PGenerate::GS_NBLOCK;
pform_cur_generate->loop_init = 0;
pform_cur_generate->loop_test = 0;
pform_cur_generate->loop_step = 0;
pform_cur_generate->scope_name = lex_strings.make(name);
delete[]name;
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
add_local_symbol(pform_cur_generate->parent_scope(),
pform_cur_generate->scope_name,
pform_cur_generate);
Add support for the 1364-2001 generate of a named block. This is obsolete in 1364-2005, but is supported 1364-2001. Icarus already supported generate with unnamed block.
2008-11-15 03:35:39 +01:00
}
Add support for generate case Generate case is a complex generate scheme where the items are sub-schemes of the case generate itself. The parser handles them something like nested generate statements, but storing the case guards as the test expression. Then the elaborator notes the case scheme and reaches into the case item schemes inside to make up tests, select the generate item, and elaborate.
2008-02-10 07:19:42 +01:00
/*
* The generate case item is a special case schema that takes its id
* from the case schema that it is a part of. The idea is that the
* case schema can only instantiate exactly one item, so the items
* need not have a unique number.
*/
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
void pform_generate_case_item(const struct vlltype&li, list<PExpr*>*expr_list)
Add support for generate case Generate case is a complex generate scheme where the items are sub-schemes of the case generate itself. The parser handles them something like nested generate statements, but storing the case guards as the test expression. Then the elaborator notes the case scheme and reaches into the case item schemes inside to make up tests, select the generate item, and elaborate.
2008-02-10 07:19:42 +01:00
{
assert(pform_cur_generate);
assert(pform_cur_generate->scheme_type == PGenerate::GS_CASE);
Rework of lexical scope handling in parser. This patch modifies the parser to use a single stack to track lexical scopes, rather than starting a new stack for each generate construct.
2010-01-08 23:49:48 +01:00
PGenerate*gen = new PGenerate(lexical_scope, pform_cur_generate->id_number);
lexical_scope = gen;
Add support for generate case Generate case is a complex generate scheme where the items are sub-schemes of the case generate itself. The parser handles them something like nested generate statements, but storing the case guards as the test expression. Then the elaborator notes the case scheme and reaches into the case item schemes inside to make up tests, select the generate item, and elaborate.
2008-02-10 07:19:42 +01:00
FILE_NAME(gen, li);
pform_cur_generate = gen;
pform_cur_generate->scheme_type = PGenerate::GS_CASE_ITEM;
pform_cur_generate->loop_init = 0;
Support direct nesting of conditional generate schemes. Verilog generate schemes support a special case where conditional generate schemes that contain only a nested conditional generate scheme do not create a new scope. Instead, it relies on the nested generate scheme to generate the scope.
2008-11-28 04:45:22 +01:00
pform_cur_generate->loop_test = 0;
Add support for generate case Generate case is a complex generate scheme where the items are sub-schemes of the case generate itself. The parser handles them something like nested generate statements, but storing the case guards as the test expression. Then the elaborator notes the case scheme and reaches into the case item schemes inside to make up tests, select the generate item, and elaborate.
2008-02-10 07:19:42 +01:00
pform_cur_generate->loop_step = 0;
Support direct nesting of conditional generate schemes. Verilog generate schemes support a special case where conditional generate schemes that contain only a nested conditional generate scheme do not create a new scope. Instead, it relies on the nested generate scheme to generate the scope.
2008-11-28 04:45:22 +01:00
if (expr_list != 0) {
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
list<PExpr*>::iterator expr_cur = expr_list->begin();
pform_cur_generate->item_test.resize(expr_list->size());
for (unsigned idx = 0 ; idx < expr_list->size() ; idx += 1) {
pform_cur_generate->item_test[idx] = *expr_cur;
++ expr_cur;
}
assert(expr_cur == expr_list->end());
Support direct nesting of conditional generate schemes. Verilog generate schemes support a special case where conditional generate schemes that contain only a nested conditional generate scheme do not create a new scope. Instead, it relies on the nested generate scheme to generate the scope.
2008-11-28 04:45:22 +01:00
}
Add support for generate case Generate case is a complex generate scheme where the items are sub-schemes of the case generate itself. The parser handles them something like nested generate statements, but storing the case guards as the test expression. Then the elaborator notes the case scheme and reaches into the case item schemes inside to make up tests, select the generate item, and elaborate.
2008-02-10 07:19:42 +01:00
}
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
void pform_generate_block_name(char*name)
{
assert(pform_cur_generate != 0);
assert(pform_cur_generate->scope_name == 0);
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
perm_string scope_name = lex_strings.make(name);
pform_cur_generate->scope_name = scope_name;
if (pform_cur_generate->scheme_type == PGenerate::GS_CONDIT
|| pform_cur_generate->scheme_type == PGenerate::GS_ELSE
|| pform_cur_generate->scheme_type == PGenerate::GS_CASE_ITEM) {
if (conditional_block_names.front().count(scope_name))
return;
conditional_block_names.front().insert(scope_name);
}
add_local_symbol(pform_cur_generate->parent_scope(),
scope_name, pform_cur_generate);
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
}
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
void pform_endgenerate(bool end_conditional)
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
{
assert(pform_cur_generate != 0);
Fix some cppcheck warnings in the main directory
2012-08-08 20:26:46 +02:00
assert(! pform_cur_module.empty());
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
if (end_conditional)
conditional_block_names.pop_front();
Correct naming of unnamed generate blocks. This patch causes unnamed generate blocks to be automatically named using the naming scheme defined in the Verilog-2005 standard. This is a fix for the problem discussed in pr1821610.
2007-11-17 19:17:23 +01:00
// If there is no explicit block name then generate a temporary
// name. This will be replaced by the correct name later, once
// we know all the explicit names in the surrounding scope. If
// the naming scheme used here is changed, PGenerate::elaborate
// must be changed to match.
Add support for conditional generate. In the process, fix bugs related to generate used multiple times by multiple scopes causing spurious generation results. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-06-22 04:04:48 +02:00
if (pform_cur_generate->scope_name == 0) {
char tmp[16];
Fix print token/argument mismatches and other cppcheck fixes
2013-09-09 22:32:55 +02:00
snprintf(tmp, sizeof tmp, "$gen%u", pform_cur_generate->id_number);
Add support for conditional generate. In the process, fix bugs related to generate used multiple times by multiple scopes causing spurious generation results. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-06-22 04:04:48 +02:00
pform_cur_generate->scope_name = lex_strings.make(tmp);
}
Rework of lexical scope handling in parser. This patch modifies the parser to use a single stack to track lexical scopes, rather than starting a new stack for each generate construct.
2010-01-08 23:49:48 +01:00
// The current lexical scope should be this generate construct by now
ivl_assert(*pform_cur_generate, lexical_scope == pform_cur_generate);
pform_pop_scope();
Properly evaluate scope path expressions.
2007-06-02 05:42:12 +02:00
Rework of lexical scope handling in parser. This patch modifies the parser to use a single stack to track lexical scopes, rather than starting a new stack for each generate construct.
2010-01-08 23:49:48 +01:00
PGenerate*parent_generate = dynamic_cast<PGenerate*>(lexical_scope);
if (parent_generate) {
assert(pform_cur_generate->scheme_type == PGenerate::GS_CASE_ITEM
|| parent_generate->scheme_type != PGenerate::GS_CASE);
parent_generate->generate_schemes.push_back(pform_cur_generate);
Add support for generate case Generate case is a complex generate scheme where the items are sub-schemes of the case generate itself. The parser handles them something like nested generate statements, but storing the case guards as the test expression. Then the elaborator notes the case scheme and reaches into the case item schemes inside to make up tests, select the generate item, and elaborate.
2008-02-10 07:19:42 +01:00
} else {
Rework of lexical scope handling in parser. This patch modifies the parser to use a single stack to track lexical scopes, rather than starting a new stack for each generate construct.
2010-01-08 23:49:48 +01:00
assert(pform_cur_generate->scheme_type != PGenerate::GS_CASE_ITEM);
Allow modules (and program blocks in particular) to nest. An important advantage of program blocks is its ability to nest within a module. This winds up also allowing modules to nest, which is legal but presumably less used feature.
2012-05-10 04:35:11 +02:00
pform_cur_module.front()->generate_schemes.push_back(pform_cur_generate);
Add support for generate case Generate case is a complex generate scheme where the items are sub-schemes of the case generate itself. The parser handles them something like nested generate statements, but storing the case guards as the test expression. Then the elaborator notes the case scheme and reaches into the case item schemes inside to make up tests, select the generate item, and elaborate.
2008-02-10 07:19:42 +01:00
}
Rework of lexical scope handling in parser. This patch modifies the parser to use a single stack to track lexical scopes, rather than starting a new stack for each generate construct.
2010-01-08 23:49:48 +01:00
pform_cur_generate = parent_generate;
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
}
Introduce min:typ:max support.
2000-07-29 19:58:20 +02:00
MIN_TYP_MAX min_typ_max_flag = TYP;
unsigned min_typ_max_warn = 10;
PExpr* pform_select_mtm_expr(PExpr*min, PExpr*typ, PExpr*max)
{
PExpr*res = 0;
switch (min_typ_max_flag) {
case MIN:
res = min;
delete typ;
delete max;
break;
case TYP:
res = typ;
delete min;
delete max;
break;
case MAX:
res = max;
delete min;
Deleted wrong time when -Tmax is selected.
2001-05-20 17:03:25 +02:00
delete typ;
Introduce min:typ:max support.
2000-07-29 19:58:20 +02:00
break;
}
if (min_typ_max_warn > 0) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << res->get_fileline() << ": warning: choosing ";
Introduce min:typ:max support.
2000-07-29 19:58:20 +02:00
switch (min_typ_max_flag) {
case MIN:
cerr << "min";
break;
case TYP:
cerr << "typ";
break;
case MAX:
cerr << "max";
break;
}
cerr << " expression." << endl;
min_typ_max_warn -= 1;
}
return res;
}
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
template <> inline svector<perm_string>::svector(unsigned size)
: nitems_(size), items_(new perm_string[size])
{
}
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
static void process_udp_table(PUdp*udp, list<string>*table,
const char*file, unsigned lineno)
{
const bool synchronous_flag = udp->sequential;
/* Interpret and check the table entry strings, to make sure
they correspond to the inputs, output and output type. Make
up vectors for the fully interpreted result that can be
placed in the PUdp object.
The table strings are made up by the parser to be two or
Spelling fixes mostly comments, but includes some identifiers and message text
2008-01-25 22:34:51 +01:00
three substrings separated by ';', i.e.:
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
0101:1:1 (synchronous device entry)
0101:0 (combinational device entry)
The parser doesn't check that we got the right kind here,
so this loop must watch out. */
svector<string> input (table->size());
svector<char> current (table->size());
svector<char> output (table->size());
{ unsigned idx = 0;
for (list<string>::iterator cur = table->begin()
Change iterators to use prefix ++ since it is more efficient. This patch changes all the iterator code to use a prefix ++ instead of postfix since it is more efficient (no need for a temporary). It is likely that the compiler could optimize this away, but lets make it efficient from the start.
2010-10-23 23:57:59 +02:00
; cur != table->end() ; ++ cur , idx += 1) {
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
string tmp = *cur;
/* Pull the input values from the string. */
assert(tmp.find(':') == (udp->ports.count() - 1));
input[idx] = tmp.substr(0, udp->ports.count()-1);
tmp = tmp.substr(udp->ports.count()-1);
assert(tmp[0] == ':');
/* If this is a synchronous device, get the current
output string. */
if (synchronous_flag) {
if (tmp.size() != 4) {
cerr << file<<":"<<lineno << ": error: "
<< "Invalid table format for"
<< " sequential primitive." << endl;
error_count += 1;
break;
}
assert(tmp.size() == 4);
current[idx] = tmp[1];
tmp = tmp.substr(2);
} else if (tmp.size() != 2) {
cerr << file<<":"<<lineno << ": error: "
<< "Invalid table format for"
<< " combinational primitive." << endl;
error_count += 1;
break;
}
/* Finally, extract the desired output. */
assert(tmp.size() == 2);
output[idx] = tmp[1];
}
}
udp->tinput = input;
udp->tcurrent = current;
udp->toutput = output;
}
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
void pform_make_udp(perm_string name, list<perm_string>*parms,
Remove svector template from port handling.
2013-02-25 03:06:12 +01:00
vector<PWire*>*decl, list<string>*table,
Error messages for missing UDP port declarations.
2001-10-21 03:55:24 +02:00
Statement*init_expr,
const char*file, unsigned lineno)
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
{
Error messages for missing UDP port declarations.
2001-10-21 03:55:24 +02:00
unsigned local_errors = 0;
Cleanup various style issues. This patch cleans up some style issues: no need to check that a value is defined before freeing or deleting it, use C++ style casts, make sure to NULL terminate strncpy(), empty() is faster than size() for size == 0 or size >= 0 checks, re-scope some variables, etc.
2010-04-14 06:29:15 +02:00
assert(!parms->empty());
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
Remove svector template from port handling.
2013-02-25 03:06:12 +01:00
assert(decl);
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
/* Put the declarations into a map, so that I can check them
Clean up interface of the PWire class, Properly match wire ranges.
1999-06-17 07:34:42 +02:00
off with the parameters in the list. If the port is already
in the map, merge the port type. I will rebuild a list
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
of parameters for the PUdp object. */
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
map<perm_string,PWire*> defs;
Remove svector template from port handling.
2013-02-25 03:06:12 +01:00
for (unsigned idx = 0 ; idx < decl->size() ; idx += 1) {
Clean up interface of the PWire class, Properly match wire ranges.
1999-06-17 07:34:42 +02:00
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
perm_string port_name = (*decl)[idx]->basename();
Parser and pform use hierarchical names as hname_t objects instead of encoded strings.
2001-12-03 05:47:14 +01:00
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
if (PWire*cur = defs[port_name]) {
Fix merging of UDP port type in decls.
1999-06-21 03:02:16 +02:00
bool rc = true;
assert((*decl)[idx]);
if ((*decl)[idx]->get_port_type() != NetNet::PIMPLICIT) {
rc = cur->set_port_type((*decl)[idx]->get_port_type());
assert(rc);
}
if ((*decl)[idx]->get_wire_type() != NetNet::IMPLICIT) {
rc = cur->set_wire_type((*decl)[idx]->get_wire_type());
assert(rc);
}
Clean up interface of the PWire class, Properly match wire ranges.
1999-06-17 07:34:42 +02:00
} else {
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
defs[port_name] = (*decl)[idx];
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
}
Clean up interface of the PWire class, Properly match wire ranges.
1999-06-17 07:34:42 +02:00
}
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
/* Put the parameters into a vector of wire descriptions. Look
Error messages for missing UDP port declarations.
2001-10-21 03:55:24 +02:00
in the map for the definitions of the name. In this loop,
the parms list in the list of ports in the port list of the
UDP declaration, and the defs map maps that name to a
PWire* created by an input or output declaration. */
Get rid of the STL vector template.
1999-06-15 05:44:53 +02:00
svector<PWire*> pins (parms->size());
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
svector<perm_string> pin_names (parms->size());
{ list<perm_string>::iterator cur;
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
unsigned idx;
for (cur = parms->begin(), idx = 0
; cur != parms->end()
Some more cppcheck cleanup/updates
2014-06-30 05:38:23 +02:00
; ++ idx, ++ cur) {
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
pins[idx] = defs[*cur];
Error messages for missing UDP port declarations.
2001-10-21 03:55:24 +02:00
pin_names[idx] = *cur;
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
}
}
/* Check that the output is an output and the inputs are
inputs. I can also make sure that only the single output is
Error messages for missing UDP port declarations.
2001-10-21 03:55:24 +02:00
declared a register, if anything. The possible errors are:
-- an input port (not the first) is missing an input
declaration.
-- An input port is declared output.
*/
Get rid of the STL vector template.
1999-06-15 05:44:53 +02:00
assert(pins.count() > 0);
Error messages for missing UDP port declarations.
2001-10-21 03:55:24 +02:00
do {
if (pins[0] == 0) {
cerr << file<<":"<<lineno << ": error: "
<< "Output port of primitive " << name
<< " missing output declaration." << endl;
cerr << file<<":"<<lineno << ": : "
<< "Try: output " << pin_names[0] << ";"
<< endl;
error_count += 1;
local_errors += 1;
break;
}
if (pins[0]->get_port_type() != NetNet::POUTPUT) {
cerr << file<<":"<<lineno << ": error: "
<< "The first port of a primitive"
<< " must be an output." << endl;
cerr << file<<":"<<lineno << ": : "
<< "Try: output " << pin_names[0] << ";"
<< endl;
error_count += 1;
local_errors += 1;
break;;
}
} while (0);
Get rid of the STL vector template.
1999-06-15 05:44:53 +02:00
for (unsigned idx = 1 ; idx < pins.count() ; idx += 1) {
Error messages for missing UDP port declarations.
2001-10-21 03:55:24 +02:00
if (pins[idx] == 0) {
cerr << file<<":"<<lineno << ": error: "
<< "Port " << (idx+1)
<< " of primitive " << name << " missing"
<< " input declaration." << endl;
cerr << file<<":"<<lineno << ": : "
<< "Try: input " << pin_names[idx] << ";"
<< endl;
error_count += 1;
local_errors += 1;
continue;
}
if (pins[idx]->get_port_type() != NetNet::PINPUT) {
Better error checking of primitive tables.
2004-02-15 18:48:28 +01:00
cerr << file<<":"<<lineno << ": error: "
<< "Input port " << (idx+1)
<< " of primitive " << name
<< " has an output (or missing) declaration." << endl;
cerr << file<<":"<<lineno << ": : "
<< "Note that only the first port can be an output."
<< endl;
cerr << file<<":"<<lineno << ": : "
<< "Try \"input " << name << ";\""
<< endl;
error_count += 1;
local_errors += 1;
continue;
}
if (pins[idx]->get_wire_type() == NetNet::REG) {
Error messages for missing UDP port declarations.
2001-10-21 03:55:24 +02:00
cerr << file<<":"<<lineno << ": error: "
<< "Port " << (idx+1)
Better error checking of primitive tables.
2004-02-15 18:48:28 +01:00
<< " of primitive " << name << " is an input port"
<< " with a reg declaration." << endl;
Error messages for missing UDP port declarations.
2001-10-21 03:55:24 +02:00
cerr << file<<":"<<lineno << ": : "
Better error checking of primitive tables.
2004-02-15 18:48:28 +01:00
<< "primitive inputs cannot be reg."
Error messages for missing UDP port declarations.
2001-10-21 03:55:24 +02:00
<< endl;
error_count += 1;
local_errors += 1;
continue;
}
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
}
Better error checking of primitive tables.
2004-02-15 18:48:28 +01:00
Error messages for missing UDP port declarations.
2001-10-21 03:55:24 +02:00
if (local_errors > 0) {
delete parms;
delete decl;
delete table;
delete init_expr;
return;
}
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
Better error checking of primitive tables.
2004-02-15 18:48:28 +01:00
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
/* Verify the "initial" statement, if present, to be sure that
it only assigns to the output and the output is
registered. Then save the initial value that I get. */
verinum::V init = verinum::Vx;
if (init_expr) {
// XXXX
assert(pins[0]->get_wire_type() == NetNet::REG);
Better error checking of primitive tables.
2004-02-15 18:48:28 +01:00
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
PAssign*pa = dynamic_cast<PAssign*>(init_expr);
assert(pa);
Better error checking of primitive tables.
2004-02-15 18:48:28 +01:00
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
const PEIdent*id = dynamic_cast<const PEIdent*>(pa->lval());
assert(id);
Better error checking of primitive tables.
2004-02-15 18:48:28 +01:00
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
// XXXX
//assert(id->name() == pins[0]->name());
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
const PENumber*np = dynamic_cast<const PENumber*>(pa->rval());
assert(np);
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
init = np->value()[0];
}
Better error checking of primitive tables.
2004-02-15 18:48:28 +01:00
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
// Put the primitive into the primitives table
if (pform_primitives[name]) {
emit only warning for primitive redefinition
2019-05-17 15:20:49 +02:00
VLwarn("UDP primitive already exists.");
Better error checking of primitive tables.
2004-02-15 18:48:28 +01:00
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
} else {
PUdp*udp = new PUdp(name, parms->size());
Add more file/line and scope information to the ivl interface, etc. This patch adds/fixes the following: Adds file/line information to a UDP definition. Prints an error message if a UDP is passed signals wider than 1 bit. A UDP should supports a range, but the compiler currently does not. Add scope information for constants. Fix the Icarus extension UDP table entry element 'h' to use h. The ivl_udp_init() value is a char not unsigned. Add FILE_NAME() for a bunch more of the ivl interface objects.
2011-02-07 04:47:11 +01:00
FILE_NAME(udp, file, lineno);
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
// Detect sequential udp.
if (pins[0]->get_wire_type() == NetNet::REG)
udp->sequential = true;
// Make the port list for the UDP
for (unsigned idx = 0 ; idx < pins.count() ; idx += 1)
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
udp->ports[idx] = pins[idx]->basename();
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
process_udp_table(udp, table, file, lineno);
udp->initial = init;
pform_primitives[name] = udp;
}
/* Delete the excess tables and lists from the parser. */
delete parms;
delete decl;
delete table;
delete init_expr;
}
void pform_make_udp(perm_string name, bool synchronous_flag,
perm_string out_name, PExpr*init_expr,
list<perm_string>*parms, list<string>*table,
const char*file, unsigned lineno)
{
svector<PWire*> pins(parms->size() + 1);
/* Make the PWire for the output port. */
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
pins[0] = new PWire(out_name,
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
synchronous_flag? NetNet::REG : NetNet::WIRE,
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
NetNet::POUTPUT, IVL_VT_LOGIC);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(pins[0], file, lineno);
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
/* Make the PWire objects for the input ports. */
{ list<perm_string>::iterator cur;
unsigned idx;
for (cur = parms->begin(), idx = 1
; cur != parms->end()
Some more cppcheck cleanup/updates
2014-06-30 05:38:23 +02:00
; idx += 1, ++ cur) {
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
assert(idx < pins.count());
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
pins[idx] = new PWire(*cur, NetNet::WIRE,
NetNet::PINPUT, IVL_VT_LOGIC);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(pins[idx], file, lineno);
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
}
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
assert(idx == pins.count());
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
}
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
/* Verify the initial expression, if present, to be sure that
Spelling fixes.
2003-01-10 04:08:13 +01:00
it only assigns to the output and the output is
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
registered. Then save the initial value that I get. */
verinum::V init = verinum::Vx;
if (init_expr) {
// XXXX
Clean up interface of the PWire class, Properly match wire ranges.
1999-06-17 07:34:42 +02:00
assert(pins[0]->get_wire_type() == NetNet::REG);
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
PAssign*pa = dynamic_cast<PAssign*>(init_expr);
assert(pa);
Parse and elaborate the concatenate operator in structural contexts, Replace vector<PExpr*> and list<PExpr*> with svector<PExpr*>, evaluate constant expressions with parameters, handle memories as lvalues. Parse task declarations, integer types.
1999-05-10 02:16:57 +02:00
const PEIdent*id = dynamic_cast<const PEIdent*>(pa->lval());
assert(id);
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
// XXXX
Parser and pform use hierarchical names as hname_t objects instead of encoded strings.
2001-12-03 05:47:14 +01:00
//assert(id->name() == pins[0]->name());
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
l-value part select for procedural assignments.
1999-06-14 01:51:16 +02:00
const PENumber*np = dynamic_cast<const PENumber*>(pa->rval());
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
assert(np);
init = np->value()[0];
}
// Put the primitive into the primitives table
Add automatic module libraries.
2001-10-21 01:02:39 +02:00
if (pform_primitives[name]) {
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
VLerror("UDP primitive already exists.");
} else {
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
PUdp*udp = new PUdp(name, pins.count());
Add more file/line and scope information to the ivl interface, etc. This patch adds/fixes the following: Adds file/line information to a UDP definition. Prints an error message if a UDP is passed signals wider than 1 bit. A UDP should supports a range, but the compiler currently does not. Add scope information for constants. Fix the Icarus extension UDP table entry element 'h' to use h. The ivl_udp_init() value is a char not unsigned. Add FILE_NAME() for a bunch more of the ivl interface objects.
2011-02-07 04:47:11 +01:00
FILE_NAME(udp, file, lineno);
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
// Detect sequential udp.
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
udp->sequential = synchronous_flag;
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
// Make the port list for the UDP
Get rid of the STL vector template.
1999-06-15 05:44:53 +02:00
for (unsigned idx = 0 ; idx < pins.count() ; idx += 1)
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
udp->ports[idx] = pins[idx]->basename();
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
assert(udp);
assert(table);
process_udp_table(udp, table, file, lineno);
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
udp->initial = init;
Add automatic module libraries.
2001-10-21 01:02:39 +02:00
pform_primitives[name] = udp;
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
}
delete parms;
delete table;
delete init_expr;
}
Remove C++ string from variable lists.
2000-10-31 18:00:04 +01:00
/*
* This function attaches a range to a given name. The function is
* only called by the parser within the scope of the net declaration,
* and the name that I receive only has the tail component.
*/
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
static void pform_set_net_range(perm_string name,
Use data_type_t instead of raw type bits.
2012-09-03 18:13:52 +02:00
NetNet::Type net_type,
Ranges are ranges, not expression lists. This is a cleanup in preparation for better support of range lists. (cherry picked from commit 8f7cf3255acad55841f8b3725e3786ef49daad68) Conflicts: PTask.h elab_scope.cc elab_sig.cc parse.y pform.cc pform.h pform_types.h Signed-off-by: Stephen Williams <steve@icarus.com>
2012-04-10 23:29:28 +02:00
const list<pform_range_t>*range,
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
bool signed_flag,
Fix range handling/checking and add a flag to allow deprecated port syntax. This patch is rather large and fixes a couple of problems. The major change is that instead of keeping all the range specifications in a list that is later processed the information is now kept as individual entries for the port and net definitions. This allows easier checking for multiple definitions (pr1660028), more detailed error messages and the ability to pass the now deprecated style of a scalar I/O definition used with a vectored net definition. These changes did require extra code to prevent a single definition from setting the range values in more than on place. When using the new ANSI-C style of port declarations (1364-2001 12.3.4 list_of_port_declarations) the compiler ensures that you do not redeclare the port in the body (it is already completely defined). This caught a few errors in the test suite (pr859 and sqrt32*). The flag to disable the normal port checking and allow the deprecated port syntax is -gno-io-range-error. This will print a warning for the case of a scalar port with a vectored definition in the body. All other cases are still considered an error.
2007-08-22 04:52:42 +02:00
ivl_variable_type_t dt,
Repair handling of attributes attached to variables.
2012-05-09 19:56:52 +02:00
PWSRType rt,
std::list<named_pexpr_t>*attr)
Remove C++ string from variable lists.
2000-10-31 18:00:04 +01:00
{
Attach disciplines to wires Allow discipline declaration of nets that attaches the discipline to a new wire or a wire that is already declared.
2008-05-12 02:30:33 +02:00
PWire*cur = pform_get_wire_in_scope(name);
Remove C++ string from variable lists.
2000-10-31 18:00:04 +01:00
if (cur == 0) {
Match memories within task scopes. (PR#101)
2001-01-10 06:32:44 +01:00
VLerror("error: name is not a valid net.");
Remove C++ string from variable lists.
2000-10-31 18:00:04 +01:00
return;
}
Fix for br974 - support SV types in non-ansi port declarations.
2016-04-04 21:40:30 +02:00
Use data_type_t instead of raw type bits.
2012-09-03 18:13:52 +02:00
// If this is not implicit ("implicit" meaning we don't
// know what the type is yet) then set the type now.
if (net_type != NetNet::IMPLICIT && net_type != NetNet::NONE) {
bool rc = cur->set_wire_type(net_type);
if (rc == false) {
ostringstream msg;
msg << name << " " << net_type
<< " definition conflicts with " << cur->get_wire_type()
<< " definition at " << cur->get_fileline()
<< ".";
VLerror(msg.str().c_str());
}
}
Remove C++ string from variable lists.
2000-10-31 18:00:04 +01:00
Detect scalar/vector declarion mismatch.
2002-01-26 06:28:28 +01:00
if (range == 0) {
/* This is the special case that we really mean a
scalar. Set a fake range. */
Parse multi-dimension packed arrays to pform.
2012-02-05 01:19:27 +01:00
cur->set_range_scalar(rt);
Detect scalar/vector declarion mismatch.
2002-01-26 06:28:28 +01:00
} else {
Ranges are ranges, not expression lists. This is a cleanup in preparation for better support of range lists. (cherry picked from commit 8f7cf3255acad55841f8b3725e3786ef49daad68) Conflicts: PTask.h elab_scope.cc elab_sig.cc parse.y pform.cc pform.h pform_types.h Signed-off-by: Stephen Williams <steve@icarus.com>
2012-04-10 23:29:28 +02:00
cur->set_range(*range, rt);
Detect scalar/vector declarion mismatch.
2002-01-26 06:28:28 +01:00
}
Add support for signed reg variables, simulate in t-vvm signed comparisons.
2000-12-11 01:31:43 +01:00
cur->set_signed(signed_flag);
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
if (dt != IVL_VT_NO_TYPE)
cur->set_data_type(dt);
Repair handling of attributes attached to variables.
2012-05-09 19:56:52 +02:00
pform_bind_attributes(cur->attributes, attr, true);
Remove C++ string from variable lists.
2000-10-31 18:00:04 +01:00
}
Clean up PWire handling of wire data type. / Reword packed type handling
2012-08-03 05:14:55 +02:00
static void pform_set_net_range(list<perm_string>*names,
list<pform_range_t>*range,
bool signed_flag,
ivl_variable_type_t dt,
Use data_type_t instead of raw type bits.
2012-09-03 18:13:52 +02:00
NetNet::Type net_type,
Clean up PWire handling of wire data type. / Reword packed type handling
2012-08-03 05:14:55 +02:00
std::list<named_pexpr_t>*attr)
Remove C++ string from variable lists.
2000-10-31 18:00:04 +01:00
{
More identifier lists use perm_strings.
2004-05-25 21:21:06 +02:00
for (list<perm_string>::iterator cur = names->begin()
Change iterators to use prefix ++ since it is more efficient. This patch changes all the iterator code to use a prefix ++ instead of postfix since it is more efficient (no need for a temporary). It is likely that the compiler could optimize this away, but lets make it efficient from the start.
2010-10-23 23:57:59 +02:00
; cur != names->end() ; ++ cur ) {
More identifier lists use perm_strings.
2004-05-25 21:21:06 +02:00
perm_string txt = *cur;
Use data_type_t instead of raw type bits.
2012-09-03 18:13:52 +02:00
pform_set_net_range(txt, net_type, range, signed_flag, dt, SR_NET, attr);
Remove C++ string from variable lists.
2000-10-31 18:00:04 +01:00
}
}
Named events as far as the pform.
2000-04-01 21:31:57 +02:00
/*
* This is invoked to make a named event. This is the declaration of
* the event, and not necessarily the use of it.
*/
More identifier lists use perm_strings.
2004-05-25 21:21:06 +02:00
static void pform_make_event(perm_string name, const char*fn, unsigned ln)
Named events as far as the pform.
2000-04-01 21:31:57 +02:00
{
More identifier lists use perm_strings.
2004-05-25 21:21:06 +02:00
PEvent*event = new PEvent(name);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(event, fn, ln);
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
add_local_symbol(lexical_scope, name, event);
Rework of lexical scope handling in parser. This patch modifies the parser to use a single stack to track lexical scopes, rather than starting a new stack for each generate construct.
2010-01-08 23:49:48 +01:00
lexical_scope->events[name] = event;
Named events as far as the pform.
2000-04-01 21:31:57 +02:00
}
More identifier lists use perm_strings.
2004-05-25 21:21:06 +02:00
void pform_make_events(list<perm_string>*names, const char*fn, unsigned ln)
Named events as far as the pform.
2000-04-01 21:31:57 +02:00
{
More identifier lists use perm_strings.
2004-05-25 21:21:06 +02:00
list<perm_string>::iterator cur;
Change iterators to use prefix ++ since it is more efficient. This patch changes all the iterator code to use a prefix ++ instead of postfix since it is more efficient (no need for a temporary). It is likely that the compiler could optimize this away, but lets make it efficient from the start.
2010-10-23 23:57:59 +02:00
for (cur = names->begin() ; cur != names->end() ; ++ cur ) {
More identifier lists use perm_strings.
2004-05-25 21:21:06 +02:00
perm_string txt = *cur;
Remove C++ string from variable lists.
2000-10-31 18:00:04 +01:00
pform_make_event(txt, fn, ln);
}
delete names;
Named events as far as the pform.
2000-04-01 21:31:57 +02:00
}
Elaborate gate ranges.
1999-02-15 03:06:15 +01:00
/*
* pform_makegates is called when a list of gates (with the same type)
* are ready to be instantiated. The function runs through the list of
module parameter bind by name.
1999-05-29 04:36:17 +02:00
* gates and calls the pform_makegate function to make the individual gate.
Elaborate gate ranges.
1999-02-15 03:06:15 +01:00
*/
Enumeration element values can be expressions Allow more complex enumeration expressions, which means putting off the evaluation of the expression values until elaboration.
2010-11-13 03:47:06 +01:00
static void pform_makegate(PGBuiltin::Type type,
struct str_pair_t str,
list<PExpr*>* delay,
const lgate&info,
list<named_pexpr_t>*attr)
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
{
module parameter bind by name.
1999-05-29 04:36:17 +02:00
if (info.parms_by_name) {
cerr << info.file << ":" << info.lineno << ": Gates do not "
"have port names." << endl;
error_count += 1;
return;
}
Fix for GitHub issue #152 - segfault on gate connection syntax error. If there is a syntax error in the source code, pform_makegate may be passed a null list of port connections. The error is already reported, so we just need to ignore it.
2017-04-21 22:37:17 +02:00
if (info.parms) {
for (list<PExpr*>::iterator cur = info.parms->begin()
; cur != info.parms->end() ; ++cur) {
pform_declare_implicit_nets(*cur);
}
Fix for pr2924354. Creation of implicit nets requires knowledge of whether an identifier has been declared before it is used. Currently implicit nets are created during elaboration, but by this stage the order of declaration and use is not known. This patch moves the creation of implicit nets into the parser stage.
2010-01-12 21:11:01 +01:00
}
Use perm_strings for named langiage items.
2004-02-18 18:11:54 +01:00
perm_string dev_name = lex_strings.make(info.name);
PGBuiltin*cur = new PGBuiltin(type, dev_name, info.parms, delay);
Ranges are ranges, not expression lists. This is a cleanup in preparation for better support of range lists. (cherry picked from commit 8f7cf3255acad55841f8b3725e3786ef49daad68) Conflicts: PTask.h elab_scope.cc elab_sig.cc parse.y pform.cc pform.h pform_types.h Signed-off-by: Stephen Williams <steve@icarus.com>
2012-04-10 23:29:28 +02:00
if (info.range.first)
cur->set_range(info.range.first, info.range.second);
Elaborate gate ranges.
1999-02-15 03:06:15 +01:00
Enumeration element values can be expressions Allow more complex enumeration expressions, which means putting off the evaluation of the expression values until elaboration.
2010-11-13 03:47:06 +01:00
// The pform_makegates() that calls me will take care of
// deleting the attr pointer, so tell the
// pform_bind_attributes function to keep the attr object.
pform_bind_attributes(cur->attributes, attr, true);
Add language support for Verilog-2001 attribute syntax. Hook this support into existing $attribute handling, and add number and void value types. Add to the ivl_target API new functions for access of complex attributes attached to gates.
2002-05-23 05:08:50 +02:00
Deliver gate output strengths to the netlist.
2000-05-08 07:30:19 +02:00
cur->strength0(str.str0);
cur->strength1(str.str1);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(cur, info.file, info.lineno);
Elaborate gate ranges.
1999-02-15 03:06:15 +01:00
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
if (pform_cur_generate) {
if (dev_name != "") add_local_symbol(pform_cur_generate, dev_name, cur);
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
pform_cur_generate->add_gate(cur);
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
} else {
if (dev_name != "") add_local_symbol(pform_cur_module.front(), dev_name, cur);
Allow modules (and program blocks in particular) to nest. An important advantage of program blocks is its ability to nest within a module. This winds up also allowing modules to nest, which is legal but presumably less used feature.
2012-05-10 04:35:11 +02:00
pform_cur_module.front()->add_gate(cur);
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
}
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
Disallow modules/gates in program blocks.
2012-05-15 04:13:57 +02:00
void pform_makegates(const struct vlltype&loc,
PGBuiltin::Type type,
Deliver gate output strengths to the netlist.
2000-05-08 07:30:19 +02:00
struct str_pair_t str,
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
list<PExpr*>*delay,
Add language support for Verilog-2001 attribute syntax. Hook this support into existing $attribute handling, and add number and void value types. Add to the ivl_target API new functions for access of complex attributes attached to gates.
2002-05-23 05:08:50 +02:00
svector<lgate>*gates,
Enumeration element values can be expressions Allow more complex enumeration expressions, which means putting off the evaluation of the expression values until elaboration.
2010-11-13 03:47:06 +01:00
list<named_pexpr_t>*attr)
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
{
Fix some cppcheck warnings in the main directory
2012-08-08 20:26:46 +02:00
assert(! pform_cur_module.empty());
Disallow modules/gates in program blocks.
2012-05-15 04:13:57 +02:00
if (pform_cur_module.front()->program_block) {
Added support for interface declaration and instantiation. modport and extern tf declarations are not yet supported.
2014-12-20 00:10:14 +01:00
cerr << loc << ": error: Gates and switches may not be instantiated in "
<< "program blocks." << endl;
error_count += 1;
}
if (pform_cur_module.front()->is_interface) {
cerr << loc << ": error: Gates and switches may not be instantiated in "
<< "interfaces." << endl;
Disallow modules/gates in program blocks.
2012-05-15 04:13:57 +02:00
error_count += 1;
}
makegates infinite loop fixed.
1999-05-31 17:45:59 +02:00
for (unsigned idx = 0 ; idx < gates->count() ; idx += 1) {
Add language support for Verilog-2001 attribute syntax. Hook this support into existing $attribute handling, and add number and void value types. Add to the ivl_target API new functions for access of complex attributes attached to gates.
2002-05-23 05:08:50 +02:00
pform_makegate(type, str, delay, (*gates)[idx], attr);
}
Enumeration element values can be expressions Allow more complex enumeration expressions, which means putting off the evaluation of the expression values until elaboration.
2010-11-13 03:47:06 +01:00
if (attr) delete attr;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
delete gates;
}
module parameter bind by name.
1999-05-29 04:36:17 +02:00
/*
* A module is different from a gate in that there are different
Catch module instantiation arrays.
2000-02-18 06:15:02 +01:00
* constraints, and sometimes different syntax. The X_modgate
Spelling fixes.
2003-01-10 04:08:13 +01:00
* functions handle the instantiations of modules (and UDP objects) by
Catch module instantiation arrays.
2000-02-18 06:15:02 +01:00
* making PGModule objects.
Put instantiated modules in the proper generated scope.
2007-06-12 06:05:45 +02:00
*
* The first pform_make_modgate handles the case of a module
* instantiated with ports passed by position. The "wires" is an
* ordered array of port expressions.
*
* The second pform_make_modgate handles the case of a module
* instantiated with ports passed by name. The "bind" argument is the
* ports matched with names.
module parameter bind by name.
1999-05-29 04:36:17 +02:00
*/
Use perm_strings for named langiage items.
2004-02-18 18:11:54 +01:00
static void pform_make_modgate(perm_string type,
perm_string name,
Support named parameter override lists.
2000-01-09 06:50:48 +01:00
struct parmvalue_t*overrides,
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
list<PExpr*>*wires,
Catch module instantiation arrays.
2000-02-18 06:15:02 +01:00
PExpr*msb, PExpr*lsb,
Add support to handle attributes at module instantiation sites. (* my_fancy_attribute *) foobar1 foobar (clk(clk), rst(rst) ...); - Modifies PGModule to hold the attribute map (can be verified with pform_dump) - pform_make_modgate(s) bind the attributes from the parser to the above map - The attributes from PGModule are inserted into the NetScope of that module PGModule::elaborate_scope_mod_instances_ - Currently these attributes automatically make it into netlist - These attributes are accessible via ivl_scope_attr_cnt and ivl_scope_attr_val from ivl_target.h
2017-03-16 15:41:10 +01:00
const char*fn, unsigned ln,
std::list<named_pexpr_t>*attr)
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
{
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
for (list<PExpr*>::iterator idx = wires->begin()
; idx != wires->end() ; ++idx) {
pform_declare_implicit_nets(*idx);
Fix for pr2924354. Creation of implicit nets requires knowledge of whether an identifier has been declared before it is used. Currently implicit nets are created during elaboration, but by this stage the order of declaration and use is not known. This patch moves the creation of implicit nets into the parser stage.
2010-01-12 21:11:01 +01:00
}
Support named parameter override lists.
2000-01-09 06:50:48 +01:00
PGModule*cur = new PGModule(type, name, wires);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(cur, fn, ln);
Catch module instantiation arrays.
2000-02-18 06:15:02 +01:00
cur->set_range(msb,lsb);
Support named parameter override lists.
2000-01-09 06:50:48 +01:00
if (overrides && overrides->by_name) {
Enumeration element values can be expressions Allow more complex enumeration expressions, which means putting off the evaluation of the expression values until elaboration.
2010-11-13 03:47:06 +01:00
unsigned cnt = overrides->by_name->size();
Support named parameter override lists.
2000-01-09 06:50:48 +01:00
named<PExpr*>*byname = new named<PExpr*>[cnt];
Enumeration element values can be expressions Allow more complex enumeration expressions, which means putting off the evaluation of the expression values until elaboration.
2010-11-13 03:47:06 +01:00
list<named_pexpr_t>::iterator by_name_cur = overrides->by_name->begin();
for (unsigned idx = 0 ; idx < cnt ; idx += 1, ++ by_name_cur) {
byname[idx].name = by_name_cur->name;
byname[idx].parm = by_name_cur->parm;
Support named parameter override lists.
2000-01-09 06:50:48 +01:00
}
cur->set_parameters(byname, cnt);
} else if (overrides && overrides->by_order) {
cur->set_parameters(overrides->by_order);
}
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
if (pform_cur_generate) {
if (name != "") add_local_symbol(pform_cur_generate, name, cur);
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
pform_cur_generate->add_gate(cur);
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
} else {
if (name != "") add_local_symbol(pform_cur_module.front(), name, cur);
Allow modules (and program blocks in particular) to nest. An important advantage of program blocks is its ability to nest within a module. This winds up also allowing modules to nest, which is legal but presumably less used feature.
2012-05-10 04:35:11 +02:00
pform_cur_module.front()->add_gate(cur);
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
}
Add support to handle attributes at module instantiation sites. (* my_fancy_attribute *) foobar1 foobar (clk(clk), rst(rst) ...); - Modifies PGModule to hold the attribute map (can be verified with pform_dump) - pform_make_modgate(s) bind the attributes from the parser to the above map - The attributes from PGModule are inserted into the NetScope of that module PGModule::elaborate_scope_mod_instances_ - Currently these attributes automatically make it into netlist - These attributes are accessible via ivl_scope_attr_cnt and ivl_scope_attr_val from ivl_target.h
2017-03-16 15:41:10 +01:00
pform_bind_attributes(cur->attributes, attr);
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
Use perm_strings for named langiage items.
2004-02-18 18:11:54 +01:00
static void pform_make_modgate(perm_string type,
perm_string name,
Support named parameter override lists.
2000-01-09 06:50:48 +01:00
struct parmvalue_t*overrides,
Enumeration element values can be expressions Allow more complex enumeration expressions, which means putting off the evaluation of the expression values until elaboration.
2010-11-13 03:47:06 +01:00
list<named_pexpr_t>*bind,
Catch module instantiation arrays.
2000-02-18 06:15:02 +01:00
PExpr*msb, PExpr*lsb,
Add support to handle attributes at module instantiation sites. (* my_fancy_attribute *) foobar1 foobar (clk(clk), rst(rst) ...); - Modifies PGModule to hold the attribute map (can be verified with pform_dump) - pform_make_modgate(s) bind the attributes from the parser to the above map - The attributes from PGModule are inserted into the NetScope of that module PGModule::elaborate_scope_mod_instances_ - Currently these attributes automatically make it into netlist - These attributes are accessible via ivl_scope_attr_cnt and ivl_scope_attr_val from ivl_target.h
2017-03-16 15:41:10 +01:00
const char*fn, unsigned ln,
std::list<named_pexpr_t>*attr)
module parameter bind by name.
1999-05-29 04:36:17 +02:00
{
Enumeration element values can be expressions Allow more complex enumeration expressions, which means putting off the evaluation of the expression values until elaboration.
2010-11-13 03:47:06 +01:00
unsigned npins = bind->size();
Support named parameter override lists.
2000-01-09 06:50:48 +01:00
named<PExpr*>*pins = new named<PExpr*>[npins];
Enumeration element values can be expressions Allow more complex enumeration expressions, which means putting off the evaluation of the expression values until elaboration.
2010-11-13 03:47:06 +01:00
list<named_pexpr_t>::iterator bind_cur = bind->begin();
for (unsigned idx = 0 ; idx < npins ; idx += 1, ++bind_cur) {
pins[idx].name = bind_cur->name;
pins[idx].parm = bind_cur->parm;
pform_declare_implicit_nets(bind_cur->parm);
module parameter bind by name.
1999-05-29 04:36:17 +02:00
}
Support named parameter override lists.
2000-01-09 06:50:48 +01:00
PGModule*cur = new PGModule(type, name, pins, npins);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(cur, fn, ln);
Catch module instantiation arrays.
2000-02-18 06:15:02 +01:00
cur->set_range(msb,lsb);
Support named parameter override lists.
2000-01-09 06:50:48 +01:00
if (overrides && overrides->by_name) {
Enumeration element values can be expressions Allow more complex enumeration expressions, which means putting off the evaluation of the expression values until elaboration.
2010-11-13 03:47:06 +01:00
unsigned cnt = overrides->by_name->size();
Support named parameter override lists.
2000-01-09 06:50:48 +01:00
named<PExpr*>*byname = new named<PExpr*>[cnt];
Enumeration element values can be expressions Allow more complex enumeration expressions, which means putting off the evaluation of the expression values until elaboration.
2010-11-13 03:47:06 +01:00
list<named_pexpr_t>::iterator by_name_cur = overrides->by_name->begin();
for (unsigned idx = 0 ; idx < cnt ; idx += 1, ++by_name_cur) {
byname[idx].name = by_name_cur->name;
byname[idx].parm = by_name_cur->parm;
Support named parameter override lists.
2000-01-09 06:50:48 +01:00
}
cur->set_parameters(byname, cnt);
} else if (overrides && overrides->by_order) {
cur->set_parameters(overrides->by_order);
}
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
if (pform_cur_generate) {
add_local_symbol(pform_cur_generate, name, cur);
Put instantiated modules in the proper generated scope.
2007-06-12 06:05:45 +02:00
pform_cur_generate->add_gate(cur);
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
} else {
add_local_symbol(pform_cur_module.front(), name, cur);
Allow modules (and program blocks in particular) to nest. An important advantage of program blocks is its ability to nest within a module. This winds up also allowing modules to nest, which is legal but presumably less used feature.
2012-05-10 04:35:11 +02:00
pform_cur_module.front()->add_gate(cur);
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
}
Add support to handle attributes at module instantiation sites. (* my_fancy_attribute *) foobar1 foobar (clk(clk), rst(rst) ...); - Modifies PGModule to hold the attribute map (can be verified with pform_dump) - pform_make_modgate(s) bind the attributes from the parser to the above map - The attributes from PGModule are inserted into the NetScope of that module PGModule::elaborate_scope_mod_instances_ - Currently these attributes automatically make it into netlist - These attributes are accessible via ivl_scope_attr_cnt and ivl_scope_attr_val from ivl_target.h
2017-03-16 15:41:10 +01:00
pform_bind_attributes(cur->attributes, attr);
module parameter bind by name.
1999-05-29 04:36:17 +02:00
}
Disallow modules/gates in program blocks.
2012-05-15 04:13:57 +02:00
void pform_make_modgates(const struct vlltype&loc,
perm_string type,
Support named parameter override lists.
2000-01-09 06:50:48 +01:00
struct parmvalue_t*overrides,
Add support to handle attributes at module instantiation sites. (* my_fancy_attribute *) foobar1 foobar (clk(clk), rst(rst) ...); - Modifies PGModule to hold the attribute map (can be verified with pform_dump) - pform_make_modgate(s) bind the attributes from the parser to the above map - The attributes from PGModule are inserted into the NetScope of that module PGModule::elaborate_scope_mod_instances_ - Currently these attributes automatically make it into netlist - These attributes are accessible via ivl_scope_attr_cnt and ivl_scope_attr_val from ivl_target.h
2017-03-16 15:41:10 +01:00
svector<lgate>*gates,
std::list<named_pexpr_t>*attr)
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
{
Fix some cppcheck warnings in the main directory
2012-08-08 20:26:46 +02:00
assert(! pform_cur_module.empty());
Disallow modules/gates in program blocks.
2012-05-15 04:13:57 +02:00
if (pform_cur_module.front()->program_block) {
Added support for interface declaration and instantiation. modport and extern tf declarations are not yet supported.
2014-12-20 00:10:14 +01:00
cerr << loc << ": error: Module instantiations are not allowed in "
<< "program blocks." << endl;
error_count += 1;
}
if (pform_cur_module.front()->is_interface) {
cerr << loc << ": error: Module instantiations are not allowed in "
<< "interfaces." << endl;
Disallow modules/gates in program blocks.
2012-05-15 04:13:57 +02:00
error_count += 1;
}
Pass scope type information to the target module.
2001-01-15 01:47:01 +01:00
Get rid of list<lgate> types.
1999-05-06 06:37:17 +02:00
for (unsigned idx = 0 ; idx < gates->count() ; idx += 1) {
lgate cur = (*gates)[idx];
Use perm_strings for named langiage items.
2004-02-18 18:11:54 +01:00
perm_string cur_name = lex_strings.make(cur.name);
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
module parameter bind by name.
1999-05-29 04:36:17 +02:00
if (cur.parms_by_name) {
Use perm_strings for named langiage items.
2004-02-18 18:11:54 +01:00
pform_make_modgate(type, cur_name, overrides,
Catch module instantiation arrays.
2000-02-18 06:15:02 +01:00
cur.parms_by_name,
Ranges are ranges, not expression lists. This is a cleanup in preparation for better support of range lists. (cherry picked from commit 8f7cf3255acad55841f8b3725e3786ef49daad68) Conflicts: PTask.h elab_scope.cc elab_sig.cc parse.y pform.cc pform.h pform_types.h Signed-off-by: Stephen Williams <steve@icarus.com>
2012-04-10 23:29:28 +02:00
cur.range.first, cur.range.second,
Add support to handle attributes at module instantiation sites. (* my_fancy_attribute *) foobar1 foobar (clk(clk), rst(rst) ...); - Modifies PGModule to hold the attribute map (can be verified with pform_dump) - pform_make_modgate(s) bind the attributes from the parser to the above map - The attributes from PGModule are inserted into the NetScope of that module PGModule::elaborate_scope_mod_instances_ - Currently these attributes automatically make it into netlist - These attributes are accessible via ivl_scope_attr_cnt and ivl_scope_attr_val from ivl_target.h
2017-03-16 15:41:10 +01:00
cur.file, cur.lineno, attr);
module parameter bind by name.
1999-05-29 04:36:17 +02:00
} else if (cur.parms) {
Better parsing of expressions lists will empty expressoins.
2000-05-23 18:03:13 +02:00
/* If there are no parameters, the parser will be
tricked into thinking it is one empty
parameter. This fixes that. */
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
if ((cur.parms->size() == 1) && (cur.parms->front() == 0)) {
Better parsing of expressions lists will empty expressoins.
2000-05-23 18:03:13 +02:00
delete cur.parms;
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
cur.parms = new list<PExpr*>;
Better parsing of expressions lists will empty expressoins.
2000-05-23 18:03:13 +02:00
}
Use perm_strings for named langiage items.
2004-02-18 18:11:54 +01:00
pform_make_modgate(type, cur_name, overrides,
Catch module instantiation arrays.
2000-02-18 06:15:02 +01:00
cur.parms,
Ranges are ranges, not expression lists. This is a cleanup in preparation for better support of range lists. (cherry picked from commit 8f7cf3255acad55841f8b3725e3786ef49daad68) Conflicts: PTask.h elab_scope.cc elab_sig.cc parse.y pform.cc pform.h pform_types.h Signed-off-by: Stephen Williams <steve@icarus.com>
2012-04-10 23:29:28 +02:00
cur.range.first, cur.range.second,
Add support to handle attributes at module instantiation sites. (* my_fancy_attribute *) foobar1 foobar (clk(clk), rst(rst) ...); - Modifies PGModule to hold the attribute map (can be verified with pform_dump) - pform_make_modgate(s) bind the attributes from the parser to the above map - The attributes from PGModule are inserted into the NetScope of that module PGModule::elaborate_scope_mod_instances_ - Currently these attributes automatically make it into netlist - These attributes are accessible via ivl_scope_attr_cnt and ivl_scope_attr_val from ivl_target.h
2017-03-16 15:41:10 +01:00
cur.file, cur.lineno, attr);
Better parsing of expressions lists will empty expressoins.
2000-05-23 18:03:13 +02:00
Parse and elaborate the concatenate operator in structural contexts, Replace vector<PExpr*> and list<PExpr*> with svector<PExpr*>, evaluate constant expressions with parameters, handle memories as lvalues. Parse task declarations, integer types.
1999-05-10 02:16:57 +02:00
} else {
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
list<PExpr*>*wires = new list<PExpr*>;
Use perm_strings for named langiage items.
2004-02-18 18:11:54 +01:00
pform_make_modgate(type, cur_name, overrides,
Catch module instantiation arrays.
2000-02-18 06:15:02 +01:00
wires,
Ranges are ranges, not expression lists. This is a cleanup in preparation for better support of range lists. (cherry picked from commit 8f7cf3255acad55841f8b3725e3786ef49daad68) Conflicts: PTask.h elab_scope.cc elab_sig.cc parse.y pform.cc pform.h pform_types.h Signed-off-by: Stephen Williams <steve@icarus.com>
2012-04-10 23:29:28 +02:00
cur.range.first, cur.range.second,
Add support to handle attributes at module instantiation sites. (* my_fancy_attribute *) foobar1 foobar (clk(clk), rst(rst) ...); - Modifies PGModule to hold the attribute map (can be verified with pform_dump) - pform_make_modgate(s) bind the attributes from the parser to the above map - The attributes from PGModule are inserted into the NetScope of that module PGModule::elaborate_scope_mod_instances_ - Currently these attributes automatically make it into netlist - These attributes are accessible via ivl_scope_attr_cnt and ivl_scope_attr_val from ivl_target.h
2017-03-16 15:41:10 +01:00
cur.file, cur.lineno, attr);
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
}
delete gates;
}
Rework of internals to carry vectors through nexus instead of single bits. Make the ivl, tgt-vvp and vvp initial changes down this path.
2004-12-11 03:31:25 +01:00
static PGAssign* pform_make_pgassign(PExpr*lval, PExpr*rval,
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
list<PExpr*>*del,
Carry assignment strength to pform.
2000-05-06 17:41:56 +02:00
struct str_pair_t str)
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
{
Fix for pr2924354. Creation of implicit nets requires knowledge of whether an identifier has been declared before it is used. Currently implicit nets are created during elaboration, but by this stage the order of declaration and use is not known. This patch moves the creation of implicit nets into the parser stage.
2010-01-12 21:11:01 +01:00
/* Implicit declaration of nets on the LHS of a continuous
assignment was introduced in IEEE1364-2001. */
if (generation_flag != GN_VER1995)
pform_declare_implicit_nets(lval);
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
list<PExpr*>*wires = new list<PExpr*>;
wires->push_back(lval);
wires->push_back(rval);
Parse and elaborate rise/fall/decay times for gates, and handle the rules for partial lists of times.
1999-08-01 18:34:50 +02:00
PGAssign*cur;
if (del == 0)
cur = new PGAssign(wires);
else
cur = new PGAssign(wires, del);
Carry assignment strength to pform.
2000-05-06 17:41:56 +02:00
cur->strength0(str.str0);
cur->strength1(str.str1);
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
if (pform_cur_generate)
pform_cur_generate->add_gate(cur);
else
Allow modules (and program blocks in particular) to nest. An important advantage of program blocks is its ability to nest within a module. This winds up also allowing modules to nest, which is legal but presumably less used feature.
2012-05-10 04:35:11 +02:00
pform_cur_module.front()->add_gate(cur);
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
Much expression parsing work, mark continuous assigns with source line info, replace some assertion failures with Sorry messages.
1999-05-20 06:31:45 +02:00
return cur;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
void pform_make_pgassign_list(list<PExpr*>*alist,
list<PExpr*>*del,
Carry assignment strength to pform.
2000-05-06 17:41:56 +02:00
struct str_pair_t str,
Change LineInfo to store const C strings.
2000-11-30 18:31:42 +01:00
const char* fn,
continuous assignment lists.
1999-08-27 17:08:37 +02:00
unsigned lineno)
{
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
assert(alist->size() % 2 == 0);
while (! alist->empty()) {
PExpr*lval = alist->front(); alist->pop_front();
PExpr*rval = alist->front(); alist->pop_front();
PGAssign*tmp = pform_make_pgassign(lval, rval, del, str);
FILE_NAME(tmp, fn, lineno);
}
continuous assignment lists.
1999-08-27 17:08:37 +02:00
}
Support reg initial assignment syntax.
1999-12-30 20:06:14 +01:00
/*
Fully support variable initialization in tasks/functions/named blocks.
2016-03-19 14:04:38 +01:00
* This function makes the initial assignment to a variable as given
* in the source. It handles the case where a variable is assigned
* where it is declared, e.g.
Support reg initial assignment syntax.
1999-12-30 20:06:14 +01:00
*
* reg foo = <expr>;
*
Fully support variable initialization in tasks/functions/named blocks.
2016-03-19 14:04:38 +01:00
* In Verilog-2001 this is only supported at the module level, and is
* equivalent to the combination of statements:
Support reg initial assignment syntax.
1999-12-30 20:06:14 +01:00
*
* reg foo;
Spelling fixes.
2003-01-10 04:08:13 +01:00
* initial foo = <expr>;
Support reg initial assignment syntax.
1999-12-30 20:06:14 +01:00
*
Fully support variable initialization in tasks/functions/named blocks.
2016-03-19 14:04:38 +01:00
* In SystemVerilog, variable initializations are allowed in any scope.
* For static variables, initializations are performed before the start
* of simulation. For automatic variables, initializations are performed
* each time the enclosing block is entered. Here we store the variable
* assignments in the current scope, and later elaboration creates an
* initialization block that will be executed at the appropriate time.
*
* This syntax is not part of the IEEE1364-1995 standard, but is
* approved by OVI as enhancement BTF-B14.
Support reg initial assignment syntax.
1999-12-30 20:06:14 +01:00
*/
Fully support variable initialization in tasks/functions/named blocks.
2016-03-19 14:04:38 +01:00
void pform_make_var_init(const struct vlltype&li,
perm_string name, PExpr*expr)
Support reg initial assignment syntax.
1999-12-30 20:06:14 +01:00
{
Allow variable initialization in any scope. This is a SystemVerilog feature, so only allow it when compiling SystemVerilog files.
2012-03-11 23:08:42 +01:00
if (! pform_at_module_level() && !gn_system_verilog()) {
VLerror(li, "error: variable declaration assignments are only "
Rework of automatic task/function support. This patch splits any VVP net functor that needs to access both statically and automatically allocated state into two sub-classes, one for handling operations on statically allocated state, the other for handling operations on automatically allocated state. This undoes the increase in run-time memory use introduced when automatic task/function support was first introduced. This patch also fixes various issues with event handling in automatic scopes. Event expressions in automatic scopes may now reference either statically or automatically allocated variables or arrays, or part selects or word selects thereof. More complex expressions (e.g. containing arithmetic or logical operators, function calls, etc.) are not currently supported. This patch introduces some error checking for language constructs that may not reference automatically allocated variables. Further error checking will follow in a subsequent patch.
2008-10-28 18:52:39 +01:00
"allowed at the module level.");
delete expr;
return;
}
Make reg initializations account for generated scope. During parse, reg initialization may be in generated scopes. Handle that properly.
2008-06-15 06:50:48 +02:00
PWire*cur = pform_get_wire_in_scope(name);
Support reg initial assignment syntax.
1999-12-30 20:06:14 +01:00
if (cur == 0) {
Fully support variable initialization in tasks/functions/named blocks.
2016-03-19 14:04:38 +01:00
VLerror(li, "internal error: var_init to non-register?");
Support reg initial assignment syntax.
1999-12-30 20:06:14 +01:00
delete expr;
return;
}
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
PEIdent*lval = new PEIdent(name);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(lval, li);
Revert "ivl: Allow to initialize variables with other variables (since Verilog-2001)." This reverts commit 610ca95cbede2bc2ebe31ed01b79f4c6b583f496. It turns out that the new feature is actually a bug.
2014-12-03 17:27:01 +01:00
PAssign*ass = new PAssign(lval, expr, true);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(ass, li);
Support reg initial assignment syntax.
1999-12-30 20:06:14 +01:00
Fully support variable initialization in tasks/functions/named blocks.
2016-03-19 14:04:38 +01:00
lexical_scope->var_inits.push_back(ass);
Support reg initial assignment syntax.
1999-12-30 20:06:14 +01:00
}
Add ranges and signed to port list declarations.
2002-05-20 04:06:01 +02:00
/*
* This function is used by the parser when I have port definition of
* the form like this:
*
* input wire signed [7:0] nm;
*
* The port_type, type, signed_flag and range are known all at once,
* so we can create the PWire object all at once instead of piecemeal
* as is done for the old method.
*/
void pform_module_define_port(const struct vlltype&li,
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
perm_string name,
Clean up pform_module_define_port in preparation for new tricks. Get rid of the data_type, signed_flag, and range arguments to the pform_module_define_port because they add no value within the parse.y parser. Cleaning these out will hopefully ease the addition of new functionality.
2014-03-10 03:22:13 +01:00
NetNet::PortType port_kind,
Add ranges and signed to port list declarations.
2002-05-20 04:06:01 +02:00
NetNet::Type type,
Rework port input and inout to use data_type_or_implicit rule for types.
2012-04-13 05:20:37 +02:00
data_type_t*vtype,
Fix for br974 - support SV types in non-ansi port declarations.
2016-04-04 21:40:30 +02:00
list<named_pexpr_t>*attr,
bool keep_attr)
Add ranges and signed to port list declarations.
2002-05-20 04:06:01 +02:00
{
Handle properly parsed structs in module ports.
2012-04-21 17:56:47 +02:00
struct_type_t*struct_type = 0;
Clean up pform_module_define_port in preparation for new tricks. Get rid of the data_type, signed_flag, and range arguments to the pform_module_define_port because they add no value within the parse.y parser. Cleaning these out will hopefully ease the addition of new functionality.
2014-03-10 03:22:13 +01:00
ivl_variable_type_t data_type = IVL_VT_NO_TYPE;
bool signed_flag = false;
Handle properly parsed structs in module ports.
2012-04-21 17:56:47 +02:00
Better handle nesting of scopes inside generate blocks. Within generate schemes it is possible to have nested scopes, even more liberally then outside generate blocks. So see to it that the scopes properly stack with the generate blocks, and that wires and behaviors are put in the right scopes.
2008-06-20 06:31:53 +02:00
PWire*cur = pform_get_wire_in_scope(name);
Add ranges and signed to port list declarations.
2002-05-20 04:06:01 +02:00
if (cur) {
Move strstream to ostringstream for compatibility.
2003-01-14 22:16:18 +01:00
ostringstream msg;
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
msg << name << " definition conflicts with "
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
<< "definition at " << cur->get_fileline()
Move strstream to ostringstream for compatibility.
2003-01-14 22:16:18 +01:00
<< ".";
VLerror(msg.str().c_str());
Add ranges and signed to port list declarations.
2002-05-20 04:06:01 +02:00
return;
}
First pass at support for continuous assign of unpacked net arrays.
2014-03-17 01:08:38 +01:00
// Packed ranges
list<pform_range_t>*prange = 0;
// Unpacked dimensions
list<pform_range_t>*urange = 0;
// If this is an unpacked array, then split out the parts that
// we can send to the PWire object that we create.
if (uarray_type_t*uarr_type = dynamic_cast<uarray_type_t*> (vtype)) {
urange = uarr_type->dims.get();
vtype = uarr_type->base_type;
}
Rework port input and inout to use data_type_or_implicit rule for types.
2012-04-13 05:20:37 +02:00
if (vector_type_t*vec_type = dynamic_cast<vector_type_t*> (vtype)) {
data_type = vec_type->base_type;
signed_flag = vec_type->signed_flag;
First pass at support for continuous assign of unpacked net arrays.
2014-03-17 01:08:38 +01:00
prange = vec_type->pdims.get();
module output ports use data_type_t types. This is in place of ad hoc type information passed to the pform_module_define_port function.
2012-04-16 00:45:49 +02:00
if (vec_type->reg_flag)
type = NetNet::REG;
Rework port input and inout to use data_type_or_implicit rule for types.
2012-04-13 05:20:37 +02:00
} else if (atom2_type_t*atype = dynamic_cast<atom2_type_t*>(vtype)) {
data_type = IVL_VT_BOOL;
signed_flag = atype->signed_flag;
First pass at support for continuous assign of unpacked net arrays.
2014-03-17 01:08:38 +01:00
prange = make_range_from_width(atype->type_code);
Rework port input and inout to use data_type_or_implicit rule for types.
2012-04-13 05:20:37 +02:00
} else if (real_type_t*rtype = dynamic_cast<real_type_t*>(vtype)) {
data_type = IVL_VT_REAL;
signed_flag = true;
First pass at support for continuous assign of unpacked net arrays.
2014-03-17 01:08:38 +01:00
prange = 0;
Rework port input and inout to use data_type_or_implicit rule for types.
2012-04-13 05:20:37 +02:00
if (rtype->type_code != real_type_t::REAL) {
VLerror(li, "sorry: Only real (not shortreal) supported here (%s:%d).",
__FILE__, __LINE__);
}
Merge branch 'pei1'
2012-05-26 01:32:12 +02:00
} else if ((struct_type = dynamic_cast<struct_type_t*>(vtype))) {
Clean up PWire handling of wire data type. / Reword packed type handling
2012-08-03 05:14:55 +02:00
data_type = struct_type->figure_packed_base_type();
Handle properly parsed structs in module ports.
2012-04-21 17:56:47 +02:00
signed_flag = false;
First pass at support for continuous assign of unpacked net arrays.
2014-03-17 01:08:38 +01:00
prange = 0;
Handle properly parsed structs in module ports.
2012-04-21 17:56:47 +02:00
ivl: Enum type can be used in port declarations.
2015-02-05 17:17:33 +01:00
} else if (enum_type_t*enum_type = dynamic_cast<enum_type_t*>(vtype)) {
data_type = enum_type->base_type;
signed_flag = enum_type->signed_flag;
prange = enum_type->range.get();
Rework port input and inout to use data_type_or_implicit rule for types.
2012-04-13 05:20:37 +02:00
} else if (vtype) {
VLerror(li, "sorry: Given type %s not supported here (%s:%d).",
typeid(*vtype).name(), __FILE__, __LINE__);
}
Add support for primitive types of ports. The infrastructure is already there, all that's missing is the syntax in the parser.
2010-03-11 21:22:41 +01:00
// The default type for all flavor of ports is LOGIC.
if (data_type == IVL_VT_NO_TYPE)
data_type = IVL_VT_LOGIC;
Add ranges and signed to port list declarations.
2002-05-20 04:06:01 +02:00
Clean up pform_module_define_port in preparation for new tricks. Get rid of the data_type, signed_flag, and range arguments to the pform_module_define_port because they add no value within the parse.y parser. Cleaning these out will hopefully ease the addition of new functionality.
2014-03-10 03:22:13 +01:00
cur = new PWire(name, type, port_kind, data_type);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(cur, li);
Add ranges and signed to port list declarations.
2002-05-20 04:06:01 +02:00
cur->set_signed(signed_flag);
Handle properly parsed structs in module ports.
2012-04-21 17:56:47 +02:00
if (struct_type) {
Elaborate class_new and (null) expressions This gets the types right for class_new and null expressions, and elaborate them down to the ivl_target.h API.
2012-11-12 02:42:31 +01:00
cur->set_data_type(struct_type);
Handle properly parsed structs in module ports.
2012-04-21 17:56:47 +02:00
First pass at support for continuous assign of unpacked net arrays.
2014-03-17 01:08:38 +01:00
} else if (prange == 0) {
Parse multi-dimension packed arrays to pform.
2012-02-05 01:19:27 +01:00
cur->set_range_scalar((type == NetNet::IMPLICIT) ? SR_PORT : SR_BOTH);
Add ranges and signed to port list declarations.
2002-05-20 04:06:01 +02:00
} else {
First pass at support for continuous assign of unpacked net arrays.
2014-03-17 01:08:38 +01:00
cur->set_range(*prange, (type == NetNet::IMPLICIT) ? SR_PORT : SR_BOTH);
}
if (urange) {
cur->set_unpacked_idx(*urange);
Add ranges and signed to port list declarations.
2002-05-20 04:06:01 +02:00
}
Fix for br974 - support SV types in non-ansi port declarations.
2016-04-04 21:40:30 +02:00
pform_bind_attributes(cur->attributes, attr, keep_attr);
Better handle nesting of scopes inside generate blocks. Within generate schemes it is possible to have nested scopes, even more liberally then outside generate blocks. So see to it that the scopes properly stack with the generate blocks, and that wires and behaviors are put in the right scopes.
2008-06-20 06:31:53 +02:00
pform_put_wire_in_scope(name, cur);
Add ranges and signed to port list declarations.
2002-05-20 04:06:01 +02:00
}
Fix for br974 - support SV types in non-ansi port declarations.
2016-04-04 21:40:30 +02:00
void pform_module_define_port(const struct vlltype&li,
list<pform_port_t>*ports,
NetNet::PortType port_kind,
NetNet::Type type,
data_type_t*vtype,
list<named_pexpr_t>*attr)
{
for (list<pform_port_t>::iterator cur = ports->begin()
; cur != ports->end() ; ++ cur ) {
data_type_t*use_type = vtype;
if (cur->udims)
use_type = new uarray_type_t(vtype, cur->udims);
pform_module_define_port(li, cur->name, port_kind, type, use_type,
attr, true);
if (cur->udims)
delete use_type;
if (cur->expr)
pform_make_var_init(li, cur->name, cur->expr);
}
delete ports;
delete attr;
}
Detect input and input ports declared as reg.
2001-05-25 04:21:34 +02:00
/*
* This function makes a single signal (a wire, a reg, etc) as
* requested by the parser. The name is unscoped, so I attach the
* current scope to it (with the scoped_name function) and I try to
* resolve it with an existing PWire in the scope.
*
* The wire might already exist because of an implicit declaration in
* a module port, i.e.:
*
* module foo (bar...
*
* reg bar;
*
* The output (or other port direction indicator) may or may not have
Spelling fixes.
2003-01-10 04:08:13 +01:00
* been seen already, so I do not do any checking with it yet. But I
Detect input and input ports declared as reg.
2001-05-25 04:21:34 +02:00
* do check to see if the name has already been declared, as this
* function is called for every declaration.
*/
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
Handle nets that are packed structures.
2011-12-18 21:00:18 +01:00
static PWire* pform_get_or_make_wire(const vlltype&li, perm_string name,
NetNet::Type type, NetNet::PortType ptype,
ivl_variable_type_t dtype)
{
PWire*cur = pform_get_wire_in_scope(name);
Fix for br975 - assertion failure due to duplicate declaration of struct var. Added proper error handling for duplicate declarations of all variable types.
2015-05-17 21:54:53 +02:00
// If the wire already exists but isn't yet fully defined,
// carry on adding details.
Fix overzealous detection of duplicate net/variable declarations. As reported by Larry Doolittle on iverilog-devel.
2015-06-07 09:48:33 +02:00
if (cur && (cur->get_data_type() == IVL_VT_NO_TYPE ||
cur->get_wire_type() == NetNet::IMPLICIT) ) {
Handle nets that are packed structures.
2011-12-18 21:00:18 +01:00
// If this is not implicit ("implicit" meaning we don't
// know what the type is yet) then set the type now.
if (type != NetNet::IMPLICIT) {
bool rc = cur->set_wire_type(type);
if (rc == false) {
ostringstream msg;
msg << name << " " << type
<< " definition conflicts with " << cur->get_wire_type()
<< " definition at " << cur->get_fileline()
<< ".";
VLerror(msg.str().c_str());
}
FILE_NAME(cur, li.text, li.first_line);
}
return cur;
}
Fix for br975 - assertion failure due to duplicate declaration of struct var. Added proper error handling for duplicate declarations of all variable types.
2015-05-17 21:54:53 +02:00
// If the wire already exists and is fully defined, this
// must be a redeclaration. Start again with a new wire.
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
// The error will be reported when we add the new wire
// to the scope. Do not delete the old wire - it will
// remain in the local symbol map.
Fix for br975 - assertion failure due to duplicate declaration of struct var. Added proper error handling for duplicate declarations of all variable types.
2015-05-17 21:54:53 +02:00
Handle nets that are packed structures.
2011-12-18 21:00:18 +01:00
cur = new PWire(name, type, ptype, dtype);
FILE_NAME(cur, li.text, li.first_line);
pform_put_wire_in_scope(name, cur);
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
Handle nets that are packed structures.
2011-12-18 21:00:18 +01:00
return cur;
}
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
/*
Spelling fixes only comments and documentation some punctuation and capitalization for good measure Changelogs are purposefully untouched
2008-01-29 21:19:59 +01:00
* this is the basic form of pform_makewire. This takes a single simple
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
* name, port type, net type, data type, and attributes, and creates
* the variable/net. Other forms of pform_makewire ultimately call
* this one to create the wire and stash it.
*/
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
void pform_makewire(const vlltype&li, perm_string name,
More 2001 port declaration support.
2003-04-28 19:50:57 +02:00
NetNet::Type type, NetNet::PortType pt,
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
ivl_variable_type_t dt,
Enumeration element values can be expressions Allow more complex enumeration expressions, which means putting off the evaluation of the expression values until elaboration.
2010-11-13 03:47:06 +01:00
list<named_pexpr_t>*attr)
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
{
Handle nets that are packed structures.
2011-12-18 21:00:18 +01:00
PWire*cur = pform_get_or_make_wire(li, name, type, pt, dt);
Initialize assignments of reals Support initialization assignments of real value variables. In the process, clean up the processing of real variable declarations in the parser. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-08-05 06:50:06 +02:00
if (! cur) {
cur = new PWire(name, type, pt, dt);
Improve error message about signal type conflict. When the parser detects a signal type conflict, print a more useful error message. In the process, be more careful with what line number is actually attributed to the declaration.
2008-11-18 23:34:34 +01:00
FILE_NAME(cur, li.text, li.first_line);
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
Data type handling of module ports. Fix data type handling of module ports. When ports are declared as ports and given data types in different statements, the parser incorrectly (and silently) dropped the intended data type for the default LOGIC type.
2008-01-04 05:13:56 +01:00
bool flag;
Initialize assignments of reals Support initialization assignments of real value variables. In the process, clean up the processing of real variable declarations in the parser. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-08-05 06:50:06 +02:00
switch (dt) {
case IVL_VT_REAL:
Data type handling of module ports. Fix data type handling of module ports. When ports are declared as ports and given data types in different statements, the parser incorrectly (and silently) dropped the intended data type for the default LOGIC type.
2008-01-04 05:13:56 +01:00
flag = cur->set_data_type(dt);
if (flag == false) {
cerr << cur->get_fileline() << ": internal error: "
<< " wire data type handling mismatch. Cannot change "
<< cur->get_data_type()
<< " to " << dt << "." << endl;
}
ivl_assert(*cur, flag);
Parse multi-dimension packed arrays to pform.
2012-02-05 01:19:27 +01:00
cur->set_range_scalar(SR_NET);
Initialize assignments of reals Support initialization assignments of real value variables. In the process, clean up the processing of real variable declarations in the parser. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-08-05 06:50:06 +02:00
cur->set_signed(true);
break;
default:
break;
}
Verilog 2001 attriubtes on nets/wires.
2002-05-24 06:36:23 +02:00
if (attr) {
Enumeration element values can be expressions Allow more complex enumeration expressions, which means putting off the evaluation of the expression values until elaboration.
2010-11-13 03:47:06 +01:00
for (list<named_pexpr_t>::iterator attr_cur = attr->begin()
; attr_cur != attr->end() ; ++attr_cur) {
cur->attributes[attr_cur->name] = attr_cur->parm;
Verilog 2001 attriubtes on nets/wires.
2002-05-24 06:36:23 +02:00
}
}
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
/*
* This form takes a list of names and some type information, and
Fix range handling/checking and add a flag to allow deprecated port syntax. This patch is rather large and fixes a couple of problems. The major change is that instead of keeping all the range specifications in a list that is later processed the information is now kept as individual entries for the port and net definitions. This allows easier checking for multiple definitions (pr1660028), more detailed error messages and the ability to pass the now deprecated style of a scalar I/O definition used with a vectored net definition. These changes did require extra code to prevent a single definition from setting the range values in more than on place. When using the new ANSI-C style of port declarations (1364-2001 12.3.4 list_of_port_declarations) the compiler ensures that you do not redeclare the port in the body (it is already completely defined). This caught a few errors in the test suite (pr859 and sqrt32*). The flag to disable the normal port checking and allow the deprecated port syntax is -gno-io-range-error. This will print a warning for the case of a scalar port with a vectored definition in the body. All other cases are still considered an error.
2007-08-22 04:52:42 +02:00
* generates a bunch of variables/nets. We use the basic
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
* pform_makewire above.
*/
Remove C++ string from variable lists.
2000-10-31 18:00:04 +01:00
void pform_makewire(const vlltype&li,
Ranges are ranges, not expression lists. This is a cleanup in preparation for better support of range lists. (cherry picked from commit 8f7cf3255acad55841f8b3725e3786ef49daad68) Conflicts: PTask.h elab_scope.cc elab_sig.cc parse.y pform.cc pform.h pform_types.h Signed-off-by: Stephen Williams <steve@icarus.com>
2012-04-10 23:29:28 +02:00
list<pform_range_t>*range,
Add support for signed ports and nets.
2003-02-02 20:02:39 +01:00
bool signed_flag,
More identifier lists use perm_strings.
2004-05-25 21:21:06 +02:00
list<perm_string>*names,
Verilog 2001 attriubtes on nets/wires.
2002-05-24 06:36:23 +02:00
NetNet::Type type,
More 2001 port declaration support.
2003-04-28 19:50:57 +02:00
NetNet::PortType pt,
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
ivl_variable_type_t dt,
Enumeration element values can be expressions Allow more complex enumeration expressions, which means putting off the evaluation of the expression values until elaboration.
2010-11-13 03:47:06 +01:00
list<named_pexpr_t>*attr,
Fix range handling/checking and add a flag to allow deprecated port syntax. This patch is rather large and fixes a couple of problems. The major change is that instead of keeping all the range specifications in a list that is later processed the information is now kept as individual entries for the port and net definitions. This allows easier checking for multiple definitions (pr1660028), more detailed error messages and the ability to pass the now deprecated style of a scalar I/O definition used with a vectored net definition. These changes did require extra code to prevent a single definition from setting the range values in more than on place. When using the new ANSI-C style of port declarations (1364-2001 12.3.4 list_of_port_declarations) the compiler ensures that you do not redeclare the port in the body (it is already completely defined). This caught a few errors in the test suite (pr859 and sqrt32*). The flag to disable the normal port checking and allow the deprecated port syntax is -gno-io-range-error. This will print a warning for the case of a scalar port with a vectored definition in the body. All other cases are still considered an error.
2007-08-22 04:52:42 +02:00
PWSRType rt)
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
{
More identifier lists use perm_strings.
2004-05-25 21:21:06 +02:00
for (list<perm_string>::iterator cur = names->begin()
Change iterators to use prefix ++ since it is more efficient. This patch changes all the iterator code to use a prefix ++ instead of postfix since it is more efficient (no need for a temporary). It is likely that the compiler could optimize this away, but lets make it efficient from the start.
2010-10-23 23:57:59 +02:00
; cur != names->end() ; ++ cur ) {
More identifier lists use perm_strings.
2004-05-25 21:21:06 +02:00
perm_string txt = *cur;
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
pform_makewire(li, txt, type, pt, dt, attr);
Fix range handling/checking and add a flag to allow deprecated port syntax. This patch is rather large and fixes a couple of problems. The major change is that instead of keeping all the range specifications in a list that is later processed the information is now kept as individual entries for the port and net definitions. This allows easier checking for multiple definitions (pr1660028), more detailed error messages and the ability to pass the now deprecated style of a scalar I/O definition used with a vectored net definition. These changes did require extra code to prevent a single definition from setting the range values in more than on place. When using the new ANSI-C style of port declarations (1364-2001 12.3.4 list_of_port_declarations) the compiler ensures that you do not redeclare the port in the body (it is already completely defined). This caught a few errors in the test suite (pr859 and sqrt32*). The flag to disable the normal port checking and allow the deprecated port syntax is -gno-io-range-error. This will print a warning for the case of a scalar port with a vectored definition in the body. All other cases are still considered an error.
2007-08-22 04:52:42 +02:00
/* This has already been done for real variables. */
if (dt != IVL_VT_REAL) {
Use data_type_t instead of raw type bits.
2012-09-03 18:13:52 +02:00
pform_set_net_range(txt, type, range, signed_flag, dt, rt, 0);
Fix range handling/checking and add a flag to allow deprecated port syntax. This patch is rather large and fixes a couple of problems. The major change is that instead of keeping all the range specifications in a list that is later processed the information is now kept as individual entries for the port and net definitions. This allows easier checking for multiple definitions (pr1660028), more detailed error messages and the ability to pass the now deprecated style of a scalar I/O definition used with a vectored net definition. These changes did require extra code to prevent a single definition from setting the range values in more than on place. When using the new ANSI-C style of port declarations (1364-2001 12.3.4 list_of_port_declarations) the compiler ensures that you do not redeclare the port in the body (it is already completely defined). This caught a few errors in the test suite (pr859 and sqrt32*). The flag to disable the normal port checking and allow the deprecated port syntax is -gno-io-range-error. This will print a warning for the case of a scalar port with a vectored definition in the body. All other cases are still considered an error.
2007-08-22 04:52:42 +02:00
}
Remove C++ string from variable lists.
2000-10-31 18:00:04 +01:00
}
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
Remove C++ string from variable lists.
2000-10-31 18:00:04 +01:00
delete names;
Cleanup various style issues. This patch cleans up some style issues: no need to check that a value is defined before freeing or deleting it, use C++ style casts, make sure to NULL terminate strncpy(), empty() is faster than size() for size == 0 or size >= 0 checks, re-scope some variables, etc.
2010-04-14 06:29:15 +02:00
delete range;
Fix for br930 - support attributes on old-style port declarations.
2013-05-19 10:16:24 +02:00
delete attr;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
/*
* This form makes nets with delays and continuous assignments.
*/
Properly parse net_decl assignments with delays.
2001-11-29 18:37:51 +01:00
void pform_makewire(const vlltype&li,
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
list<PExpr*>*delay,
Drive strengths for continuous assignments.
2002-01-12 05:03:39 +01:00
str_pair_t str,
Properly parse net_decl assignments with delays.
2001-11-29 18:37:51 +01:00
net_decl_assign_t*decls,
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
NetNet::Type type,
Use data_type_t instead of raw type bits.
2012-09-03 18:13:52 +02:00
data_type_t*data_type)
Properly parse net_decl assignments with delays.
2001-11-29 18:37:51 +01:00
{
Use data_type_t instead of raw type bits.
2012-09-03 18:13:52 +02:00
// The decls pointer is a circularly linked list.
Properly parse net_decl assignments with delays.
2001-11-29 18:37:51 +01:00
net_decl_assign_t*first = decls->next;
Use data_type_t instead of raw type bits.
2012-09-03 18:13:52 +02:00
list<perm_string>*names = new list<perm_string>;
Properly parse net_decl assignments with delays.
2001-11-29 18:37:51 +01:00
Use data_type_t instead of raw type bits.
2012-09-03 18:13:52 +02:00
// Go through the circularly linked list non-destructively.
do {
pform_makewire(li, first->name, type, NetNet::NOT_A_PORT, IVL_VT_NO_TYPE, 0);
names->push_back(first->name);
first = first->next;
} while (first != decls->next);
Properly parse net_decl assignments with delays.
2001-11-29 18:37:51 +01:00
packages can contain variables.
2013-04-08 01:38:48 +02:00
// The pform_set_data_type function will delete the names list.
Use data_type_t instead of raw type bits.
2012-09-03 18:13:52 +02:00
pform_set_data_type(li, data_type, names, type, 0);
// This time, go through the list, deleting cells as I'm done.
first = decls->next;
decls->next = 0;
while (first) {
net_decl_assign_t*next = first->next;
Attach disciplines to wires Allow discipline declaration of nets that attaches the discipline to a new wire or a wire that is already declared.
2008-05-12 02:30:33 +02:00
PWire*cur = pform_get_wire_in_scope(first->name);
Properly parse net_decl assignments with delays.
2001-11-29 18:37:51 +01:00
if (cur != 0) {
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
PEIdent*lval = new PEIdent(first->name);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(lval, li.text, li.first_line);
Handle synthesis of concatenation expressions.
2005-05-06 02:25:13 +02:00
PGAssign*ass = pform_make_pgassign(lval, first->expr,
delay, str);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(ass, li.text, li.first_line);
Properly parse net_decl assignments with delays.
2001-11-29 18:37:51 +01:00
}
delete first;
first = next;
}
}
packages can contain variables.
2013-04-08 01:38:48 +02:00
/*
More spelling fixes Mostly comments Changs "initilzers" in a string visible with debug_elaborate. Includes a few British->American changes in the root directory only.
2014-01-31 01:16:19 +01:00
* This should eventually replace the form above that takes a
packages can contain variables.
2013-04-08 01:38:48 +02:00
* net_decl_assign_t argument.
*/
void pform_makewire(const struct vlltype&li,
Enable variable declarations/initialisations in the compilation unit scope.
2018-02-18 15:09:03 +01:00
std::list<PExpr*>*delay,
str_pair_t str,
packages can contain variables.
2013-04-08 01:38:48 +02:00
std::list<decl_assignment_t*>*assign_list,
NetNet::Type type,
data_type_t*data_type)
{
Support separate compilation units in SystemVerilog. The compilation unit scope is now treated as a specialised form of package (with an automatically generated name). All items declared outside a design element are added to the current compilation unit package. Apart from when searching for a symbol, once we get into elaboration we can treat these just like any other package.
2017-10-21 16:04:25 +02:00
if (is_compilation_unit(lexical_scope) && !gn_system_verilog()) {
Fix for br992 - prevent assertion/crash on declarations outside a module. parse.y has been updated to allow declarations outside a module (legal in SystemVerilog), but not all types of declaration are supported yet. Output a sorry or error message as appropriate.
2015-08-21 00:55:00 +02:00
VLerror(li, "error: variable declarations must be contained within a module.");
return;
}
packages can contain variables.
2013-04-08 01:38:48 +02:00
list<perm_string>*names = new list<perm_string>;
for (list<decl_assignment_t*>::iterator cur = assign_list->begin()
; cur != assign_list->end() ; ++ cur) {
decl_assignment_t* curp = *cur;
Support dynamic array initialisation in variable declarations.
2019-09-16 21:35:27 +02:00
pform_makewire(li, curp->name, type, NetNet::NOT_A_PORT, IVL_VT_NO_TYPE, 0);
pform_set_reg_idx(curp->name, &curp->index);
packages can contain variables.
2013-04-08 01:38:48 +02:00
names->push_back(curp->name);
}
pform_set_data_type(li, data_type, names, type, 0);
while (! assign_list->empty()) {
decl_assignment_t*first = assign_list->front();
assign_list->pop_front();
Enable variable declarations/initialisations in the compilation unit scope.
2018-02-18 15:09:03 +01:00
if (PExpr*expr = first->expr.release()) {
if (type == NetNet::REG || type == NetNet::IMPLICIT_REG) {
pform_make_var_init(li, first->name, expr);
} else {
PEIdent*lval = new PEIdent(first->name);
FILE_NAME(lval, li.text, li.first_line);
PGAssign*ass = pform_make_pgassign(lval, expr, delay, str);
FILE_NAME(ass, li.text, li.first_line);
}
}
packages can contain variables.
2013-04-08 01:38:48 +02:00
delete first;
}
}
Elaborate task input ports.
1999-07-24 04:11:19 +02:00
/*
* This function is called by the parser to create task ports. The
* resulting wire (which should be a register) is put into a list to
* be packed into the task parameter list.
*
* It is possible that the wire (er, register) was already created,
* but we know that if the name matches it is a part of the current
* task, so in that case I just assign direction to it.
*
Add functions up to elaboration (Ed Carter)
1999-07-31 21:14:47 +02:00
* The following example demonstrates some of the issues:
Elaborate task input ports.
1999-07-24 04:11:19 +02:00
*
* task foo;
* input a;
* reg a, b;
* input b;
* [...]
* endtask
*
* This function is called when the parser matches the "input a" and
* the "input b" statements. For ``a'', this function is called before
* the wire is declared as a register, so I create the foo.a
* wire. For ``b'', I will find that there is already a foo.b and I
* just set the port direction. In either case, the ``reg a, b''
Add functions up to elaboration (Ed Carter)
1999-07-31 21:14:47 +02:00
* statement is caught by the block_item non-terminal and processed
* there.
*
* Ports are implicitly type reg, because it must be possible for the
* port to act as an l-value in a procedural assignment. It is obvious
* for output and inout ports that the type is reg, because the task
* only contains behavior (no structure) to a procedural assignment is
misspelled comment.
1999-07-31 21:15:21 +02:00
* the *only* way to affect the output. It is less obvious for input
Add functions up to elaboration (Ed Carter)
1999-07-31 21:14:47 +02:00
* ports, but in practice an input port receives its value as if by a
* procedural assignment from the calling behavior.
*
* This function also handles the input ports of function
* definitions. Input ports to function definitions have the same
* constraints as those of tasks, so this works fine. Functions have
* no output or inout ports.
Elaborate task input ports.
1999-07-24 04:11:19 +02:00
*/
Handle task/function default expressions in parsing/pform. This gets it to (but not through) the elaborator.
2013-09-14 02:04:25 +02:00
vector<pform_tf_port_t>*pform_make_task_ports(const struct vlltype&loc,
Remove svector template from port handling.
2013-02-25 03:06:12 +01:00
NetNet::PortType pt,
ivl_variable_type_t vtype,
bool signed_flag,
list<pform_range_t>*range,
list<perm_string>*names,
bool isint)
Elaborate task input ports.
1999-07-24 04:11:19 +02:00
{
Bunches more SystemVerilog syntax.
2012-03-10 03:54:05 +01:00
assert(pt != NetNet::PIMPLICIT && pt != NetNet::NOT_A_PORT);
Handle integers at task parameters.
1999-09-10 07:02:09 +02:00
assert(names);
Handle task/function default expressions in parsing/pform. This gets it to (but not through) the elaborator.
2013-09-14 02:04:25 +02:00
vector<pform_tf_port_t>*res = new vector<pform_tf_port_t>(0);
More identifier lists use perm_strings.
2004-05-25 21:21:06 +02:00
for (list<perm_string>::iterator cur = names->begin()
Change iterators to use prefix ++ since it is more efficient. This patch changes all the iterator code to use a prefix ++ instead of postfix since it is more efficient (no need for a temporary). It is likely that the compiler could optimize this away, but lets make it efficient from the start.
2010-10-23 23:57:59 +02:00
; cur != names->end() ; ++ cur ) {
Elaborate task input ports.
1999-07-24 04:11:19 +02:00
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
perm_string name = *cur;
Elaborate task input ports.
1999-07-24 04:11:19 +02:00
/* Look for a preexisting wire. If it exists, set the
port direction. If not, create it. */
Better handle nesting of scopes inside generate blocks. Within generate schemes it is possible to have nested scopes, even more liberally then outside generate blocks. So see to it that the scopes properly stack with the generate blocks, and that wires and behaviors are put in the right scopes.
2008-06-20 06:31:53 +02:00
PWire*curw = pform_get_wire_in_scope(name);
Elaborate task input ports.
1999-07-24 04:11:19 +02:00
if (curw) {
curw->set_port_type(pt);
} else {
task/function ports can have types.
2006-03-30 07:22:34 +02:00
curw = new PWire(name, NetNet::IMPLICIT_REG, pt, vtype);
Parse array literals / rearrange task declaration rules.
2012-02-20 02:31:15 +01:00
FILE_NAME(curw, loc);
Better handle nesting of scopes inside generate blocks. Within generate schemes it is possible to have nested scopes, even more liberally then outside generate blocks. So see to it that the scopes properly stack with the generate blocks, and that wires and behaviors are put in the right scopes.
2008-06-20 06:31:53 +02:00
pform_put_wire_in_scope(name, curw);
Elaborate task input ports.
1999-07-24 04:11:19 +02:00
}
Task/functions can have signed ports.
2003-06-13 02:27:09 +02:00
curw->set_signed(signed_flag);
Changes for pform.cc First area of Change for "Microsoft Visual Studio Express 2015 RC Web" was for compiling with error when NDEBUG defined. The second and third areas of change for "Microsoft Visual Studio Express 2015 RC Web", the dynamic_cast has to come first so parpkg_test.v, parpkg_test1.v, parpkg_test2.v would pass.
2015-07-10 18:50:38 +02:00
if (isint) {
Fix shadow warning introduced by MVSE 2015 hacks.
2015-08-08 00:05:02 +02:00
bool flag = curw->set_wire_type(NetNet::INTEGER);
assert(flag);
Changes for pform.cc First area of Change for "Microsoft Visual Studio Express 2015 RC Web" was for compiling with error when NDEBUG defined. The second and third areas of change for "Microsoft Visual Studio Express 2015 RC Web", the dynamic_cast has to come first so parpkg_test.v, parpkg_test1.v, parpkg_test2.v would pass.
2015-07-10 18:50:38 +02:00
}
Task/functions can have signed ports.
2003-06-13 02:27:09 +02:00
Elaborate task input ports.
1999-07-24 04:11:19 +02:00
/* If there is a range involved, it needs to be set. */
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
if (range) {
Ranges are ranges, not expression lists. This is a cleanup in preparation for better support of range lists. (cherry picked from commit 8f7cf3255acad55841f8b3725e3786ef49daad68) Conflicts: PTask.h elab_scope.cc elab_sig.cc parse.y pform.cc pform.h pform_types.h Signed-off-by: Stephen Williams <steve@icarus.com>
2012-04-10 23:29:28 +02:00
curw->set_range(*range, SR_PORT);
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
}
Elaborate task input ports.
1999-07-24 04:11:19 +02:00
Handle task/function default expressions in parsing/pform. This gets it to (but not through) the elaborator.
2013-09-14 02:04:25 +02:00
res->push_back(pform_tf_port_t(curw));
Elaborate task input ports.
1999-07-24 04:11:19 +02:00
}
Cleanup various style issues. This patch cleans up some style issues: no need to check that a value is defined before freeing or deleting it, use C++ style casts, make sure to NULL terminate strncpy(), empty() is faster than size() for size == 0 or size >= 0 checks, re-scope some variables, etc.
2010-04-14 06:29:15 +02:00
delete range;
Elaborate task input ports.
1999-07-24 04:11:19 +02:00
return res;
}
Handle task/function default expressions in parsing/pform. This gets it to (but not through) the elaborator.
2013-09-14 02:04:25 +02:00
static vector<pform_tf_port_t>*do_make_task_ports(const struct vlltype&loc,
Elaborate class task and function methods. The parse of class methods already works, this patch forms the methods into their own scopes, and elaborates those scopes. The "this"
2013-03-15 04:08:32 +01:00
NetNet::PortType pt,
ivl_variable_type_t var_type,
data_type_t*data_type,
list<perm_string>*names)
{
assert(pt != NetNet::PIMPLICIT && pt != NetNet::NOT_A_PORT);
assert(names);
Handle task/function default expressions in parsing/pform. This gets it to (but not through) the elaborator.
2013-09-14 02:04:25 +02:00
vector<pform_tf_port_t>*res = new vector<pform_tf_port_t>(0);
Elaborate class task and function methods. The parse of class methods already works, this patch forms the methods into their own scopes, and elaborates those scopes. The "this"
2013-03-15 04:08:32 +01:00
for (list<perm_string>::iterator cur = names->begin()
; cur != names->end() ; ++cur) {
perm_string name = *cur;
PWire*curw = pform_get_wire_in_scope(name);
if (curw) {
curw->set_port_type(pt);
} else {
curw = new PWire(name, NetNet::IMPLICIT_REG, pt, var_type);
FILE_NAME(curw, loc);
curw->set_data_type(data_type);
pform_put_wire_in_scope(name, curw);
}
Handle task/function default expressions in parsing/pform. This gets it to (but not through) the elaborator.
2013-09-14 02:04:25 +02:00
res->push_back(pform_tf_port_t(curw));
Elaborate class task and function methods. The parse of class methods already works, this patch forms the methods into their own scopes, and elaborates those scopes. The "this"
2013-03-15 04:08:32 +01:00
}
return res;
}
Handle task/function default expressions in parsing/pform. This gets it to (but not through) the elaborator.
2013-09-14 02:04:25 +02:00
vector<pform_tf_port_t>*pform_make_task_ports(const struct vlltype&loc,
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
NetNet::PortType pt,
data_type_t*vtype,
list<perm_string>*names)
{
ivl: Unpacked array typedefs are correctly recognized when used in function parameters.
2015-01-13 10:07:16 +01:00
vector<pform_tf_port_t>*ret = NULL;
std::list<pform_range_t>*unpacked_dims = NULL;
if (uarray_type_t*uarray = dynamic_cast<uarray_type_t*> (vtype)) {
unpacked_dims = uarray->dims.get();
vtype = uarray->base_type;
}
Rework data_type parsing to bring integer vectors into data_type_t method. This adds the vector_type_t and real_type_t types to handle vector and real types in tf_port items. This cleans up a lot of the parsing for these items.
2012-02-26 07:05:00 +01:00
if (atom2_type_t*atype = dynamic_cast<atom2_type_t*> (vtype)) {
Ranges are ranges, not expression lists. This is a cleanup in preparation for better support of range lists. (cherry picked from commit 8f7cf3255acad55841f8b3725e3786ef49daad68) Conflicts: PTask.h elab_scope.cc elab_sig.cc parse.y pform.cc pform.h pform_types.h Signed-off-by: Stephen Williams <steve@icarus.com>
2012-04-10 23:29:28 +02:00
list<pform_range_t>*range_tmp = make_range_from_width(atype->type_code);
ivl: Unpacked array typedefs are correctly recognized when used in function parameters.
2015-01-13 10:07:16 +01:00
ret = pform_make_task_ports(loc, pt, IVL_VT_BOOL,
Rework data_type parsing to bring integer vectors into data_type_t method. This adds the vector_type_t and real_type_t types to handle vector and real types in tf_port items. This cleans up a lot of the parsing for these items.
2012-02-26 07:05:00 +01:00
atype->signed_flag,
range_tmp, names);
}
if (vector_type_t*vec_type = dynamic_cast<vector_type_t*> (vtype)) {
ivl: Unpacked array typedefs are correctly recognized when used in function parameters.
2015-01-13 10:07:16 +01:00
ret = pform_make_task_ports(loc, pt, vec_type->base_type,
Rework data_type parsing to bring integer vectors into data_type_t method. This adds the vector_type_t and real_type_t types to handle vector and real types in tf_port items. This cleans up a lot of the parsing for these items.
2012-02-26 07:05:00 +01:00
vec_type->signed_flag,
copy_range(vec_type->pdims.get()),
A time variable is always unsigned and pass the integer property
2013-04-30 23:04:57 +02:00
names, vec_type->integer_flag);
Rework data_type parsing to bring integer vectors into data_type_t method. This adds the vector_type_t and real_type_t types to handle vector and real types in tf_port items. This cleans up a lot of the parsing for these items.
2012-02-26 07:05:00 +01:00
}
Rework rules for variable_dimensions, and support more syntax.
2012-03-03 03:34:43 +01:00
if (/*real_type_t*real_type = */ dynamic_cast<real_type_t*> (vtype)) {
ivl: Unpacked array typedefs are correctly recognized when used in function parameters.
2015-01-13 10:07:16 +01:00
ret = pform_make_task_ports(loc, pt, IVL_VT_REAL,
Rework data_type parsing to bring integer vectors into data_type_t method. This adds the vector_type_t and real_type_t types to handle vector and real types in tf_port items. This cleans up a lot of the parsing for these items.
2012-02-26 07:05:00 +01:00
true, 0, names);
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
}
Fix for br932 - support string types in task input ports.
2013-06-14 00:18:23 +02:00
if (dynamic_cast<string_type_t*> (vtype)) {
ivl: Unpacked array typedefs are correctly recognized when used in function parameters.
2015-01-13 10:07:16 +01:00
ret = pform_make_task_ports(loc, pt, IVL_VT_STRING,
Fix for br932 - support string types in task input ports.
2013-06-14 00:18:23 +02:00
false, 0, names);
}
Elaborate class task and function methods. The parse of class methods already works, this patch forms the methods into their own scopes, and elaborates those scopes. The "this"
2013-03-15 04:08:32 +01:00
if (class_type_t*class_type = dynamic_cast<class_type_t*> (vtype)) {
ivl: Unpacked array typedefs are correctly recognized when used in function parameters.
2015-01-13 10:07:16 +01:00
ret = do_make_task_ports(loc, pt, IVL_VT_CLASS, class_type, names);
Elaborate class task and function methods. The parse of class methods already works, this patch forms the methods into their own scopes, and elaborates those scopes. The "this"
2013-03-15 04:08:32 +01:00
}
If ret is already defined then don't overwrite it.
2015-12-20 21:27:41 +01:00
if (! ret) {
ret = do_make_task_ports(loc, pt, IVL_VT_NO_TYPE, vtype, names);
}
ivl: Unpacked array typedefs are correctly recognized when used in function parameters.
2015-01-13 10:07:16 +01:00
if (unpacked_dims) {
for (list<perm_string>::iterator cur = names->begin()
; cur != names->end() ; ++ cur ) {
PWire*wire = pform_get_wire_in_scope(*cur);
wire->set_unpacked_idx(*unpacked_dims);
}
}
delete names;
return ret;
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
}
Implement increment/decrement statements. During parse/pform processing, convert increment statements to the equivalent compressed assignment statement. This is less weird for elaboration processing and better expresses what is going on.
2012-02-20 03:54:58 +01:00
/*
* The parser calls this in the rule that matches increment/decrement
* statements. The rule that does the matching creates a PEUnary with
* all the information we need, but here we convert that expression to
* a compressed assignment statement.
*/
PAssign* pform_compressed_assign_from_inc_dec(const struct vlltype&loc, PExpr*exp)
{
PEUnary*expu = dynamic_cast<PEUnary*> (exp);
ivl_assert(*exp, expu != 0);
char use_op = 0;
switch (expu->get_op()) {
case 'i':
case 'I':
use_op = '+';
break;
case 'd':
case 'D':
use_op = '-';
break;
default:
ivl_assert(*exp, 0);
break;
}
PExpr*lval = expu->get_expr();
PExpr*rval = new PENumber(new verinum((uint64_t)1, 1));
FILE_NAME(rval, loc);
PAssign*tmp = new PAssign(lval, use_op, rval);
FILE_NAME(tmp, loc);
delete exp;
return tmp;
}
Addtrbute keys are perm_strings.
2004-02-20 19:53:33 +01:00
void pform_set_attrib(perm_string name, perm_string key, char*value)
NetAssign handles lvalues as pin links instead of a signal pointer, Wire attributes added, Ability to parse UDP descriptions added, XNF generates EXT records for signals with the PAD attribute.
1998-11-23 01:20:22 +01:00
{
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
if (PWire*cur = lexical_scope->wires_find(name)) {
Add language support for Verilog-2001 attribute syntax. Hook this support into existing $attribute handling, and add number and void value types. Add to the ivl_target API new functions for access of complex attributes attached to gates.
2002-05-23 05:08:50 +02:00
cur->attributes[key] = new PEString(value);
Fix support for attaching attributes to primitive gates.
1999-12-11 06:45:41 +01:00
Allow modules (and program blocks in particular) to nest. An important advantage of program blocks is its ability to nest within a module. This winds up also allowing modules to nest, which is legal but presumably less used feature.
2012-05-10 04:35:11 +02:00
} else if (PGate*curg = pform_cur_module.front()->get_gate(name)) {
Shadow reduction part 2 Continue cleaning up shadowed variables, flagged by turning on -Wshadow. No intended change in functionality. Patch looks right, and is tested to compile and run on my machine. No regressions in test suite.
2008-10-13 18:51:05 +02:00
curg->attributes[key] = new PEString(value);
Fix support for attaching attributes to primitive gates.
1999-12-11 06:45:41 +01:00
} else {
Make lexical token STRING new based. The STRING lexical token was malloc based, but then was passed to routines that are expecting a new based result. This patch standardizes on a new/delete based approach.
2009-01-09 02:03:33 +01:00
delete[] value;
Fix support for attaching attributes to primitive gates.
1999-12-11 06:45:41 +01:00
VLerror("Unable to match name for setting attribute.");
}
NetAssign handles lvalues as pin links instead of a signal pointer, Wire attributes added, Ability to parse UDP descriptions added, XNF generates EXT records for signals with the PAD attribute.
1998-11-23 01:20:22 +01:00
}
Elaborate UDP devices, Support UDP type attributes, and pass those attributes to nodes that are instantiated by elaboration, Put modules into a map instead of a simple list.
1998-12-01 01:42:13 +01:00
/*
* Set the attribute of a TYPE. This is different from an object in
* that this applies to every instantiation of the given type.
*/
Use perm_strings for named langiage items.
2004-02-18 18:11:54 +01:00
void pform_set_type_attrib(perm_string name, const string&key,
Add language support for Verilog-2001 attribute syntax. Hook this support into existing $attribute handling, and add number and void value types. Add to the ivl_target API new functions for access of complex attributes attached to gates.
2002-05-23 05:08:50 +02:00
char*value)
Elaborate UDP devices, Support UDP type attributes, and pass those attributes to nodes that are instantiated by elaboration, Put modules into a map instead of a simple list.
1998-12-01 01:42:13 +01:00
{
Use perm_strings for named langiage items.
2004-02-18 18:11:54 +01:00
map<perm_string,PUdp*>::const_iterator udp = pform_primitives.find(name);
Add automatic module libraries.
2001-10-21 01:02:39 +02:00
if (udp == pform_primitives.end()) {
Elaborate UDP devices, Support UDP type attributes, and pass those attributes to nodes that are instantiated by elaboration, Put modules into a map instead of a simple list.
1998-12-01 01:42:13 +01:00
VLerror("type name is not (yet) defined.");
Make lexical token STRING new based. The STRING lexical token was malloc based, but then was passed to routines that are expecting a new based result. This patch standardizes on a new/delete based approach.
2009-01-09 02:03:33 +01:00
delete[] value;
Elaborate UDP devices, Support UDP type attributes, and pass those attributes to nodes that are instantiated by elaboration, Put modules into a map instead of a simple list.
1998-12-01 01:42:13 +01:00
return;
}
Add language support for Verilog-2001 attribute syntax. Hook this support into existing $attribute handling, and add number and void value types. Add to the ivl_target API new functions for access of complex attributes attached to gates.
2002-05-23 05:08:50 +02:00
(*udp).second ->attributes[key] = new PEString(value);
Elaborate UDP devices, Support UDP type attributes, and pass those attributes to nodes that are instantiated by elaboration, Put modules into a map instead of a simple list.
1998-12-01 01:42:13 +01:00
}
Clean up interface of the PWire class, Properly match wire ranges.
1999-06-17 07:34:42 +02:00
/*
* This function attaches a memory index range to an existing
* register. (The named wire must be a register.
*/
Get unpacked arrays working.
2012-05-26 00:58:29 +02:00
void pform_set_reg_idx(perm_string name, list<pform_range_t>*indices)
Add memories to the parse and elaboration phases.
1999-04-19 03:59:36 +02:00
{
Rework of lexical scope handling in parser. This patch modifies the parser to use a single stack to track lexical scopes, rather than starting a new stack for each generate construct.
2010-01-08 23:49:48 +01:00
PWire*cur = lexical_scope->wires_find(name);
Add memories to the parse and elaboration phases.
1999-04-19 03:59:36 +02:00
if (cur == 0) {
Match memories within task scopes. (PR#101)
2001-01-10 06:32:44 +01:00
VLerror("internal error: name is not a valid memory for index.");
Add memories to the parse and elaboration phases.
1999-04-19 03:59:36 +02:00
return;
}
Get unpacked arrays working.
2012-05-26 00:58:29 +02:00
if (indices && !indices->empty())
cur->set_unpacked_idx(*indices);
Add memories to the parse and elaboration phases.
1999-04-19 03:59:36 +02:00
}
Support parameter, localparam, and event declarations in any scope. Currently, parameters and localparams declared in tasks, functions, generate blocks, and named blocks are placed in the parent module scope. Event declarations in these scopes are not permitted (a syntax error is reported). This patch corrects this behaviour, so that all the above declarations are accepted and are placed in the scope in which they are declared. Note that the IEEE standard does not permit parameter declarations in generate blocks. This patch causes the parser to reject such declarations.
2008-09-17 22:25:59 +02:00
LexicalScope::range_t* pform_parameter_value_range(bool exclude_flag,
Parse parameter value ranges into pform. Handle parameter value ranges as far as the pform. The +-inf expressions are not handled yet, nor is the single value exclude, but the other cases are handled.
2008-05-13 06:26:38 +02:00
bool low_open, PExpr*low_expr,
bool hig_open, PExpr*hig_expr)
{
Get parameter ranges as far as the netlist form. The pform is now translated/elaborated into NetScope objects. All that remains is to check the parameter values against the ranges. This is to be done in the evaluate_parameters() method.
2008-05-14 06:22:52 +02:00
// Detect +-inf and make the the *_open flags false to force
// the range interpretation as inf.
if (low_expr == 0) low_open = false;
if (hig_expr == 0) hig_open = false;
Support parameter, localparam, and event declarations in any scope. Currently, parameters and localparams declared in tasks, functions, generate blocks, and named blocks are placed in the parent module scope. Event declarations in these scopes are not permitted (a syntax error is reported). This patch corrects this behaviour, so that all the above declarations are accepted and are placed in the scope in which they are declared. Note that the IEEE standard does not permit parameter declarations in generate blocks. This patch causes the parser to reject such declarations.
2008-09-17 22:25:59 +02:00
LexicalScope::range_t*tmp = new LexicalScope::range_t;
Parse parameter value ranges into pform. Handle parameter value ranges as far as the pform. The +-inf expressions are not handled yet, nor is the single value exclude, but the other cases are handled.
2008-05-13 06:26:38 +02:00
tmp->exclude_flag = exclude_flag;
tmp->low_open_flag = low_open;
tmp->low_expr = low_expr;
tmp->high_open_flag = hig_open;
tmp->high_expr = hig_expr;
tmp->next = 0;
return tmp;
}
void pform_set_parameter(const struct vlltype&loc,
Add support for explicit parameter types, including real. Before this, the types of parameters were always logic, only the width and signed-ness could be controlled. A parameter may take on implicit real values if the expression were real. With this patch, the type for the parameter can be explicitly set to logic or real. This also means that the parameter real valued expressions need to be more crefully treated, possibly with casting integral expressions to real values, or real expressions to integral values.
2008-05-18 01:25:58 +02:00
perm_string name, ivl_variable_type_t type,
Ranges are ranges, not expression lists. This is a cleanup in preparation for better support of range lists. (cherry picked from commit 8f7cf3255acad55841f8b3725e3786ef49daad68) Conflicts: PTask.h elab_scope.cc elab_sig.cc parse.y pform.cc pform.h pform_types.h Signed-off-by: Stephen Williams <steve@icarus.com>
2012-04-10 23:29:28 +02:00
bool signed_flag, list<pform_range_t>*range, PExpr*expr,
Support parameter, localparam, and event declarations in any scope. Currently, parameters and localparams declared in tasks, functions, generate blocks, and named blocks are placed in the parent module scope. Event declarations in these scopes are not permitted (a syntax error is reported). This patch corrects this behaviour, so that all the above declarations are accepted and are placed in the scope in which they are declared. Note that the IEEE standard does not permit parameter declarations in generate blocks. This patch causes the parser to reject such declarations.
2008-09-17 22:25:59 +02:00
LexicalScope::range_t*value_range)
Add support for module parameters.
1999-02-21 18:01:57 +01:00
{
Rework of lexical scope handling in parser. This patch modifies the parser to use a single stack to track lexical scopes, rather than starting a new stack for each generate construct.
2010-01-08 23:49:48 +01:00
LexicalScope*scope = lexical_scope;
Support separate compilation units in SystemVerilog. The compilation unit scope is now treated as a specialised form of package (with an automatically generated name). All items declared outside a design element are added to the current compilation unit package. Apart from when searching for a symbol, once we get into elaboration we can treat these just like any other package.
2017-10-21 16:04:25 +02:00
if (is_compilation_unit(scope) && !gn_system_verilog()) {
Fix for br992 - prevent assertion/crash on declarations outside a module. parse.y has been updated to allow declarations outside a module (legal in SystemVerilog), but not all types of declaration are supported yet. Output a sorry or error message as appropriate.
2015-08-21 00:55:00 +02:00
VLerror(loc, "error: parameter declarations must be contained within a module.");
return;
}
Check for name space collisions. This patch adds code to check for most of the name space collisions. genvars are not checked correctly since they are not completely implemented.
2009-04-25 04:07:48 +02:00
if (scope == pform_cur_generate) {
Support parameter, localparam, and event declarations in any scope. Currently, parameters and localparams declared in tasks, functions, generate blocks, and named blocks are placed in the parent module scope. Event declarations in these scopes are not permitted (a syntax error is reported). This patch corrects this behaviour, so that all the above declarations are accepted and are placed in the scope in which they are declared. Note that the IEEE standard does not permit parameter declarations in generate blocks. This patch causes the parser to reject such declarations.
2008-09-17 22:25:59 +02:00
VLerror("parameter declarations are not permitted in generate blocks");
return;
}
Check for name space collisions. This patch adds code to check for most of the name space collisions. genvars are not checked correctly since they are not completely implemented.
2009-04-25 04:07:48 +02:00
Redesign the implementation of scopes and parameters. I now generate the scopes and notice the parameters in a separate pass over the pform. Once the scopes are generated, I can process overrides and evalutate paremeters before elaboration begins.
2000-03-08 05:36:53 +01:00
assert(expr);
Check for name space collisions. This patch adds code to check for most of the name space collisions. genvars are not checked correctly since they are not completely implemented.
2009-04-25 04:07:48 +02:00
Module::param_expr_t&parm = scope->parameters[name];
Parse parameter value ranges into pform. Handle parameter value ranges as far as the pform. The +-inf expressions are not handled yet, nor is the single value exclude, but the other cases are handled.
2008-05-13 06:26:38 +02:00
FILE_NAME(&parm, loc);
parm.expr = expr;
Support parameters with defined ranges.
2002-08-19 04:39:16 +02:00
Add support for explicit parameter types, including real. Before this, the types of parameters were always logic, only the width and signed-ness could be controlled. A parameter may take on implicit real values if the expression were real. With this patch, the type for the parameter can be explicitly set to logic or real. This also means that the parameter real valued expressions need to be more crefully treated, possibly with casting integral expressions to real values, or real expressions to integral values.
2008-05-18 01:25:58 +02:00
parm.type = type;
Support parameters with defined ranges.
2002-08-19 04:39:16 +02:00
if (range) {
Rework rules for variable_dimensions, and support more syntax.
2012-03-03 03:34:43 +01:00
assert(range->size() == 1);
Ranges are ranges, not expression lists. This is a cleanup in preparation for better support of range lists. (cherry picked from commit 8f7cf3255acad55841f8b3725e3786ef49daad68) Conflicts: PTask.h elab_scope.cc elab_sig.cc parse.y pform.cc pform.h pform_types.h Signed-off-by: Stephen Williams <steve@icarus.com>
2012-04-10 23:29:28 +02:00
pform_range_t&rng = range->front();
assert(rng.first);
assert(rng.second);
parm.msb = rng.first;
parm.lsb = rng.second;
Support parameters with defined ranges.
2002-08-19 04:39:16 +02:00
} else {
Parse parameter value ranges into pform. Handle parameter value ranges as far as the pform. The +-inf expressions are not handled yet, nor is the single value exclude, but the other cases are handled.
2008-05-13 06:26:38 +02:00
parm.msb = 0;
parm.lsb = 0;
Support parameters with defined ranges.
2002-08-19 04:39:16 +02:00
}
Parse parameter value ranges into pform. Handle parameter value ranges as far as the pform. The +-inf expressions are not handled yet, nor is the single value exclude, but the other cases are handled.
2008-05-13 06:26:38 +02:00
parm.signed_flag = signed_flag;
parm.range = value_range;
Support parameters with defined ranges.
2002-08-19 04:39:16 +02:00
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
add_local_symbol(scope, name, &parm);
Update parameter add code to correctly handle a non-Module scope A package can have parameters, but it does not have specparams or keep the order the parameters are defined. This patch skips these items if the scope is not a Module.
2013-03-08 18:59:25 +01:00
// Only a Module keeps the position of the parameter.
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
if ((dynamic_cast<Module*>(scope)) && (scope == pform_cur_module.front()))
Allow modules (and program blocks in particular) to nest. An important advantage of program blocks is its ability to nest within a module. This winds up also allowing modules to nest, which is legal but presumably less used feature.
2012-05-10 04:35:11 +02:00
pform_cur_module.front()->param_names.push_back(name);
Add support for module parameters.
1999-02-21 18:01:57 +01:00
}
Parse parameter value ranges into pform. Handle parameter value ranges as far as the pform. The +-inf expressions are not handled yet, nor is the single value exclude, but the other cases are handled.
2008-05-13 06:26:38 +02:00
void pform_set_localparam(const struct vlltype&loc,
Add support for explicit parameter types, including real. Before this, the types of parameters were always logic, only the width and signed-ness could be controlled. A parameter may take on implicit real values if the expression were real. With this patch, the type for the parameter can be explicitly set to logic or real. This also means that the parameter real valued expressions need to be more crefully treated, possibly with casting integral expressions to real values, or real expressions to integral values.
2008-05-18 01:25:58 +02:00
perm_string name, ivl_variable_type_t type,
Ranges are ranges, not expression lists. This is a cleanup in preparation for better support of range lists. (cherry picked from commit 8f7cf3255acad55841f8b3725e3786ef49daad68) Conflicts: PTask.h elab_scope.cc elab_sig.cc parse.y pform.cc pform.h pform_types.h Signed-off-by: Stephen Williams <steve@icarus.com>
2012-04-10 23:29:28 +02:00
bool signed_flag, list<pform_range_t>*range, PExpr*expr)
Support localparam.
2000-03-12 18:09:40 +01:00
{
Rework of lexical scope handling in parser. This patch modifies the parser to use a single stack to track lexical scopes, rather than starting a new stack for each generate construct.
2010-01-08 23:49:48 +01:00
LexicalScope*scope = lexical_scope;
Support separate compilation units in SystemVerilog. The compilation unit scope is now treated as a specialised form of package (with an automatically generated name). All items declared outside a design element are added to the current compilation unit package. Apart from when searching for a symbol, once we get into elaboration we can treat these just like any other package.
2017-10-21 16:04:25 +02:00
if (is_compilation_unit(scope) && !gn_system_verilog()) {
Fix for br992 - prevent assertion/crash on declarations outside a module. parse.y has been updated to allow declarations outside a module (legal in SystemVerilog), but not all types of declaration are supported yet. Output a sorry or error message as appropriate.
2015-08-21 00:55:00 +02:00
VLerror(loc, "error: localparam declarations must be contained within a module.");
return;
}
Check for name space collisions. This patch adds code to check for most of the name space collisions. genvars are not checked correctly since they are not completely implemented.
2009-04-25 04:07:48 +02:00
Support localparam.
2000-03-12 18:09:40 +01:00
assert(expr);
Rework of lexical scope handling in parser. This patch modifies the parser to use a single stack to track lexical scopes, rather than starting a new stack for each generate construct.
2010-01-08 23:49:48 +01:00
Module::param_expr_t&parm = scope->localparams[name];
Parse parameter value ranges into pform. Handle parameter value ranges as far as the pform. The +-inf expressions are not handled yet, nor is the single value exclude, but the other cases are handled.
2008-05-13 06:26:38 +02:00
FILE_NAME(&parm, loc);
parm.expr = expr;
Add support for localparam ranges.
2004-08-26 06:02:03 +02:00
Add support for explicit parameter types, including real. Before this, the types of parameters were always logic, only the width and signed-ness could be controlled. A parameter may take on implicit real values if the expression were real. With this patch, the type for the parameter can be explicitly set to logic or real. This also means that the parameter real valued expressions need to be more crefully treated, possibly with casting integral expressions to real values, or real expressions to integral values.
2008-05-18 01:25:58 +02:00
parm.type = type;
Add support for localparam ranges.
2004-08-26 06:02:03 +02:00
if (range) {
Rework rules for variable_dimensions, and support more syntax.
2012-03-03 03:34:43 +01:00
assert(range->size() == 1);
Ranges are ranges, not expression lists. This is a cleanup in preparation for better support of range lists. (cherry picked from commit 8f7cf3255acad55841f8b3725e3786ef49daad68) Conflicts: PTask.h elab_scope.cc elab_sig.cc parse.y pform.cc pform.h pform_types.h Signed-off-by: Stephen Williams <steve@icarus.com>
2012-04-10 23:29:28 +02:00
pform_range_t&rng = range->front();
assert(rng.first);
assert(rng.second);
parm.msb = rng.first;
parm.lsb = rng.second;
Add support for localparam ranges.
2004-08-26 06:02:03 +02:00
} else {
Parse parameter value ranges into pform. Handle parameter value ranges as far as the pform. The +-inf expressions are not handled yet, nor is the single value exclude, but the other cases are handled.
2008-05-13 06:26:38 +02:00
parm.msb = 0;
parm.lsb = 0;
Add support for localparam ranges.
2004-08-26 06:02:03 +02:00
}
Parse parameter value ranges into pform. Handle parameter value ranges as far as the pform. The +-inf expressions are not handled yet, nor is the single value exclude, but the other cases are handled.
2008-05-13 06:26:38 +02:00
parm.signed_flag = signed_flag;
parm.range = 0;
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
add_local_symbol(scope, name, &parm);
Support localparam.
2000-03-12 18:09:40 +01:00
}
Allow specparam declarations outside specify blocks. This patch extends the compiler to support all specparam declarations allowed by the 1364-2005 standard. For compatibility with other simulators, it allows specparam values to be used in any constant expression, but outputs a warning message and disables run-time annotation of a specparam if it is used in an expression that must be evaluated at compile time.
2012-05-07 00:11:26 +02:00
void pform_set_specparam(const struct vlltype&loc, perm_string name,
list<pform_range_t>*range, PExpr*expr)
specparams as far as pform.
2003-02-27 07:45:11 +01:00
{
Fix some cppcheck warnings in the main directory
2012-08-08 20:26:46 +02:00
assert(! pform_cur_module.empty());
Allow modules (and program blocks in particular) to nest. An important advantage of program blocks is its ability to nest within a module. This winds up also allowing modules to nest, which is legal but presumably less used feature.
2012-05-10 04:35:11 +02:00
Module*scope = pform_cur_module.front();
Allow specparam declarations outside specify blocks. This patch extends the compiler to support all specparam declarations allowed by the 1364-2005 standard. For compatibility with other simulators, it allows specparam values to be used in any constant expression, but outputs a warning message and disables run-time annotation of a specparam if it is used in an expression that must be evaluated at compile time.
2012-05-07 00:11:26 +02:00
assert(scope == lexical_scope);
specparams as far as pform.
2003-02-27 07:45:11 +01:00
assert(expr);
Allow modules (and program blocks in particular) to nest. An important advantage of program blocks is its ability to nest within a module. This winds up also allowing modules to nest, which is legal but presumably less used feature.
2012-05-10 04:35:11 +02:00
Module::param_expr_t&parm = pform_cur_module.front()->specparams[name];
Allow specparam declarations outside specify blocks. This patch extends the compiler to support all specparam declarations allowed by the 1364-2005 standard. For compatibility with other simulators, it allows specparam values to be used in any constant expression, but outputs a warning message and disables run-time annotation of a specparam if it is used in an expression that must be evaluated at compile time.
2012-05-07 00:11:26 +02:00
FILE_NAME(&parm, loc);
parm.expr = expr;
if (range) {
assert(range->size() == 1);
pform_range_t&rng = range->front();
assert(rng.first);
assert(rng.second);
Fix implicit casts in assignments (part 6). IVL_VT_NO_TYPE is now used to signal an untyped LHS in a parameter declaration. The parser function that handles specparam declarations needs to do this too. Also, although it should never happen, make sure we don't set the expression width in a NetECast object to a negative number. Make constant evaluation of NetECast objects observe the expression width.
2013-03-06 19:24:11 +01:00
parm.type = IVL_VT_LOGIC;
Allow specparam declarations outside specify blocks. This patch extends the compiler to support all specparam declarations allowed by the 1364-2005 standard. For compatibility with other simulators, it allows specparam values to be used in any constant expression, but outputs a warning message and disables run-time annotation of a specparam if it is used in an expression that must be evaluated at compile time.
2012-05-07 00:11:26 +02:00
parm.msb = rng.first;
parm.lsb = rng.second;
} else {
Fix implicit casts in assignments (part 6). IVL_VT_NO_TYPE is now used to signal an untyped LHS in a parameter declaration. The parser function that handles specparam declarations needs to do this too. Also, although it should never happen, make sure we don't set the expression width in a NetECast object to a negative number. Make constant evaluation of NetECast objects observe the expression width.
2013-03-06 19:24:11 +01:00
parm.type = IVL_VT_NO_TYPE;
Allow specparam declarations outside specify blocks. This patch extends the compiler to support all specparam declarations allowed by the 1364-2005 standard. For compatibility with other simulators, it allows specparam values to be used in any constant expression, but outputs a warning message and disables run-time annotation of a specparam if it is used in an expression that must be evaluated at compile time.
2012-05-07 00:11:26 +02:00
parm.msb = 0;
parm.lsb = 0;
}
parm.signed_flag = false;
parm.range = 0;
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
add_local_symbol(scope, name, &parm);
specparams as far as pform.
2003-02-27 07:45:11 +01:00
}
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
void pform_set_defparam(const pform_name_t&name, PExpr*expr)
Redesign the implementation of scopes and parameters. I now generate the scopes and notice the parameters in a separate pass over the pform. Once the scopes are generated, I can process overrides and evalutate paremeters before elaboration begins.
2000-03-08 05:36:53 +01:00
{
assert(expr);
Fix for pr3557493. defparam assignments found inside a generate block were being stored in the enclosing module scope. They should be stored in the generate block scope. Also removed the genvar list from the PGenerate class, as this is already declared in the base LexicalScope class.
2012-08-16 01:07:50 +02:00
if (pform_cur_generate)
pform_cur_generate->defparms.push_back(make_pair(name,expr));
else
pform_cur_module.front()->defparms.push_back(make_pair(name,expr));
Redesign the implementation of scopes and parameters. I now generate the scopes and notice the parameters in a separate pass over the pform. Once the scopes are generated, I can process overrides and evalutate paremeters before elaboration begins.
2000-03-08 05:36:53 +01:00
}
Add basic support for parameters using typedefs
2016-05-14 19:33:37 +02:00
void pform_set_param_from_type(const struct vlltype&loc,
const data_type_t *data_type,
const char *name,
list<pform_range_t> *&param_range,
bool &param_signed,
ivl_variable_type_t &param_type)
{
if (const vector_type_t *vec = dynamic_cast<const vector_type_t*> (data_type)) {
param_range = vec->pdims.get();
param_signed = vec->signed_flag;
param_type = vec->base_type;
return;
}
param_range = 0;
param_signed = false;
param_type = IVL_VT_NO_TYPE;
cerr << loc.get_fileline() << ": sorry: cannot currently create a "
"parameter of type '" << name << "' which was defined at: "
<< data_type->get_fileline() << "." << endl;
error_count += 1;
}
specparams as far as pform.
2003-02-27 07:45:11 +01:00
/*
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
* Specify paths.
specparams as far as pform.
2003-02-27 07:45:11 +01:00
*/
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
extern PSpecPath* pform_make_specify_path(const struct vlltype&li,
list<perm_string>*src, char pol,
bool full_flag, list<perm_string>*dst)
specparams as far as pform.
2003-02-27 07:45:11 +01:00
{
Update PSpecPath to take the polarity and full_flag when constructed To avoid a variables not initialized in the construct this patch modifies the PSpecPath class to take the polarity and full_flag as arguments to the constructor.
2011-11-23 04:38:36 +01:00
PSpecPath*path = new PSpecPath(src->size(), dst->size(), pol, full_flag);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(path, li.text, li.first_line);
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
unsigned idx;
list<perm_string>::const_iterator cur;
idx = 0;
Some more cppcheck cleanup/updates
2014-06-30 05:38:23 +02:00
for (idx = 0, cur = src->begin() ; cur != src->end() ; ++ idx, ++ cur) {
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
path->src[idx] = *cur;
}
assert(idx == path->src.size());
specparams as far as pform.
2003-02-27 07:45:11 +01:00
delete src;
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
Some more cppcheck cleanup/updates
2014-06-30 05:38:23 +02:00
for (idx = 0, cur = dst->begin() ; cur != dst->end() ; ++ idx, ++ cur) {
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
path->dst[idx] = *cur;
}
assert(idx == path->dst.size());
specparams as far as pform.
2003-02-27 07:45:11 +01:00
delete dst;
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
return path;
}
Parse all specify paths to pform.
2007-02-12 02:52:21 +01:00
extern PSpecPath*pform_make_specify_edge_path(const struct vlltype&li,
Parse edge sensitive paths without edge specifier.
2007-04-13 04:34:35 +02:00
int edge_flag, /*posedge==true */
Parse all specify paths to pform.
2007-02-12 02:52:21 +01:00
list<perm_string>*src, char pol,
bool full_flag, list<perm_string>*dst,
PExpr*data_source_expression)
{
PSpecPath*tmp = pform_make_specify_path(li, src, pol, full_flag, dst);
Parse edge sensitive paths without edge specifier.
2007-04-13 04:34:35 +02:00
tmp->edge = edge_flag;
Parse all specify paths to pform.
2007-02-12 02:52:21 +01:00
tmp->data_source_expression = data_source_expression;
return tmp;
}
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
extern PSpecPath* pform_assign_path_delay(PSpecPath*path, list<PExpr*>*del)
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
{
Parse all specify paths to pform.
2007-02-12 02:52:21 +01:00
if (path == 0)
return 0;
Some more cppcheck cleanup. This patch cleans up most of the warnings in the main (ivl) directory.
2011-04-19 03:17:16 +02:00
assert(path->delays.empty());
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
path->delays.resize(del->size());
for (unsigned idx = 0 ; idx < path->delays.size() ; idx += 1) {
path->delays[idx] = del->front();
del->pop_front();
}
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
delete del;
return path;
}
extern void pform_module_specify_path(PSpecPath*obj)
{
Parse all specify paths to pform.
2007-02-12 02:52:21 +01:00
if (obj == 0)
return;
Allow modules (and program blocks in particular) to nest. An important advantage of program blocks is its ability to nest within a module. This winds up also allowing modules to nest, which is legal but presumably less used feature.
2012-05-10 04:35:11 +02:00
pform_cur_module.front()->specify_paths.push_back(obj);
specparams as far as pform.
2003-02-27 07:45:11 +01:00
}
Bunches more SystemVerilog syntax.
2012-03-10 03:54:05 +01:00
static void pform_set_port_type(perm_string name, NetNet::PortType pt,
const char*file, unsigned lineno)
{
PWire*cur = pform_get_wire_in_scope(name);
if (cur == 0) {
cur = new PWire(name, NetNet::IMPLICIT, NetNet::PIMPLICIT, IVL_VT_NO_TYPE);
FILE_NAME(cur, file, lineno);
pform_put_wire_in_scope(name, cur);
}
switch (cur->get_port_type()) {
case NetNet::PIMPLICIT:
if (! cur->set_port_type(pt))
VLerror("error setting port direction.");
break;
case NetNet::NOT_A_PORT:
cerr << file << ":" << lineno << ": error: "
<< "port " << name << " is not in the port list."
<< endl;
error_count += 1;
break;
default:
cerr << file << ":" << lineno << ": error: "
<< "port " << name << " already has a port declaration."
<< endl;
error_count += 1;
break;
}
}
Coerse input to inout when assigned to.
2001-11-10 03:08:49 +01:00
void pform_set_port_type(const struct vlltype&li,
Fix for br974 - support SV types in non-ansi port declarations.
2016-04-04 21:40:30 +02:00
list<pform_port_t>*ports,
Fix for br930 - support attributes on old-style port declarations.
2013-05-19 10:16:24 +02:00
NetNet::PortType pt,
Fix for br974 - support SV types in non-ansi port declarations.
2016-04-04 21:40:30 +02:00
data_type_t*dt,
Fix for br930 - support attributes on old-style port declarations.
2013-05-19 10:16:24 +02:00
list<named_pexpr_t>*attr)
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
{
Bunches more SystemVerilog syntax.
2012-03-10 03:54:05 +01:00
assert(pt != NetNet::PIMPLICIT && pt != NetNet::NOT_A_PORT);
Fix for br974 - support SV types in non-ansi port declarations.
2016-04-04 21:40:30 +02:00
list<pform_range_t>*range = 0;
bool signed_flag = false;
if (vector_type_t*vt = dynamic_cast<vector_type_t*> (dt)) {
assert(vt->implicit_flag);
range = vt->pdims.get();
signed_flag = vt->signed_flag;
} else {
assert(dt == 0);
}
bool have_init_expr = false;
for (list<pform_port_t>::iterator cur = ports->begin()
; cur != ports->end() ; ++ cur ) {
pform_set_port_type(cur->name, pt, li.text, li.first_line);
pform_set_net_range(cur->name, NetNet::NONE, range, signed_flag,
IVL_VT_NO_TYPE, SR_PORT, attr);
if (cur->udims) {
cerr << li.text << ":" << li.first_line << ": warning: "
<< "Array dimensions in incomplete port declarations "
<< "are currently ignored." << endl;
cerr << li.text << ":" << li.first_line << ": : "
<< "The dimensions specified in the net or variable "
<< "declaration will be used." << endl;
delete cur->udims;
}
if (cur->expr) {
have_init_expr = true;
delete cur->expr;
}
}
if (have_init_expr) {
cerr << li.text << ":" << li.first_line << ": error: "
<< "Incomplete port declarations cannot be initialized."
<< endl;
error_count += 1;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
Remove C++ string from variable lists.
2000-10-31 18:00:04 +01:00
Fix for br974 - support SV types in non-ansi port declarations.
2016-04-04 21:40:30 +02:00
delete ports;
delete dt;
Fix for br930 - support attributes on old-style port declarations.
2013-05-19 10:16:24 +02:00
delete attr;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
Output an error message when a SV variable declaration reuses a name. Assertion failures are not the right way to handle user code errors.
2018-02-18 18:51:56 +01:00
static void pform_set_integer_2atom(const struct vlltype&li, uint64_t width, bool signed_flag, perm_string name, NetNet::Type net_type, list<named_pexpr_t>*attr)
Parse support for SystemVerilog atom2 types.
2010-10-02 19:13:11 +02:00
{
Output an error message when a SV variable declaration reuses a name. Assertion failures are not the right way to handle user code errors.
2018-02-18 18:51:56 +01:00
PWire*cur = pform_get_make_wire_in_scope(li, name, net_type, NetNet::NOT_A_PORT, IVL_VT_BOOL);
Parse support for SystemVerilog atom2 types.
2010-10-02 19:13:11 +02:00
assert(cur);
cur->set_signed(signed_flag);
Parse multi-dimension packed arrays to pform.
2012-02-05 01:19:27 +01:00
Ranges are ranges, not expression lists. This is a cleanup in preparation for better support of range lists. (cherry picked from commit 8f7cf3255acad55841f8b3725e3786ef49daad68) Conflicts: PTask.h elab_scope.cc elab_sig.cc parse.y pform.cc pform.h pform_types.h Signed-off-by: Stephen Williams <steve@icarus.com>
2012-04-10 23:29:28 +02:00
pform_range_t rng;
rng.first = new PENumber(new verinum(width-1, integer_width));
rng.second = new PENumber(new verinum((uint64_t)0, integer_width));
list<pform_range_t>rlist;
Parse multi-dimension packed arrays to pform.
2012-02-05 01:19:27 +01:00
rlist.push_back(rng);
cur->set_range(rlist, SR_NET);
Repair handling of attributes attached to variables.
2012-05-09 19:56:52 +02:00
pform_bind_attributes(cur->attributes, attr, true);
Parse support for SystemVerilog atom2 types.
2010-10-02 19:13:11 +02:00
}
Output an error message when a SV variable declaration reuses a name. Assertion failures are not the right way to handle user code errors.
2018-02-18 18:51:56 +01:00
static void pform_set_integer_2atom(const struct vlltype&li, uint64_t width, bool signed_flag, list<perm_string>*names, NetNet::Type net_type, list<named_pexpr_t>*attr)
Parse support for SystemVerilog atom2 types.
2010-10-02 19:13:11 +02:00
{
for (list<perm_string>::iterator cur = names->begin()
Change iterators to use prefix ++ since it is more efficient. This patch changes all the iterator code to use a prefix ++ instead of postfix since it is more efficient (no need for a temporary). It is likely that the compiler could optimize this away, but lets make it efficient from the start.
2010-10-23 23:57:59 +02:00
; cur != names->end() ; ++ cur ) {
Parse support for SystemVerilog atom2 types.
2010-10-02 19:13:11 +02:00
perm_string txt = *cur;
Output an error message when a SV variable declaration reuses a name. Assertion failures are not the right way to handle user code errors.
2018-02-18 18:51:56 +01:00
pform_set_integer_2atom(li, width, signed_flag, txt, net_type, attr);
Parse support for SystemVerilog atom2 types.
2010-10-02 19:13:11 +02:00
}
}
Use data_type_t instead of raw type bits.
2012-09-03 18:13:52 +02:00
template <class T> static void pform_set2_data_type(const struct vlltype&li, T*data_type, perm_string name, NetNet::Type net_type, list<named_pexpr_t>*attr)
Clean up PWire handling of wire data type. / Reword packed type handling
2012-08-03 05:14:55 +02:00
{
ivl_variable_type_t base_type = data_type->figure_packed_base_type();
if (base_type == IVL_VT_NO_TYPE) {
VLerror(li, "Compound type is not PACKED in this context.");
}
Output an error message when a SV variable declaration reuses a name. Assertion failures are not the right way to handle user code errors.
2018-02-18 18:51:56 +01:00
PWire*net = pform_get_make_wire_in_scope(li, name, net_type, NetNet::NOT_A_PORT, base_type);
Catch enumerations with the same name.
2014-11-01 04:05:22 +01:00
assert(net);
Elaborate class_new and (null) expressions This gets the types right for class_new and null expressions, and elaborate them down to the ivl_target.h API.
2012-11-12 02:42:31 +01:00
net->set_data_type(data_type);
Clean up PWire handling of wire data type. / Reword packed type handling
2012-08-03 05:14:55 +02:00
pform_bind_attributes(net->attributes, attr, true);
}
Use data_type_t instead of raw type bits.
2012-09-03 18:13:52 +02:00
template <class T> static void pform_set2_data_type(const struct vlltype&li, T*data_type, list<perm_string>*names, NetNet::Type net_type, list<named_pexpr_t>*attr)
Clean up PWire handling of wire data type. / Reword packed type handling
2012-08-03 05:14:55 +02:00
{
for (list<perm_string>::iterator cur = names->begin()
; cur != names->end() ; ++ cur) {
Use data_type_t instead of raw type bits.
2012-09-03 18:13:52 +02:00
pform_set2_data_type(li, data_type, *cur, net_type, attr);
Clean up PWire handling of wire data type. / Reword packed type handling
2012-08-03 05:14:55 +02:00
}
}
Output an error message when a SV variable declaration reuses a name. Assertion failures are not the right way to handle user code errors.
2018-02-18 18:51:56 +01:00
static void pform_set_enum(const struct vlltype&li, enum_type_t*enum_type,
Use data_type_t instead of raw type bits.
2012-09-03 18:13:52 +02:00
perm_string name, NetNet::Type net_type,
std::list<named_pexpr_t>*attr)
{
Output an error message when a SV variable declaration reuses a name. Assertion failures are not the right way to handle user code errors.
2018-02-18 18:51:56 +01:00
PWire*cur = pform_get_make_wire_in_scope(li, name, net_type, NetNet::NOT_A_PORT, enum_type->base_type);
Fix for br975 - assertion failure due to duplicate declaration of struct var. Added proper error handling for duplicate declarations of all variable types.
2015-05-17 21:54:53 +02:00
assert(cur);
Use data_type_t instead of raw type bits.
2012-09-03 18:13:52 +02:00
cur->set_signed(enum_type->signed_flag);
assert(enum_type->range.get() != 0);
assert(enum_type->range->size() == 1);
//XXXXcur->set_range(*enum_type->range, SR_NET);
Elaborate class_new and (null) expressions This gets the types right for class_new and null expressions, and elaborate them down to the ivl_target.h API.
2012-11-12 02:42:31 +01:00
cur->set_data_type(enum_type);
Pass the integer type for enumerations to the IVL target stage
2014-11-01 02:07:46 +01:00
// If this is an integer enumeration switch the wire to an integer.
if (enum_type->integer_flag) {
bool res = cur->set_wire_type(NetNet::INTEGER);
assert(res);
}
Use data_type_t instead of raw type bits.
2012-09-03 18:13:52 +02:00
pform_bind_attributes(cur->attributes, attr, true);
}
static void pform_set_enum(const struct vlltype&li, enum_type_t*enum_type,
list<perm_string>*names, NetNet::Type net_type,
std::list<named_pexpr_t>*attr)
{
// By definition, the base type can only be IVL_VT_LOGIC or
// IVL_VT_BOOL.
assert(enum_type->base_type==IVL_VT_LOGIC || enum_type->base_type==IVL_VT_BOOL);
assert(enum_type->range.get() != 0);
assert(enum_type->range->size() == 1);
// Add the file and line information to the enumeration type.
FILE_NAME(&(enum_type->li), li);
// Attach the enumeration to the current scope.
pform_put_enum_type_in_scope(enum_type);
// Now apply the checked enumeration type to the variables
// that are being declared with this type.
for (list<perm_string>::iterator cur = names->begin()
; cur != names->end() ; ++ cur) {
perm_string txt = *cur;
Output an error message when a SV variable declaration reuses a name. Assertion failures are not the right way to handle user code errors.
2018-02-18 18:51:56 +01:00
pform_set_enum(li, enum_type, txt, net_type, attr);
Use data_type_t instead of raw type bits.
2012-09-03 18:13:52 +02:00
}
}
Parse simple typedefs Parse typedefs with structs and enums, but give a sorry message, because they are not yet supported. Rearrange some of the parse rules for variables in order to increase comonality with the typedef rules.
2012-01-08 00:37:30 +01:00
/*
* This function detects the derived class for the given type and
* dispatches the type to the proper subtype function.
*/
Use data_type_t instead of raw type bits.
2012-09-03 18:13:52 +02:00
void pform_set_data_type(const struct vlltype&li, data_type_t*data_type, list<perm_string>*names, NetNet::Type net_type, list<named_pexpr_t>*attr)
Parse simple typedefs Parse typedefs with structs and enums, but give a sorry message, because they are not yet supported. Rearrange some of the parse rules for variables in order to increase comonality with the typedef rules.
2012-01-08 00:37:30 +01:00
{
ivl: Typedefs may use unpacked arrays.
2014-12-15 11:25:35 +01:00
const std::list<pform_range_t>*unpacked_dims = NULL;
Rework parse rules to handle more net types. This makes the rules for types to be more in line with IEEE1800.
2012-09-03 20:20:29 +02:00
if (data_type == 0) {
VLerror(li, "internal error: data_type==0.");
assert(0);
}
ivl: Typedefs may use unpacked arrays.
2014-12-15 11:25:35 +01:00
if(uarray_type_t*uarray_type = dynamic_cast<uarray_type_t*> (data_type)) {
unpacked_dims = uarray_type->dims.get();
data_type = uarray_type->base_type;
}
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
if (atom2_type_t*atom2_type = dynamic_cast<atom2_type_t*> (data_type)) {
Output an error message when a SV variable declaration reuses a name. Assertion failures are not the right way to handle user code errors.
2018-02-18 18:51:56 +01:00
pform_set_integer_2atom(li, atom2_type->type_code, atom2_type->signed_flag, names, net_type, attr);
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
}
ivl: Typedefs may use unpacked arrays.
2014-12-15 11:25:35 +01:00
else if (struct_type_t*struct_type = dynamic_cast<struct_type_t*> (data_type)) {
Output an error message when a SV variable declaration reuses a name. Assertion failures are not the right way to handle user code errors.
2018-02-18 18:51:56 +01:00
pform_set_struct_type(li, struct_type, names, net_type, attr);
Parse simple typedefs Parse typedefs with structs and enums, but give a sorry message, because they are not yet supported. Rearrange some of the parse rules for variables in order to increase comonality with the typedef rules.
2012-01-08 00:37:30 +01:00
}
ivl: Typedefs may use unpacked arrays.
2014-12-15 11:25:35 +01:00
else if (enum_type_t*enum_type = dynamic_cast<enum_type_t*> (data_type)) {
Use data_type_t instead of raw type bits.
2012-09-03 18:13:52 +02:00
pform_set_enum(li, enum_type, names, net_type, attr);
Parse simple typedefs Parse typedefs with structs and enums, but give a sorry message, because they are not yet supported. Rearrange some of the parse rules for variables in order to increase comonality with the typedef rules.
2012-01-08 00:37:30 +01:00
}
ivl: Typedefs may use unpacked arrays.
2014-12-15 11:25:35 +01:00
else if (vector_type_t*vec_type = dynamic_cast<vector_type_t*> (data_type)) {
Generalize user defined function return type handling. I'm gonna need functions to return class objects, so generalize the output types of user defined functions.
2013-04-15 03:03:21 +02:00
if (net_type==NetNet::REG && vec_type->integer_flag)
net_type=NetNet::INTEGER;
Rework data_type parsing to bring integer vectors into data_type_t method. This adds the vector_type_t and real_type_t types to handle vector and real types in tf_port items. This cleans up a lot of the parsing for these items.
2012-02-26 07:05:00 +01:00
pform_set_net_range(names, vec_type->pdims.get(),
vec_type->signed_flag,
Use data_type_t instead of raw type bits.
2012-09-03 18:13:52 +02:00
vec_type->base_type, net_type, attr);
Rework data_type parsing to bring integer vectors into data_type_t method. This adds the vector_type_t and real_type_t types to handle vector and real types in tf_port items. This cleans up a lot of the parsing for these items.
2012-02-26 07:05:00 +01:00
}
ivl: Typedefs may use unpacked arrays.
2014-12-15 11:25:35 +01:00
else if (/*real_type_t*real_type =*/ dynamic_cast<real_type_t*> (data_type)) {
Use data_type_t instead of raw type bits.
2012-09-03 18:13:52 +02:00
pform_set_net_range(names, 0, true, IVL_VT_REAL, net_type, attr);
Rework data_type parsing to bring integer vectors into data_type_t method. This adds the vector_type_t and real_type_t types to handle vector and real types in tf_port items. This cleans up a lot of the parsing for these items.
2012-02-26 07:05:00 +01:00
}
ivl: Typedefs may use unpacked arrays.
2014-12-15 11:25:35 +01:00
else if (class_type_t*class_type = dynamic_cast<class_type_t*> (data_type)) {
Output an error message when a SV variable declaration reuses a name. Assertion failures are not the right way to handle user code errors.
2018-02-18 18:51:56 +01:00
pform_set_class_type(li, class_type, names, net_type, attr);
Bunches more SystemVerilog syntax.
2012-03-10 03:54:05 +01:00
}
ivl: Typedefs may use unpacked arrays.
2014-12-15 11:25:35 +01:00
else if (parray_type_t*array_type = dynamic_cast<parray_type_t*> (data_type)) {
Use data_type_t instead of raw type bits.
2012-09-03 18:13:52 +02:00
pform_set2_data_type(li, array_type, names, net_type, attr);
Parse (to "sorry") arrays of named types.
2012-05-14 02:05:09 +02:00
}
ivl: Typedefs may use unpacked arrays.
2014-12-15 11:25:35 +01:00
else if (string_type_t*string_type = dynamic_cast<string_type_t*> (data_type)) {
Output an error message when a SV variable declaration reuses a name. Assertion failures are not the right way to handle user code errors.
2018-02-18 18:51:56 +01:00
pform_set_string_type(li, string_type, names, net_type, attr);
ivl: Typedefs may use unpacked arrays.
2014-12-15 11:25:35 +01:00
} else {
VLerror(li, "internal error: Unexpected data_type.");
assert(0);
First pass at getting strings to work. In vvp, create the .var/str variable for representing strings, and handle strings in the $display system task. Add to vvp threads the concept of a stack of strings. This is going to be how complex objects are to me handled in the future: forth-like operation stacks. Also add the first two instructions to minimally get strings to work. In the parser, handle the variable declaration and make it available to the ivl_target.h code generator. The vvp code generator can use this information to generate the code for new vvp support.
2012-06-18 03:22:50 +02:00
}
ivl: Typedefs may use unpacked arrays.
2014-12-15 11:25:35 +01:00
if(unpacked_dims) {
for (list<perm_string>::iterator cur = names->begin()
; cur != names->end() ; ++ cur ) {
PWire*wire = pform_get_wire_in_scope(*cur);
wire->set_unpacked_idx(*unpacked_dims);
}
}
delete names;
Parse simple typedefs Parse typedefs with structs and enums, but give a sorry message, because they are not yet supported. Rearrange some of the parse rules for variables in order to increase comonality with the typedef rules.
2012-01-08 00:37:30 +01:00
}
Remove svector template from port handling.
2013-02-25 03:06:12 +01:00
vector<PWire*>* pform_make_udp_input_ports(list<perm_string>*names)
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
{
Remove svector template from port handling.
2013-02-25 03:06:12 +01:00
vector<PWire*>*out = new vector<PWire*>(names->size());
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
parse more verilog.
1999-06-12 22:35:27 +02:00
unsigned idx = 0;
More identifier lists use perm_strings.
2004-05-25 21:21:06 +02:00
for (list<perm_string>::iterator cur = names->begin()
Change iterators to use prefix ++ since it is more efficient. This patch changes all the iterator code to use a prefix ++ instead of postfix since it is more efficient (no need for a temporary). It is likely that the compiler could optimize this away, but lets make it efficient from the start.
2010-10-23 23:57:59 +02:00
; cur != names->end() ; ++ cur ) {
More identifier lists use perm_strings.
2004-05-25 21:21:06 +02:00
perm_string txt = *cur;
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
PWire*pp = new PWire(txt,
More identifier lists use perm_strings.
2004-05-25 21:21:06 +02:00
NetNet::IMPLICIT,
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
NetNet::PINPUT,
IVL_VT_LOGIC);
parse more verilog.
1999-06-12 22:35:27 +02:00
(*out)[idx] = pp;
Fix merging of UDP port type in decls.
1999-06-21 03:02:16 +02:00
idx += 1;
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
}
delete names;
return out;
}
Infrastructure for elaborating analog statements. Put together the infrastructure for elaborating analog statements, including create the NetAnalogTop objects that hold analog statements and are in turn held by the design. While doing this, clean up the various unique initial/always enumerations to use the ivl_process_type_t type.
2008-10-22 07:15:49 +02:00
PProcess* pform_make_behavior(ivl_process_type_t type, Statement*st,
Enumeration element values can be expressions Allow more complex enumeration expressions, which means putting off the evaluation of the expression values until elaboration.
2010-11-13 03:47:06 +01:00
list<named_pexpr_t>*attr)
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
{
Add preliminary support for always_comb, always_ff and always_latch
2017-11-20 16:48:35 +01:00
// Add an implicit @* around the statement for the always_comb and
// always_latch statements.
if ((type == IVL_PR_ALWAYS_COMB) || (type == IVL_PR_ALWAYS_LATCH)) {
PEventStatement *tmp = new PEventStatement(true);
tmp->set_file(st->get_file());
tmp->set_lineno(st->get_lineno());
tmp->set_statement(st);
st = tmp;
}
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
PProcess*pp = new PProcess(type, st);
Carry Verilog 2001 attributes with processes, all the way through to the ivl_target API. Divide signal reference counts between rval and lval references.
2002-05-26 03:39:02 +02:00
Add support for synthesis translate meta-comments.
2014-07-16 03:03:40 +02:00
// If we are in a part of the code where the meta-comment
// synthesis translate_off is in effect, then implicitly add
// the ivl_synthesis_off attribute to any behavioral code that
// we run into.
if (pform_mc_translate_flag == false) {
if (attr == 0) attr = new list<named_pexpr_t>;
named_pexpr_t tmp;
tmp.name = perm_string::literal("ivl_synthesis_off");
tmp.parm = 0;
attr->push_back(tmp);
}
Parse attributes on statements within event statements. Statements can have attributes attached to them. Handle a few cases in the parser where attributes may be attached to statements, and get them as far as the pform.
2008-09-05 06:27:21 +02:00
pform_bind_attributes(pp->attributes, attr);
Carry Verilog 2001 attributes with processes, all the way through to the ivl_target API. Divide signal reference counts between rval and lval references.
2002-05-26 03:39:02 +02:00
Better handle nesting of scopes inside generate blocks. Within generate schemes it is possible to have nested scopes, even more liberally then outside generate blocks. So see to it that the scopes properly stack with the generate blocks, and that wires and behaviors are put in the right scopes.
2008-06-20 06:31:53 +02:00
pform_put_behavior_in_scope(pp);
Prevent non-blocking assignment in program blocks.
2012-05-06 19:21:51 +02:00
Fix some cppcheck warnings in the main directory
2012-08-08 20:26:46 +02:00
ivl_assert(*st, ! pform_cur_module.empty());
Add preliminary support for always_comb, always_ff and always_latch
2017-11-20 16:48:35 +01:00
if (pform_cur_module.front()->program_block &&
((type == IVL_PR_ALWAYS) || (type == IVL_PR_ALWAYS_COMB) ||
(type == IVL_PR_ALWAYS_FF) || (type == IVL_PR_ALWAYS_LATCH))) {
cerr << st->get_fileline() << ": error: Always statements are not allowed"
Prevent non-blocking assignment in program blocks.
2012-05-06 19:21:51 +02:00
<< " in program blocks." << endl;
error_count += 1;
}
Add the LineInfo class to carry the source file location of things. PGate, Statement and PProcess. elaborate handles module parameter mismatches, missing or incorrect lvalues for procedural assignment, and errors are propogated to the top of the elaboration call tree. Attach line numbers to processes, gates and assignment statements.
1999-01-25 06:45:56 +01:00
return pp;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
Added parser support for SV modport declarations.
2015-01-10 12:09:42 +01:00
void pform_start_modport_item(const struct vlltype&loc, const char*name)
{
Module*scope = pform_cur_module.front();
ivl_assert(loc, scope && scope->is_interface);
ivl_assert(loc, pform_cur_modport == 0);
perm_string use_name = lex_strings.make(name);
pform_cur_modport = new PModport(use_name);
FILE_NAME(pform_cur_modport, loc);
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
add_local_symbol(scope, use_name, pform_cur_modport);
Added parser support for SV modport declarations.
2015-01-10 12:09:42 +01:00
scope->modports[use_name] = pform_cur_modport;
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
Added parser support for SV modport declarations.
2015-01-10 12:09:42 +01:00
delete[] name;
}
void pform_end_modport_item(const struct vlltype&loc)
{
ivl_assert(loc, pform_cur_modport);
pform_cur_modport = 0;
}
void pform_add_modport_port(const struct vlltype&loc,
NetNet::PortType port_type,
perm_string name, PExpr*expr)
{
ivl_assert(loc, pform_cur_modport);
if (pform_cur_modport->simple_ports.find(name)
!= pform_cur_modport->simple_ports.end()) {
cerr << loc << ": error: duplicate declaration of port '"
<< name << "' in modport list '"
<< pform_cur_modport->name() << "'." << endl;
error_count += 1;
}
pform_cur_modport->simple_ports[name] = make_pair(port_type, expr);
}
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
FILE*vl_input = 0;
Add automatic module libraries.
2001-10-21 01:02:39 +02:00
extern void reset_lexor();
First step towards supporting separate compilation units in SV. This adds a -u option to the driver to allow the user to specify that they want each source file to be treated as a separate compilation unit, and modifies the compiler to accept a list of files (either on the command line or via a file specified by a new -F option). This list of files is then preprocessed and parsed separately, causing all compiler directives (including macro definitions) to only apply to the file containing them, as required by the SystemVerilog standard.
2017-10-15 12:45:35 +02:00
int pform_parse(const char*path)
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
{
Support the include directive.
1998-12-09 05:02:47 +01:00
vl_file = path;
First step towards supporting separate compilation units in SV. This adds a -u option to the driver to allow the user to specify that they want each source file to be treated as a separate compilation unit, and modifies the compiler to accept a list of files (either on the command line or via a file specified by a new -F option). This list of files is then preprocessed and parsed separately, causing all compiler directives (including macro definitions) to only apply to the file containing them, as required by the SystemVerilog standard.
2017-10-15 12:45:35 +02:00
if (strcmp(path, "-") == 0) {
vl_input = stdin;
} else if (ivlpp_string) {
char*cmdline = (char*)malloc(strlen(ivlpp_string) +
strlen(path) + 4);
strcpy(cmdline, ivlpp_string);
strcat(cmdline, " \"");
strcat(cmdline, path);
strcat(cmdline, "\"");
if (verbose_flag)
cerr << "Executing: " << cmdline << endl<< flush;
vl_input = popen(cmdline, "r");
Add automatic module libraries.
2001-10-21 01:02:39 +02:00
if (vl_input == 0) {
First step towards supporting separate compilation units in SV. This adds a -u option to the driver to allow the user to specify that they want each source file to be treated as a separate compilation unit, and modifies the compiler to accept a list of files (either on the command line or via a file specified by a new -F option). This list of files is then preprocessed and parsed separately, causing all compiler directives (including macro definitions) to only apply to the file containing them, as required by the SystemVerilog standard.
2017-10-15 12:45:35 +02:00
cerr << "Unable to preprocess " << path << "." << endl;
return 1;
Add automatic module libraries.
2001-10-21 01:02:39 +02:00
}
First step towards supporting separate compilation units in SV. This adds a -u option to the driver to allow the user to specify that they want each source file to be treated as a separate compilation unit, and modifies the compiler to accept a list of files (either on the command line or via a file specified by a new -F option). This list of files is then preprocessed and parsed separately, causing all compiler directives (including macro definitions) to only apply to the file containing them, as required by the SystemVerilog standard.
2017-10-15 12:45:35 +02:00
if (verbose_flag)
cerr << "...parsing output from preprocessor..." << endl << flush;
free(cmdline);
Add automatic module libraries.
2001-10-21 01:02:39 +02:00
} else {
First step towards supporting separate compilation units in SV. This adds a -u option to the driver to allow the user to specify that they want each source file to be treated as a separate compilation unit, and modifies the compiler to accept a list of files (either on the command line or via a file specified by a new -F option). This list of files is then preprocessed and parsed separately, causing all compiler directives (including macro definitions) to only apply to the file containing them, as required by the SystemVerilog standard.
2017-10-15 12:45:35 +02:00
vl_input = fopen(path, "r");
if (vl_input == 0) {
cerr << "Unable to open " << path << "." << endl;
return 1;
}
Support the include directive.
1998-12-09 05:02:47 +01:00
}
Support separate compilation units in SystemVerilog. The compilation unit scope is now treated as a specialised form of package (with an automatically generated name). All items declared outside a design element are added to the current compilation unit package. Apart from when searching for a symbol, once we get into elaboration we can treat these just like any other package.
2017-10-21 16:04:25 +02:00
if (pform_units.empty() || separate_compilation) {
char unit_name[20];
static unsigned nunits = 0;
if (separate_compilation)
sprintf(unit_name, "$unit#%u", ++nunits);
else
sprintf(unit_name, "$unit");
Rework handling of timescales in parser. This implements and enforces the full set of rules for determining timescales in SystemVerilog. The previous relaxation of the rules that allowed timescales to be redefined within the compilation unit scope has been removed. Time unit and precision redeclarations are now recognised after a nested module declaration.
2017-11-05 18:50:05 +01:00
Support separate compilation units in SystemVerilog. The compilation unit scope is now treated as a specialised form of package (with an automatically generated name). All items declared outside a design element are added to the current compilation unit package. Apart from when searching for a symbol, once we get into elaboration we can treat these just like any other package.
2017-10-21 16:04:25 +02:00
PPackage*unit = new PPackage(lex_strings.make(unit_name), 0);
unit->default_lifetime = LexicalScope::STATIC;
Rework handling of timescales in parser. This implements and enforces the full set of rules for determining timescales in SystemVerilog. The previous relaxation of the rules that allowed timescales to be redefined within the compilation unit scope has been removed. Time unit and precision redeclarations are now recognised after a nested module declaration.
2017-11-05 18:50:05 +01:00
unit->set_file(filename_strings.make(path));
unit->set_lineno(1);
Support separate compilation units in SystemVerilog. The compilation unit scope is now treated as a specialised form of package (with an automatically generated name). All items declared outside a design element are added to the current compilation unit package. Apart from when searching for a symbol, once we get into elaboration we can treat these just like any other package.
2017-10-21 16:04:25 +02:00
pform_units.push_back(unit);
Rework handling of timescales in parser. This implements and enforces the full set of rules for determining timescales in SystemVerilog. The previous relaxation of the rules that allowed timescales to be redefined within the compilation unit scope has been removed. Time unit and precision redeclarations are now recognised after a nested module declaration.
2017-11-05 18:50:05 +01:00
Reset parser tracking variables when starting a new compilation unit. This fixes the problem reported in GitHub issue #254, where if the parser aborted on one compilation unit, spurious errors were reported for the next compilation unit.
2019-07-23 23:18:39 +02:00
pform_cur_module.clear();
pform_cur_generate = 0;
pform_cur_modport = 0;
Rework handling of timescales in parser. This implements and enforces the full set of rules for determining timescales in SystemVerilog. The previous relaxation of the rules that allowed timescales to be redefined within the compilation unit scope has been removed. Time unit and precision redeclarations are now recognised after a nested module declaration.
2017-11-05 18:50:05 +01:00
pform_set_timescale(def_ts_units, def_ts_prec, 0, 0);
allow_timeunit_decl = true;
allow_timeprec_decl = true;
Support separate compilation units in SystemVerilog. The compilation unit scope is now treated as a specialised form of package (with an automatically generated name). All items declared outside a design element are added to the current compilation unit package. Apart from when searching for a symbol, once we get into elaboration we can treat these just like any other package.
2017-10-21 16:04:25 +02:00
lexical_scope = unit;
}
Add automatic module libraries.
2001-10-21 01:02:39 +02:00
reset_lexor();
Handle procedural conditional, and some of the conditional expressions. Elaborate signals and identifiers differently, allowing the netlist to hold signal information.
1998-11-07 18:05:05 +01:00
error_count = 0;
warn_count = 0;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
int rc = VLparse();
Add automatic module libraries.
2001-10-21 01:02:39 +02:00
First step towards supporting separate compilation units in SV. This adds a -u option to the driver to allow the user to specify that they want each source file to be treated as a separate compilation unit, and modifies the compiler to accept a list of files (either on the command line or via a file specified by a new -F option). This list of files is then preprocessed and parsed separately, causing all compiler directives (including macro definitions) to only apply to the file containing them, as required by the SystemVerilog standard.
2017-10-15 12:45:35 +02:00
if (vl_input != stdin) {
if (ivlpp_string)
pclose(vl_input);
Fix trailing whitespace.
2017-11-05 23:28:21 +01:00
else
First step towards supporting separate compilation units in SV. This adds a -u option to the driver to allow the user to specify that they want each source file to be treated as a separate compilation unit, and modifies the compiler to accept a list of files (either on the command line or via a file specified by a new -F option). This list of files is then preprocessed and parsed separately, causing all compiler directives (including macro definitions) to only apply to the file containing them, as required by the SystemVerilog standard.
2017-10-15 12:45:35 +02:00
fclose(vl_input);
}
Add automatic module libraries.
2001-10-21 01:02:39 +02:00
Handle procedural conditional, and some of the conditional expressions. Elaborate signals and identifiers differently, allowing the netlist to hold signal information.
1998-11-07 18:05:05 +01:00
if (rc) {
cerr << "I give up." << endl;
Error message for invalid variable list.
2000-09-13 18:32:26 +02:00
error_count += 1;
Handle procedural conditional, and some of the conditional expressions. Elaborate signals and identifiers differently, allowing the netlist to hold signal information.
1998-11-07 18:05:05 +01:00
}
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
Some compiler cleanup and minor memory leak fixes. This patch cleans up some unneeded code. Releases some allocated memory before the compiler quits and fixes a couple minor memory leaks in the compiler and vvp code generator.
2009-06-09 22:12:45 +02:00
destroy_lexor();
Handle procedural conditional, and some of the conditional expressions. Elaborate signals and identifiers differently, allowing the netlist to hold signal information.
1998-11-07 18:05:05 +01:00
return error_count;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}