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iverilog/elaborate.cc

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Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
/*
Keep processes in proper lexical scope Normally processes are found in the lexical scope of a module, but there are special cases where processes (other then task/function definitions) are in other lexical scopes. The most likely case is initilizations that are in the lexical scope where the assigned variable is declared. In the process, the behaviors list is kept in the base PScope class instead of the Module or any other derived lexical scope class.
2008-03-04 05:49:52 +01:00
* Copyright (c) 1998-2008 Stephen Williams (steve@icarus.com)
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
Create a config.h.in file to hold all the config junk, and support gcc 3.0. (Stephan Boettcher)
2001-07-25 05:10:48 +02:00
# include "config.h"
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
/*
* Elaboration takes as input a complete parse tree and the name of a
* root module, and generates as output the elaborated design. This
* elaborated design is presented as a Module, which does not
* reference any other modules. It is entirely self contained.
*/
# include <typeinfo>
header includes for gcc-4.3 compatibility minimal changes required to build without error tested with gcc-4.3 (Debian 4.3-20071130-1) 4.3.0 20071130 (experimental)
2008-01-05 00:23:47 +01:00
# include <cstdlib>
Move strstream to ostringstream for compatibility.
2003-01-14 22:16:18 +01:00
# include <sstream>
Support multiple root modules (Philip Blundell)
2001-10-19 23:53:24 +02:00
# include <list>
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
# include "pform.h"
Simulate named event trigger and waits.
2000-04-04 05:20:15 +02:00
# include "PEvent.h"
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
# include "PGenerate.h"
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
# include "PSpec.h"
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
# include "netlist.h"
Allow expanding of additive operators.
1999-09-29 02:42:50 +02:00
# include "netmisc.h"
Catch memory word parameters to tasks.
2000-04-28 18:50:53 +02:00
# include "util.h"
Add automatic module libraries.
2001-10-21 01:02:39 +02:00
# include "parse_api.h"
Do not allow implicit wires in sensitivity lists.
2002-04-22 02:53:39 +02:00
# include "compiler.h"
Parse all specify paths to pform.
2007-02-12 02:52:21 +01:00
# include "ivl_assert.h"
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
Add language support for Verilog-2001 attribute syntax. Hook this support into existing $attribute handling, and add number and void value types. Add to the ivl_target API new functions for access of complex attributes attached to gates.
2002-05-23 05:08:50 +02:00
Carry strength values from Verilog source to the pform and netlist for gates. Change vvm constants to use the driver_t to drive a constant value. This works better if there are multiple drivers on a signal.
2000-05-07 06:37:55 +02:00
static Link::strength_t drive_type(PGate::strength_t drv)
{
switch (drv) {
case PGate::HIGHZ:
return Link::HIGHZ;
case PGate::WEAK:
return Link::WEAK;
case PGate::PULL:
return Link::PULL;
case PGate::STRONG:
return Link::STRONG;
case PGate::SUPPLY:
return Link::SUPPLY;
default:
assert(0);
}
return Link::STRONG;
}
Catch memory word parameters to tasks.
2000-04-28 18:50:53 +02:00
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
void PGate::elaborate(Design*des, NetScope*scope) const
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
{
Add non-const bit select in l-value of assignment.
1999-10-07 07:25:33 +02:00
cerr << "internal error: what kind of gate? " <<
typeid(*this).name() << endl;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
separate assign lval elaboration for error checking.
1999-09-15 06:17:52 +02:00
/*
* Elaborate the continuous assign. (This is *not* the procedural
* assign.) Elaborate the lvalue and rvalue, and do the assignment.
*/
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
void PGAssign::elaborate(Design*des, NetScope*scope) const
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
{
Put logic devices into scopes.
2000-10-07 21:45:42 +02:00
assert(scope);
Node delays can be more general expressions in structural contexts.
2006-01-02 06:33:19 +01:00
NetExpr* rise_time, *fall_time, *decay_time;
Handle complex net node delays.
2006-01-03 06:22:14 +01:00
eval_delays(des, scope, rise_time, fall_time, decay_time, true);
elaborate rise/fall/decay for continuous assign.
1999-08-01 23:18:55 +02:00
Carry strength values from Verilog source to the pform and netlist for gates. Change vvm constants to use the driver_t to drive a constant value. This works better if there are multiple drivers on a signal.
2000-05-07 06:37:55 +02:00
Link::strength_t drive0 = drive_type(strength0());
Link::strength_t drive1 = drive_type(strength1());
Add support for the Ternary operator, Add support for repeat concatenation, Correct some seg faults cause by elaboration errors, Parse the casex anc casez statements.
1999-06-10 06:03:52 +02:00
assert(pin(0));
assert(pin(1));
Much expression parsing work, mark continuous assigns with source line info, replace some assertion failures with Sorry messages.
1999-05-20 06:31:45 +02:00
separate assign lval elaboration for error checking.
1999-09-15 06:17:52 +02:00
/* Elaborate the l-value. */
Move implicit net creation from elaboration to elaborate_sig If implicit nets are declared during elaboration, then the success of binding during elaboration will depend on the order of the code in the source file.
2008-03-19 04:50:40 +01:00
NetNet*lval = pin(0)->elaborate_lnet(des, scope);
Much expression parsing work, mark continuous assigns with source line info, replace some assertion failures with Sorry messages.
1999-05-20 06:31:45 +02:00
if (lval == 0) {
return;
}
Use the expression with to calculate expression width in assignments. In continuous assignment, the width of the expression needs to come from the expression itself, and not just from the width of the l-value. Use the PExpr::test_width method to get the width of the expression to pass to the elaborate.
2008-08-27 06:33:24 +02:00
ivl_assert(*this, lval->pin_count() == 1);
Rework of internals to carry vectors through nexus instead of single bits. Make the ivl, tgt-vvp and vvp initial changes down this path.
2004-12-11 03:31:25 +01:00
if (debug_elaborate) {
Comparison arguments are in a self determined context. This patch makes comparison arguments be evaluated in a self determined context. It also cleans up some other code items.
2008-06-14 00:50:17 +02:00
cerr << get_fileline() << ": debug: PGAssign: elaborated l-value"
More debug information.
2005-07-15 02:41:09 +02:00
<< " width=" << lval->vector_width()
<< ", type=" << lval->data_type() << endl;
Rework of internals to carry vectors through nexus instead of single bits. Make the ivl, tgt-vvp and vvp initial changes down this path.
2004-12-11 03:31:25 +01:00
}
separate assign lval elaboration for error checking.
1999-09-15 06:17:52 +02:00
Unify all the r-value elaboration. R-value expression elaboration happens in several places. Factor out the common code so that they are all handled correctly and uniformly.
2008-09-26 06:22:21 +02:00
NetExpr*rval_expr = elaborate_rval_expr(des, scope, lval->data_type(),
lval->vector_width(), pin(1));
Fix bit padding of assign signal-to-signal
2000-09-07 03:29:44 +02:00
Continuous assign no longer uses elaborate_net. convert the continuous assign elaboration to use elaborate_expr and synthesize methods instead of the elaborate_net methods of PExpr. This exposes problems with the synthesize methods, but it is a better way to do it.
2008-08-12 06:21:33 +02:00
if (rval_expr == 0) {
cerr << get_fileline() << ": error: Unable to elaborate r-value: "
<< *pin(1) << endl;
des->errors += 1;
Use bufz to make assignments directional.
2000-05-08 07:28:29 +02:00
return;
}
Sign extend r-values that refuse to pad themselves. There are cases where the r-value doesn't pad itself to the width that is requested by the call to elaborate_expr. This impacts the elaboration of PGAssign. Pad/sign extend as appropreate.
2008-10-03 07:02:35 +02:00
if (type_is_vectorable(rval_expr->expr_type())
&& type_is_vectorable(lval->data_type())
&& rval_expr->expr_width() < lval->vector_width()) {
if (debug_elaborate) {
cerr << get_fileline() << ": debug: "
<< "r-value expressions width "<<rval_expr->expr_width()
<< " of " << (rval_expr->has_sign()? "signed":"unsigned")
<< " expression is to small for l-value width "
<< lval->vector_width() << "." << endl;
}
rval_expr = pad_to_width(rval_expr, lval->vector_width());
}
Continuous assign no longer uses elaborate_net. convert the continuous assign elaboration to use elaborate_expr and synthesize methods instead of the elaborate_net methods of PExpr. This exposes problems with the synthesize methods, but it is a better way to do it.
2008-08-12 06:21:33 +02:00
NetNet*rval = rval_expr->synthesize(des, scope);
Much expression parsing work, mark continuous assigns with source line info, replace some assertion failures with Sorry messages.
1999-05-20 06:31:45 +02:00
if (rval == 0) {
Continuous assign no longer uses elaborate_net. convert the continuous assign elaboration to use elaborate_expr and synthesize methods instead of the elaborate_net methods of PExpr. This exposes problems with the synthesize methods, but it is a better way to do it.
2008-08-12 06:21:33 +02:00
cerr << get_fileline() << ": internal error: "
<< "Failed to synthesize expression: " << *rval_expr << endl;
Much expression parsing work, mark continuous assigns with source line info, replace some assertion failures with Sorry messages.
1999-05-20 06:31:45 +02:00
des->errors += 1;
return;
}
Debug messages for PGAssign elaboration.
2005-01-30 02:42:05 +01:00
if (debug_elaborate) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": debug: PGAssign: elaborated r-value"
Continuous assign no longer uses elaborate_net. convert the continuous assign elaboration to use elaborate_expr and synthesize methods instead of the elaborate_net methods of PExpr. This exposes problems with the synthesize methods, but it is a better way to do it.
2008-08-12 06:21:33 +02:00
<< " width="<< rval->vector_width()
Extra diagnostic details in elaboration of continuous assignment.
2008-08-16 06:19:04 +02:00
<< ", type="<< rval->data_type()
<< ", expr=" << *rval_expr << endl;
Debug messages for PGAssign elaboration.
2005-01-30 02:42:05 +01:00
}
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
assert(lval && rval);
Rework of internals to carry vectors through nexus instead of single bits. Make the ivl, tgt-vvp and vvp initial changes down this path.
2004-12-11 03:31:25 +01:00
assert(rval->pin_count() == 1);
Pad limited r-values in continuous assignments.
2001-11-05 00:12:29 +01:00
Handle special case of net assigned to net. When nets are assigned directly to a net, we need to create a driver to carry the strength. Normally, the implied drive of a continuous assignment is carried by whatever gate the r-value expression ends with, but with simble net-to-net assignment, there is no net so we need to install a BUFZ to carry the assignment.
2008-08-13 06:03:38 +02:00
// Detect the case that the rvalue-expression is a simple
// expression. In this case, we will need to create a driver
// (later) to carry strengths.
bool need_driver_flag = false;
if (dynamic_cast<NetESignal*>(rval_expr))
need_driver_flag = true;
Add .cast/int and update .cast/real. This patch adds .cast/int and updates .cast/real to act as a local (temporary) net and to support either a signed or unsigned input. The vvp_vector4_t class not can convert an arbitrarily sized double to a vector value. This removes the restriction of lround(). Also document the new statements.
2008-06-21 03:11:11 +02:00
/* Cast the right side when needed. */
if ((lval->data_type() == IVL_VT_REAL &&
rval->data_type() != IVL_VT_REAL)) {
rval = cast_to_real(des, scope, rval);
Handle special case of net assigned to net. When nets are assigned directly to a net, we need to create a driver to carry the strength. Normally, the implied drive of a continuous assignment is carried by whatever gate the r-value expression ends with, but with simble net-to-net assignment, there is no net so we need to install a BUFZ to carry the assignment.
2008-08-13 06:03:38 +02:00
need_driver_flag = false;
Add .cast/int and update .cast/real. This patch adds .cast/int and updates .cast/real to act as a local (temporary) net and to support either a signed or unsigned input. The vvp_vector4_t class not can convert an arbitrarily sized double to a vector value. This removes the restriction of lround(). Also document the new statements.
2008-06-21 03:11:11 +02:00
} else if ((lval->data_type() != IVL_VT_REAL &&
rval->data_type() == IVL_VT_REAL)) {
rval = cast_to_int(des, scope, rval, lval->vector_width());
Handle special case of net assigned to net. When nets are assigned directly to a net, we need to create a driver to carry the strength. Normally, the implied drive of a continuous assignment is carried by whatever gate the r-value expression ends with, but with simble net-to-net assignment, there is no net so we need to install a BUFZ to carry the assignment.
2008-08-13 06:03:38 +02:00
need_driver_flag = false;
Force the L-value and R-value to match for real values. Check that if either the L-value or the R-value are real then both must be real. This prevents a runtime crash.
2008-02-13 23:02:35 +01:00
}
Pad limited r-values in continuous assignments.
2001-11-05 00:12:29 +01:00
/* If the r-value insists on being smaller then the l-value
(perhaps it is explicitly sized) the pad it out to be the
right width so that something is connected to all the bits
of the l-value. */
Pad signed expressions in continuous asignments When the continuous assignment is signed, then sign-extend the r-value in the few cases where the expression is stubbornly smaller then the desired width.
2008-08-15 05:38:34 +02:00
if (lval->vector_width() > rval->vector_width()) {
if (rval->get_signed())
rval = pad_to_width_signed(des, rval, lval->vector_width());
else
rval = pad_to_width(des, rval, lval->vector_width());
}
Handle part selects as l-values to continuous assign.
1999-06-13 01:16:37 +02:00
Chop down assign r-values that elaborate too wide.
2006-04-26 06:43:50 +02:00
/* If, on the other hand, the r-value insists on being
LARGER then the l-value, use a part select to chop it down
down to size. */
if (lval->vector_width() < rval->vector_width()) {
NetPartSelect*tmp = new NetPartSelect(rval, 0,lval->vector_width(),
NetPartSelect::VP);
des->add_node(tmp);
tmp->set_line(*this);
NetNet*osig = new NetNet(scope, scope->local_symbol(),
NetNet::TRI, lval->vector_width());
osig->set_line(*this);
Fix a spurious non-local net. During elaboration of continuous assignment that connected the rval to the lval with a part select forgot to mark the signal it created as temporary.
2008-08-13 06:31:39 +02:00
osig->local_flag(true);
Chop down assign r-values that elaborate too wide.
2006-04-26 06:43:50 +02:00
osig->data_type(rval->data_type());
connect(osig->pin(0), tmp->pin(0));
rval = osig;
Handle special case of net assigned to net. When nets are assigned directly to a net, we need to create a driver to carry the strength. Normally, the implied drive of a continuous assignment is carried by whatever gate the r-value expression ends with, but with simble net-to-net assignment, there is no net so we need to install a BUFZ to carry the assignment.
2008-08-13 06:03:38 +02:00
need_driver_flag = false;
}
if (need_driver_flag) {
NetBUFZ*driver = new NetBUFZ(scope, scope->local_symbol(),
rval->vector_width());
driver->set_line(*this);
des->add_node(driver);
connect(rval->pin(0), driver->pin(1));
NetNet*tmp = new NetNet(scope, scope->local_symbol(),
NetNet::WIRE, rval->vector_width());
tmp->set_line(*this);
tmp->data_type(rval->data_type());
tmp->local_flag(true);
connect(driver->pin(0), tmp->pin(0));
rval = tmp;
Chop down assign r-values that elaborate too wide.
2006-04-26 06:43:50 +02:00
}
Continuous assign no longer uses elaborate_net. convert the continuous assign elaboration to use elaborate_expr and synthesize methods instead of the elaborate_net methods of PExpr. This exposes problems with the synthesize methods, but it is a better way to do it.
2008-08-12 06:21:33 +02:00
/* Set the drive and delays for the r-val. */
if (drive0 != Link::STRONG || drive1 != Link::STRONG)
rval->pin(0).drivers_drive(drive0, drive1);
if (rise_time || fall_time || decay_time)
Get delays of signed extended continuous assignments right. Padding and continuous assignment caused problems if the continuous assignment includes a delay. The problem is that the padding was not necessarily included in the delay. Rework the elaboration to make sure the padding is indeed included in the delay.
2008-02-02 05:13:23 +01:00
rval->pin(0).drivers_delays(rise_time, fall_time, decay_time);
Rework of internals to carry vectors through nexus instead of single bits. Make the ivl, tgt-vvp and vvp initial changes down this path.
2004-12-11 03:31:25 +01:00
connect(lval->pin(0), rval->pin(0));
Accept adder parameters with different widths, and simplify continuous assign construction.
1999-10-08 19:27:23 +02:00
if (lval->local_flag())
delete lval;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
Handle logic gates with multiple outputs. Logic gates usually have one output and several inputs, but a few have multiple outputs and one input. Since the NetNode objects have only a single output, handle the case by creating multiple NetNode objects, one for each output.
2008-09-15 06:04:03 +02:00
unsigned PGBuiltin::calculate_array_count_(Design*des, NetScope*scope,
long&high, long&low) const
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
{
Elaborate gate ranges.
1999-02-15 03:06:15 +01:00
unsigned count = 1;
Handle logic gates with multiple outputs. Logic gates usually have one output and several inputs, but a few have multiple outputs and one input. Since the NetNode objects have only a single output, handle the case by creating multiple NetNode objects, one for each output.
2008-09-15 06:04:03 +02:00
high = 0;
low = 0;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
Spelling fixes.
2003-01-27 06:09:17 +01:00
/* If the Verilog source has a range specification for the
Spelling fixes from Larry
2007-03-22 17:08:14 +01:00
gates, then I am expected to make more than one
Elaborate gate ranges.
1999-02-15 03:06:15 +01:00
gate. Figure out how many are desired. */
if (msb_) {
Make elaborate_expr methods aware of the width that the context requires of it. In the process, fix sizing of the width of unary minus is context determined sizes.
2006-06-02 06:48:49 +02:00
NetExpr*msb_exp = elab_and_eval(des, scope, msb_, -1);
NetExpr*lsb_exp = elab_and_eval(des, scope, lsb_, -1);
Elaborate gate ranges.
1999-02-15 03:06:15 +01:00
Evaluate gate array index constants using elab_and_eval.
2003-09-20 08:00:37 +02:00
NetEConst*msb_con = dynamic_cast<NetEConst*>(msb_exp);
NetEConst*lsb_con = dynamic_cast<NetEConst*>(lsb_exp);
if (msb_con == 0) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: Unable to evaluate "
Add non-const bit select in l-value of assignment.
1999-10-07 07:25:33 +02:00
"expression " << *msb_ << endl;
Elaborate gate ranges.
1999-02-15 03:06:15 +01:00
des->errors += 1;
Handle logic gates with multiple outputs. Logic gates usually have one output and several inputs, but a few have multiple outputs and one input. Since the NetNode objects have only a single output, handle the case by creating multiple NetNode objects, one for each output.
2008-09-15 06:04:03 +02:00
return 0;
Elaborate gate ranges.
1999-02-15 03:06:15 +01:00
}
Evaluate gate array index constants using elab_and_eval.
2003-09-20 08:00:37 +02:00
if (lsb_con == 0) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: Unable to evaluate "
Add non-const bit select in l-value of assignment.
1999-10-07 07:25:33 +02:00
"expression " << *lsb_ << endl;
Elaborate gate ranges.
1999-02-15 03:06:15 +01:00
des->errors += 1;
Handle logic gates with multiple outputs. Logic gates usually have one output and several inputs, but a few have multiple outputs and one input. Since the NetNode objects have only a single output, handle the case by creating multiple NetNode objects, one for each output.
2008-09-15 06:04:03 +02:00
return 0;
Elaborate gate ranges.
1999-02-15 03:06:15 +01:00
}
Evaluate gate array index constants using elab_and_eval.
2003-09-20 08:00:37 +02:00
verinum msb = msb_con->value();
verinum lsb = lsb_con->value();
delete msb_exp;
delete lsb_exp;
if (msb.as_long() > lsb.as_long())
count = msb.as_long() - lsb.as_long() + 1;
Elaborate gate ranges.
1999-02-15 03:06:15 +01:00
else
Evaluate gate array index constants using elab_and_eval.
2003-09-20 08:00:37 +02:00
count = lsb.as_long() - msb.as_long() + 1;
Elaborate gate ranges.
1999-02-15 03:06:15 +01:00
Evaluate gate array index constants using elab_and_eval.
2003-09-20 08:00:37 +02:00
low = lsb.as_long();
high = msb.as_long();
Unify elaboration of l-values for all proceedural assignments, including assing, cassign and force. Generate NetConcat devices for gate outputs that feed into a vector results. Use this to hande gate arrays. Also let gate arrays handle vectors of gates when the outputs allow for it.
2004-12-30 00:55:43 +01:00
if (debug_elaborate) {
Spelling fixes Mostly comments, but includes quite a few user-visible error, debug, and help messages.
2008-06-12 19:04:29 +02:00
cerr << get_fileline() << ": debug: PGBuiltin: Make array "
Unify elaboration of l-values for all proceedural assignments, including assing, cassign and force. Generate NetConcat devices for gate outputs that feed into a vector results. Use this to hande gate arrays. Also let gate arrays handle vectors of gates when the outputs allow for it.
2004-12-30 00:55:43 +01:00
<< "[" << high << ":" << low << "]"
Handle logic gates with multiple outputs. Logic gates usually have one output and several inputs, but a few have multiple outputs and one input. Since the NetNode objects have only a single output, handle the case by creating multiple NetNode objects, one for each output.
2008-09-15 06:04:03 +02:00
<< " of " << count << " gates for " << get_name() << endl;
Unify elaboration of l-values for all proceedural assignments, including assing, cassign and force. Generate NetConcat devices for gate outputs that feed into a vector results. Use this to hande gate arrays. Also let gate arrays handle vectors of gates when the outputs allow for it.
2004-12-30 00:55:43 +01:00
}
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
Handle logic gates with multiple outputs. Logic gates usually have one output and several inputs, but a few have multiple outputs and one input. Since the NetNode objects have only a single output, handle the case by creating multiple NetNode objects, one for each output.
2008-09-15 06:04:03 +02:00
return count;
}
unsigned PGBuiltin::calculate_output_count_(void) const
{
unsigned output_count;
switch (type()) {
case BUF:
case NOT:
output_count = pin_count() - 1;
break;
case PULLDOWN:
case PULLUP:
output_count = pin_count();
break;
default:
output_count = 1;
break;
}
return output_count;
}
NetNode* PGBuiltin::create_gate_for_output_(Design*des, NetScope*scope,
perm_string gate_name,
unsigned instance_width) const
{
NetNode*gate = 0;
switch (type()) {
case AND:
if (pin_count() < 2) {
cerr << get_fileline() << ": error: the AND "
"primitive must have an input." << endl;
des->errors += 1;
} else {
gate = new NetLogic(scope, gate_name, pin_count(),
NetLogic::AND, instance_width);
}
break;
case BUF:
gate = new NetLogic(scope, gate_name, 2,
NetLogic::BUF, instance_width);
break;
case BUFIF0:
if (pin_count() != 3) {
cerr << get_fileline() << ": error: the BUFIF0 "
"primitive must have three arguments." << endl;
des->errors += 1;
} else {
gate = new NetLogic(scope, gate_name, pin_count(),
NetLogic::BUFIF0, instance_width);
}
break;
case BUFIF1:
if (pin_count() != 3) {
cerr << get_fileline() << ": error: the BUFIF1 "
"primitive must have three arguments." << endl;
des->errors += 1;
} else {
gate = new NetLogic(scope, gate_name, pin_count(),
NetLogic::BUFIF1, instance_width);
}
break;
case CMOS:
if (pin_count() != 4) {
cerr << get_fileline() << ": error: the CMOS "
"primitive must have four arguments." << endl;
des->errors += 1;
} else {
gate = new NetLogic(scope, gate_name, pin_count(),
NetLogic::CMOS, instance_width);
}
break;
case NAND:
if (pin_count() < 2) {
cerr << get_fileline() << ": error: the NAND "
"primitive must have an input." << endl;
des->errors += 1;
} else {
gate = new NetLogic(scope, gate_name, pin_count(),
NetLogic::NAND, instance_width);
}
break;
case NMOS:
if (pin_count() != 3) {
cerr << get_fileline() << ": error: the NMOS "
"primitive must have three arguments." << endl;
des->errors += 1;
} else {
gate = new NetLogic(scope, gate_name, pin_count(),
NetLogic::NMOS, instance_width);
}
break;
case NOR:
if (pin_count() < 2) {
cerr << get_fileline() << ": error: the NOR "
"primitive must have an input." << endl;
des->errors += 1;
} else {
gate = new NetLogic(scope, gate_name, pin_count(),
NetLogic::NOR, instance_width);
}
break;
case NOT:
gate = new NetLogic(scope, gate_name, 2,
NetLogic::NOT, instance_width);
break;
case NOTIF0:
if (pin_count() != 3) {
cerr << get_fileline() << ": error: the NOTIF0 "
"primitive must have three arguments." << endl;
des->errors += 1;
} else {
gate = new NetLogic(scope, gate_name, pin_count(),
NetLogic::NOTIF0, instance_width);
}
break;
case NOTIF1:
if (pin_count() != 3) {
cerr << get_fileline() << ": error: the NOTIF1 "
"primitive must have three arguments." << endl;
des->errors += 1;
} else {
gate = new NetLogic(scope, gate_name, pin_count(),
NetLogic::NOTIF1, instance_width);
}
break;
case OR:
if (pin_count() < 2) {
cerr << get_fileline() << ": error: the OR "
"primitive must have an input." << endl;
des->errors += 1;
} else {
gate = new NetLogic(scope, gate_name, pin_count(),
NetLogic::OR, instance_width);
}
break;
case RCMOS:
if (pin_count() != 4) {
cerr << get_fileline() << ": error: the RCMOS "
"primitive must have four arguments." << endl;
des->errors += 1;
} else {
gate = new NetLogic(scope, gate_name, pin_count(),
NetLogic::RCMOS, instance_width);
}
break;
Unify elaboration of l-values for all proceedural assignments, including assing, cassign and force. Generate NetConcat devices for gate outputs that feed into a vector results. Use this to hande gate arrays. Also let gate arrays handle vectors of gates when the outputs allow for it.
2004-12-30 00:55:43 +01:00
Handle logic gates with multiple outputs. Logic gates usually have one output and several inputs, but a few have multiple outputs and one input. Since the NetNode objects have only a single output, handle the case by creating multiple NetNode objects, one for each output.
2008-09-15 06:04:03 +02:00
case RNMOS:
if (pin_count() != 3) {
cerr << get_fileline() << ": error: the RNMOS "
"primitive must have three arguments." << endl;
des->errors += 1;
} else {
gate = new NetLogic(scope, gate_name, pin_count(),
NetLogic::RNMOS, instance_width);
}
break;
case RPMOS:
if (pin_count() != 3) {
cerr << get_fileline() << ": error: the RPMOS "
"primitive must have three arguments." << endl;
des->errors += 1;
} else {
gate = new NetLogic(scope, gate_name, pin_count(),
NetLogic::RPMOS, instance_width);
}
break;
case PMOS:
if (pin_count() != 3) {
cerr << get_fileline() << ": error: the PMOS "
"primitive must have three arguments." << endl;
des->errors += 1;
} else {
gate = new NetLogic(scope, gate_name, pin_count(),
NetLogic::PMOS, instance_width);
}
break;
case PULLDOWN:
gate = new NetLogic(scope, gate_name, 1,
NetLogic::PULLDOWN, instance_width);
break;
case PULLUP:
gate = new NetLogic(scope, gate_name, 1,
NetLogic::PULLUP, instance_width);
break;
case XNOR:
if (pin_count() < 2) {
cerr << get_fileline() << ": error: the XNOR "
"primitive must have an input." << endl;
des->errors += 1;
} else {
gate = new NetLogic(scope, gate_name, pin_count(),
NetLogic::XNOR, instance_width);
}
break;
case XOR:
if (pin_count() < 2) {
cerr << get_fileline() << ": error: the XOR "
"primitive must have an input." << endl;
des->errors += 1;
} else {
gate = new NetLogic(scope, gate_name, pin_count(),
NetLogic::XOR, instance_width);
}
break;
case TRAN:
if (pin_count() != 2) {
cerr << get_fileline() << ": error: Pin count for "
<< "tran device." << endl;
des->errors += 1;
} else {
gate = new NetTran(scope, gate_name, IVL_SW_TRAN);
}
break;
case RTRAN:
if (pin_count() != 2) {
cerr << get_fileline() << ": error: Pin count for "
<< "rtran device." << endl;
des->errors += 1;
} else {
gate = new NetTran(scope, gate_name, IVL_SW_RTRAN);
}
break;
case TRANIF0:
if (pin_count() != 3) {
cerr << get_fileline() << ": error: Pin count for "
<< "tranif0 device." << endl;
des->errors += 1;
} else {
gate = new NetTran(scope, gate_name, IVL_SW_TRANIF0);
}
break;
case RTRANIF0:
if (pin_count() != 3) {
cerr << get_fileline() << ": error: Pin count for "
<< "rtranif0 device." << endl;
des->errors += 1;
} else {
gate = new NetTran(scope, gate_name, IVL_SW_RTRANIF0);
}
break;
case TRANIF1:
if (pin_count() != 3) {
cerr << get_fileline() << ": error: Pin count for "
<< "tranif1 device." << endl;
des->errors += 1;
} else {
gate = new NetTran(scope, gate_name, IVL_SW_TRANIF1);
}
break;
case RTRANIF1:
if (pin_count() != 3) {
cerr << get_fileline() << ": error: Pin count for "
<< "rtranif1 device." << endl;
des->errors += 1;
} else {
gate = new NetTran(scope, gate_name, IVL_SW_RTRANIF1);
}
break;
default:
cerr << get_fileline() << ": internal error: unhandled "
"gate type." << endl;
Check that logic gates are not given null ports. Logic gates do not handle null ports so check for this and issue an error message when it happens.
2007-08-30 02:29:56 +02:00
des->errors += 1;
Handle logic gates with multiple outputs. Logic gates usually have one output and several inputs, but a few have multiple outputs and one input. Since the NetNode objects have only a single output, handle the case by creating multiple NetNode objects, one for each output.
2008-09-15 06:04:03 +02:00
break;
}
return gate;
}
/*
* Elaborate a Builtin gate. These normally get translated into
* NetLogic nodes that reflect the particular logic function.
*/
void PGBuiltin::elaborate(Design*des, NetScope*scope) const
{
unsigned instance_width = 1;
perm_string name = get_name();
if (name == "")
name = scope->local_symbol();
/* Calculate the array bounds and instance count for the gate,
as described in the Verilog source. If there is none, then
the count is 1, and high==low==0. */
long low=0, high=0;
unsigned array_count = calculate_array_count_(des, scope, high, low);
if (array_count == 0)
Check that logic gates are not given null ports. Logic gates do not handle null ports so check for this and issue an error message when it happens.
2007-08-30 02:29:56 +02:00
return;
Handle logic gates with multiple outputs. Logic gates usually have one output and several inputs, but a few have multiple outputs and one input. Since the NetNode objects have only a single output, handle the case by creating multiple NetNode objects, one for each output.
2008-09-15 06:04:03 +02:00
unsigned output_count = calculate_output_count_();
/* Now we have a gate count. Elaborate the output expressions
only. We do it early so that we can see if we can make
wide gates instead of an array of gates. */
vector<NetNet*>lval_sigs (output_count);
for (unsigned idx = 0 ; idx < output_count ; idx += 1) {
if (pin(idx) == 0) {
cerr << get_fileline() << ": error: Logic gate port "
"expressions are not optional." << endl;
des->errors += 1;
return;
}
lval_sigs[idx] = pin(idx)->elaborate_lnet(des, scope);
ivl_assert(*this, lval_sigs[idx]);
// For now, assume all the outputs are the same width.
ivl_assert(*this, idx == 0 || lval_sigs[idx]->vector_width() == lval_sigs[0]->vector_width());
Check that logic gates are not given null ports. Logic gates do not handle null ports so check for this and issue an error message when it happens.
2007-08-30 02:29:56 +02:00
}
Unify elaboration of l-values for all proceedural assignments, including assing, cassign and force. Generate NetConcat devices for gate outputs that feed into a vector results. Use this to hande gate arrays. Also let gate arrays handle vectors of gates when the outputs allow for it.
2004-12-30 00:55:43 +01:00
/* Detect the special case that the l-value width exactly
matches the gate count. In this case, we will make a single
Handle logic gates with multiple outputs. Logic gates usually have one output and several inputs, but a few have multiple outputs and one input. Since the NetNode objects have only a single output, handle the case by creating multiple NetNode objects, one for each output.
2008-09-15 06:04:03 +02:00
gate that has the desired vector width.
NOTE: This assumes that all the outputs have the same
width. For gates with 1 output, this is trivially true. */
if (lval_sigs[0]->vector_width() == array_count) {
instance_width = array_count;
array_count = 1;
Unify elaboration of l-values for all proceedural assignments, including assing, cassign and force. Generate NetConcat devices for gate outputs that feed into a vector results. Use this to hande gate arrays. Also let gate arrays handle vectors of gates when the outputs allow for it.
2004-12-30 00:55:43 +01:00
Use PartSelect/PV and VP to handle part selects through ports.
2005-01-09 21:16:00 +01:00
if (debug_elaborate && instance_width != 1)
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": debug: PGBuiltin: "
Unify elaboration of l-values for all proceedural assignments, including assing, cassign and force. Generate NetConcat devices for gate outputs that feed into a vector results. Use this to hande gate arrays. Also let gate arrays handle vectors of gates when the outputs allow for it.
2004-12-30 00:55:43 +01:00
"Collapsed gate array into single wide "
"(" << instance_width << ") instance." << endl;
}
Elaborate gate ranges.
1999-02-15 03:06:15 +01:00
Parse and elaborate rise/fall/decay times for gates, and handle the rules for partial lists of times.
1999-08-01 18:34:50 +02:00
/* Calculate the gate delays from the delay expressions
given in the source. For logic gates, the decay time
is meaningless because it can never go to high
Spelling fixes.
2003-01-27 06:09:17 +01:00
impedance. However, the bufif devices can generate
Parse and elaborate rise/fall/decay times for gates, and handle the rules for partial lists of times.
1999-08-01 18:34:50 +02:00
'bz output, so we will pretend that anything can.
Spelling fixes.
2003-01-27 06:09:17 +01:00
If only one delay value expression is given (i.e., #5
Parse and elaborate rise/fall/decay times for gates, and handle the rules for partial lists of times.
1999-08-01 18:34:50 +02:00
nand(foo,...)) then rise, fall and decay times are
all the same value. If two values are given, rise and
fall times are use, and the decay time is the minimum
of the rise and fall times. Finally, if all three
values are given, they are taken as specified. */
Node delays can be more general expressions in structural contexts.
2006-01-02 06:33:19 +01:00
NetExpr* rise_time, *fall_time, *decay_time;
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
eval_delays(des, scope, rise_time, fall_time, decay_time);
Parse and elaborate rise/fall/decay times for gates, and handle the rules for partial lists of times.
1999-08-01 18:34:50 +02:00
Add language support for Verilog-2001 attribute syntax. Hook this support into existing $attribute handling, and add number and void value types. Add to the ivl_target API new functions for access of complex attributes attached to gates.
2002-05-23 05:08:50 +02:00
struct attrib_list_t*attrib_list = 0;
unsigned attrib_list_n = 0;
attrib_list = evaluate_attributes(attributes, attrib_list_n,
des, scope);
Handle logic gates with multiple outputs. Logic gates usually have one output and several inputs, but a few have multiple outputs and one input. Since the NetNode objects have only a single output, handle the case by creating multiple NetNode objects, one for each output.
2008-09-15 06:04:03 +02:00
/* Allocate all the netlist nodes for the gates. */
vector<NetNode*>cur (array_count*output_count);
Parse and elaborate rise/fall/decay times for gates, and handle the rules for partial lists of times.
1999-08-01 18:34:50 +02:00
/* Now make as many gates as the bit count dictates. Give each
a unique name, and set the delay times. */
Handle logic gates with multiple outputs. Logic gates usually have one output and several inputs, but a few have multiple outputs and one input. Since the NetNode objects have only a single output, handle the case by creating multiple NetNode objects, one for each output.
2008-09-15 06:04:03 +02:00
for (unsigned idx = 0 ; idx < array_count*output_count ; idx += 1) {
unsigned array_idx = idx/output_count;
unsigned output_idx = idx%output_count;
Move strstream to ostringstream for compatibility.
2003-01-14 22:16:18 +01:00
ostringstream tmp;
Handle logic gates with multiple outputs. Logic gates usually have one output and several inputs, but a few have multiple outputs and one input. Since the NetNode objects have only a single output, handle the case by creating multiple NetNode objects, one for each output.
2008-09-15 06:04:03 +02:00
unsigned index = (low < high)? (low+array_idx) : (low-array_idx);
Elaborate gate ranges.
1999-02-15 03:06:15 +01:00
Handle logic gates with multiple outputs. Logic gates usually have one output and several inputs, but a few have multiple outputs and one input. Since the NetNode objects have only a single output, handle the case by creating multiple NetNode objects, one for each output.
2008-09-15 06:04:03 +02:00
tmp << name << "<" << index << "." << output_idx << ">";
Use perm_strings for named langiage items.
2004-02-18 18:11:54 +01:00
perm_string inm = lex_strings.make(tmp.str());
Elaborate gate ranges.
1999-02-15 03:06:15 +01:00
Handle logic gates with multiple outputs. Logic gates usually have one output and several inputs, but a few have multiple outputs and one input. Since the NetNode objects have only a single output, handle the case by creating multiple NetNode objects, one for each output.
2008-09-15 06:04:03 +02:00
cur[idx] = create_gate_for_output_(des, scope, inm, instance_width);
if (cur[idx] == 0)
Support named parameter override lists.
2000-01-09 06:50:48 +01:00
return;
Elaborate gate ranges.
1999-02-15 03:06:15 +01:00
Add language support for Verilog-2001 attribute syntax. Hook this support into existing $attribute handling, and add number and void value types. Add to the ivl_target API new functions for access of complex attributes attached to gates.
2002-05-23 05:08:50 +02:00
for (unsigned adx = 0 ; adx < attrib_list_n ; adx += 1)
cur[idx]->attribute(attrib_list[adx].key,
attrib_list[adx].val);
Elaborate tran devices The tran devices include tran, rtran, tranif0/1 and rtranif0/1. These are all elaborated as options on a NetTran device. It is still not clear the best way to present tran devices via the ivl_target.h API.
2008-05-20 06:42:52 +02:00
/* The logic devices have some uniform processing. Then
all may have output delays and output drive strength. */
if (NetLogic*log = dynamic_cast<NetLogic*> (cur[idx])) {
log->rise_time(rise_time);
log->fall_time(fall_time);
log->decay_time(decay_time);
Parse and elaborate rise/fall/decay times for gates, and handle the rules for partial lists of times.
1999-08-01 18:34:50 +02:00
Elaborate tran devices The tran devices include tran, rtran, tranif0/1 and rtranif0/1. These are all elaborated as options on a NetTran device. It is still not clear the best way to present tran devices via the ivl_target.h API.
2008-05-20 06:42:52 +02:00
log->pin(0).drive0(drive_type(strength0()));
log->pin(0).drive1(drive_type(strength1()));
}
Use bufz to make assignments directional.
2000-05-08 07:28:29 +02:00
Elaborate tran devices The tran devices include tran, rtran, tranif0/1 and rtranif0/1. These are all elaborated as options on a NetTran device. It is still not clear the best way to present tran devices via the ivl_target.h API.
2008-05-20 06:42:52 +02:00
cur[idx]->set_line(*this);
Elaborate gate ranges.
1999-02-15 03:06:15 +01:00
des->add_node(cur[idx]);
}
Add language support for Verilog-2001 attribute syntax. Hook this support into existing $attribute handling, and add number and void value types. Add to the ivl_target API new functions for access of complex attributes attached to gates.
2002-05-23 05:08:50 +02:00
delete[]attrib_list;
Elaborate gate ranges.
1999-02-15 03:06:15 +01:00
/* The gates have all been allocated, this loop runs through
the parameters and attaches the ports of the objects. */
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
for (unsigned idx = 0 ; idx < pin_count() ; idx += 1) {
Handle logic gates with multiple outputs. Logic gates usually have one output and several inputs, but a few have multiple outputs and one input. Since the NetNode objects have only a single output, handle the case by creating multiple NetNode objects, one for each output.
2008-09-15 06:04:03 +02:00
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
const PExpr*ex = pin(idx);
Check that logic gates are not given null ports. Logic gates do not handle null ports so check for this and issue an error message when it happens.
2007-08-30 02:29:56 +02:00
if (ex == 0) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: Logic gate port "
Check that logic gates are not given null ports. Logic gates do not handle null ports so check for this and issue an error message when it happens.
2007-08-30 02:29:56 +02:00
"expressions are not optional." << endl;
des->errors += 1;
return;
}
Remove elaborate_net from all elaborations. Use elaborate_expr and synthesize() methods in place of the elaborate_net methods, so that elaboration is more consistent.
2008-09-09 04:13:49 +02:00
NetNet*sig = 0;
Handle logic gates with multiple outputs. Logic gates usually have one output and several inputs, but a few have multiple outputs and one input. Since the NetNode objects have only a single output, handle the case by creating multiple NetNode objects, one for each output.
2008-09-15 06:04:03 +02:00
if (idx < output_count) {
sig = lval_sigs[idx];
Remove elaborate_net from all elaborations. Use elaborate_expr and synthesize() methods in place of the elaborate_net methods, so that elaboration is more consistent.
2008-09-09 04:13:49 +02:00
} else {
Handle logic gates with multiple outputs. Logic gates usually have one output and several inputs, but a few have multiple outputs and one input. Since the NetNode objects have only a single output, handle the case by creating multiple NetNode objects, one for each output.
2008-09-15 06:04:03 +02:00
unsigned use_width = array_count * instance_width;
Remove elaborate_net from all elaborations. Use elaborate_expr and synthesize() methods in place of the elaborate_net methods, so that elaboration is more consistent.
2008-09-09 04:13:49 +02:00
NetExpr*tmp = elab_and_eval(des, scope, ex,
use_width, use_width);
sig = tmp->synthesize(des, scope);
delete tmp;
}
implicitly declare wires if needed.
1999-09-14 03:50:52 +02:00
if (sig == 0)
continue;
Handle logic gates with multiple outputs. Logic gates usually have one output and several inputs, but a few have multiple outputs and one input. Since the NetNode objects have only a single output, handle the case by creating multiple NetNode objects, one for each output.
2008-09-15 06:04:03 +02:00
ivl_assert(*this, sig);
Elaborate gate ranges.
1999-02-15 03:06:15 +01:00
Handle logic gates with multiple outputs. Logic gates usually have one output and several inputs, but a few have multiple outputs and one input. Since the NetNode objects have only a single output, handle the case by creating multiple NetNode objects, one for each output.
2008-09-15 06:04:03 +02:00
if (array_count == 1) {
Unify elaboration of l-values for all proceedural assignments, including assing, cassign and force. Generate NetConcat devices for gate outputs that feed into a vector results. Use this to hande gate arrays. Also let gate arrays handle vectors of gates when the outputs allow for it.
2004-12-30 00:55:43 +01:00
/* Handle the case where there is one gate that
carries the whole vector width. */
Add the NetRepeat node, and code generator support.
2005-02-08 01:12:36 +01:00
Proper error message when logic array pi count is bad.
2006-09-23 00:14:27 +02:00
if (1 == sig->vector_width() && instance_width != 1) {
Add the NetRepeat node, and code generator support.
2005-02-08 01:12:36 +01:00
assert(sig->vector_width() == 1);
NetReplicate*rep
= new NetReplicate(scope,
scope->local_symbol(),
instance_width,
instance_width);
rep->set_line(*this);
des->add_node(rep);
connect(rep->pin(1), sig->pin(0));
sig = new NetNet(scope, scope->local_symbol(),
NetNet::WIRE, instance_width);
More explicit datatype setup.
2006-05-01 22:47:58 +02:00
sig->data_type(IVL_VT_LOGIC);
Add the NetRepeat node, and code generator support.
2005-02-08 01:12:36 +01:00
sig->local_flag(true);
sig->set_line(*this);
connect(rep->pin(0), sig->pin(0));
Proper error message when logic array pi count is bad.
2006-09-23 00:14:27 +02:00
}
if (instance_width != sig->vector_width()) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: "
Proper error message when logic array pi count is bad.
2006-09-23 00:14:27 +02:00
<< "Expression width " << sig->vector_width()
<< " does not match width " << instance_width
<< " of logic gate array port " << idx
<< "." << endl;
des->errors += 1;
Add the NetRepeat node, and code generator support.
2005-02-08 01:12:36 +01:00
}
Handle logic gates with multiple outputs. Logic gates usually have one output and several inputs, but a few have multiple outputs and one input. Since the NetNode objects have only a single output, handle the case by creating multiple NetNode objects, one for each output.
2008-09-15 06:04:03 +02:00
// There is only 1 instance, but there may be
// multiple outputs to that gate. That would
// potentially mean multiple actual gates.
// Although in Verilog proper a multiple
// output gate has only 1 input, this conditional
// handles gates with N outputs and M inputs.
if (idx < output_count) {
connect(cur[idx]->pin(0), sig->pin(0));
} else {
for (unsigned dev = 0 ; dev < output_count; dev += 1)
connect(cur[dev]->pin(idx-output_count+1), sig->pin(0));
}
Unify elaboration of l-values for all proceedural assignments, including assing, cassign and force. Generate NetConcat devices for gate outputs that feed into a vector results. Use this to hande gate arrays. Also let gate arrays handle vectors of gates when the outputs allow for it.
2004-12-30 00:55:43 +01:00
} else if (sig->vector_width() == 1) {
Handle logic gates with multiple outputs. Logic gates usually have one output and several inputs, but a few have multiple outputs and one input. Since the NetNode objects have only a single output, handle the case by creating multiple NetNode objects, one for each output.
2008-09-15 06:04:03 +02:00
Unify elaboration of l-values for all proceedural assignments, including assing, cassign and force. Generate NetConcat devices for gate outputs that feed into a vector results. Use this to hande gate arrays. Also let gate arrays handle vectors of gates when the outputs allow for it.
2004-12-30 00:55:43 +01:00
/* Handle the case where a single bit is connected
Instance arrays with multiple outputs and not vectorized. It takes a carefully crafted source file to cause elabortion to make an arrayed multiple-output gate that is not vectorized into a single wide gate. But that special case does need to be handled.
2008-09-17 06:03:26 +02:00
repetitively to all the instances. If idx is an
output port, connect it to all array_count
devices that have outputs at this
position. Otherwise, idx is an input to all
array_count*output_count devices. */
if (idx < output_count) {
for (unsigned gdx = 0 ; gdx < array_count ; gdx += 1) {
unsigned dev = gdx*output_count;
connect(cur[dev+idx]->pin(0), sig->pin(0));
}
} else {
unsigned use_idx = idx - output_count + 1;
for (unsigned gdx = 0 ; gdx < cur.size() ; gdx += 1)
connect(cur[gdx]->pin(use_idx), sig->pin(0));
}
Elaborate gate ranges.
1999-02-15 03:06:15 +01:00
Handle logic gates with multiple outputs. Logic gates usually have one output and several inputs, but a few have multiple outputs and one input. Since the NetNode objects have only a single output, handle the case by creating multiple NetNode objects, one for each output.
2008-09-15 06:04:03 +02:00
} else if (sig->vector_width() == array_count) {
Unify elaboration of l-values for all proceedural assignments, including assing, cassign and force. Generate NetConcat devices for gate outputs that feed into a vector results. Use this to hande gate arrays. Also let gate arrays handle vectors of gates when the outputs allow for it.
2004-12-30 00:55:43 +01:00
/* Handle the general case that each bit of the
value is connected to a different instance. In
this case, the output is handled slightly
different from the inputs. */
Instance arrays with multiple outputs and not vectorized. It takes a carefully crafted source file to cause elabortion to make an arrayed multiple-output gate that is not vectorized into a single wide gate. But that special case does need to be handled.
2008-09-17 06:03:26 +02:00
if (idx < output_count) {
Unify elaboration of l-values for all proceedural assignments, including assing, cassign and force. Generate NetConcat devices for gate outputs that feed into a vector results. Use this to hande gate arrays. Also let gate arrays handle vectors of gates when the outputs allow for it.
2004-12-30 00:55:43 +01:00
NetConcat*cc = new NetConcat(scope,
scope->local_symbol(),
sig->vector_width(),
Handle logic gates with multiple outputs. Logic gates usually have one output and several inputs, but a few have multiple outputs and one input. Since the NetNode objects have only a single output, handle the case by creating multiple NetNode objects, one for each output.
2008-09-15 06:04:03 +02:00
array_count);
Unify elaboration of l-values for all proceedural assignments, including assing, cassign and force. Generate NetConcat devices for gate outputs that feed into a vector results. Use this to hande gate arrays. Also let gate arrays handle vectors of gates when the outputs allow for it.
2004-12-30 00:55:43 +01:00
des->add_node(cc);
/* Connect the concat to the signal. */
connect(cc->pin(0), sig->pin(0));
/* Connect the outputs of the gates to the concat. */
Handle logic gates with multiple outputs. Logic gates usually have one output and several inputs, but a few have multiple outputs and one input. Since the NetNode objects have only a single output, handle the case by creating multiple NetNode objects, one for each output.
2008-09-15 06:04:03 +02:00
for (unsigned gdx = 0 ; gdx < array_count; gdx += 1) {
Instance arrays with multiple outputs and not vectorized. It takes a carefully crafted source file to cause elabortion to make an arrayed multiple-output gate that is not vectorized into a single wide gate. But that special case does need to be handled.
2008-09-17 06:03:26 +02:00
unsigned dev = gdx*output_count;
connect(cur[dev+idx]->pin(0), cc->pin(gdx+1));
Unify elaboration of l-values for all proceedural assignments, including assing, cassign and force. Generate NetConcat devices for gate outputs that feed into a vector results. Use this to hande gate arrays. Also let gate arrays handle vectors of gates when the outputs allow for it.
2004-12-30 00:55:43 +01:00
NetNet*tmp2 = new NetNet(scope,
scope->local_symbol(),
NetNet::WIRE, 1);
More explicit datatype setup.
2006-05-01 22:47:58 +02:00
tmp2->local_flag(true);
tmp2->data_type(IVL_VT_LOGIC);
Unify elaboration of l-values for all proceedural assignments, including assing, cassign and force. Generate NetConcat devices for gate outputs that feed into a vector results. Use this to hande gate arrays. Also let gate arrays handle vectors of gates when the outputs allow for it.
2004-12-30 00:55:43 +01:00
connect(cc->pin(gdx+1), tmp2->pin(0));
}
Elaborate gate ranges.
1999-02-15 03:06:15 +01:00
Handle logic gates with multiple outputs. Logic gates usually have one output and several inputs, but a few have multiple outputs and one input. Since the NetNode objects have only a single output, handle the case by creating multiple NetNode objects, one for each output.
2008-09-15 06:04:03 +02:00
} else for (unsigned gdx = 0 ; gdx < array_count ; gdx += 1) {
Unify elaboration of l-values for all proceedural assignments, including assing, cassign and force. Generate NetConcat devices for gate outputs that feed into a vector results. Use this to hande gate arrays. Also let gate arrays handle vectors of gates when the outputs allow for it.
2004-12-30 00:55:43 +01:00
/* Use part selects to get the bits
connected to the inputs of out gate. */
Use PartSelect/PV and VP to handle part selects through ports.
2005-01-09 21:16:00 +01:00
NetPartSelect*tmp1 = new NetPartSelect(sig, gdx, 1,
NetPartSelect::VP);
Unify elaboration of l-values for all proceedural assignments, including assing, cassign and force. Generate NetConcat devices for gate outputs that feed into a vector results. Use this to hande gate arrays. Also let gate arrays handle vectors of gates when the outputs allow for it.
2004-12-30 00:55:43 +01:00
tmp1->set_line(*this);
des->add_node(tmp1);
connect(tmp1->pin(1), sig->pin(0));
NetNet*tmp2 = new NetNet(scope, scope->local_symbol(),
NetNet::WIRE, 1);
More explicit datatype setup.
2006-05-01 22:47:58 +02:00
tmp2->local_flag(true);
Get the data type of part select results right.
2006-04-30 07:17:48 +02:00
tmp2->data_type(sig->data_type());
Unify elaboration of l-values for all proceedural assignments, including assing, cassign and force. Generate NetConcat devices for gate outputs that feed into a vector results. Use this to hande gate arrays. Also let gate arrays handle vectors of gates when the outputs allow for it.
2004-12-30 00:55:43 +01:00
connect(tmp1->pin(0), tmp2->pin(0));
Instance arrays with multiple outputs and not vectorized. It takes a carefully crafted source file to cause elabortion to make an arrayed multiple-output gate that is not vectorized into a single wide gate. But that special case does need to be handled.
2008-09-17 06:03:26 +02:00
unsigned use_idx = idx - output_count + 1;
unsigned dev = gdx*output_count;
for (unsigned gdx2 = 0 ; gdx2 < output_count ; gdx2 += 1)
connect(cur[dev+gdx2]->pin(use_idx), tmp1->pin(0));
Unify elaboration of l-values for all proceedural assignments, including assing, cassign and force. Generate NetConcat devices for gate outputs that feed into a vector results. Use this to hande gate arrays. Also let gate arrays handle vectors of gates when the outputs allow for it.
2004-12-30 00:55:43 +01:00
}
} else {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: Gate count of " <<
Handle logic gates with multiple outputs. Logic gates usually have one output and several inputs, but a few have multiple outputs and one input. Since the NetNode objects have only a single output, handle the case by creating multiple NetNode objects, one for each output.
2008-09-15 06:04:03 +02:00
array_count << " does not match net width of " <<
Unify elaboration of l-values for all proceedural assignments, including assing, cassign and force. Generate NetConcat devices for gate outputs that feed into a vector results. Use this to hande gate arrays. Also let gate arrays handle vectors of gates when the outputs allow for it.
2004-12-30 00:55:43 +01:00
sig->vector_width() << " at pin " << idx << "."
Elaborate gate ranges.
1999-02-15 03:06:15 +01:00
<< endl;
des->errors += 1;
}
Collect NetTran devices into islands. NetTran devices must be collected into islands because they are all a bi-directional mass. This is how vvp will process them and the code generator will need a head start organizing them.
2008-06-02 04:45:12 +02:00
}
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
Resize vectors to mismatched ports It is legal in Verilog to bind expressions to ports that do not match the port width. Icarus Verilog needs to create the necessary part selects to get the connections right. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-09-10 06:14:52 +02:00
NetNet*PGModule::resize_net_to_port_(Design*des, NetScope*scope,
NetNet*sig, unsigned port_wid,
Pad input and output ports correctly. This patch pads inputs and output ports correctly when the port and the port expression have different widths. It does not fix inout ports. It also sets the file and line number information in the unsigned pad_to_width() routine.
2008-10-03 03:38:53 +02:00
NetNet::PortType dir, bool as_signed) const
Resize vectors to mismatched ports It is legal in Verilog to bind expressions to ports that do not match the port width. Icarus Verilog needs to create the necessary part selects to get the connections right. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-09-10 06:14:52 +02:00
{
ivl_assert(*this, dir != NetNet::NOT_A_PORT);
ivl_assert(*this, dir != NetNet::PIMPLICIT);
NetNet*tmp = new NetNet(scope, scope->local_symbol(),
NetNet::WIRE, port_wid);
tmp->local_flag(true);
tmp->set_line(*sig);
Replace the NetPartSelect:BI with NetTran(VP). Fold the bi-directional part select into the pass switch (tran) support so that it can be really bi-directional. This involves adding a new tranvp device that does part select in tran islands, and reworking the tran island resolution to handle non-identical nodes. This will be needed for resistive tran devices anyhow.
2008-06-03 20:16:25 +02:00
// Handle the special case of a bi-directional part
// select. Create a NetTran(VP) instead of a uni-directional
// NetPartSelect node.
if (dir == NetNet::PINOUT) {
unsigned wida = sig->vector_width();
unsigned widb = tmp->vector_width();
bool part_b = widb < wida;
Pad input and output ports correctly. This patch pads inputs and output ports correctly when the port and the port expression have different widths. It does not fix inout ports. It also sets the file and line number information in the unsigned pad_to_width() routine.
2008-10-03 03:38:53 +02:00
// This needs to pad the value!
// Also delete the inout specific warning when this is fixed.
// It is located just before this routine is called.
Replace the NetPartSelect:BI with NetTran(VP). Fold the bi-directional part select into the pass switch (tran) support so that it can be really bi-directional. This involves adding a new tranvp device that does part select in tran islands, and reworking the tran island resolution to handle non-identical nodes. This will be needed for resistive tran devices anyhow.
2008-06-03 20:16:25 +02:00
NetTran*node = new NetTran(scope, scope->local_symbol(),
part_b? wida : widb,
part_b? widb : wida,
0);
if (part_b) {
connect(node->pin(0), sig->pin(0));
connect(node->pin(1), tmp->pin(0));
Got sense of tranvp wrong in connections to module ports.
2008-06-04 02:23:01 +02:00
} else {
connect(node->pin(0), tmp->pin(0));
connect(node->pin(1), sig->pin(0));
Replace the NetPartSelect:BI with NetTran(VP). Fold the bi-directional part select into the pass switch (tran) support so that it can be really bi-directional. This involves adding a new tranvp device that does part select in tran islands, and reworking the tran island resolution to handle non-identical nodes. This will be needed for resistive tran devices anyhow.
2008-06-03 20:16:25 +02:00
}
node->set_line(*this);
des->add_node(node);
return tmp;
}
Pad input and output ports correctly. This patch pads inputs and output ports correctly when the port and the port expression have different widths. It does not fix inout ports. It also sets the file and line number information in the unsigned pad_to_width() routine.
2008-10-03 03:38:53 +02:00
unsigned pwidth = tmp->vector_width();
unsigned swidth = sig->vector_width();
Resize vectors to mismatched ports It is legal in Verilog to bind expressions to ports that do not match the port width. Icarus Verilog needs to create the necessary part selects to get the connections right. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-09-10 06:14:52 +02:00
switch (dir) {
case NetNet::POUTPUT:
Pad input and output ports correctly. This patch pads inputs and output ports correctly when the port and the port expression have different widths. It does not fix inout ports. It also sets the file and line number information in the unsigned pad_to_width() routine.
2008-10-03 03:38:53 +02:00
if (pwidth > swidth) {
NetPartSelect*node = new NetPartSelect(tmp, 0, swidth,
Resize vectors to mismatched ports It is legal in Verilog to bind expressions to ports that do not match the port width. Icarus Verilog needs to create the necessary part selects to get the connections right. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-09-10 06:14:52 +02:00
NetPartSelect::VP);
Hook up output port part select properly. The output part select that is used to match a module port to a long vector connected to it was wired incorrectly.
2008-01-11 03:20:21 +01:00
connect(node->pin(0), sig->pin(0));
Pad input and output ports correctly. This patch pads inputs and output ports correctly when the port and the port expression have different widths. It does not fix inout ports. It also sets the file and line number information in the unsigned pad_to_width() routine.
2008-10-03 03:38:53 +02:00
des->add_node(node);
Resize vectors to mismatched ports It is legal in Verilog to bind expressions to ports that do not match the port width. Icarus Verilog needs to create the necessary part selects to get the connections right. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-09-10 06:14:52 +02:00
} else {
Pad input and output ports correctly. This patch pads inputs and output ports correctly when the port and the port expression have different widths. It does not fix inout ports. It also sets the file and line number information in the unsigned pad_to_width() routine.
2008-10-03 03:38:53 +02:00
NetNet*osig;
if (as_signed) {
osig = pad_to_width_signed(des, tmp, swidth);
} else {
osig = pad_to_width(des, tmp, swidth);
}
connect(osig->pin(0), sig->pin(0));
Resize vectors to mismatched ports It is legal in Verilog to bind expressions to ports that do not match the port width. Icarus Verilog needs to create the necessary part selects to get the connections right. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-09-10 06:14:52 +02:00
}
break;
case NetNet::PINPUT:
Pad input and output ports correctly. This patch pads inputs and output ports correctly when the port and the port expression have different widths. It does not fix inout ports. It also sets the file and line number information in the unsigned pad_to_width() routine.
2008-10-03 03:38:53 +02:00
if (pwidth > swidth) {
delete tmp;
if (as_signed) {
tmp = pad_to_width_signed(des, sig, pwidth);
} else {
tmp = pad_to_width(des, sig, pwidth);
}
Resize vectors to mismatched ports It is legal in Verilog to bind expressions to ports that do not match the port width. Icarus Verilog needs to create the necessary part selects to get the connections right. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-09-10 06:14:52 +02:00
} else {
Pad input and output ports correctly. This patch pads inputs and output ports correctly when the port and the port expression have different widths. It does not fix inout ports. It also sets the file and line number information in the unsigned pad_to_width() routine.
2008-10-03 03:38:53 +02:00
NetPartSelect*node = new NetPartSelect(sig, 0, pwidth,
Resize vectors to mismatched ports It is legal in Verilog to bind expressions to ports that do not match the port width. Icarus Verilog needs to create the necessary part selects to get the connections right. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-09-10 06:14:52 +02:00
NetPartSelect::VP);
Hook up input port part select properly. The input part select that is used to match a module port to a short vector connected to it was wired incorrectly.
2008-01-11 05:47:06 +01:00
connect(node->pin(0), tmp->pin(0));
Pad input and output ports correctly. This patch pads inputs and output ports correctly when the port and the port expression have different widths. It does not fix inout ports. It also sets the file and line number information in the unsigned pad_to_width() routine.
2008-10-03 03:38:53 +02:00
des->add_node(node);
Resize vectors to mismatched ports It is legal in Verilog to bind expressions to ports that do not match the port width. Icarus Verilog needs to create the necessary part selects to get the connections right. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-09-10 06:14:52 +02:00
}
break;
case NetNet::PINOUT:
Replace the NetPartSelect:BI with NetTran(VP). Fold the bi-directional part select into the pass switch (tran) support so that it can be really bi-directional. This involves adding a new tranvp device that does part select in tran islands, and reworking the tran island resolution to handle non-identical nodes. This will be needed for resistive tran devices anyhow.
2008-06-03 20:16:25 +02:00
ivl_assert(*this, 0);
Resize vectors to mismatched ports It is legal in Verilog to bind expressions to ports that do not match the port width. Icarus Verilog needs to create the necessary part selects to get the connections right. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-09-10 06:14:52 +02:00
break;
default:
ivl_assert(*this, 0);
}
return tmp;
}
Add BUFZ to input ports when necessary. When driving an input port to a module, watch out for the case where the net is also driven within the instance. If this is the case, take pains to make sure what goes on in the instance doesn't leak out through the input port. Add a BUFZ (continuous assignment) to isolate the context from internal driving.
2008-08-07 06:04:52 +02:00
static bool need_bufz_for_input_port(const svector<NetNet*>&prts)
{
if (prts[0]->port_type() != NetNet::PINPUT)
return false;
if (prts[0]->pin(0).nexus()->drivers_present())
return true;
return false;
}
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
/*
* Instantiate a module by recursively elaborating it. Set the path of
* the recursive elaboration so that signal names get properly
* set. Connect the ports of the instantiated module to the signals of
* the parameters. This is done with BUFZ gates so that they look just
* like continuous assignment connections.
*/
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
{
Catch module instantiation arrays.
2000-02-18 06:15:02 +01:00
Redesign the implementation of scopes and parameters. I now generate the scopes and notice the parameters in a separate pass over the pform. Once the scopes are generated, I can process overrides and evalutate paremeters before elaboration begins.
2000-03-08 05:36:53 +01:00
assert(scope);
distinguish between single port namy instances, and single instances many sub-ports.
2005-02-10 05:56:58 +01:00
if (debug_elaborate) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": debug: Instantiate module "
Reorganize signal part select handling, and add support for indexed part selects. Expand expression constant propagation to eliminate extra sums in certain cases.
2005-11-10 14:28:11 +01:00
<< rmod->mod_name() << " with instance name "
Properly evaluate scope path expressions.
2007-06-02 05:42:12 +02:00
<< get_name() << " in scope " << scope_path(scope) << endl;
distinguish between single port namy instances, and single instances many sub-ports.
2005-02-10 05:56:58 +01:00
}
primitive ports can bind bi name.
2004-03-08 01:47:44 +01:00
// This is the array of pin expressions, shuffled to match the
// order of the declaration. If the source instantiation uses
distinguish between single port namy instances, and single instances many sub-ports.
2005-02-10 05:56:58 +01:00
// bind by order, this is the same as the source list.Otherwise,
// the source list is rearranged by name binding into this list.
primitive ports can bind bi name.
2004-03-08 01:47:44 +01:00
svector<PExpr*>pins (rmod->port_count());
module parameter bind by name.
1999-05-29 04:36:17 +02:00
distinguish between single port namy instances, and single instances many sub-ports.
2005-02-10 05:56:58 +01:00
// If the instance has a pins_ member, then we know we are
// binding by name. Therefore, make up a pins array that
// reflects the positions of the named ports.
module parameter bind by name.
1999-05-29 04:36:17 +02:00
if (pins_) {
Parse into pform arbitrarily complex module port declarations.
1999-08-03 06:14:49 +02:00
unsigned nexp = rmod->port_count();
module parameter bind by name.
1999-05-29 04:36:17 +02:00
// Scan the bindings, matching them with port names.
for (unsigned idx = 0 ; idx < npins_ ; idx += 1) {
// Given a binding, look at the module port names
// for the position that matches the binding name.
Parse into pform arbitrarily complex module port declarations.
1999-08-03 06:14:49 +02:00
unsigned pidx = rmod->find_port(pins_[idx].name);
module parameter bind by name.
1999-05-29 04:36:17 +02:00
Parse into pform arbitrarily complex module port declarations.
1999-08-03 06:14:49 +02:00
// If the port name doesn't exist, the find_port
// method will return the port count. Detect that
// as an error.
module parameter bind by name.
1999-05-29 04:36:17 +02:00
if (pidx == nexp) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: port ``" <<
module parameter bind by name.
1999-05-29 04:36:17 +02:00
pins_[idx].name << "'' is not a port of "
<< get_name() << "." << endl;
des->errors += 1;
continue;
}
Parse into pform arbitrarily complex module port declarations.
1999-08-03 06:14:49 +02:00
// If I already bound something to this port, then
distinguish between single port namy instances, and single instances many sub-ports.
2005-02-10 05:56:58 +01:00
// the pins array will already have a pointer
Parse into pform arbitrarily complex module port declarations.
1999-08-03 06:14:49 +02:00
// value where I want to place this expression.
primitive ports can bind bi name.
2004-03-08 01:47:44 +01:00
if (pins[pidx]) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: port ``" <<
module parameter bind by name.
1999-05-29 04:36:17 +02:00
pins_[idx].name << "'' already bound." <<
endl;
des->errors += 1;
continue;
}
Parse into pform arbitrarily complex module port declarations.
1999-08-03 06:14:49 +02:00
// OK, do the binding by placing the expression in
module parameter bind by name.
1999-05-29 04:36:17 +02:00
// the right place.
primitive ports can bind bi name.
2004-03-08 01:47:44 +01:00
pins[pidx] = pins_[idx].parm;
module parameter bind by name.
1999-05-29 04:36:17 +02:00
}
Accept empty port lists to module instantiation.
2001-08-01 07:17:31 +02:00
} else if (pin_count() == 0) {
/* Handle the special case that no ports are
connected. It is possible that this is an empty
Spelling fixes.
2003-01-27 06:09:17 +01:00
connect-by-name list, so we'll allow it and assume
Accept empty port lists to module instantiation.
2001-08-01 07:17:31 +02:00
that is the case. */
for (unsigned idx = 0 ; idx < rmod->port_count() ; idx += 1)
primitive ports can bind bi name.
2004-03-08 01:47:44 +01:00
pins[idx] = 0;
Accept empty port lists to module instantiation.
2001-08-01 07:17:31 +02:00
module parameter bind by name.
1999-05-29 04:36:17 +02:00
} else {
Use PartSelect/PV and VP to handle part selects through ports.
2005-01-09 21:16:00 +01:00
/* Otherwise, this is a positional list of port
Accept empty port lists to module instantiation.
2001-08-01 07:17:31 +02:00
connections. In this case, the port count must be
right. Check that is is, the get the pin list. */
Parse into pform arbitrarily complex module port declarations.
1999-08-03 06:14:49 +02:00
if (pin_count() != rmod->port_count()) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: Wrong number "
Accept empty port lists to module instantiation.
2001-08-01 07:17:31 +02:00
"of ports. Expecting " << rmod->port_count() <<
module parameter bind by name.
1999-05-29 04:36:17 +02:00
", got " << pin_count() << "."
<< endl;
des->errors += 1;
return;
}
// No named bindings, just use the positional list I
// already have.
Parse into pform arbitrarily complex module port declarations.
1999-08-03 06:14:49 +02:00
assert(pin_count() == rmod->port_count());
module parameter bind by name.
1999-05-29 04:36:17 +02:00
pins = get_pins();
}
Add support for module instance arrays.
2004-09-05 19:44:41 +02:00
// Elaborate these instances of the module. The recursive
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
// elaboration causes the module to generate a netlist with
// the ports represented by NetNet objects. I will find them
// later.
Add support for module instance arrays.
2004-09-05 19:44:41 +02:00
NetScope::scope_vec_t&instance = scope->instance_arrays[get_name()];
for (unsigned inst = 0 ; inst < instance.count() ; inst += 1) {
rmod->elaborate(des, instance[inst]);
}
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
// Now connect the ports of the newly elaborated designs to
module parameter bind by name.
1999-05-29 04:36:17 +02:00
// the expressions that are the instantiation parameters. Scan
// the pins, elaborate the expressions attached to them, and
// bind them to the port of the elaborated module.
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
Handle connectsion to internally unconnected modules (PR#38)
2000-11-05 07:05:59 +01:00
// This can get rather complicated because the port can be
Spelling fixes.
2003-01-27 06:09:17 +01:00
// unconnected (meaning an empty parameter is passed) connected
Handle connectsion to internally unconnected modules (PR#38)
2000-11-05 07:05:59 +01:00
// to a concatenation, or connected to an internally
// unconnected port.
primitive ports can bind bi name.
2004-03-08 01:47:44 +01:00
for (unsigned idx = 0 ; idx < pins.count() ; idx += 1) {
Handle connectsion to internally unconnected modules (PR#38)
2000-11-05 07:05:59 +01:00
// Skip unconnected module ports. This happens when a
// null parameter is passed in.
Add the portbind warning.
2003-02-22 05:12:49 +01:00
primitive ports can bind bi name.
2004-03-08 01:47:44 +01:00
if (pins[idx] == 0) {
Add the portbind warning.
2003-02-22 05:12:49 +01:00
// While we're here, look to see if this
// unconnected (from the outside) port is an
// input. If so, consider printing a port binding
// warning.
if (warn_portbinding) {
svector<PEIdent*> mport = rmod->get_port(idx);
if (mport.count() == 0)
continue;
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
perm_string pname = peek_tail_name(mport[0]->path());
NetNet*tmp = instance[0]->find_signal(pname);
Add the portbind warning.
2003-02-22 05:12:49 +01:00
assert(tmp);
if (tmp->port_type() == NetNet::PINPUT) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": warning: "
Add the portbind warning.
2003-02-22 05:12:49 +01:00
<< "Instantiating module "
<< rmod->mod_name()
<< " with dangling input port "
<< rmod->ports[idx]->name
<< "." << endl;
}
}
Add procedural while loops, Parse procedural for loops, Add procedural wait statements, Add constant nodes, Add XNOR logic gate, Make vvm output look a bit prettier.
1998-11-09 19:55:33 +01:00
continue;
Add the portbind warning.
2003-02-22 05:12:49 +01:00
}
Handle connectsion to internally unconnected modules (PR#38)
2000-11-05 07:05:59 +01:00
// Inside the module, the port is zero or more signals
// that were already elaborated. List all those signals
Add support for module instance arrays.
2004-09-05 19:44:41 +02:00
// and the NetNet equivalents, for all the instances.
Module ports are really special PEIdent expressions, because a name can be used many places in the port list.
2000-05-16 06:05:15 +02:00
svector<PEIdent*> mport = rmod->get_port(idx);
Add support for module instance arrays.
2004-09-05 19:44:41 +02:00
svector<NetNet*>prts (mport.count() * instance.count());
Elaborate module ports that are concatenations of module signals.
1999-08-04 04:13:02 +02:00
distinguish between single port namy instances, and single instances many sub-ports.
2005-02-10 05:56:58 +01:00
if (debug_elaborate) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": debug: " << get_name()
distinguish between single port namy instances, and single instances many sub-ports.
2005-02-10 05:56:58 +01:00
<< ": Port " << idx << " has " << prts.count()
<< " sub-ports." << endl;
}
Use PartSelect/PV and VP to handle part selects through ports.
2005-01-09 21:16:00 +01:00
// Count the internal vector bits of the port.
unsigned prts_vector_width = 0;
Proper error messages when port direction is missing.
2000-08-18 06:38:57 +02:00
Add support for module instance arrays.
2004-09-05 19:44:41 +02:00
for (unsigned inst = 0 ; inst < instance.count() ; inst += 1) {
Connect module instance arrays MSB to MSB. When a bit port of a module instance is connected to a vector argument, the MSB module instance should be connected to the MSB of the vector argument. This matters only in the rare case that the %m is used. It also makes wave dumps come out right.
2008-03-07 05:37:08 +01:00
// Scan the instances from MSB to LSB. The port
// will be assembled in that order as well.
NetScope*inst_scope = instance[instance.count()-inst-1];
Add support for module instance arrays.
2004-09-05 19:44:41 +02:00
// Scan the module sub-ports for this instance...
for (unsigned ldx = 0 ; ldx < mport.count() ; ldx += 1) {
unsigned lbase = inst * mport.count();
PEIdent*pport = mport[ldx];
assert(pport);
prts[lbase + ldx]
= pport->elaborate_port(des, inst_scope);
if (prts[lbase + ldx] == 0)
continue;
assert(prts[lbase + ldx]);
Use PartSelect/PV and VP to handle part selects through ports.
2005-01-09 21:16:00 +01:00
prts_vector_width += prts[lbase + ldx]->vector_width();
Add support for module instance arrays.
2004-09-05 19:44:41 +02:00
}
Elaborate module ports that are concatenations of module signals.
1999-08-04 04:13:02 +02:00
}
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
Use PartSelect/PV and VP to handle part selects through ports.
2005-01-09 21:16:00 +01:00
// If I find that the port is unconnected inside the
Handle connectsion to internally unconnected modules (PR#38)
2000-11-05 07:05:59 +01:00
// module, then there is nothing to connect. Skip the
Add support for module instance arrays.
2004-09-05 19:44:41 +02:00
// argument.
Use PartSelect/PV and VP to handle part selects through ports.
2005-01-09 21:16:00 +01:00
if (prts_vector_width == 0) {
Handle connectsion to internally unconnected modules (PR#38)
2000-11-05 07:05:59 +01:00
continue;
}
Add support for module instance arrays.
2004-09-05 19:44:41 +02:00
// We know by design that each instance has the same
// width port. Therefore, the prts_pin_count must be an
// even multiple of the instance count.
Use PartSelect/PV and VP to handle part selects through ports.
2005-01-09 21:16:00 +01:00
assert(prts_vector_width % instance.count() == 0);
Add support for module instance arrays.
2004-09-05 19:44:41 +02:00
Implement bi-directional part selects.
2005-08-06 19:58:16 +02:00
unsigned desired_vector_width = prts_vector_width;
if (instance.count() != 1)
desired_vector_width = 0;
Add support for module instance arrays.
2004-09-05 19:44:41 +02:00
// Elaborate the expression that connects to the
// module[s] port. sig is the thing outside the module
// that connects to the port.
Do not connect reg to module outputs.
2001-07-19 05:43:15 +02:00
Port expressions for output ports are lnets, not nets.
2002-11-09 20:20:48 +01:00
NetNet*sig;
Implement bi-directional part selects.
2005-08-06 19:58:16 +02:00
if ((prts.count() == 0)
|| (prts[0]->port_type() == NetNet::PINPUT)) {
Port expressions for output ports are lnets, not nets.
2002-11-09 20:20:48 +01:00
Implement bi-directional part selects.
2005-08-06 19:58:16 +02:00
/* Input to module. elaborate the expression to
the desired width. If this in an instance
Spelling fixes comments, documentation, a variable name, and a couple of messages
2008-06-24 17:46:16 +02:00
array, then let the net determine its own
Implement bi-directional part selects.
2005-08-06 19:58:16 +02:00
width. We use that, then, to decide how to hook
it up.
Add BUFZ to input ports when necessary. When driving an input port to a module, watch out for the case where the net is also driven within the instance. If this is the case, take pains to make sure what goes on in the instance doesn't leak out through the input port. Add a BUFZ (continuous assignment) to isolate the context from internal driving.
2008-08-07 06:04:52 +02:00
v NOTE that this also handles the case that the
Implement bi-directional part selects.
2005-08-06 19:58:16 +02:00
port is actually empty on the inside. We assume
in that case that the port is input. */
Remove elaborate_net from all elaborations. Use elaborate_expr and synthesize() methods in place of the elaborate_net methods, so that elaboration is more consistent.
2008-09-09 04:13:49 +02:00
NetExpr*tmp_expr = elab_and_eval(des, scope, pins[idx],
desired_vector_width,
desired_vector_width);
if (tmp_expr == 0) {
cerr << pins[idx]->get_fileline()
<< ": internal error: Port expression "
<< "too complicated for elaboration." << endl;
continue;
}
sig = tmp_expr->synthesize(des, scope);
Implement bi-directional part selects.
2005-08-06 19:58:16 +02:00
if (sig == 0) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << pins[idx]->get_fileline()
Implement bi-directional part selects.
2005-08-06 19:58:16 +02:00
<< ": internal error: Port expression "
<< "too complicated for elaboration." << endl;
continue;
}
Remove elaborate_net from all elaborations. Use elaborate_expr and synthesize() methods in place of the elaborate_net methods, so that elaboration is more consistent.
2008-09-09 04:13:49 +02:00
delete tmp_expr;
sig->set_line(*this);
Add BUFZ to input ports when necessary. When driving an input port to a module, watch out for the case where the net is also driven within the instance. If this is the case, take pains to make sure what goes on in the instance doesn't leak out through the input port. Add a BUFZ (continuous assignment) to isolate the context from internal driving.
2008-08-07 06:04:52 +02:00
if (need_bufz_for_input_port(prts)) {
NetBUFZ*tmp = new NetBUFZ(scope, scope->local_symbol(),
sig->vector_width());
des->add_node(tmp);
connect(tmp->pin(1), sig->pin(0));
NetNet*tmp2 = new NetNet(scope, scope->local_symbol(),
NetNet::WIRE, sig->vector_width());
tmp2->local_flag(true);
tmp2->set_line(*this);
tmp2->data_type(sig->data_type());
connect(tmp->pin(0), tmp2->pin(0));
sig = tmp2;
}
Implement bi-directional part selects.
2005-08-06 19:58:16 +02:00
} else if (prts[0]->port_type() == NetNet::PINOUT) {
/* Inout to/from module. This is a more
complicated case, where the expression must be
an lnet, but also an r-value net.
Normally, this winds up being the same as if we
just elaborated as an lnet, as passing a simple
identifier elaborates to the same NetNet in
both cases so the extra elaboration has no
effect. But if the expression passed to the
Spelling fixes Mostly comments, but includes quite a few user-visible error, debug, and help messages.
2008-06-12 19:04:29 +02:00
inout port is a part select, a special part
select must be created that can pass data in
Implement bi-directional part selects.
2005-08-06 19:58:16 +02:00
both directions.
Use the elaborate_bi_net method to handle all
the possible cases. */
sig = pins[idx]->elaborate_bi_net(des, scope);
Port expressions for output ports are lnets, not nets.
2002-11-09 20:20:48 +01:00
if (sig == 0) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << pins[idx]->get_fileline() << ": error: "
Implement bi-directional part selects.
2005-08-06 19:58:16 +02:00
<< "Inout port expression must support "
Port expressions for output ports are lnets, not nets.
2002-11-09 20:20:48 +01:00
<< "continuous assignment." << endl;
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << pins[idx]->get_fileline() << ": : "
Include port name in port assignment error message.
2003-04-24 07:25:55 +02:00
<< "Port of " << rmod->mod_name()
<< " is " << rmod->ports[idx]->name << endl;
Port expressions for output ports are lnets, not nets.
2002-11-09 20:20:48 +01:00
des->errors += 1;
continue;
}
Implement bi-directional part selects.
2005-08-06 19:58:16 +02:00
Port expressions for output ports are lnets, not nets.
2002-11-09 20:20:48 +01:00
} else {
Add support for module instance arrays.
2004-09-05 19:44:41 +02:00
Implement bi-directional part selects.
2005-08-06 19:58:16 +02:00
/* Port type must be OUTPUT here. */
/* Output from module. Elaborate the port
expression as the l-value of a continuous
assignment, as the port will continuous assign
into the port. */
Move implicit net creation from elaboration to elaborate_sig If implicit nets are declared during elaboration, then the success of binding during elaboration will depend on the order of the code in the source file.
2008-03-19 04:50:40 +01:00
sig = pins[idx]->elaborate_lnet(des, scope);
Port expressions for output ports are lnets, not nets.
2002-11-09 20:20:48 +01:00
if (sig == 0) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << pins[idx]->get_fileline() << ": error: "
Implement bi-directional part selects.
2005-08-06 19:58:16 +02:00
<< "Output port expression must support "
<< "continuous assignment." << endl;
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << pins[idx]->get_fileline() << ": : "
Implement bi-directional part selects.
2005-08-06 19:58:16 +02:00
<< "Port of " << rmod->mod_name()
<< " is " << rmod->ports[idx]->name << endl;
des->errors += 1;
Port expressions for output ports are lnets, not nets.
2002-11-09 20:20:48 +01:00
continue;
}
Implement bi-directional part selects.
2005-08-06 19:58:16 +02:00
Add to netlist links pin name and instance number, and arrange in vvm for pin connections by name and instance number.
1999-10-31 05:11:27 +01:00
}
assert(sig);
Port expressions for output ports are lnets, not nets.
2002-11-09 20:20:48 +01:00
#ifndef NDEBUG
if ((prts.count() >= 1)
Do not connect reg to module outputs.
2001-07-19 05:43:15 +02:00
&& (prts[0]->port_type() != NetNet::PINPUT)) {
Port expressions for output ports are lnets, not nets.
2002-11-09 20:20:48 +01:00
assert(sig->type() != NetNet::REG);
Do not connect reg to module outputs.
2001-07-19 05:43:15 +02:00
}
Port expressions for output ports are lnets, not nets.
2002-11-09 20:20:48 +01:00
#endif
Handle connectsion to internally unconnected modules (PR#38)
2000-11-05 07:05:59 +01:00
Add support for module instance arrays.
2004-09-05 19:44:41 +02:00
/* If we are working with an instance array, then the
signal width must match the port width exactly. */
if ((instance.count() != 1)
Use PartSelect/PV and VP to handle part selects through ports.
2005-01-09 21:16:00 +01:00
&& (sig->vector_width() != prts_vector_width)
&& (sig->vector_width() != prts_vector_width/instance.count())) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << pins[idx]->get_fileline() << ": error: "
Use PartSelect/PV and VP to handle part selects through ports.
2005-01-09 21:16:00 +01:00
<< "Port expression width " << sig->vector_width()
<< " does not match expected width "<< prts_vector_width
<< " or " << (prts_vector_width/instance.count())
Add support for module instance arrays.
2004-09-05 19:44:41 +02:00
<< "." << endl;
des->errors += 1;
continue;
}
distinguish between single port namy instances, and single instances many sub-ports.
2005-02-10 05:56:58 +01:00
if (debug_elaborate) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": debug: " << get_name()
Error resiliency (ldoolitt)
2007-06-05 23:35:51 +02:00
<< ": Port " << (idx+1) << " has vector width of "
distinguish between single port namy instances, and single instances many sub-ports.
2005-02-10 05:56:58 +01:00
<< prts_vector_width << "." << endl;
}
Carry some line info to the netlist, Dump line numbers for processes. Elaborate prints errors about port vector width mismatch Emit better handles null statements.
1999-02-01 01:26:48 +01:00
// Check that the parts have matching pin counts. If
Fix handling of errors in behavioral lvalues. (PR#28)
2000-10-26 19:09:46 +02:00
// not, they are different widths. Note that idx is 0
// based, but users count parameter positions from 1.
Add support for module instance arrays.
2004-09-05 19:44:41 +02:00
if ((instance.count() == 1)
Use PartSelect/PV and VP to handle part selects through ports.
2005-01-09 21:16:00 +01:00
&& (prts_vector_width != sig->vector_width())) {
Error resiliency (ldoolitt)
2007-06-05 23:35:51 +02:00
const char *tmp3 = rmod->ports[idx]->name.str();
if (tmp3 == 0) tmp3 = "???";
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": warning: Port " << (idx+1)
Error resiliency (ldoolitt)
2007-06-05 23:35:51 +02:00
<< " (" << tmp3 << ") of "
Use PartSelect/PV and VP to handle part selects through ports.
2005-01-09 21:16:00 +01:00
<< type_ << " expects " << prts_vector_width <<
" bits, got " << sig->vector_width() << "." << endl;
Cope with width mismatches to module ports (PR#89)
2001-01-09 06:58:47 +01:00
Pad input and output ports correctly. This patch pads inputs and output ports correctly when the port and the port expression have different widths. It does not fix inout ports. It also sets the file and line number information in the unsigned pad_to_width() routine.
2008-10-03 03:38:53 +02:00
// Delete this when inout ports pad correctly.
if (prts[0]->port_type() == NetNet::PINOUT) {
if (prts_vector_width > sig->vector_width()) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": : Leaving "
Use PartSelect/PV and VP to handle part selects through ports.
2005-01-09 21:16:00 +01:00
<< (prts_vector_width-sig->vector_width())
Cope with width mismatches to module ports (PR#89)
2001-01-09 06:58:47 +01:00
<< " high bits of the port unconnected."
<< endl;
Pad input and output ports correctly. This patch pads inputs and output ports correctly when the port and the port expression have different widths. It does not fix inout ports. It also sets the file and line number information in the unsigned pad_to_width() routine.
2008-10-03 03:38:53 +02:00
} else {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": : Leaving "
Use PartSelect/PV and VP to handle part selects through ports.
2005-01-09 21:16:00 +01:00
<< (sig->vector_width()-prts_vector_width)
Add port name to pin size error message.
2002-08-01 01:55:38 +02:00
<< " high bits of the expression dangling."
Cope with width mismatches to module ports (PR#89)
2001-01-09 06:58:47 +01:00
<< endl;
Pad input and output ports correctly. This patch pads inputs and output ports correctly when the port and the port expression have different widths. It does not fix inout ports. It also sets the file and line number information in the unsigned pad_to_width() routine.
2008-10-03 03:38:53 +02:00
}
// Keep the if, but delete the "} else" when fixed.
} else if (prts_vector_width > sig->vector_width()) {
cerr << get_fileline() << ": : Padding "
<< (prts_vector_width-sig->vector_width())
<< " high bits of the port."
<< endl;
} else {
cerr << get_fileline() << ": : Padding "
<< (sig->vector_width()-prts_vector_width)
<< " high bits of the expression."
<< endl;
Cope with width mismatches to module ports (PR#89)
2001-01-09 06:58:47 +01:00
}
Resize vectors to mismatched ports It is legal in Verilog to bind expressions to ports that do not match the port width. Icarus Verilog needs to create the necessary part selects to get the connections right. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-09-10 06:14:52 +02:00
sig = resize_net_to_port_(des, scope, sig, prts_vector_width,
Pad input and output ports correctly. This patch pads inputs and output ports correctly when the port and the port expression have different widths. It does not fix inout ports. It also sets the file and line number information in the unsigned pad_to_width() routine.
2008-10-03 03:38:53 +02:00
prts[0]->port_type(),
prts[0]->get_signed() &&
sig->get_signed());
Carry some line info to the netlist, Dump line numbers for processes. Elaborate prints errors about port vector width mismatch Emit better handles null statements.
1999-02-01 01:26:48 +01:00
}
Elaborate module ports that are concatenations of module signals.
1999-08-04 04:13:02 +02:00
// Connect the sig expression that is the context of the
Cope with width mismatches to module ports (PR#89)
2001-01-09 06:58:47 +01:00
// module instance to the ports of the elaborated module.
// The prts_pin_count variable is the total width of the
// port and is the maximum number of connections to
// make. sig is the elaborated expression that connects
// to that port. If sig has too few pins, then reduce
// the number of connections to make.
// Connect this many of the port pins. If the expression
Use PartSelect/PV and VP to handle part selects through ports.
2005-01-09 21:16:00 +01:00
// is too small, then reduce the number of connects.
unsigned ccount = prts_vector_width;
if (instance.count() == 1 && sig->vector_width() < ccount)
ccount = sig->vector_width();
Cope with width mismatches to module ports (PR#89)
2001-01-09 06:58:47 +01:00
Add support for module instance arrays.
2004-09-05 19:44:41 +02:00
// The spin_modulus is the width of the signal (not the
// port) if this is an instance array. This causes
// signals wide enough for a single instance to be
// connected to all the instances.
Use PartSelect/PV and VP to handle part selects through ports.
2005-01-09 21:16:00 +01:00
unsigned spin_modulus = prts_vector_width;
Add support for module instance arrays.
2004-09-05 19:44:41 +02:00
if (instance.count() != 1)
Use PartSelect/PV and VP to handle part selects through ports.
2005-01-09 21:16:00 +01:00
spin_modulus = sig->vector_width();
Add support for module instance arrays.
2004-09-05 19:44:41 +02:00
Cope with width mismatches to module ports (PR#89)
2001-01-09 06:58:47 +01:00
// Now scan the concatenation that makes up the port,
// connecting pins until we run out of port pins or sig
Use PartSelect/PV and VP to handle part selects through ports.
2005-01-09 21:16:00 +01:00
// pins. The sig object is the NetNet that is connected
// to the port from the outside, and the prts object is
// an array of signals to be connected to the sig.
Cope with width mismatches to module ports (PR#89)
2001-01-09 06:58:47 +01:00
Use PartSelect/PV and VP to handle part selects through ports.
2005-01-09 21:16:00 +01:00
NetConcat*ctmp;
Cope with width mismatches to module ports (PR#89)
2001-01-09 06:58:47 +01:00
unsigned spin = 0;
Use PartSelect/PV and VP to handle part selects through ports.
2005-01-09 21:16:00 +01:00
if (prts.count() == 1) {
// The simplest case, there are no
// parts/concatenations on the inside of the
// module, so the port and sig need simply be
// connected directly.
connect(prts[0]->pin(0), sig->pin(0));
distinguish between single port namy instances, and single instances many sub-ports.
2005-02-10 05:56:58 +01:00
} else if (sig->vector_width()==prts_vector_width/instance.count()
&& prts.count()/instance.count() == 1) {
if (debug_elaborate){
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": debug: " << get_name()
distinguish between single port namy instances, and single instances many sub-ports.
2005-02-10 05:56:58 +01:00
<< ": Replicating " << prts_vector_width
<< " bits across all "
<< prts_vector_width/instance.count()
<< " sub-ports." << endl;
}
Use PartSelect/PV and VP to handle part selects through ports.
2005-01-09 21:16:00 +01:00
// The signal width is exactly the width of a
// single instance of the port. In this case,
// connect the sig to all the ports identically.
for (unsigned ldx = 0 ; ldx < prts.count() ; ldx += 1)
connect(prts[ldx]->pin(0), sig->pin(0));
} else switch (prts[0]->port_type()) {
case NetNet::POUTPUT:
ctmp = new NetConcat(scope, scope->local_symbol(),
prts_vector_width,
prts.count());
des->add_node(ctmp);
connect(ctmp->pin(0), sig->pin(0));
for (unsigned ldx = 0 ; ldx < prts.count() ; ldx += 1) {
connect(ctmp->pin(ldx+1),
prts[prts.count()-ldx-1]->pin(0));
Elaborate module ports that are concatenations of module signals.
1999-08-04 04:13:02 +02:00
}
Use PartSelect/PV and VP to handle part selects through ports.
2005-01-09 21:16:00 +01:00
break;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
Use PartSelect/PV and VP to handle part selects through ports.
2005-01-09 21:16:00 +01:00
case NetNet::PINPUT:
distinguish between single port namy instances, and single instances many sub-ports.
2005-02-10 05:56:58 +01:00
if (debug_elaborate){
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": debug: " << get_name()
distinguish between single port namy instances, and single instances many sub-ports.
2005-02-10 05:56:58 +01:00
<< ": Dividing " << prts_vector_width
<< " bits across all "
<< prts_vector_width/instance.count()
<< " input sub-ports of port "
<< idx << "." << endl;
}
Use PartSelect/PV and VP to handle part selects through ports.
2005-01-09 21:16:00 +01:00
for (unsigned ldx = 0 ; ldx < prts.count() ; ldx += 1) {
NetNet*sp = prts[prts.count()-ldx-1];
NetPartSelect*ptmp = new NetPartSelect(sig, spin,
sp->vector_width(),
NetPartSelect::VP);
des->add_node(ptmp);
connect(ptmp->pin(0), sp->pin(0));
spin += sp->vector_width();
}
break;
case NetNet::PINOUT:
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": XXXX: "
Implement bi-directional part selects.
2005-08-06 19:58:16 +02:00
<< "Forgot how to bind inout ports!" << endl;
Use PartSelect/PV and VP to handle part selects through ports.
2005-01-09 21:16:00 +01:00
des->errors += 1;
break;
case NetNet::PIMPLICIT:
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": internal error: "
Use PartSelect/PV and VP to handle part selects through ports.
2005-01-09 21:16:00 +01:00
<< "Unexpected IMPLICIT port" << endl;
des->errors += 1;
break;
case NetNet::NOT_A_PORT:
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": internal error: "
Use PartSelect/PV and VP to handle part selects through ports.
2005-01-09 21:16:00 +01:00
<< "Unexpected NOT_A_PORT port." << endl;
des->errors += 1;
break;
}
Cope with width mismatches to module ports (PR#89)
2001-01-09 06:58:47 +01:00
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
Add support for module instance arrays.
2004-09-05 19:44:41 +02:00
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
Fully elaborate Sequential UDP behavior.
1998-12-14 03:01:34 +01:00
/*
* From a UDP definition in the source, make a NetUDP
* object. Elaborate the pin expressions as netlists, then connect
* those networks to the pins.
*/
More UDP consolidation from Stephan Boettcher.
2001-04-23 01:09:45 +02:00
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
void PGModule::elaborate_udp_(Design*des, PUdp*udp, NetScope*scope) const
Elaborate UDP devices, Support UDP type attributes, and pass those attributes to nodes that are instantiated by elaboration, Put modules into a map instead of a simple list.
1998-12-01 01:42:13 +01:00
{
Node delays can be more general expressions in structural contexts.
2006-01-02 06:33:19 +01:00
NetExpr*rise_expr =0, *fall_expr =0, *decay_expr =0;
UDP instances need not have user supplied names.
2001-04-29 01:18:08 +02:00
Use perm_strings for named langiage items.
2004-02-18 18:11:54 +01:00
perm_string my_name = get_name();
if (my_name == 0)
All NetObj objects have lex_string base names.
2003-03-06 01:28:41 +01:00
my_name = scope->local_symbol();
UDP instances need not have user supplied names.
2001-04-29 01:18:08 +02:00
Support delays on UDP instances.
2001-12-06 05:44:11 +01:00
/* When the parser notices delay expressions in front of a
module or primitive, it interprets them as parameter
overrides. Correct that misconception here. */
if (overrides_) {
PDelays tmp_del;
Do not delete delay expressions of UDP instances.
2001-12-29 21:19:31 +01:00
tmp_del.set_delays(overrides_, false);
Node delays can be more general expressions in structural contexts.
2006-01-02 06:33:19 +01:00
tmp_del.eval_delays(des, scope, rise_expr, fall_expr, decay_expr);
if (dynamic_cast<NetEConst*> (rise_expr)) {
} else {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: Delay expressions must be "
Node delays can be more general expressions in structural contexts.
2006-01-02 06:33:19 +01:00
<< "constant for primitives." << endl;
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": : Cannot calculate "
Node delays can be more general expressions in structural contexts.
2006-01-02 06:33:19 +01:00
<< *rise_expr << endl;
des->errors += 1;
}
if (dynamic_cast<NetEConst*> (fall_expr)) {
} else {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: Delay expressions must be "
Node delays can be more general expressions in structural contexts.
2006-01-02 06:33:19 +01:00
<< "constant for primitives." << endl;
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": : Cannot calculate "
Node delays can be more general expressions in structural contexts.
2006-01-02 06:33:19 +01:00
<< *rise_expr << endl;
des->errors += 1;
}
if (dynamic_cast<NetEConst*> (decay_expr)) {
} else {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: Delay expressions must be "
Node delays can be more general expressions in structural contexts.
2006-01-02 06:33:19 +01:00
<< "constant for primitives." << endl;
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": : Cannot calculate "
Node delays can be more general expressions in structural contexts.
2006-01-02 06:33:19 +01:00
<< *rise_expr << endl;
des->errors += 1;
}
Support delays on UDP instances.
2001-12-06 05:44:11 +01:00
}
Do not delete delay expressions of UDP instances.
2001-12-29 21:19:31 +01:00
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
assert(udp);
Support for UDP devices in VVP (Stephen Boettcher)
2001-04-24 04:23:58 +02:00
NetUDP*net = new NetUDP(scope, my_name, udp->ports.count(), udp);
Node delays can be more general expressions in structural contexts.
2006-01-02 06:33:19 +01:00
net->rise_time(rise_expr);
net->fall_time(fall_expr);
net->decay_time(decay_expr);
Elaborate UDP devices, Support UDP type attributes, and pass those attributes to nodes that are instantiated by elaboration, Put modules into a map instead of a simple list.
1998-12-01 01:42:13 +01:00
Add language support for Verilog-2001 attribute syntax. Hook this support into existing $attribute handling, and add number and void value types. Add to the ivl_target API new functions for access of complex attributes attached to gates.
2002-05-23 05:08:50 +02:00
struct attrib_list_t*attrib_list = 0;
unsigned attrib_list_n = 0;
attrib_list = evaluate_attributes(attributes, attrib_list_n,
des, scope);
for (unsigned adx = 0 ; adx < attrib_list_n ; adx += 1)
net->attribute(attrib_list[adx].key, attrib_list[adx].val);
delete[]attrib_list;
primitive ports can bind bi name.
2004-03-08 01:47:44 +01:00
// This is the array of pin expressions, shuffled to match the
// order of the declaration. If the source instantiation uses
// bind by order, this is the same as the source
// list. Otherwise, the source list is rearranged by name
// binding into this list.
svector<PExpr*>pins;
// Detect binding by name. If I am binding by name, then make
// up a pins array that reflects the positions of the named
// ports. If this is simply positional binding in the first
// place, then get the binding from the base class.
if (pins_) {
unsigned nexp = udp->ports.count();
pins = svector<PExpr*>(nexp);
// Scan the bindings, matching them with port names.
for (unsigned idx = 0 ; idx < npins_ ; idx += 1) {
// Given a binding, look at the module port names
// for the position that matches the binding name.
unsigned pidx = udp->find_port(pins_[idx].name);
// If the port name doesn't exist, the find_port
// method will return the port count. Detect that
// as an error.
if (pidx == nexp) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: port ``" <<
primitive ports can bind bi name.
2004-03-08 01:47:44 +01:00
pins_[idx].name << "'' is not a port of "
<< get_name() << "." << endl;
des->errors += 1;
continue;
}
// If I already bound something to this port, then
// the (*exp) array will already have a pointer
// value where I want to place this expression.
if (pins[pidx]) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: port ``" <<
primitive ports can bind bi name.
2004-03-08 01:47:44 +01:00
pins_[idx].name << "'' already bound." <<
endl;
des->errors += 1;
continue;
}
// OK, do the binding by placing the expression in
// the right place.
pins[pidx] = pins_[idx].parm;
}
} else {
/* Otherwise, this is a positional list of port
connections. In this case, the port count must be
right. Check that is is, the get the pin list. */
if (pin_count() != udp->ports.count()) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: Wrong number "
primitive ports can bind bi name.
2004-03-08 01:47:44 +01:00
"of ports. Expecting " << udp->ports.count() <<
", got " << pin_count() << "."
<< endl;
des->errors += 1;
return;
}
// No named bindings, just use the positional list I
// already have.
assert(pin_count() == udp->ports.count());
pins = get_pins();
}
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
/* Handle the output port of the primitive special. It is an
output port (the only output port) so must be passed an
l-value net. */
primitive ports can bind bi name.
2004-03-08 01:47:44 +01:00
if (pins[0] == 0) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": warning: output port unconnected."
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
<< endl;
} else {
Move implicit net creation from elaboration to elaborate_sig If implicit nets are declared during elaboration, then the success of binding during elaboration will depend on the order of the code in the source file.
2008-03-19 04:50:40 +01:00
NetNet*sig = pins[0]->elaborate_lnet(des, scope);
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
if (sig == 0) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: "
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
<< "Output port expression is not valid." << endl;
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": : Output "
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
<< "port of " << udp->name_
<< " is " << udp->ports[0] << "." << endl;
des->errors += 1;
} else {
connect(sig->pin(0), net->pin(0));
}
}
Fully elaborate Sequential UDP behavior.
1998-12-14 03:01:34 +01:00
/* Run through the pins, making netlists for the pin
expressions and connecting them to the pin in question. All
of this is independent of the nature of the UDP. */
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
for (unsigned idx = 1 ; idx < net->pin_count() ; idx += 1) {
primitive ports can bind bi name.
2004-03-08 01:47:44 +01:00
if (pins[idx] == 0)
Add the nobufz function to eliminate bufz objects, Object links are marked with direction, constant propagation is more careful will wide links, Signal folding is aware of attributes, and the XNF target can dump UDP objects based on LCA attributes.
1998-12-02 05:37:13 +01:00
continue;
Remove elaborate_net from all elaborations. Use elaborate_expr and synthesize() methods in place of the elaborate_net methods, so that elaboration is more consistent.
2008-09-09 04:13:49 +02:00
NetExpr*expr_tmp = elab_and_eval(des, scope, pins[idx], 1, 1);
if (expr_tmp == 0) {
Add non-const bit select in l-value of assignment.
1999-10-07 07:25:33 +02:00
cerr << "internal error: Expression too complicated "
primitive ports can bind bi name.
2004-03-08 01:47:44 +01:00
"for elaboration:" << pins[idx] << endl;
Elaborate UDP devices, Support UDP type attributes, and pass those attributes to nodes that are instantiated by elaboration, Put modules into a map instead of a simple list.
1998-12-01 01:42:13 +01:00
continue;
}
Remove elaborate_net from all elaborations. Use elaborate_expr and synthesize() methods in place of the elaborate_net methods, so that elaboration is more consistent.
2008-09-09 04:13:49 +02:00
NetNet*sig = expr_tmp->synthesize(des, scope);
ivl_assert(*this, sig);
sig->set_line(*this);
delete expr_tmp;
Elaborate UDP devices, Support UDP type attributes, and pass those attributes to nodes that are instantiated by elaboration, Put modules into a map instead of a simple list.
1998-12-01 01:42:13 +01:00
connect(sig->pin(0), net->pin(idx));
}
Clean up spurious trailing white space.
2004-10-04 03:10:51 +02:00
Fully elaborate Sequential UDP behavior.
1998-12-14 03:01:34 +01:00
// All done. Add the object to the design.
Elaborate UDP devices, Support UDP type attributes, and pass those attributes to nodes that are instantiated by elaboration, Put modules into a map instead of a simple list.
1998-12-01 01:42:13 +01:00
des->add_node(net);
}
Move signal elaboration to a seperate pass.
2000-05-02 18:27:38 +02:00
bool PGModule::elaborate_sig(Design*des, NetScope*scope) const
{
// Look for the module type
Use perm_strings for named langiage items.
2004-02-18 18:11:54 +01:00
map<perm_string,Module*>::const_iterator mod = pform_modules.find(type_);
Add automatic module libraries.
2001-10-21 01:02:39 +02:00
if (mod != pform_modules.end())
Move signal elaboration to a seperate pass.
2000-05-02 18:27:38 +02:00
return elaborate_sig_mod_(des, scope, (*mod).second);
Implicit declaration handling in ports to UDP. Scan port expressions for implicit nets using elaborate_sig.
2008-03-21 05:44:35 +01:00
map<perm_string,PUdp*>::const_iterator udp = pform_primitives.find(type_);
if (udp != pform_primitives.end())
return elaborate_sig_udp_(des, scope, (*udp).second);
Move signal elaboration to a seperate pass.
2000-05-02 18:27:38 +02:00
return true;
}
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
void PGModule::elaborate(Design*des, NetScope*scope) const
Elaborate UDP devices, Support UDP type attributes, and pass those attributes to nodes that are instantiated by elaboration, Put modules into a map instead of a simple list.
1998-12-01 01:42:13 +01:00
{
// Look for the module type
Use perm_strings for named langiage items.
2004-02-18 18:11:54 +01:00
map<perm_string,Module*>::const_iterator mod = pform_modules.find(type_);
Add automatic module libraries.
2001-10-21 01:02:39 +02:00
if (mod != pform_modules.end()) {
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
elaborate_mod_(des, (*mod).second, scope);
Elaborate UDP devices, Support UDP type attributes, and pass those attributes to nodes that are instantiated by elaboration, Put modules into a map instead of a simple list.
1998-12-01 01:42:13 +01:00
return;
}
// Try a primitive type
Use perm_strings for named langiage items.
2004-02-18 18:11:54 +01:00
map<perm_string,PUdp*>::const_iterator udp = pform_primitives.find(type_);
Add automatic module libraries.
2001-10-21 01:02:39 +02:00
if (udp != pform_primitives.end()) {
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
assert((*udp).second);
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
elaborate_udp_(des, (*udp).second, scope);
Elaborate UDP devices, Support UDP type attributes, and pass those attributes to nodes that are instantiated by elaboration, Put modules into a map instead of a simple list.
1998-12-01 01:42:13 +01:00
return;
}
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": internal error: Unknown module type: " <<
Redesign the implementation of scopes and parameters. I now generate the scopes and notice the parameters in a separate pass over the pform. Once the scopes are generated, I can process overrides and evalutate paremeters before elaboration begins.
2000-03-08 05:36:53 +01:00
type_ << endl;
}
void PGModule::elaborate_scope(Design*des, NetScope*sc) const
{
// Look for the module type
Use perm_strings for named langiage items.
2004-02-18 18:11:54 +01:00
map<perm_string,Module*>::const_iterator mod = pform_modules.find(type_);
Add automatic module libraries.
2001-10-21 01:02:39 +02:00
if (mod != pform_modules.end()) {
Redesign the implementation of scopes and parameters. I now generate the scopes and notice the parameters in a separate pass over the pform. Once the scopes are generated, I can process overrides and evalutate paremeters before elaboration begins.
2000-03-08 05:36:53 +01:00
elaborate_scope_mod_(des, (*mod).second, sc);
return;
}
// Try a primitive type
Use perm_strings for named langiage items.
2004-02-18 18:11:54 +01:00
map<perm_string,PUdp*>::const_iterator udp = pform_primitives.find(type_);
Add automatic module libraries.
2001-10-21 01:02:39 +02:00
if (udp != pform_primitives.end())
Redesign the implementation of scopes and parameters. I now generate the scopes and notice the parameters in a separate pass over the pform. Once the scopes are generated, I can process overrides and evalutate paremeters before elaboration begins.
2000-03-08 05:36:53 +01:00
return;
Add automatic module libraries.
2001-10-21 01:02:39 +02:00
// Not a module or primitive that I know about yet, so try to
// load a library module file (which parses some new Verilog
// code) and try again.
Module types in pform are char* instead of string.
2001-10-21 02:42:47 +02:00
if (load_module(type_)) {
Add automatic module libraries.
2001-10-21 01:02:39 +02:00
// Try again to find the module type
mod = pform_modules.find(type_);
if (mod != pform_modules.end()) {
elaborate_scope_mod_(des, (*mod).second, sc);
return;
}
Redesign the implementation of scopes and parameters. I now generate the scopes and notice the parameters in a separate pass over the pform. Once the scopes are generated, I can process overrides and evalutate paremeters before elaboration begins.
2000-03-08 05:36:53 +01:00
Add automatic module libraries.
2001-10-21 01:02:39 +02:00
// Try again to find a primitive type
udp = pform_primitives.find(type_);
if (udp != pform_primitives.end())
return;
}
// Not a module or primitive that I know about or can find by
// any means, so give up.
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: Unknown module type: " << type_ << endl;
Summary list of missing modules.
2003-09-25 02:25:14 +02:00
missing_modules[type_] += 1;
Redesign the implementation of scopes and parameters. I now generate the scopes and notice the parameters in a separate pass over the pform. Once the scopes are generated, I can process overrides and evalutate paremeters before elaboration begins.
2000-03-08 05:36:53 +01:00
des->errors += 1;
Elaborate UDP devices, Support UDP type attributes, and pass those attributes to nodes that are instantiated by elaboration, Put modules into a map instead of a simple list.
1998-12-01 01:42:13 +01:00
}
separate assign lval elaboration for error checking.
1999-09-15 06:17:52 +02:00
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
NetProc* Statement::elaborate(Design*des, NetScope*) const
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
{
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": internal error: elaborate: "
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
"What kind of statement? " << typeid(*this).name() << endl;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
NetProc*cur = new NetProc;
Parse disable statements to pform.
2000-07-26 07:08:07 +02:00
des->errors += 1;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
return cur;
}
Parse and elaborate the concatenate operator in structural contexts, Replace vector<PExpr*> and list<PExpr*> with svector<PExpr*>, evaluate constant expressions with parameters, handle memories as lvalues. Parse task declarations, integer types.
1999-05-10 02:16:57 +02:00
move lval elaboration to PExpr virtual methods.
2000-09-09 17:21:26 +02:00
NetAssign_* PAssign_::elaborate_lval(Design*des, NetScope*scope) const
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
{
Add support for memory words in l-value of blocking assignments, and remove the special NetAssignMem class.
2002-06-04 07:38:43 +02:00
assert(lval_);
Unify elaboration of l-values for all proceedural assignments, including assing, cassign and force. Generate NetConcat devices for gate outputs that feed into a vector results. Use this to hande gate arrays. Also let gate arrays handle vectors of gates when the outputs allow for it.
2004-12-30 00:55:43 +01:00
return lval_->elaborate_lval(des, scope, false);
l-value part select for procedural assignments.
1999-06-14 01:51:16 +02:00
}
Process shift by constant amounts early in expression elaboration. The expr:::synthesize methods need not deal with saturating left or right shifts if they are dealt with early, in elaborate_expr methods. So the elaborate_expr for shift takes on much more responsibility.
2008-08-21 06:47:07 +02:00
NetExpr* PAssign_::elaborate_rval_(Design*des, NetScope*scope,
Account for real type l-values when working with widths. Widths of real values are always 1. When paired with vectorable types in expressions, the vectorable type is processed as losslessly self- determined. ("unsized" in the test_width methods.)
2008-09-23 06:09:06 +02:00
unsigned lv_width,
ivl_variable_type_t lv_type) const
Process shift by constant amounts early in expression elaboration. The expr:::synthesize methods need not deal with saturating left or right shifts if they are dealt with early, in elaborate_expr methods. So the elaborate_expr for shift takes on much more responsibility.
2008-08-21 06:47:07 +02:00
{
ivl_assert(*this, rval_);
Unify all the r-value elaboration. R-value expression elaboration happens in several places. Factor out the common code so that they are all handled correctly and uniformly.
2008-09-26 06:22:21 +02:00
NetExpr*rv = elaborate_rval_expr(des, scope, lv_type, lv_width, rval());
Process shift by constant amounts early in expression elaboration. The expr:::synthesize methods need not deal with saturating left or right shifts if they are dealt with early, in elaborate_expr methods. So the elaborate_expr for shift takes on much more responsibility.
2008-08-21 06:47:07 +02:00
return rv;
}
Redo handling of assignment internal delays. Leave it possible for them to be calculated at run time.
2002-04-22 00:31:02 +02:00
/*
* This function elaborates delay expressions. This is a little
* different from normal elaboration because the result may need to be
* scaled.
*/
static NetExpr*elaborate_delay_expr(PExpr*expr, Design*des, NetScope*scope)
{
Make elaborate_expr methods aware of the width that the context requires of it. In the process, fix sizing of the width of unary minus is context determined sizes.
2006-06-02 06:48:49 +02:00
NetExpr*dex = elab_and_eval(des, scope, expr, -1);
Calculate delay statement delays using elaborated expressions instead of pre-elaborated expression trees. Remove the eval_pexpr methods from PExpr.
2003-02-08 20:49:21 +01:00
/* If the delay expression is a real constant or vector
constant, then evaluate it, scale it to the local time
units, and return an adjusted NetEConst. */
if (NetECReal*tmp = dynamic_cast<NetECReal*>(dex)) {
verireal fn = tmp->value();
Redo handling of assignment internal delays. Leave it possible for them to be calculated at run time.
2002-04-22 00:31:02 +02:00
int shift = scope->time_unit() - des->get_precision();
Handle 64bit delay constants.
2006-08-08 07:11:37 +02:00
int64_t delay = fn.as_long64(shift);
Calculate delay statement delays using elaborated expressions instead of pre-elaborated expression trees. Remove the eval_pexpr methods from PExpr.
2003-02-08 20:49:21 +01:00
if (delay < 0)
delay = 0;
Redo handling of assignment internal delays. Leave it possible for them to be calculated at run time.
2002-04-22 00:31:02 +02:00
Calculate delay statement delays using elaborated expressions instead of pre-elaborated expression trees. Remove the eval_pexpr methods from PExpr.
2003-02-08 20:49:21 +01:00
delete tmp;
return new NetEConst(verinum(delay));
Redo handling of assignment internal delays. Leave it possible for them to be calculated at run time.
2002-04-22 00:31:02 +02:00
}
Calculate delay statement delays using elaborated expressions instead of pre-elaborated expression trees. Remove the eval_pexpr methods from PExpr.
2003-02-08 20:49:21 +01:00
if (NetEConst*tmp = dynamic_cast<NetEConst*>(dex)) {
verinum fn = tmp->value();
Handle 64bit delay constants.
2006-08-08 07:11:37 +02:00
uint64_t delay =
des->scale_to_precision(fn.as_ulong64(), scope);
Calculate delay statement delays using elaborated expressions instead of pre-elaborated expression trees. Remove the eval_pexpr methods from PExpr.
2003-02-08 20:49:21 +01:00
delete tmp;
return new NetEConst(verinum(delay));
Redo handling of assignment internal delays. Leave it possible for them to be calculated at run time.
2002-04-22 00:31:02 +02:00
}
Calculate delay statement delays using elaborated expressions instead of pre-elaborated expression trees. Remove the eval_pexpr methods from PExpr.
2003-02-08 20:49:21 +01:00
/* The expression is not constant, so generate an expanded
expression that includes the necessary scale shifts, and
return that expression. */
Redo handling of assignment internal delays. Leave it possible for them to be calculated at run time.
2002-04-22 00:31:02 +02:00
int shift = scope->time_unit() - des->get_precision();
if (shift > 0) {
Handle 64bit delay constants.
2006-08-08 07:11:37 +02:00
uint64_t scale = 1;
Redo handling of assignment internal delays. Leave it possible for them to be calculated at run time.
2002-04-22 00:31:02 +02:00
while (shift > 0) {
scale *= 10;
shift -= 1;
}
NetExpr*scal_val = new NetEConst(verinum(scale));
Calculate delay statement delays using elaborated expressions instead of pre-elaborated expression trees. Remove the eval_pexpr methods from PExpr.
2003-02-08 20:49:21 +01:00
dex = new NetEBMult('*', dex, scal_val);
Redo handling of assignment internal delays. Leave it possible for them to be calculated at run time.
2002-04-22 00:31:02 +02:00
}
if (shift < 0) {
unsigned long scale = 1;
while (shift < 0) {
scale *= 10;
shift += 1;
}
NetExpr*scal_val = new NetEConst(verinum(scale));
Calculate delay statement delays using elaborated expressions instead of pre-elaborated expression trees. Remove the eval_pexpr methods from PExpr.
2003-02-08 20:49:21 +01:00
dex = new NetEBDiv('/', dex, scal_val);
Redo handling of assignment internal delays. Leave it possible for them to be calculated at run time.
2002-04-22 00:31:02 +02:00
}
Calculate delay statement delays using elaborated expressions instead of pre-elaborated expression trees. Remove the eval_pexpr methods from PExpr.
2003-02-08 20:49:21 +01:00
return dex;
Redo handling of assignment internal delays. Leave it possible for them to be calculated at run time.
2002-04-22 00:31:02 +02:00
}
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
NetProc* PAssign::elaborate(Design*des, NetScope*scope) const
l-value part select for procedural assignments.
1999-06-14 01:51:16 +02:00
{
Redesign the implementation of scopes and parameters. I now generate the scopes and notice the parameters in a separate pass over the pform. Once the scopes are generated, I can process overrides and evalutate paremeters before elaboration begins.
2000-03-08 05:36:53 +01:00
assert(scope);
procedural blocking assignment delays.
1999-07-12 02:59:36 +02:00
/* elaborate the lval. This detects any part selects and mux
expressions that might exist. */
Change elaborate_lval to return NetAssign_ objects.
2000-09-03 19:58:35 +02:00
NetAssign_*lv = elaborate_lval(des, scope);
if (lv == 0) return 0;
l-value part select for procedural assignments.
1999-06-14 01:51:16 +02:00
Redo handling of assignment internal delays. Leave it possible for them to be calculated at run time.
2002-04-22 00:31:02 +02:00
/* If there is an internal delay expression, elaborate it. */
NetExpr*delay = 0;
if (delay_ != 0)
delay = elaborate_delay_expr(delay_, des, scope);
procedural blocking assignment delays.
1999-07-12 02:59:36 +02:00
l-value part select for procedural assignments.
1999-06-14 01:51:16 +02:00
Rework expression parsing and elaboration to accommodate real/realtime values and expressions.
2003-01-26 22:15:58 +01:00
/* Elaborate the r-value expression, then try to evaluate it. */
Account for real type l-values when working with widths. Widths of real values are always 1. When paired with vectorable types in expressions, the vectorable type is processed as losslessly self- determined. ("unsized" in the test_width methods.)
2008-09-23 06:09:06 +02:00
NetExpr*rv = elaborate_rval_(des, scope, count_lval_width(lv), lv->expr_type());
Rewire/generalize parsing an elaboration of function return values to allow for better speed and more type support.
2004-06-01 01:34:36 +02:00
if (rv == 0) return 0;
l-value part select for procedural assignments.
1999-06-14 01:51:16 +02:00
assert(rv);
Add blocking repeat event control, make repeat sign aware This patch adds blocking repeat event controls and also makes the base repeat statement sign aware. If the argument to repeat is negative (it must be a signed variable) then this is treated just like an argument of 0 (there is no looping). Doing this allows us to model the repeat event control as follows. lhs = repeat(count) @(event) rhs; is translated to: begin temp = rhs; repeat (count) @(event); lhs = temp; end This patch also pushes the non-blocking event control information to the elaboration phase where it will report they are not currently supported.
2008-09-04 01:05:12 +02:00
if (count_) assert(event_);
Catch memory word parameters to tasks.
2000-04-28 18:50:53 +02:00
procedural blocking assignment delays.
1999-07-12 02:59:36 +02:00
/* Rewrite delayed assignments as assignments that are
Construct delayed assignment as an equivilent block.
1999-07-13 06:08:26 +02:00
delayed. For example, a = #<d> b; becomes:
begin
tmp = b;
#<d> a = tmp;
end
assignment with blocking event delay.
1999-09-22 04:00:48 +02:00
If the delay is an event delay, then the transform is
similar, with the event delay replacing the time delay. It
is an event delay if the event_ member has a value.
Construct delayed assignment as an equivilent block.
1999-07-13 06:08:26 +02:00
This rewriting of the expression allows me to not bother to
actually and literally represent the delayed assign in the
Fixup spelling and some error messages. <LRDoolittle@lbl.gov>
1999-08-18 06:00:02 +02:00
netlist. The compound statement is exactly equivalent. */
Construct delayed assignment as an equivilent block.
1999-07-13 06:08:26 +02:00
Redo handling of assignment internal delays. Leave it possible for them to be calculated at run time.
2002-04-22 00:31:02 +02:00
if (delay || event_) {
Properly pad results of function calls. The elaborator improperly allowed user function call nodes to take on the expression width requested of them. The result was that generated code had junk pad bits in certain cases.
2008-05-10 00:25:42 +02:00
unsigned wid = count_lval_width(lv);
Better handling of bit width of + operators.
1999-07-17 20:06:02 +02:00
Change the NetAssign_ class to refer to the signal instead of link into the netlist. This is faster and uses less space. Make the NetAssignNB carry the delays instead of the NetAssign_ lval objects. Change the vvp code generator to support multiple l-values, i.e. concatenations of part selects.
2001-08-26 01:50:02 +02:00
rv->set_width(wid);
rv = pad_to_width(rv, wid);
Expand bits in delayed assignments.
1999-09-22 23:25:42 +02:00
Fix truncation of signed constant in constant addition.
2003-05-04 22:04:08 +02:00
if (wid > rv->expr_width()) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: Unable to match "
Expand bits in delayed assignments.
1999-09-22 23:25:42 +02:00
"expression width of " << rv->expr_width() <<
" to l-value width of " << wid << "." << endl;
Better handling of bit width of + operators.
1999-07-17 20:06:02 +02:00
//XXXX delete rv;
return 0;
}
All NetObj objects have lex_string base names.
2003-03-06 01:28:41 +01:00
NetNet*tmp = new NetNet(scope, scope->local_symbol(),
NetNet::REG, wid);
Better track signals marked local.
2007-12-28 00:47:01 +01:00
tmp->local_flag(true);
Construct delayed assignment as an equivilent block.
1999-07-13 06:08:26 +02:00
tmp->set_line(*this);
More explicit datatype setup.
2006-05-01 22:47:58 +02:00
tmp->data_type(rv->expr_type());
Construct delayed assignment as an equivilent block.
1999-07-13 06:08:26 +02:00
Change elaborate_lval to return NetAssign_ objects.
2000-09-03 19:58:35 +02:00
NetESignal*sig = new NetESignal(tmp);
Clarify msb/lsb in context of netlist. Properly handle part selects in lval and rval of expressions, and document where the least significant bit goes in NetNet objects.
1999-09-13 05:10:59 +02:00
/* Generate an assignment of the l-value to the temporary... */
Change the NetAssign_ class to refer to the signal instead of link into the netlist. This is faster and uses less space. Make the NetAssignNB carry the delays instead of the NetAssign_ lval objects. Change the vvp code generator to support multiple l-values, i.e. concatenations of part selects.
2001-08-26 01:50:02 +02:00
NetAssign_*lvt = new NetAssign_(tmp);
Pull NetAssign_ creation out of constructors.
2000-09-03 01:40:12 +02:00
Change elaborate_lval to return NetAssign_ objects.
2000-09-03 19:58:35 +02:00
NetAssign*a1 = new NetAssign(lvt, rv);
Pull NetAssign_ creation out of constructors.
2000-09-03 01:40:12 +02:00
a1->set_line(*this);
procedural blocking assignment delays.
1999-07-12 02:59:36 +02:00
Clarify msb/lsb in context of netlist. Properly handle part selects in lval and rval of expressions, and document where the least significant bit goes in NetNet objects.
1999-09-13 05:10:59 +02:00
/* Generate an assignment of the temporary to the r-value... */
Pull NetAssign_ creation out of constructors.
2000-09-03 01:40:12 +02:00
NetAssign*a2 = new NetAssign(lv, sig);
a2->set_line(*this);
Construct delayed assignment as an equivilent block.
1999-07-13 06:08:26 +02:00
assignment with blocking event delay.
1999-09-22 04:00:48 +02:00
/* Generate the delay statement with the final
assignment attached to it. If this is an event delay,
elaborate the PEventStatement. Otherwise, create the
Add blocking repeat event control, make repeat sign aware This patch adds blocking repeat event controls and also makes the base repeat statement sign aware. If the argument to repeat is negative (it must be a signed variable) then this is treated just like an argument of 0 (there is no looping). Doing this allows us to model the repeat event control as follows. lhs = repeat(count) @(event) rhs; is translated to: begin temp = rhs; repeat (count) @(event); lhs = temp; end This patch also pushes the non-blocking event control information to the elaboration phase where it will report they are not currently supported.
2008-09-04 01:05:12 +02:00
right NetPDelay object. For a repeat event control
repeat the event and then do the final assignment. */
assignment with blocking event delay.
1999-09-22 04:00:48 +02:00
NetProc*st;
if (event_) {
Add blocking repeat event control, make repeat sign aware This patch adds blocking repeat event controls and also makes the base repeat statement sign aware. If the argument to repeat is negative (it must be a signed variable) then this is treated just like an argument of 0 (there is no looping). Doing this allows us to model the repeat event control as follows. lhs = repeat(count) @(event) rhs; is translated to: begin temp = rhs; repeat (count) @(event); lhs = temp; end This patch also pushes the non-blocking event control information to the elaboration phase where it will report they are not currently supported.
2008-09-04 01:05:12 +02:00
if (count_) {
NetExpr*count = elab_and_eval(des, scope, count_, -1);
if (count == 0) {
cerr << get_fileline() << ": Unable to "
"elaborate repeat expression." << endl;
des->errors += 1;
return 0;
}
st = event_->elaborate(des, scope);
if (st == 0) {
cerr << event_->get_fileline() << ": error: "
"unable to elaborate event expression."
<< endl;
des->errors += 1;
return 0;
}
assignment with blocking event delay.
1999-09-22 04:00:48 +02:00
Add blocking repeat event control, make repeat sign aware This patch adds blocking repeat event controls and also makes the base repeat statement sign aware. If the argument to repeat is negative (it must be a signed variable) then this is treated just like an argument of 0 (there is no looping). Doing this allows us to model the repeat event control as follows. lhs = repeat(count) @(event) rhs; is translated to: begin temp = rhs; repeat (count) @(event); lhs = temp; end This patch also pushes the non-blocking event control information to the elaboration phase where it will report they are not currently supported.
2008-09-04 01:05:12 +02:00
// If the expression is a constant, handle
// certain special iteration counts.
if (NetEConst*ce = dynamic_cast<NetEConst*>(count)) {
long val = ce->value().as_long();
// We only need the real statement.
if (val <= 0) {
delete count;
delete st;
st = 0;
// We don't need the repeat statement.
} else if (val == 1) {
delete count;
// We need a repeat statement.
} else {
st = new NetRepeat(count, st);
}
} else {
st = new NetRepeat(count, st);
}
} else {
st = event_->elaborate_st(des, scope, a2);
if (st == 0) {
cerr << event_->get_fileline() << ": error: "
"unable to elaborate event expression."
<< endl;
des->errors += 1;
return 0;
}
}
assignment with blocking event delay.
1999-09-22 04:00:48 +02:00
} else {
Redo handling of assignment internal delays. Leave it possible for them to be calculated at run time.
2002-04-22 00:31:02 +02:00
NetPDelay*de = new NetPDelay(delay, a2);
Propagate source line number in synthetic delay statements.
2004-06-30 17:32:02 +02:00
de->set_line(*this);
assignment with blocking event delay.
1999-09-22 04:00:48 +02:00
st = de;
}
Construct delayed assignment as an equivilent block.
1999-07-13 06:08:26 +02:00
assignment with blocking event delay.
1999-09-22 04:00:48 +02:00
/* And build up the complex statement. */
Support carrying the scope of named begin-end blocks down to the code generator, and have the vvp code generator use that to support disable.
2002-05-27 02:08:45 +02:00
NetBlock*bl = new NetBlock(NetBlock::SEQU, 0);
Construct delayed assignment as an equivilent block.
1999-07-13 06:08:26 +02:00
bl->append(a1);
Add blocking repeat event control, make repeat sign aware This patch adds blocking repeat event controls and also makes the base repeat statement sign aware. If the argument to repeat is negative (it must be a signed variable) then this is treated just like an argument of 0 (there is no looping). Doing this allows us to model the repeat event control as follows. lhs = repeat(count) @(event) rhs; is translated to: begin temp = rhs; repeat (count) @(event); lhs = temp; end This patch also pushes the non-blocking event control information to the elaboration phase where it will report they are not currently supported.
2008-09-04 01:05:12 +02:00
if (st) bl->append(st);
if (count_) bl->append(a2);
procedural blocking assignment delays.
1999-07-12 02:59:36 +02:00
Construct delayed assignment as an equivilent block.
1999-07-13 06:08:26 +02:00
return bl;
procedural blocking assignment delays.
1999-07-12 02:59:36 +02:00
}
Rework expression parsing and elaboration to accommodate real/realtime values and expressions.
2003-01-26 22:15:58 +01:00
/* Based on the specific type of the l-value, do cleanup
processing on the r-value. */
Remove NetVariable and ivl_variable_t structures.
2005-07-11 18:56:50 +02:00
if (rv->expr_type() == IVL_VT_REAL) {
Handle assign of real to vector.
2003-06-13 21:10:20 +02:00
// The r-value is a real. Casting will happen in the
// code generator, so leave it.
Rework expression parsing and elaboration to accommodate real/realtime values and expressions.
2003-01-26 22:15:58 +01:00
} else {
unsigned wid = count_lval_width(lv);
Remove NetVariable and ivl_variable_t structures.
2005-07-11 18:56:50 +02:00
rv->set_width(wid);
Rework expression parsing and elaboration to accommodate real/realtime values and expressions.
2003-01-26 22:15:58 +01:00
rv = pad_to_width(rv, wid);
assert(rv->expr_width() >= wid);
l-value part select for procedural assignments.
1999-06-14 01:51:16 +02:00
}
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
Change elaborate_lval to return NetAssign_ objects.
2000-09-03 19:58:35 +02:00
NetAssign*cur = new NetAssign(lv, rv);
Support more operators, especially logical.
1999-03-15 03:43:32 +01:00
cur->set_line(*this);
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
return cur;
}
Add parse and elaboration of non-blocking assignments, Replace list<PCase::Item*> with an svector version, Add integer support.
1999-06-06 22:45:38 +02:00
/*
Only pad the width of vector r-values.
2004-06-20 17:59:06 +02:00
* Elaborate non-blocking assignments. The statement is of the general
* form:
*
* <lval> <= #<delay> <rval> ;
Add parse and elaboration of non-blocking assignments, Replace list<PCase::Item*> with an svector version, Add integer support.
1999-06-06 22:45:38 +02:00
*/
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
NetProc* PAssignNB::elaborate(Design*des, NetScope*scope) const
Add parse and elaboration of non-blocking assignments, Replace list<PCase::Item*> with an svector version, Add integer support.
1999-06-06 22:45:38 +02:00
{
Redesign the implementation of scopes and parameters. I now generate the scopes and notice the parameters in a separate pass over the pform. Once the scopes are generated, I can process overrides and evalutate paremeters before elaboration begins.
2000-03-08 05:36:53 +01:00
assert(scope);
Check that functions do not call invalid statements. This patch adds checks to verify that functions do not invoke statements that are invalid for them (#, @, wait, enable/call tasks and non blocking assignment). For reference see section 10.3.4 of 1364-2001.
2007-08-25 03:48:24 +02:00
if (scope->in_func()) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: functions cannot have non "
Check that functions do not call invalid statements. This patch adds checks to verify that functions do not invoke statements that are invalid for them (#, @, wait, enable/call tasks and non blocking assignment). For reference see section 10.3.4 of 1364-2001.
2007-08-25 03:48:24 +02:00
"blocking assignment statements." << endl;
des->errors += 1;
return 0;
}
Evaluate nb-assign r-values using elab_and_eval.
2003-09-20 08:08:53 +02:00
/* Elaborate the l-value. */
Change elaborate_lval to return NetAssign_ objects.
2000-09-03 19:58:35 +02:00
NetAssign_*lv = elaborate_lval(des, scope);
if (lv == 0) return 0;
Add parse and elaboration of non-blocking assignments, Replace list<PCase::Item*> with an svector version, Add integer support.
1999-06-06 22:45:38 +02:00
Account for real type l-values when working with widths. Widths of real values are always 1. When paired with vectorable types in expressions, the vectorable type is processed as losslessly self- determined. ("unsized" in the test_width methods.)
2008-09-23 06:09:06 +02:00
NetExpr*rv = elaborate_rval_(des, scope, count_lval_width(lv), lv->expr_type());
Parse system function calls.
1999-09-25 04:57:29 +02:00
Only pad the width of vector r-values.
2004-06-20 17:59:06 +02:00
/* Handle the (common) case that the r-value is a vector. This
includes just about everything but reals. In this case, we
need to pad the r-value to match the width of the l-value.
precalculate r-values of nb assignments and task arguments.
2002-12-05 05:15:14 +01:00
Only pad the width of vector r-values.
2004-06-20 17:59:06 +02:00
If in this case the l-val is a variable (i.e. real) then
the width to pad to will be 0, so this code is harmless. */
Support bool expressions and compares handle them optimally.
2005-09-14 04:53:13 +02:00
if (rv->expr_type() == IVL_VT_REAL) {
} else {
Only pad the width of vector r-values.
2004-06-20 17:59:06 +02:00
unsigned wid = count_lval_width(lv);
rv->set_width(wid);
rv = pad_to_width(rv, wid);
Add parse and elaboration of non-blocking assignments, Replace list<PCase::Item*> with an svector version, Add integer support.
1999-06-06 22:45:38 +02:00
}
Redo handling of assignment internal delays. Leave it possible for them to be calculated at run time.
2002-04-22 00:31:02 +02:00
NetExpr*delay = 0;
Partial non-blocking event control implementation This patch pushes the non-blocking event control information to the code generator. It adds the %evctl statements that are used to put the event control information into the special thread event control registers. The signed version (%evctl/s) required the implementation of %ix/getv/s to load a signed value into an index register. It then adds %assign/wr/e event control based non-blocking assignment for real values. It also fixes the other non-blocking real assignments to use Transport instead of inertial delays.
2008-09-11 04:37:11 +02:00
if (delay_ != 0) {
assert(count_ == 0 && event_ == 0);
Redo handling of assignment internal delays. Leave it possible for them to be calculated at run time.
2002-04-22 00:31:02 +02:00
delay = elaborate_delay_expr(delay_, des, scope);
Partial non-blocking event control implementation This patch pushes the non-blocking event control information to the code generator. It adds the %evctl statements that are used to put the event control information into the special thread event control registers. The signed version (%evctl/s) required the implementation of %ix/getv/s to load a signed value into an index register. It then adds %assign/wr/e event control based non-blocking assignment for real values. It also fixes the other non-blocking real assignments to use Transport instead of inertial delays.
2008-09-11 04:37:11 +02:00
}
Add parse and elaboration of non-blocking assignments, Replace list<PCase::Item*> with an svector version, Add integer support.
1999-06-06 22:45:38 +02:00
Partial non-blocking event control implementation This patch pushes the non-blocking event control information to the code generator. It adds the %evctl statements that are used to put the event control information into the special thread event control registers. The signed version (%evctl/s) required the implementation of %ix/getv/s to load a signed value into an index register. It then adds %assign/wr/e event control based non-blocking assignment for real values. It also fixes the other non-blocking real assignments to use Transport instead of inertial delays.
2008-09-11 04:37:11 +02:00
NetExpr*count = 0;
NetEvWait*event = 0;
Add blocking repeat event control, make repeat sign aware This patch adds blocking repeat event controls and also makes the base repeat statement sign aware. If the argument to repeat is negative (it must be a signed variable) then this is treated just like an argument of 0 (there is no looping). Doing this allows us to model the repeat event control as follows. lhs = repeat(count) @(event) rhs; is translated to: begin temp = rhs; repeat (count) @(event); lhs = temp; end This patch also pushes the non-blocking event control information to the elaboration phase where it will report they are not currently supported.
2008-09-04 01:05:12 +02:00
if (count_ != 0 || event_ != 0) {
if (count_ != 0) {
assert(event_ != 0);
count = elab_and_eval(des, scope, count_, -1);
if (count == 0) {
cerr << get_fileline() << ": Unable to elaborate "
"repeat expression." << endl;
des->errors += 1;
Partial non-blocking event control implementation This patch pushes the non-blocking event control information to the code generator. It adds the %evctl statements that are used to put the event control information into the special thread event control registers. The signed version (%evctl/s) required the implementation of %ix/getv/s to load a signed value into an index register. It then adds %assign/wr/e event control based non-blocking assignment for real values. It also fixes the other non-blocking real assignments to use Transport instead of inertial delays.
2008-09-11 04:37:11 +02:00
return 0;
Add blocking repeat event control, make repeat sign aware This patch adds blocking repeat event controls and also makes the base repeat statement sign aware. If the argument to repeat is negative (it must be a signed variable) then this is treated just like an argument of 0 (there is no looping). Doing this allows us to model the repeat event control as follows. lhs = repeat(count) @(event) rhs; is translated to: begin temp = rhs; repeat (count) @(event); lhs = temp; end This patch also pushes the non-blocking event control information to the elaboration phase where it will report they are not currently supported.
2008-09-04 01:05:12 +02:00
}
}
Partial non-blocking event control implementation This patch pushes the non-blocking event control information to the code generator. It adds the %evctl statements that are used to put the event control information into the special thread event control registers. The signed version (%evctl/s) required the implementation of %ix/getv/s to load a signed value into an index register. It then adds %assign/wr/e event control based non-blocking assignment for real values. It also fixes the other non-blocking real assignments to use Transport instead of inertial delays.
2008-09-11 04:37:11 +02:00
NetProc*st = event_->elaborate(des, scope);
if (st == 0) {
Add blocking repeat event control, make repeat sign aware This patch adds blocking repeat event controls and also makes the base repeat statement sign aware. If the argument to repeat is negative (it must be a signed variable) then this is treated just like an argument of 0 (there is no looping). Doing this allows us to model the repeat event control as follows. lhs = repeat(count) @(event) rhs; is translated to: begin temp = rhs; repeat (count) @(event); lhs = temp; end This patch also pushes the non-blocking event control information to the elaboration phase where it will report they are not currently supported.
2008-09-04 01:05:12 +02:00
cerr << get_fileline() << ": unable to elaborate "
"event expression." << endl;
des->errors += 1;
Partial non-blocking event control implementation This patch pushes the non-blocking event control information to the code generator. It adds the %evctl statements that are used to put the event control information into the special thread event control registers. The signed version (%evctl/s) required the implementation of %ix/getv/s to load a signed value into an index register. It then adds %assign/wr/e event control based non-blocking assignment for real values. It also fixes the other non-blocking real assignments to use Transport instead of inertial delays.
2008-09-11 04:37:11 +02:00
return 0;
}
event = dynamic_cast<NetEvWait*>(st) ;
assert(event);
// Some constant values are special.
if (NetEConst*ce = dynamic_cast<NetEConst*>(count)) {
long val = ce->value().as_long();
// We only need the assignment statement.
if (val <= 0) {
delete count;
delete event;
count = 0;
event = 0;
// We only need the event.
} else if (val == 1) {
delete count;
count = 0;
}
Add blocking repeat event control, make repeat sign aware This patch adds blocking repeat event controls and also makes the base repeat statement sign aware. If the argument to repeat is negative (it must be a signed variable) then this is treated just like an argument of 0 (there is no looping). Doing this allows us to model the repeat event control as follows. lhs = repeat(count) @(event) rhs; is translated to: begin temp = rhs; repeat (count) @(event); lhs = temp; end This patch also pushes the non-blocking event control information to the elaboration phase where it will report they are not currently supported.
2008-09-04 01:05:12 +02:00
}
}
Spelling fixes.
2003-09-13 03:01:51 +02:00
/* All done with this node. Mark its line number and check it in. */
Partial non-blocking event control implementation This patch pushes the non-blocking event control information to the code generator. It adds the %evctl statements that are used to put the event control information into the special thread event control registers. The signed version (%evctl/s) required the implementation of %ix/getv/s to load a signed value into an index register. It then adds %assign/wr/e event control based non-blocking assignment for real values. It also fixes the other non-blocking real assignments to use Transport instead of inertial delays.
2008-09-11 04:37:11 +02:00
NetAssignNB*cur = new NetAssignNB(lv, rv, event, count);
Redo handling of assignment internal delays. Leave it possible for them to be calculated at run time.
2002-04-22 00:31:02 +02:00
cur->set_delay(delay);
Add parse and elaboration of non-blocking assignments, Replace list<PCase::Item*> with an svector version, Add integer support.
1999-06-06 22:45:38 +02:00
cur->set_line(*this);
return cur;
}
Add the LineInfo class to carry the source file location of things. PGate, Statement and PProcess. elaborate handles module parameter mismatches, missing or incorrect lvalues for procedural assignment, and errors are propogated to the top of the elaboration call tree. Attach line numbers to processes, gates and assignment statements.
1999-01-25 06:45:56 +01:00
/*
* This is the elaboration method for a begin-end block. Try to
* elaborate the entire block, even if it fails somewhere. This way I
* get all the error messages out of it. Then, if I detected a failure
* then pass the failure up.
*/
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
NetProc* PBlock::elaborate(Design*des, NetScope*scope) const
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
{
Redesign the implementation of scopes and parameters. I now generate the scopes and notice the parameters in a separate pass over the pform. Once the scopes are generated, I can process overrides and evalutate paremeters before elaboration begins.
2000-03-08 05:36:53 +01:00
assert(scope);
Parse and elaborate named for/join blocks.
1999-09-22 06:30:04 +02:00
NetBlock::Type type = (bl_type_==PBlock::BL_PAR)
? NetBlock::PARA
: NetBlock::SEQU;
Add the LineInfo class to carry the source file location of things. PGate, Statement and PProcess. elaborate handles module parameter mismatches, missing or incorrect lvalues for procedural assignment, and errors are propogated to the top of the elaboration call tree. Attach line numbers to processes, gates and assignment statements.
1999-01-25 06:45:56 +01:00
Support carrying the scope of named begin-end blocks down to the code generator, and have the vvp code generator use that to support disable.
2002-05-27 02:08:45 +02:00
NetScope*nscope = 0;
Objects of lexical scope use PScope base class. All the pform objects that represent lexical scope now are derived from the PScope class, and are kept in a lexical_scope table so that the scope can be managed.
2008-02-16 06:20:24 +01:00
if (pscope_name() != 0) {
nscope = scope->child(hname_t(pscope_name()));
Locate scopes in statements.
2000-03-11 04:25:51 +01:00
if (nscope == 0) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": internal error: "
Properly evaluate scope path expressions.
2007-06-02 05:42:12 +02:00
"unable to find block scope " << scope_path(scope)
Elaborate block scopes burried in generate schemes. Named begin/end blocks burried within generate schemes need to be elaborated. Handle this by remembering to elaborate_scope on the statements within the generate scheme. In the process, clean up/regularize some of the member names and methods.
2008-06-18 06:45:37 +02:00
<< "." << pscope_name() << endl;
Locate scopes in statements.
2000-03-11 04:25:51 +01:00
des->errors += 1;
return 0;
}
Redesign the implementation of scopes and parameters. I now generate the scopes and notice the parameters in a separate pass over the pform. Once the scopes are generated, I can process overrides and evalutate paremeters before elaboration begins.
2000-03-08 05:36:53 +01:00
assert(nscope);
Detect duplicate scopes.
1999-12-15 00:42:16 +01:00
Keep processes in proper lexical scope Normally processes are found in the lexical scope of a module, but there are special cases where processes (other then task/function definitions) are in other lexical scopes. The most likely case is initilizations that are in the lexical scope where the assigned variable is declared. In the process, the behaviors list is kept in the base PScope class instead of the Module or any other derived lexical scope class.
2008-03-04 05:49:52 +01:00
elaborate_behaviors_(des, nscope);
Detect duplicate scopes.
1999-12-15 00:42:16 +01:00
}
Handle expression widths for EEE and NEE operators, add named blocks and scope handling, add registers declared in named blocks.
1999-06-24 06:24:18 +02:00
Support carrying the scope of named begin-end blocks down to the code generator, and have the vvp code generator use that to support disable.
2002-05-27 02:08:45 +02:00
NetBlock*cur = new NetBlock(type, nscope);
if (nscope == 0)
nscope = scope;
Drop degenerate blocks.
1999-06-07 01:07:43 +02:00
// Handle the special case that the block contains only one
Do not elide named blocks.
2002-08-13 07:35:00 +02:00
// statement. There is no need to keep the block node. Also,
// don't elide named blocks, because they might be referenced
// elsewhere.
Objects of lexical scope use PScope base class. All the pform objects that represent lexical scope now are derived from the PScope class, and are kept in a lexical_scope table so that the scope can be managed.
2008-02-16 06:20:24 +01:00
if ((list_.count() == 1) && (pscope_name() == 0)) {
Handle activating tasks in another root.
2001-10-22 04:05:20 +02:00
assert(list_[0]);
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
NetProc*tmp = list_[0]->elaborate(des, nscope);
Drop degenerate blocks.
1999-06-07 01:07:43 +02:00
return tmp;
}
Handle expression widths for EEE and NEE operators, add named blocks and scope handling, add registers declared in named blocks.
1999-06-24 06:24:18 +02:00
for (unsigned idx = 0 ; idx < list_.count() ; idx += 1) {
Handle activating tasks in another root.
2001-10-22 04:05:20 +02:00
assert(list_[idx]);
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
NetProc*tmp = list_[idx]->elaborate(des, nscope);
More generous handling of errors in blocks.
2007-02-01 06:52:24 +01:00
// If the statement fails to elaborate, then simply
// ignore it. Presumably, the elaborate for the
// statement already generated an error message and
// marked the error count in the design so no need to
// do any of that here.
Add the LineInfo class to carry the source file location of things. PGate, Statement and PProcess. elaborate handles module parameter mismatches, missing or incorrect lvalues for procedural assignment, and errors are propogated to the top of the elaboration call tree. Attach line numbers to processes, gates and assignment statements.
1999-01-25 06:45:56 +01:00
if (tmp == 0) {
continue;
}
Do not put noop statements into blocks.
2000-09-30 00:58:57 +02:00
// If the result turns out to be a noop, then skip it.
if (NetBlock*tbl = dynamic_cast<NetBlock*>(tmp))
if (tbl->proc_first() == 0) {
delete tbl;
continue;
}
Add the LineInfo class to carry the source file location of things. PGate, Statement and PProcess. elaborate handles module parameter mismatches, missing or incorrect lvalues for procedural assignment, and errors are propogated to the top of the elaboration call tree. Attach line numbers to processes, gates and assignment statements.
1999-01-25 06:45:56 +01:00
cur->append(tmp);
}
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
return cur;
}
Support case expression lists.
1999-06-15 07:38:39 +02:00
/*
* Elaborate a case statement.
*/
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
NetProc* PCase::elaborate(Design*des, NetScope*scope) const
Parse and elaborate the Verilog CASE statement.
1999-02-03 05:20:11 +01:00
{
Redesign the implementation of scopes and parameters. I now generate the scopes and notice the parameters in a separate pass over the pform. Once the scopes are generated, I can process overrides and evalutate paremeters before elaboration begins.
2000-03-08 05:36:53 +01:00
assert(scope);
Make elaborate_expr methods aware of the width that the context requires of it. In the process, fix sizing of the width of unary minus is context determined sizes.
2006-06-02 06:48:49 +02:00
NetExpr*expr = elab_and_eval(des, scope, expr_, -1);
Add support for the Ternary operator, Add support for repeat concatenation, Correct some seg faults cause by elaboration errors, Parse the casex anc casez statements.
1999-06-10 06:03:52 +02:00
if (expr == 0) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: Unable to elaborate this case"
Add support for the Ternary operator, Add support for repeat concatenation, Correct some seg faults cause by elaboration errors, Parse the casex anc casez statements.
1999-06-10 06:03:52 +02:00
" expression." << endl;
return 0;
}
Spelling fixes.
2003-01-27 06:09:17 +01:00
/* Count the items in the case statement. Note that there may
Agressively evalutate case expressions.
2002-04-24 19:40:48 +02:00
be some cases that have multiple guards. Count each as a
separate item. */
Support case expression lists.
1999-06-15 07:38:39 +02:00
unsigned icount = 0;
for (unsigned idx = 0 ; idx < items_->count() ; idx += 1) {
PCase::Item*cur = (*items_)[idx];
if (cur->expr.count() == 0)
icount += 1;
else
icount += cur->expr.count();
}
Full case support
1999-09-29 20:36:02 +02:00
NetCase*res = new NetCase(type_, expr, icount);
res->set_line(*this);
Parse and elaborate the Verilog CASE statement.
1999-02-03 05:20:11 +01:00
Evaluate case guards, if possible.
2002-01-19 21:09:56 +01:00
/* Iterate over all the case items (guard/statement pairs)
elaborating them. If the guard has no expression, then this
is a "default" cause. Otherwise, the guard has one or more
expressions, and each guard is a case. */
Support case expression lists.
1999-06-15 07:38:39 +02:00
unsigned inum = 0;
Add parse and elaboration of non-blocking assignments, Replace list<PCase::Item*> with an svector version, Add integer support.
1999-06-06 22:45:38 +02:00
for (unsigned idx = 0 ; idx < items_->count() ; idx += 1) {
Parse and elaborate the Verilog CASE statement.
1999-02-03 05:20:11 +01:00
Support case expression lists.
1999-06-15 07:38:39 +02:00
assert(inum < icount);
PCase::Item*cur = (*items_)[idx];
Parse and elaborate the Verilog CASE statement.
1999-02-03 05:20:11 +01:00
Support case expression lists.
1999-06-15 07:38:39 +02:00
if (cur->expr.count() == 0) {
/* If there are no expressions, then this is the
default case. */
NetProc*st = 0;
if (cur->stat)
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
st = cur->stat->elaborate(des, scope);
Support case expression lists.
1999-06-15 07:38:39 +02:00
res->set_case(inum, 0, st);
inum += 1;
} else for (unsigned e = 0; e < cur->expr.count(); e += 1) {
/* If there are one or more expressions, then
iterate over the guard expressions, elaborating
a separate case for each. (Yes, the statement
will be elaborated again for each.) */
NetExpr*gu = 0;
NetProc*st = 0;
assert(cur->expr[e]);
Make elaborate_expr methods aware of the width that the context requires of it. In the process, fix sizing of the width of unary minus is context determined sizes.
2006-06-02 06:48:49 +02:00
gu = elab_and_eval(des, scope, cur->expr[e], -1);
Evaluate case guards, if possible.
2002-01-19 21:09:56 +01:00
Support case expression lists.
1999-06-15 07:38:39 +02:00
if (cur->stat)
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
st = cur->stat->elaborate(des, scope);
Support case expression lists.
1999-06-15 07:38:39 +02:00
res->set_case(inum, gu, st);
inum += 1;
}
Parse and elaborate the Verilog CASE statement.
1999-02-03 05:20:11 +01:00
}
return res;
}
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
NetProc* PCondit::elaborate(Design*des, NetScope*scope) const
Handle procedural conditional, and some of the conditional expressions. Elaborate signals and identifiers differently, allowing the netlist to hold signal information.
1998-11-07 18:05:05 +01:00
{
Redesign the implementation of scopes and parameters. I now generate the scopes and notice the parameters in a separate pass over the pform. Once the scopes are generated, I can process overrides and evalutate paremeters before elaboration begins.
2000-03-08 05:36:53 +01:00
assert(scope);
Evaluate parameter expressions losslessly Make sure parameter expressions are evaluated losslessly, as if the l-value is unsigned and thus virtually infinite.
2007-06-28 07:05:36 +02:00
if (debug_elaborate)
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": debug: Elaborate condition statement"
Evaluate parameter expressions losslessly Make sure parameter expressions are evaluated losslessly, as if the l-value is unsigned and thus virtually infinite.
2007-06-28 07:05:36 +02:00
<< " with conditional: " << *expr_ << endl;
Compile time evalutation of constant expressions.
1999-06-03 07:16:25 +02:00
// Elaborate and try to evaluate the conditional expression.
Make elaborate_expr methods aware of the width that the context requires of it. In the process, fix sizing of the width of unary minus is context determined sizes.
2006-06-02 06:48:49 +02:00
NetExpr*expr = elab_and_eval(des, scope, expr_, -1);
Add support for the Ternary operator, Add support for repeat concatenation, Correct some seg faults cause by elaboration errors, Parse the casex anc casez statements.
1999-06-10 06:03:52 +02:00
if (expr == 0) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: Unable to elaborate"
Add support for the Ternary operator, Add support for repeat concatenation, Correct some seg faults cause by elaboration errors, Parse the casex anc casez statements.
1999-06-10 06:03:52 +02:00
" condition expression." << endl;
des->errors += 1;
return 0;
}
Compile time evalutation of constant expressions.
1999-06-03 07:16:25 +02:00
// If the condition of the conditional statement is constant,
// then look at the value and elaborate either the if statement
// or the else statement. I don't need both. If there is no
// else_ statement, the use an empty block as a noop.
if (NetEConst*ce = dynamic_cast<NetEConst*>(expr)) {
verinum val = ce->value();
Debug messages.
2005-06-17 07:06:47 +02:00
if (debug_elaborate) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": debug: Condition expression "
Debug messages.
2005-06-17 07:06:47 +02:00
<< "is a constant " << val << "." << endl;
}
Fix compile time eval of condition expresion to do reduction OR of vectors.
2006-11-26 08:10:30 +01:00
verinum::V reduced = verinum::V0;
for (unsigned idx = 0 ; idx < val.len() ; idx += 1)
reduced = reduced | val[idx];
Compile time evalutation of constant expressions.
1999-06-03 07:16:25 +02:00
delete expr;
Fix compile time eval of condition expresion to do reduction OR of vectors.
2006-11-26 08:10:30 +01:00
if (reduced == verinum::V1)
Fix crash handling constant true conditional.
2006-11-27 03:01:07 +01:00
if (if_) {
return if_->elaborate(des, scope);
} else {
NetBlock*tmp = new NetBlock(NetBlock::SEQU, 0);
tmp->set_line(*this);
return tmp;
}
Compile time evalutation of constant expressions.
1999-06-03 07:16:25 +02:00
else if (else_)
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
return else_->elaborate(des, scope);
Compile time evalutation of constant expressions.
1999-06-03 07:16:25 +02:00
else
Support carrying the scope of named begin-end blocks down to the code generator, and have the vvp code generator use that to support disable.
2002-05-27 02:08:45 +02:00
return new NetBlock(NetBlock::SEQU, 0);
Compile time evalutation of constant expressions.
1999-06-03 07:16:25 +02:00
}
Handle expression widths for EEE and NEE operators, add named blocks and scope handling, add registers declared in named blocks.
1999-06-24 06:24:18 +02:00
Spelling fixes from Larry
2007-03-22 17:08:14 +01:00
// If the condition expression is more than 1 bits, then
Handle implicit !=0 in if statements.
1999-09-16 02:33:45 +02:00
// generate a comparison operator to get the result down to
// one bit. Turn <e> into <e> != 0;
Add support for reduction NOR.
1999-10-05 08:19:46 +02:00
if (expr->expr_width() < 1) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": internal error: "
Add support for reduction NOR.
1999-10-05 08:19:46 +02:00
"incomprehensible expression width (0)." << endl;
return 0;
}
The inputs to logical and/or are condition expressions. Logical and/or take as inputs condition expressions, which are scalar expressions. Be sure to reduce vectors using proper logic to get the right condition value.
2008-04-23 06:03:18 +02:00
// Make sure the condition expression evaluates to a condition.
expr = condition_reduce(expr);
Handle expression widths for EEE and NEE operators, add named blocks and scope handling, add registers declared in named blocks.
1999-06-24 06:24:18 +02:00
Compile time evalutation of constant expressions.
1999-06-03 07:16:25 +02:00
// Well, I actually need to generate code to handle the
// conditional, so elaborate.
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
NetProc*i = if_? if_->elaborate(des, scope) : 0;
NetProc*e = else_? else_->elaborate(des, scope) : 0;
Handle procedural conditional, and some of the conditional expressions. Elaborate signals and identifiers differently, allowing the netlist to hold signal information.
1998-11-07 18:05:05 +01:00
Elide empty begin-end in conditionals.
2003-07-02 06:19:16 +02:00
// Detect the special cases that the if or else statements are
// empty blocks. If this is the case, remove the blocks as
// null statements.
if (NetBlock*tmp = dynamic_cast<NetBlock*>(i)) {
if (tmp->proc_first() == 0) {
delete i;
i = 0;
}
}
if (NetBlock*tmp = dynamic_cast<NetBlock*>(e)) {
if (tmp->proc_first() == 0) {
delete e;
e = 0;
}
}
Handle procedural conditional, and some of the conditional expressions. Elaborate signals and identifiers differently, allowing the netlist to hold signal information.
1998-11-07 18:05:05 +01:00
NetCondit*res = new NetCondit(expr, i, e);
Mark the line numbers of NetCondit nodes.
2000-02-14 01:11:11 +01:00
res->set_line(*this);
Handle procedural conditional, and some of the conditional expressions. Elaborate signals and identifiers differently, allowing the netlist to hold signal information.
1998-11-07 18:05:05 +01:00
return res;
}
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
NetProc* PCallTask::elaborate(Design*des, NetScope*scope) const
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
{
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
if (peek_tail_name(path_)[0] == '$')
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
return elaborate_sys(des, scope);
Elaborate user defined tasks.
1999-07-03 04:12:51 +02:00
else
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
return elaborate_usr(des, scope);
Elaborate user defined tasks.
1999-07-03 04:12:51 +02:00
}
/*
* A call to a system task involves elaborating all the parameters,
* then passing the list to the NetSTask object.
Create the vpiMemory handle type.
1999-11-10 03:52:24 +01:00
*XXXX
Handle special case of empty system task argument list.
2002-08-15 04:11:54 +02:00
* There is a single special case in the call to a system
* task. Normally, an expression cannot take an unindexed
* memory. However, it is possible to take a system task parameter a
* memory if the expression is trivial.
Elaborate user defined tasks.
1999-07-03 04:12:51 +02:00
*/
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
NetProc* PCallTask::elaborate_sys(Design*des, NetScope*scope) const
Elaborate user defined tasks.
1999-07-03 04:12:51 +02:00
{
Redesign the implementation of scopes and parameters. I now generate the scopes and notice the parameters in a separate pass over the pform. Once the scopes are generated, I can process overrides and evalutate paremeters before elaboration begins.
2000-03-08 05:36:53 +01:00
assert(scope);
Handle special case of empty system task argument list.
2002-08-15 04:11:54 +02:00
unsigned parm_count = nparms();
Elaborate user defined tasks.
1999-07-03 04:12:51 +02:00
Handle special case of empty system task argument list.
2002-08-15 04:11:54 +02:00
/* Catch the special case that the system task has no
parameters. The "()" string will be parsed as a single
empty parameter, when we really mean no parameters at all. */
if ((nparms() == 1) && (parm(0) == 0))
parm_count = 0;
svector<NetExpr*>eparms (parm_count);
Create the vpiMemory handle type.
1999-11-10 03:52:24 +01:00
Handle special case of empty system task argument list.
2002-08-15 04:11:54 +02:00
for (unsigned idx = 0 ; idx < parm_count ; idx += 1) {
PExpr*ex = parm(idx);
Make elaborate_expr methods aware of the width that the context requires of it. In the process, fix sizing of the width of unary minus is context determined sizes.
2006-06-02 06:48:49 +02:00
eparms[idx] = ex? ex->elaborate_expr(des, scope, -1, true) : 0;
precalculate r-values of nb assignments and task arguments.
2002-12-05 05:15:14 +01:00
/* Attempt to pre-evaluate the parameters. It may be
possible to at least partially reduce the
expression. */
Major rework of the ternary operator elaboration code. This patch reworks much of the ternary code to short circuit when possible and supports real values better. It adds a blend operator for real values that returns 0.0 when the values differ and the value when they match. This deviates slightly from the standard which specifies that the value for reals is always 0.0 when the conditional is 'bx. There are also a couple bug fixes. These fixes have not been ported to continuous assignments yet. Ternary operators used at compile time and in procedural assignments should be complete (short circuit and support real values).
2008-03-08 03:51:50 +01:00
if (eparms[idx]) eval_expr(eparms[idx]);
Elaborate user defined tasks.
1999-07-03 04:12:51 +02:00
}
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
NetSTask*cur = new NetSTask(peek_tail_name(path_), eparms);
Make statement file lineno available to targets. Make the Verilog file/lineno of statements available to loadable code generators. Make sure the information is properly set for system task calls.
2007-12-22 15:31:24 +01:00
cur->set_line(*this);
Elaborate user defined tasks.
1999-07-03 04:12:51 +02:00
return cur;
}
Elaborate task input ports.
1999-07-24 04:11:19 +02:00
/*
* A call to a user defined task is different from a call to a system
* task because a user task in a netlist has no parameters: the
* assignments are done by the calling thread. For example:
*
* task foo;
* input a;
* output b;
* [...]
* endtask;
*
* [...] foo(x, y);
*
* is really:
*
* task foo;
* reg a;
* reg b;
* [...]
* endtask;
*
* [...]
* begin
* a = x;
* foo;
* y = b;
* end
*/
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
NetProc* PCallTask::elaborate_usr(Design*des, NetScope*scope) const
Elaborate user defined tasks.
1999-07-03 04:12:51 +02:00
{
Redesign the implementation of scopes and parameters. I now generate the scopes and notice the parameters in a separate pass over the pform. Once the scopes are generated, I can process overrides and evalutate paremeters before elaboration begins.
2000-03-08 05:36:53 +01:00
assert(scope);
Check that functions do not call invalid statements. This patch adds checks to verify that functions do not invoke statements that are invalid for them (#, @, wait, enable/call tasks and non blocking assignment). For reference see section 10.3.4 of 1364-2001.
2007-08-25 03:48:24 +02:00
if (scope->in_func()) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: functions cannot enable/call "
Check that functions do not call invalid statements. This patch adds checks to verify that functions do not invoke statements that are invalid for them (#, @, wait, enable/call tasks and non blocking assignment). For reference see section 10.3.4 of 1364-2001.
2007-08-25 03:48:24 +02:00
"tasks." << endl;
des->errors += 1;
return 0;
}
Parser and pform use hierarchical names as hname_t objects instead of encoded strings.
2001-12-03 05:47:14 +01:00
NetScope*task = des->find_task(scope, path_);
Detect a missing task definition before it crashes me.
2001-07-29 00:13:11 +02:00
if (task == 0) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: Enable of unknown task "
Parser and pform use hierarchical names as hname_t objects instead of encoded strings.
2001-12-03 05:47:14 +01:00
<< "``" << path_ << "''." << endl;
Elaborate user defined tasks.
1999-07-03 04:12:51 +02:00
des->errors += 1;
return 0;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
Detect a missing task definition before it crashes me.
2001-07-29 00:13:11 +02:00
assert(task);
Handle activating tasks in another root.
2001-10-22 04:05:20 +02:00
assert(task->type() == NetScope::TASK);
Detect a missing task definition before it crashes me.
2001-07-29 00:13:11 +02:00
NetTaskDef*def = task->task_def();
Handle activating tasks in another root.
2001-10-22 04:05:20 +02:00
if (def == 0) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": internal error: task " << path_
Properly evaluate scope path expressions.
2007-06-02 05:42:12 +02:00
<< " doesn't have a definition in " << scope_path(scope)
Handle activating tasks in another root.
2001-10-22 04:05:20 +02:00
<< "." << endl;
des->errors += 1;
return 0;
}
assert(def);
Detect a missing task definition before it crashes me.
2001-07-29 00:13:11 +02:00
Elaborate task input ports.
1999-07-24 04:11:19 +02:00
if (nparms() != def->port_count()) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: Port count mismatch in call to ``"
Improve port mismatch error message.
2007-04-02 01:01:10 +02:00
<< path_ << "''. Got " << nparms()
<< " ports, expecting " << def->port_count() << " ports." << endl;
Elaborate task input ports.
1999-07-24 04:11:19 +02:00
des->errors += 1;
return 0;
}
NetUTask*cur;
/* Handle tasks with no parameters specially. There is no need
to make a sequential block to hold the generated code. */
if (nparms() == 0) {
Generate code for task calls.
2001-04-02 04:28:12 +02:00
cur = new NetUTask(task);
Attach line number information to task calls.
2007-04-15 22:45:40 +02:00
cur->set_line(*this);
Elaborate task input ports.
1999-07-24 04:11:19 +02:00
return cur;
}
Support carrying the scope of named begin-end blocks down to the code generator, and have the vvp code generator use that to support disable.
2002-05-27 02:08:45 +02:00
NetBlock*block = new NetBlock(NetBlock::SEQU, 0);
Elaborate task input ports.
1999-07-24 04:11:19 +02:00
Catch memory word parameters to tasks.
2000-04-28 18:50:53 +02:00
Overly aggressive eliding of task calls.
2000-04-29 01:12:12 +02:00
/* Detect the case where the definition of the task is known
Skip empty tasks.
2000-04-29 00:17:47 +02:00
empty. In this case, we need not bother with calls to the
task, all the assignments, etc. Just return a no-op. */
if (const NetBlock*tp = dynamic_cast<const NetBlock*>(def->proc())) {
if (tp->proc_first() == 0)
return block;
}
Support for automatic tasks and functions. This patch adds support for automatic tasks and functions. Refer to the overview in vvp/README.txt for details.
2008-09-27 01:54:13 +02:00
/* If this is an automatic task, generate a statement to
allocate the local storage. */
if (task->is_auto()) {
NetAlloc*ap = new NetAlloc(task);
block->append(ap);
}
Elaborate task input ports.
1999-07-24 04:11:19 +02:00
/* Generate assignment statement statements for the input and
Add support for task output and inout ports.
1999-07-24 21:19:06 +02:00
INOUT ports of the task. These are managed by writing
assignments with the task port the l-value and the passed
Catch memory word parameters to tasks.
2000-04-28 18:50:53 +02:00
expression the r-value. We know by definition that the port
is a reg type, so this elaboration is pretty obvious. */
Elaborate task input ports.
1999-07-24 04:11:19 +02:00
for (unsigned idx = 0 ; idx < nparms() ; idx += 1) {
NetNet*port = def->port(idx);
assert(port->port_type() != NetNet::NOT_A_PORT);
if (port->port_type() == NetNet::POUTPUT)
continue;
Change the NetAssign_ class to refer to the signal instead of link into the netlist. This is faster and uses less space. Make the NetAssignNB carry the delays instead of the NetAssign_ lval objects. Change the vvp code generator to support multiple l-values, i.e. concatenations of part selects.
2001-08-26 01:50:02 +02:00
NetAssign_*lv = new NetAssign_(port);
Get rval width right for arguments into task calls.
2005-03-05 06:38:33 +01:00
unsigned wid = count_lval_width(lv);
Make elaborate_expr methods aware of the width that the context requires of it. In the process, fix sizing of the width of unary minus is context determined sizes.
2006-06-02 06:48:49 +02:00
NetExpr*rv = elab_and_eval(des, scope, parms_[idx], wid);
Get rval width right for arguments into task calls.
2005-03-05 06:38:33 +01:00
rv->set_width(wid);
rv = pad_to_width(rv, wid);
Pull NetAssign_ creation out of constructors.
2000-09-03 01:40:12 +02:00
NetAssign*pr = new NetAssign(lv, rv);
Elaborate task input ports.
1999-07-24 04:11:19 +02:00
block->append(pr);
}
/* Generate the task call proper... */
Generate code for task calls.
2001-04-02 04:28:12 +02:00
cur = new NetUTask(task);
Attach line number information to task calls.
2007-04-15 22:45:40 +02:00
cur->set_line(*this);
Elaborate task input ports.
1999-07-24 04:11:19 +02:00
block->append(cur);
Catch memory word parameters to tasks.
2000-04-28 18:50:53 +02:00
/* Generate assignment statements for the output and INOUT
ports of the task. The l-value in this case is the
Match bit widths comming out of task output ports.
1999-09-19 00:23:50 +02:00
expression passed as a parameter, and the r-value is the
Catch memory word parameters to tasks.
2000-04-28 18:50:53 +02:00
port to be copied out.
We know by definition that the r-value of this copy-out is
the port, which is a reg. The l-value, however, may be any
expression that can be a target to a procedural
assignment, including a memory word. */
Elaborate task input ports.
1999-07-24 04:11:19 +02:00
for (unsigned idx = 0 ; idx < nparms() ; idx += 1) {
NetNet*port = def->port(idx);
Catch memory word parameters to tasks.
2000-04-28 18:50:53 +02:00
/* Skip input ports. */
Elaborate task input ports.
1999-07-24 04:11:19 +02:00
assert(port->port_type() != NetNet::NOT_A_PORT);
if (port->port_type() == NetNet::PINPUT)
continue;
Catch memory word parameters to tasks.
2000-04-28 18:50:53 +02:00
Constant expressions are not l-values for task ports.
2002-03-09 05:02:26 +01:00
/* Elaborate an l-value version of the port expression
for output and inout ports. If the expression does
not exist then quietly skip it, but if the expression
is not a valid l-value print an error message. Note
that the elaborate_lval method already printed a
detailed message. */
NetAssign_*lv;
if (parms_[idx]) {
Unify elaboration of l-values for all proceedural assignments, including assing, cassign and force. Generate NetConcat devices for gate outputs that feed into a vector results. Use this to hande gate arrays. Also let gate arrays handle vectors of gates when the outputs allow for it.
2004-12-30 00:55:43 +01:00
lv = parms_[idx]->elaborate_lval(des, scope, false);
Constant expressions are not l-values for task ports.
2002-03-09 05:02:26 +01:00
if (lv == 0) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << parms_[idx]->get_fileline() << ": error: "
Constant expressions are not l-values for task ports.
2002-03-09 05:02:26 +01:00
<< "I give up on task port " << (idx+1)
<< " expression: " << *parms_[idx] << endl;
}
} else {
lv = 0;
}
Build task outputs as lval instead of nets. (PR#98)
2001-01-10 04:13:23 +01:00
if (lv == 0)
continue;
Add support for task output and inout ports.
1999-07-24 21:19:06 +02:00
NetESignal*sig = new NetESignal(port);
Parameters cannot have their width changed.
2005-05-17 22:56:55 +02:00
NetExpr*rv = pad_to_width(sig, count_lval_width(lv));
Add support for task output and inout ports.
1999-07-24 21:19:06 +02:00
/* Generate the assignment statement. */
Parameters cannot have their width changed.
2005-05-17 22:56:55 +02:00
NetAssign*ass = new NetAssign(lv, rv);
Add support for task output and inout ports.
1999-07-24 21:19:06 +02:00
block->append(ass);
Elaborate task input ports.
1999-07-24 04:11:19 +02:00
}
Support for automatic tasks and functions. This patch adds support for automatic tasks and functions. Refer to the overview in vvp/README.txt for details.
2008-09-27 01:54:13 +02:00
/* If this is an automatic task, generate a statement to free
the local storage. */
if (task->is_auto()) {
NetFree*fp = new NetFree(task);
block->append(fp);
}
Elaborate task input ports.
1999-07-24 04:11:19 +02:00
return block;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
Rework of internals to carry vectors through nexus instead of single bits. Make the ivl, tgt-vvp and vvp initial changes down this path.
2004-12-11 03:31:25 +01:00
/*
Fix r-value width of continuous assign.
2004-12-12 19:13:39 +01:00
* Elaborate a procedural continuous assign. This really looks very
* much like other procedural assignments, at this point, but there
Rework of internals to carry vectors through nexus instead of single bits. Make the ivl, tgt-vvp and vvp initial changes down this path.
2004-12-11 03:31:25 +01:00
* is no delay to worry about. The code generator will take care of
* the differences between continuous assign and normal assignments.
*/
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
NetCAssign* PCAssign::elaborate(Design*des, NetScope*scope) const
Add support for procedural continuous assignment.
2000-05-12 01:37:26 +02:00
{
Rework of internals to carry vectors through nexus instead of single bits. Make the ivl, tgt-vvp and vvp initial changes down this path.
2004-12-11 03:31:25 +01:00
NetCAssign*dev = 0;
Add support for procedural continuous assignment.
2000-05-12 01:37:26 +02:00
assert(scope);
Unify elaboration of l-values for all proceedural assignments, including assing, cassign and force. Generate NetConcat devices for gate outputs that feed into a vector results. Use this to hande gate arrays. Also let gate arrays handle vectors of gates when the outputs allow for it.
2004-12-30 00:55:43 +01:00
NetAssign_*lval = lval_->elaborate_lval(des, scope, false);
Add support for procedural continuous assignment.
2000-05-12 01:37:26 +02:00
if (lval == 0)
return 0;
Make elaborate_expr methods aware of the width that the context requires of it. In the process, fix sizing of the width of unary minus is context determined sizes.
2006-06-02 06:48:49 +02:00
unsigned lwid = count_lval_width(lval);
NetExpr*rexp = elab_and_eval(des, scope, expr_, lwid);
Rework of internals to carry vectors through nexus instead of single bits. Make the ivl, tgt-vvp and vvp initial changes down this path.
2004-12-11 03:31:25 +01:00
if (rexp == 0)
Add support for procedural continuous assignment.
2000-05-12 01:37:26 +02:00
return 0;
Fix r-value width of continuous assign.
2004-12-12 19:13:39 +01:00
rexp->set_width(lwid);
rexp = pad_to_width(rexp, lwid);
Rework of internals to carry vectors through nexus instead of single bits. Make the ivl, tgt-vvp and vvp initial changes down this path.
2004-12-11 03:31:25 +01:00
dev = new NetCAssign(lval, rexp);
Add support for procedural continuous assignment.
2000-05-12 01:37:26 +02:00
Rework of internals to carry vectors through nexus instead of single bits. Make the ivl, tgt-vvp and vvp initial changes down this path.
2004-12-11 03:31:25 +01:00
if (debug_elaborate) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": debug: Elaborate cassign,"
Fix r-value width of continuous assign.
2004-12-12 19:13:39 +01:00
<< " lval width=" << lwid
Rework of internals to carry vectors through nexus instead of single bits. Make the ivl, tgt-vvp and vvp initial changes down this path.
2004-12-11 03:31:25 +01:00
<< " rval width=" << rexp->expr_width()
<< " rval=" << *rexp
<< endl;
}
Add support for procedural continuous assignment.
2000-05-12 01:37:26 +02:00
Rework of internals to carry vectors through nexus instead of single bits. Make the ivl, tgt-vvp and vvp initial changes down this path.
2004-12-11 03:31:25 +01:00
dev->set_line(*this);
Add support for procedural continuous assignment.
2000-05-12 01:37:26 +02:00
return dev;
}
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
NetDeassign* PDeassign::elaborate(Design*des, NetScope*scope) const
Add support for procedural continuous assignment.
2000-05-12 01:37:26 +02:00
{
assert(scope);
Unify elaboration of l-values for all proceedural assignments, including assing, cassign and force. Generate NetConcat devices for gate outputs that feed into a vector results. Use this to hande gate arrays. Also let gate arrays handle vectors of gates when the outputs allow for it.
2004-12-30 00:55:43 +01:00
NetAssign_*lval = lval_->elaborate_lval(des, scope, false);
Add support for procedural continuous assignment.
2000-05-12 01:37:26 +02:00
if (lval == 0)
return 0;
NetDeassign*dev = new NetDeassign(lval);
dev->set_line( *this );
return dev;
}
Add support for non-constant delays in delay statements, Support evaluating ! in constant expressions, and move some code from netlist.cc to net_proc.cc.
2000-07-07 06:53:53 +02:00
/*
Spelling fixes.
2003-01-27 06:09:17 +01:00
* Elaborate the delay statement (of the form #<expr> <statement>) as a
Add support for non-constant delays in delay statements, Support evaluating ! in constant expressions, and move some code from netlist.cc to net_proc.cc.
2000-07-07 06:53:53 +02:00
* NetPDelay object. If the expression is constant, evaluate it now
* and make a constant delay. If not, then pass an elaborated
* expression to the constructor of NetPDelay so that the code
* generator knows to evaluate the expression at run time.
*/
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
NetProc* PDelayStatement::elaborate(Design*des, NetScope*scope) const
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
{
Add support for non-constant delays in delay statements, Support evaluating ! in constant expressions, and move some code from netlist.cc to net_proc.cc.
2000-07-07 06:53:53 +02:00
assert(scope);
Check that functions do not call invalid statements. This patch adds checks to verify that functions do not invoke statements that are invalid for them (#, @, wait, enable/call tasks and non blocking assignment). For reference see section 10.3.4 of 1364-2001.
2007-08-25 03:48:24 +02:00
if (scope->in_func()) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: functions cannot have "
Check that functions do not call invalid statements. This patch adds checks to verify that functions do not invoke statements that are invalid for them (#, @, wait, enable/call tasks and non blocking assignment). For reference see section 10.3.4 of 1364-2001.
2007-08-25 03:48:24 +02:00
"delay statements." << endl;
des->errors += 1;
return 0;
}
Calculate delay statement delays using elaborated expressions instead of pre-elaborated expression trees. Remove the eval_pexpr methods from PExpr.
2003-02-08 20:49:21 +01:00
/* This call evaluates the delay expression to a NetEConst, if
possible. This includes transforming NetECReal values to
integers, and applying the proper scaling. */
NetExpr*dex = elaborate_delay_expr(delay_, des, scope);
Generalize the evaluation of floating point delays, and get it working with delay assignment statements. Allow parameters to be referenced by hierarchical name.
2001-01-15 00:04:55 +01:00
Calculate delay statement delays using elaborated expressions instead of pre-elaborated expression trees. Remove the eval_pexpr methods from PExpr.
2003-02-08 20:49:21 +01:00
if (NetEConst*tmp = dynamic_cast<NetEConst*>(dex)) {
Support decimal constants in behavioral delays.
2000-12-10 23:01:35 +01:00
if (statement_)
Handle 64bit delay constants.
2006-08-08 07:11:37 +02:00
return new NetPDelay(tmp->value().as_ulong64(),
Calculate delay statement delays using elaborated expressions instead of pre-elaborated expression trees. Remove the eval_pexpr methods from PExpr.
2003-02-08 20:49:21 +01:00
statement_->elaborate(des, scope));
Support decimal constants in behavioral delays.
2000-12-10 23:01:35 +01:00
else
Calculate delay statement delays using elaborated expressions instead of pre-elaborated expression trees. Remove the eval_pexpr methods from PExpr.
2003-02-08 20:49:21 +01:00
return new NetPDelay(tmp->value().as_ulong(), 0);
Support decimal constants in behavioral delays.
2000-12-10 23:01:35 +01:00
Calculate delay statement delays using elaborated expressions instead of pre-elaborated expression trees. Remove the eval_pexpr methods from PExpr.
2003-02-08 20:49:21 +01:00
delete dex;
Account for local units in calculated delays.
2002-12-21 20:42:17 +01:00
Calculate delay statement delays using elaborated expressions instead of pre-elaborated expression trees. Remove the eval_pexpr methods from PExpr.
2003-02-08 20:49:21 +01:00
} else {
Add support for non-constant delays in delay statements, Support evaluating ! in constant expressions, and move some code from netlist.cc to net_proc.cc.
2000-07-07 06:53:53 +02:00
if (statement_)
Calculate delay statement delays using elaborated expressions instead of pre-elaborated expression trees. Remove the eval_pexpr methods from PExpr.
2003-02-08 20:49:21 +01:00
return new NetPDelay(dex, statement_->elaborate(des, scope));
Add support for non-constant delays in delay statements, Support evaluating ! in constant expressions, and move some code from netlist.cc to net_proc.cc.
2000-07-07 06:53:53 +02:00
else
Calculate delay statement delays using elaborated expressions instead of pre-elaborated expression trees. Remove the eval_pexpr methods from PExpr.
2003-02-08 20:49:21 +01:00
return new NetPDelay(dex, 0);
catch non-constant delays as unsupported.
1999-09-30 19:22:33 +02:00
}
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
Parse disable statements to pform.
2000-07-26 07:08:07 +02:00
/*
* The disable statement is not yet supported.
*/
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
NetProc* PDisable::elaborate(Design*des, NetScope*scope) const
Parse disable statements to pform.
2000-07-26 07:08:07 +02:00
{
Support elaboration of disable statements.
2000-07-27 07:13:44 +02:00
assert(scope);
Properly evaluate scope path expressions.
2007-06-02 05:42:12 +02:00
list<hname_t> spath = eval_scope_path(des, scope, scope_);
NetScope*target = des->find_scope(scope, spath);
Support elaboration of disable statements.
2000-07-27 07:13:44 +02:00
if (target == 0) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: Cannot find scope "
Properly evaluate scope path expressions.
2007-06-02 05:42:12 +02:00
<< scope_ << " in " << scope_path(scope) << endl;
Support elaboration of disable statements.
2000-07-27 07:13:44 +02:00
des->errors += 1;
return 0;
}
switch (target->type()) {
case NetScope::FUNC:
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: Cannot disable functions." << endl;
Support elaboration of disable statements.
2000-07-27 07:13:44 +02:00
des->errors += 1;
return 0;
case NetScope::MODULE:
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: Cannot disable modules." << endl;
Support elaboration of disable statements.
2000-07-27 07:13:44 +02:00
des->errors += 1;
return 0;
default:
break;
}
NetDisable*obj = new NetDisable(target);
obj->set_line(*this);
return obj;
Parse disable statements to pform.
2000-07-26 07:08:07 +02:00
}
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
/*
All events now use the NetEvent class.
2000-04-10 07:26:05 +02:00
* An event statement is an event delay of some sort, attached to a
* statement. Some Verilog examples are:
*
* @(posedge CLK) $display("clock rise");
* @event_1 $display("event triggered.");
* @(data or negedge clk) $display("data or clock fall.");
*
* The elaborated netlist uses the NetEvent, NetEvWait and NetEvProbe
* classes. The NetEvWait class represents the part of the netlist
* that is executed by behavioral code. The process starts waiting on
* the NetEvent when it executes the NetEvWait step. Net NetEvProbe
Spelling fixes.
2003-01-27 06:09:17 +01:00
* and NetEvTrig are structural and behavioral equivalents that
All events now use the NetEvent class.
2000-04-10 07:26:05 +02:00
* trigger the event, and awakens any processes blocking in the
* associated wait.
*
* The basic data structure is:
Carry some line info to the netlist, Dump line numbers for processes. Elaborate prints errors about port vector width mismatch Emit better handles null statements.
1999-02-01 01:26:48 +01:00
*
All events now use the NetEvent class.
2000-04-10 07:26:05 +02:00
* NetEvWait ---/---> NetEvent <----\---- NetEvProbe
* ... | | ...
Named events really should be expressed with PEIdent objects in the pform, Handle named events within the mix of net events and edges. As a unified lot they get caught together. wait statements are broken into more complex statements that include a conditional. Do not generate NetPEvent or NetNEvent objects in elaboration. NetEvent, NetEvWait and NetEvProbe take over those functions in the netlist.
2000-04-12 06:23:57 +02:00
* NetEvWait ---+ +---- NetEvProbe
* | ...
* +---- NetEvTrig
All events now use the NetEvent class.
2000-04-10 07:26:05 +02:00
*
* That is, many NetEvWait statements may wait on a single NetEvent
* object, and Many NetEvProbe objects may trigger the NetEvent
Named events really should be expressed with PEIdent objects in the pform, Handle named events within the mix of net events and edges. As a unified lot they get caught together. wait statements are broken into more complex statements that include a conditional. Do not generate NetPEvent or NetNEvent objects in elaboration. NetEvent, NetEvWait and NetEvProbe take over those functions in the netlist.
2000-04-12 06:23:57 +02:00
* object. The many NetEvWait objects pointing to the NetEvent object
* reflects the possibility of different places in the code blocking
* on the same named event, like so:
*
* event foo;
* [...]
* always begin @foo <statement1>; @foo <statement2> end
*
* This tends to not happen with signal edges. The multiple probes
* pointing to the same event reflect the possibility of many
* expressions in the same blocking statement, like so:
*
* wire reset, clk;
* [...]
* always @(reset or posedge clk) <stmt>;
*
* Conjunctions like this cause a NetEvent object be created to
Spelling fixes.
2003-01-27 06:09:17 +01:00
* represent the overall conjunction, and NetEvProbe objects for each
Named events really should be expressed with PEIdent objects in the pform, Handle named events within the mix of net events and edges. As a unified lot they get caught together. wait statements are broken into more complex statements that include a conditional. Do not generate NetPEvent or NetNEvent objects in elaboration. NetEvent, NetEvWait and NetEvProbe take over those functions in the netlist.
2000-04-12 06:23:57 +02:00
* event expression.
*
* If the NetEvent object represents a named event from the source,
* then there are NetEvTrig objects that represent the trigger
* statements instead of the NetEvProbe objects representing signals.
* For example:
*
* event foo;
* always @foo <stmt>;
* initial begin
* [...]
* -> foo;
* [...]
* -> foo;
* [...]
* end
*
* Each trigger statement in the source generates a separate NetEvTrig
* object in the netlist. Those trigger objects are elaborated
* elsewhere.
*
* Additional complications arise when named events show up in
* conjunctions. An example of such a case is:
*
* event foo;
* wire bar;
* always @(foo or posedge bar) <stmt>;
*
* Since there is by definition a NetEvent object for the foo object,
* this is handled by allowing the NetEvWait object to point to
* multiple NetEvent objects. All the NetEvProbe based objects are
* collected and pointed as the synthetic NetEvent object, and all the
* named events are added into the list of NetEvent object that the
* NetEvWait object can refer to.
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
*/
Named events really should be expressed with PEIdent objects in the pform, Handle named events within the mix of net events and edges. As a unified lot they get caught together. wait statements are broken into more complex statements that include a conditional. Do not generate NetPEvent or NetNEvent objects in elaboration. NetEvent, NetEvWait and NetEvProbe take over those functions in the netlist.
2000-04-12 06:23:57 +02:00
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
NetProc* PEventStatement::elaborate_st(Design*des, NetScope*scope,
Handle null statements inside a wait. (PR#60)
2000-12-02 00:52:49 +01:00
NetProc*enet) const
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
{
Simulate named event trigger and waits.
2000-04-04 05:20:15 +02:00
assert(scope);
Check that functions do not call invalid statements. This patch adds checks to verify that functions do not invoke statements that are invalid for them (#, @, wait, enable/call tasks and non blocking assignment). For reference see section 10.3.4 of 1364-2001.
2007-08-25 03:48:24 +02:00
if (scope->in_func()) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: functions cannot have "
Check that functions do not call invalid statements. This patch adds checks to verify that functions do not invoke statements that are invalid for them (#, @, wait, enable/call tasks and non blocking assignment). For reference see section 10.3.4 of 1364-2001.
2007-08-25 03:48:24 +02:00
"event statements." << endl;
des->errors += 1;
return 0;
}
Spelling fixes.
2003-01-27 06:09:17 +01:00
/* Create a single NetEvent and NetEvWait. Then, create a
All events now use the NetEvent class.
2000-04-10 07:26:05 +02:00
NetEvProbe for each conjunctive event in the event
Spelling fixes.
2003-01-27 06:09:17 +01:00
list. The NetEvProbe objects all refer back to the NetEvent
All events now use the NetEvent class.
2000-04-10 07:26:05 +02:00
object. */
Use perm_strings for named langiage items.
2004-02-18 18:11:54 +01:00
NetEvent*ev = new NetEvent(scope->local_symbol());
Named events really should be expressed with PEIdent objects in the pform, Handle named events within the mix of net events and edges. As a unified lot they get caught together. wait statements are broken into more complex statements that include a conditional. Do not generate NetPEvent or NetNEvent objects in elaboration. NetEvent, NetEvWait and NetEvProbe take over those functions in the netlist.
2000-04-12 06:23:57 +02:00
ev->set_line(*this);
unsigned expr_count = 0;
All events now use the NetEvent class.
2000-04-10 07:26:05 +02:00
Named events really should be expressed with PEIdent objects in the pform, Handle named events within the mix of net events and edges. As a unified lot they get caught together. wait statements are broken into more complex statements that include a conditional. Do not generate NetPEvent or NetNEvent objects in elaboration. NetEvent, NetEvWait and NetEvProbe take over those functions in the netlist.
2000-04-12 06:23:57 +02:00
NetEvWait*wa = new NetEvWait(enet);
wa->set_line(*this);
Handle much more complex event expressions.
1999-05-01 04:57:52 +02:00
Add support for conbinational events by finding the inputs to expressions and some statements. Get case and assignment statements working.
2002-04-21 06:59:07 +02:00
/* If there are no expressions, this is a signal that it is an
@* statement. Generate an expression to use. */
if (expr_.count() == 0) {
assert(enet);
Only remove output nets for synthesis backends. During elaboration only remove output nets for synthesis backends.
2007-10-25 22:31:00 +02:00
/* For synthesis we want just the inputs, but for the rest we
* want inputs and outputs that may cause a value to change. */
Make patch for pr1792108 synth aware. This patch makes the behavior selection fro pr1792108 depend on the synth* functors.
2007-10-31 03:14:09 +01:00
extern bool synthesis; /* Synthesis flag from main.cc */
Only remove output nets for synthesis backends. During elaboration only remove output nets for synthesis backends.
2007-10-25 22:31:00 +02:00
bool rem_out = false;
Make patch for pr1792108 synth aware. This patch makes the behavior selection fro pr1792108 depend on the synth* functors.
2007-10-31 03:14:09 +01:00
if (synthesis) {
Only remove output nets for synthesis backends. During elaboration only remove output nets for synthesis backends.
2007-10-25 22:31:00 +02:00
rem_out = true;
}
NexusSet*nset = enet->nex_input(rem_out);
Add support for conbinational events by finding the inputs to expressions and some statements. Get case and assignment statements working.
2002-04-21 06:59:07 +02:00
if (nset == 0) {
Correctly pass a concatenation elaboration error. Because Icarus tries to elaborate as much as it can even after an error has occurred we need to check for these errors during elaboration. This patch prevent an undefined identifier from crashing the compiler.
2008-08-14 21:40:53 +02:00
cerr << get_fileline() << ": error: Unable to elaborate:"
<< endl;
Add support for conbinational events by finding the inputs to expressions and some statements. Get case and assignment statements working.
2002-04-21 06:59:07 +02:00
enet->dump(cerr, 6);
des->errors += 1;
return enet;
}
if (nset->count() == 0) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: No inputs to statement."
@* without inputs is an error.
2006-12-08 05:09:41 +01:00
<< " The @* cannot execute." << endl;
des->errors += 1;
Add support for conbinational events by finding the inputs to expressions and some statements. Get case and assignment statements working.
2002-04-21 06:59:07 +02:00
return enet;
}
All NetObj objects have lex_string base names.
2003-03-06 01:28:41 +01:00
NetEvProbe*pr = new NetEvProbe(scope, scope->local_symbol(),
Add support for conbinational events by finding the inputs to expressions and some statements. Get case and assignment statements working.
2002-04-21 06:59:07 +02:00
ev, NetEvProbe::ANYEDGE,
nset->count());
for (unsigned idx = 0 ; idx < nset->count() ; idx += 1)
connect(nset[0][idx], pr->pin(idx));
delete nset;
des->add_node(pr);
expr_count = 1;
} else for (unsigned idx = 0 ; idx < expr_.count() ; idx += 1) {
Named events really should be expressed with PEIdent objects in the pform, Handle named events within the mix of net events and edges. As a unified lot they get caught together. wait statements are broken into more complex statements that include a conditional. Do not generate NetPEvent or NetNEvent objects in elaboration. NetEvent, NetEvWait and NetEvProbe take over those functions in the netlist.
2000-04-12 06:23:57 +02:00
assert(expr_[idx]->expr());
/* If the expression is an identifier that matches a
named event, then handle this case all at once at
skip the rest of the expression handling. */
detect unsupported block on named events.
2000-04-02 00:14:19 +02:00
Catch event names in parentheses.
2000-04-09 18:43:50 +02:00
if (PEIdent*id = dynamic_cast<PEIdent*>(expr_[idx]->expr())) {
Obsolete find_symbol and find_event from the Design class.
2003-09-20 03:05:35 +02:00
NetNet* sig = 0;
const NetExpr*par = 0;
NetEvent* eve = 0;
NetScope*found_in = symbol_search(des, scope, id->path(),
Major rework of array handling. Memories are replaced with the more general concept of arrays. The NetMemory and NetEMemory classes are removed from the ivl core program, and the IVL_LPM_RAM lpm type is removed from the ivl_target API.
2007-01-16 06:44:14 +01:00
sig, par, eve);
Obsolete find_symbol and find_event from the Design class.
2003-09-20 03:05:35 +02:00
if (found_in && eve) {
wa->add_event(eve);
Named events really should be expressed with PEIdent objects in the pform, Handle named events within the mix of net events and edges. As a unified lot they get caught together. wait statements are broken into more complex statements that include a conditional. Do not generate NetPEvent or NetNEvent objects in elaboration. NetEvent, NetEvWait and NetEvProbe take over those functions in the netlist.
2000-04-12 06:23:57 +02:00
continue;
Catch event names in parentheses.
2000-04-09 18:43:50 +02:00
}
}
Obsolete find_symbol and find_event from the Design class.
2003-09-20 03:05:35 +02:00
Named events really should be expressed with PEIdent objects in the pform, Handle named events within the mix of net events and edges. As a unified lot they get caught together. wait statements are broken into more complex statements that include a conditional. Do not generate NetPEvent or NetNEvent objects in elaboration. NetEvent, NetEvWait and NetEvProbe take over those functions in the netlist.
2000-04-12 06:23:57 +02:00
/* So now we have a normal event expression. Elaborate
the sub-expression as a net and decide how to handle
the edge. */
Do not allow implicit wires in sensitivity lists.
2002-04-22 02:53:39 +02:00
bool save_flag = error_implicit;
error_implicit = true;
Remove elaborate_net from all elaborations. Use elaborate_expr and synthesize() methods in place of the elaborate_net methods, so that elaboration is more consistent.
2008-09-09 04:13:49 +02:00
NetExpr*tmp = elab_and_eval(des, scope, expr_[idx]->expr(), 0);
if (tmp == 0) {
expr_[idx]->dump(cerr);
cerr << endl;
des->errors += 1;
error_implicit = save_flag;
continue;
}
NetNet*expr = tmp->synthesize(des, scope);
expr->set_line(*this);
Handle much more complex event expressions.
1999-05-01 04:57:52 +02:00
if (expr == 0) {
All events now use the NetEvent class.
2000-04-10 07:26:05 +02:00
expr_[idx]->dump(cerr);
Handle much more complex event expressions.
1999-05-01 04:57:52 +02:00
cerr << endl;
Parse and elaborate the concatenate operator in structural contexts, Replace vector<PExpr*> and list<PExpr*> with svector<PExpr*>, evaluate constant expressions with parameters, handle memories as lvalues. Parse task declarations, integer types.
1999-05-10 02:16:57 +02:00
des->errors += 1;
Remove elaborate_net from all elaborations. Use elaborate_expr and synthesize() methods in place of the elaborate_net methods, so that elaboration is more consistent.
2008-09-09 04:13:49 +02:00
error_implicit = save_flag;
Parse and elaborate the concatenate operator in structural contexts, Replace vector<PExpr*> and list<PExpr*> with svector<PExpr*>, evaluate constant expressions with parameters, handle memories as lvalues. Parse task declarations, integer types.
1999-05-10 02:16:57 +02:00
continue;
Handle much more complex event expressions.
1999-05-01 04:57:52 +02:00
}
assert(expr);
Handle wide events, such as @(a) where a has many bits in it. Add to vvm the binary ^ and unary & operators. Dump events a bit more completely.
1999-05-01 22:43:55 +02:00
Remove elaborate_net from all elaborations. Use elaborate_expr and synthesize() methods in place of the elaborate_net methods, so that elaboration is more consistent.
2008-09-09 04:13:49 +02:00
delete tmp;
error_implicit = save_flag;
Named events really should be expressed with PEIdent objects in the pform, Handle named events within the mix of net events and edges. As a unified lot they get caught together. wait statements are broken into more complex statements that include a conditional. Do not generate NetPEvent or NetNEvent objects in elaboration. NetEvent, NetEvWait and NetEvProbe take over those functions in the netlist.
2000-04-12 06:23:57 +02:00
unsigned pins = (expr_[idx]->type() == PEEvent::ANYEDGE)
Handle wide events, such as @(a) where a has many bits in it. Add to vvm the binary ^ and unary & operators. Dump events a bit more completely.
1999-05-01 22:43:55 +02:00
? expr->pin_count() : 1;
All events now use the NetEvent class.
2000-04-10 07:26:05 +02:00
NetEvProbe*pr;
switch (expr_[idx]->type()) {
Named events really should be expressed with PEIdent objects in the pform, Handle named events within the mix of net events and edges. As a unified lot they get caught together. wait statements are broken into more complex statements that include a conditional. Do not generate NetPEvent or NetNEvent objects in elaboration. NetEvent, NetEvWait and NetEvProbe take over those functions in the netlist.
2000-04-12 06:23:57 +02:00
case PEEvent::POSEDGE:
All NetObj objects have lex_string base names.
2003-03-06 01:28:41 +01:00
pr = new NetEvProbe(scope, scope->local_symbol(), ev,
All events now use the NetEvent class.
2000-04-10 07:26:05 +02:00
NetEvProbe::POSEDGE, pins);
break;
Named events really should be expressed with PEIdent objects in the pform, Handle named events within the mix of net events and edges. As a unified lot they get caught together. wait statements are broken into more complex statements that include a conditional. Do not generate NetPEvent or NetNEvent objects in elaboration. NetEvent, NetEvWait and NetEvProbe take over those functions in the netlist.
2000-04-12 06:23:57 +02:00
case PEEvent::NEGEDGE:
All NetObj objects have lex_string base names.
2003-03-06 01:28:41 +01:00
pr = new NetEvProbe(scope, scope->local_symbol(), ev,
All events now use the NetEvent class.
2000-04-10 07:26:05 +02:00
NetEvProbe::NEGEDGE, pins);
break;
Parse OR of event expressions.
1999-04-29 04:16:26 +02:00
Named events really should be expressed with PEIdent objects in the pform, Handle named events within the mix of net events and edges. As a unified lot they get caught together. wait statements are broken into more complex statements that include a conditional. Do not generate NetPEvent or NetNEvent objects in elaboration. NetEvent, NetEvWait and NetEvProbe take over those functions in the netlist.
2000-04-12 06:23:57 +02:00
case PEEvent::ANYEDGE:
All NetObj objects have lex_string base names.
2003-03-06 01:28:41 +01:00
pr = new NetEvProbe(scope, scope->local_symbol(), ev,
All events now use the NetEvent class.
2000-04-10 07:26:05 +02:00
NetEvProbe::ANYEDGE, pins);
break;
default:
assert(0);
}
for (unsigned p = 0 ; p < pr->pin_count() ; p += 1)
connect(pr->pin(p), expr->pin(p));
des->add_node(pr);
Named events really should be expressed with PEIdent objects in the pform, Handle named events within the mix of net events and edges. As a unified lot they get caught together. wait statements are broken into more complex statements that include a conditional. Do not generate NetPEvent or NetNEvent objects in elaboration. NetEvent, NetEvWait and NetEvProbe take over those functions in the netlist.
2000-04-12 06:23:57 +02:00
expr_count += 1;
}
/* If there was at least one conjunction that was an
expression (and not a named event) then add this
event. Otherwise, we didn't use it so delete it. */
if (expr_count > 0) {
Save event matching for nodangle.
2002-07-24 18:22:59 +02:00
scope->add_event(ev);
wa->add_event(ev);
/* NOTE: This event that I am adding to the wait may be
a duplicate of another event somewhere else. However,
I don't know that until all the modules are hooked
up, so it is best to leave find_similar_event to
after elaboration. */
Named events really should be expressed with PEIdent objects in the pform, Handle named events within the mix of net events and edges. As a unified lot they get caught together. wait statements are broken into more complex statements that include a conditional. Do not generate NetPEvent or NetNEvent objects in elaboration. NetEvent, NetEvWait and NetEvProbe take over those functions in the netlist.
2000-04-12 06:23:57 +02:00
} else {
delete ev;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
All events now use the NetEvent class.
2000-04-10 07:26:05 +02:00
return wa;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
Implement the wait statement behaviorally instead of as nets.
2003-05-19 04:50:58 +02:00
/*
* This is the special case of the event statement, the wait
* statement. This is elaborated into a slightly more complicated
* statement that uses non-wait statements:
*
* wait (<expr>) <statement>
*
* becomes
*
* begin
* while (1 !== <expr>)
* @(<expr inputs>) <noop>;
* <statement>;
* end
*/
NetProc* PEventStatement::elaborate_wait(Design*des, NetScope*scope,
NetProc*enet) const
{
assert(scope);
assert(expr_.count() == 1);
Check that functions do not call invalid statements. This patch adds checks to verify that functions do not invoke statements that are invalid for them (#, @, wait, enable/call tasks and non blocking assignment). For reference see section 10.3.4 of 1364-2001.
2007-08-25 03:48:24 +02:00
if (scope->in_func()) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: functions cannot have "
Check that functions do not call invalid statements. This patch adds checks to verify that functions do not invoke statements that are invalid for them (#, @, wait, enable/call tasks and non blocking assignment). For reference see section 10.3.4 of 1364-2001.
2007-08-25 03:48:24 +02:00
"wait statements." << endl;
des->errors += 1;
return 0;
}
Implement the wait statement behaviorally instead of as nets.
2003-05-19 04:50:58 +02:00
const PExpr *pe = expr_[0]->expr();
MOre thorough use of elab_and_eval function.
2004-03-07 21:04:10 +01:00
/* Elaborate wait expression. Don't eval yet, we will do that
shortly, after we apply a reduction or. */
Make elaborate_expr methods aware of the width that the context requires of it. In the process, fix sizing of the width of unary minus is context determined sizes.
2006-06-02 06:48:49 +02:00
NetExpr*expr = pe->elaborate_expr(des, scope, -1, false);
Implement the wait statement behaviorally instead of as nets.
2003-05-19 04:50:58 +02:00
if (expr == 0) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: Unable to elaborate"
Implement the wait statement behaviorally instead of as nets.
2003-05-19 04:50:58 +02:00
" wait condition expression." << endl;
des->errors += 1;
return 0;
}
Spelling fixes from Larry
2007-03-22 17:08:14 +01:00
// If the condition expression is more than 1 bits, then
Handle wait with constant-false expression.
2004-05-25 05:42:58 +02:00
// generate a reduction operator to get the result down to
// one bit. In other words, Turn <e> into |<e>;
Handle wide expressions in wait condition.
2004-01-13 04:42:49 +01:00
if (expr->expr_width() < 1) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": internal error: "
Handle wide expressions in wait condition.
2004-01-13 04:42:49 +01:00
"incomprehensible wait expression width (0)." << endl;
return 0;
}
if (expr->expr_width() > 1) {
assert(expr->expr_width() > 1);
NetEUReduce*cmp = new NetEUReduce('|', expr);
expr = cmp;
}
Support degenerat wait statements.
2004-09-05 23:07:26 +02:00
/* precalculate as much as possible of the wait expression. */
Major rework of the ternary operator elaboration code. This patch reworks much of the ternary code to short circuit when possible and supports real values better. It adds a blend operator for real values that returns 0.0 when the values differ and the value when they match. This deviates slightly from the standard which specifies that the value for reals is always 0.0 when the conditional is 'bx. There are also a couple bug fixes. These fixes have not been ported to continuous assignments yet. Ternary operators used at compile time and in procedural assignments should be complete (short circuit and support real values).
2008-03-08 03:51:50 +01:00
eval_expr(expr);
Support degenerat wait statements.
2004-09-05 23:07:26 +02:00
Implement the wait statement behaviorally instead of as nets.
2003-05-19 04:50:58 +02:00
/* Detect the unusual case that the wait expression is
constant. Constant true is OK (it becomes transparent) but
constant false is almost certainly not what is intended. */
Handle wait with constant-false expression.
2004-05-25 05:42:58 +02:00
assert(expr->expr_width() == 1);
Implement the wait statement behaviorally instead of as nets.
2003-05-19 04:50:58 +02:00
if (NetEConst*ce = dynamic_cast<NetEConst*>(expr)) {
verinum val = ce->value();
assert(val.len() == 1);
Handle wait with constant-false expression.
2004-05-25 05:42:58 +02:00
/* Constant true -- wait(1) <s1> reduces to <s1>. */
Implement the wait statement behaviorally instead of as nets.
2003-05-19 04:50:58 +02:00
if (val[0] == verinum::V1) {
delete expr;
assert(enet);
return enet;
}
Handle wait with constant-false expression.
2004-05-25 05:42:58 +02:00
/* Otherwise, false. wait(0) blocks permanently. */
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": warning: wait expression is "
Implement the wait statement behaviorally instead of as nets.
2003-05-19 04:50:58 +02:00
<< "constant false." << endl;
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": : The statement will "
Implement the wait statement behaviorally instead of as nets.
2003-05-19 04:50:58 +02:00
<< "block permanently." << endl;
Handle wait with constant-false expression.
2004-05-25 05:42:58 +02:00
/* Create an event wait and an otherwise unreferenced
event variable to force a perpetual wait. */
NetEvent*wait_event = new NetEvent(scope->local_symbol());
scope->add_event(wait_event);
NetEvWait*wait = new NetEvWait(0);
wait->add_event(wait_event);
wait->set_line(*this);
delete expr;
delete enet;
return wait;
}
/* Invert the sense of the test with an exclusive NOR. In
other words, if this adjusted expression returns TRUE, then
wait. */
assert(expr->expr_width() == 1);
expr = new NetEBComp('N', expr, new NetEConst(verinum(verinum::V1)));
Major rework of the ternary operator elaboration code. This patch reworks much of the ternary code to short circuit when possible and supports real values better. It adds a blend operator for real values that returns 0.0 when the values differ and the value when they match. This deviates slightly from the standard which specifies that the value for reals is always 0.0 when the conditional is 'bx. There are also a couple bug fixes. These fixes have not been ported to continuous assignments yet. Ternary operators used at compile time and in procedural assignments should be complete (short circuit and support real values).
2008-03-08 03:51:50 +01:00
eval_expr(expr);
Implement the wait statement behaviorally instead of as nets.
2003-05-19 04:50:58 +02:00
Use perm_strings for named langiage items.
2004-02-18 18:11:54 +01:00
NetEvent*wait_event = new NetEvent(scope->local_symbol());
Implement the wait statement behaviorally instead of as nets.
2003-05-19 04:50:58 +02:00
scope->add_event(wait_event);
NetEvWait*wait = new NetEvWait(0 /* noop */);
wait->add_event(wait_event);
wait->set_line(*this);
NexusSet*wait_set = expr->nex_input();
if (wait_set == 0) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": internal error: No NexusSet"
Implement the wait statement behaviorally instead of as nets.
2003-05-19 04:50:58 +02:00
<< " from wait expression." << endl;
des->errors += 1;
return 0;
}
if (wait_set->count() == 0) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": internal error: Empty NexusSet"
Implement the wait statement behaviorally instead of as nets.
2003-05-19 04:50:58 +02:00
<< " from wait expression." << endl;
des->errors += 1;
return 0;
}
NetEvProbe*wait_pr = new NetEvProbe(scope, scope->local_symbol(),
wait_event, NetEvProbe::ANYEDGE,
wait_set->count());
for (unsigned idx = 0; idx < wait_set->count() ; idx += 1)
connect(wait_set[0][idx], wait_pr->pin(idx));
delete wait_set;
des->add_node(wait_pr);
NetWhile*loop = new NetWhile(expr, wait);
loop->set_line(*this);
Spelling fixes.
2003-09-13 03:01:51 +02:00
/* If there is no real substatement (i.e., "wait (foo) ;") then
Implement the wait statement behaviorally instead of as nets.
2003-05-19 04:50:58 +02:00
we are done. */
if (enet == 0)
return loop;
Handle wait with constant-false expression.
2004-05-25 05:42:58 +02:00
/* Create a sequential block to combine the wait loop and the
Implement the wait statement behaviorally instead of as nets.
2003-05-19 04:50:58 +02:00
delayed statement. */
NetBlock*block = new NetBlock(NetBlock::SEQU, 0);
block->append(loop);
block->append(enet);
block->set_line(*this);
return block;
}
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
NetProc* PEventStatement::elaborate(Design*des, NetScope*scope) const
assignment with blocking event delay.
1999-09-22 04:00:48 +02:00
{
NetProc*enet = 0;
if (statement_) {
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
enet = statement_->elaborate(des, scope);
assignment with blocking event delay.
1999-09-22 04:00:48 +02:00
if (enet == 0)
return 0;
Support degenerat wait statements.
2004-09-05 23:07:26 +02:00
} else {
enet = new NetBlock(NetBlock::SEQU, 0);
enet->set_line(*this);
assignment with blocking event delay.
1999-09-22 04:00:48 +02:00
}
Implement the wait statement behaviorally instead of as nets.
2003-05-19 04:50:58 +02:00
if ((expr_.count() == 1) && (expr_[0]->type() == PEEvent::POSITIVE))
return elaborate_wait(des, scope, enet);
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
return elaborate_st(des, scope, enet);
assignment with blocking event delay.
1999-09-22 04:00:48 +02:00
}
Elaborate and supprort to vvm the forever and repeat statements.
1999-06-19 23:06:16 +02:00
/*
* Forever statements are represented directly in the netlist. It is
* theoretically possible to use a while structure with a constant
* expression to represent the loop, but why complicate the code
* generators so?
*/
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
NetProc* PForever::elaborate(Design*des, NetScope*scope) const
Elaborate and supprort to vvm the forever and repeat statements.
1999-06-19 23:06:16 +02:00
{
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
NetProc*stat = statement_->elaborate(des, scope);
Elaborate and supprort to vvm the forever and repeat statements.
1999-06-19 23:06:16 +02:00
if (stat == 0) return 0;
NetForever*proc = new NetForever(stat);
return proc;
}
Unify elaboration of l-values for all proceedural assignments, including assing, cassign and force. Generate NetConcat devices for gate outputs that feed into a vector results. Use this to hande gate arrays. Also let gate arrays handle vectors of gates when the outputs allow for it.
2004-12-30 00:55:43 +01:00
/*
Spelling fixes only comments and documentation some punctuation and capitalization for good measure Changelogs are purposefully untouched
2008-01-29 21:19:59 +01:00
* Force is like a procedural assignment, most notably procedural
Unify elaboration of l-values for all proceedural assignments, including assing, cassign and force. Generate NetConcat devices for gate outputs that feed into a vector results. Use this to hande gate arrays. Also let gate arrays handle vectors of gates when the outputs allow for it.
2004-12-30 00:55:43 +01:00
* continuous assignment:
*
* force <lval> = <rval>
*
* The <lval> can be anything that a normal behavioral assignment can
* take, plus net signals. This is a little bit more lax then the
Spelling fixes mostly comments, but includes some identifiers and message text
2008-01-25 22:34:51 +01:00
* other procedural assignments.
Unify elaboration of l-values for all proceedural assignments, including assing, cassign and force. Generate NetConcat devices for gate outputs that feed into a vector results. Use this to hande gate arrays. Also let gate arrays handle vectors of gates when the outputs allow for it.
2004-12-30 00:55:43 +01:00
*/
Rework of internals to carry vectors through nexus instead of single bits. Make the ivl, tgt-vvp and vvp initial changes down this path.
2004-12-11 03:31:25 +01:00
NetForce* PForce::elaborate(Design*des, NetScope*scope) const
Add support for force assignment.
2000-04-22 06:20:19 +02:00
{
Rework of internals to carry vectors through nexus instead of single bits. Make the ivl, tgt-vvp and vvp initial changes down this path.
2004-12-11 03:31:25 +01:00
NetForce*dev = 0;
Add support for force assignment.
2000-04-22 06:20:19 +02:00
assert(scope);
Unify elaboration of l-values for all proceedural assignments, including assing, cassign and force. Generate NetConcat devices for gate outputs that feed into a vector results. Use this to hande gate arrays. Also let gate arrays handle vectors of gates when the outputs allow for it.
2004-12-30 00:55:43 +01:00
NetAssign_*lval = lval_->elaborate_lval(des, scope, true);
Add support for force assignment.
2000-04-22 06:20:19 +02:00
if (lval == 0)
return 0;
Make elaborate_expr methods aware of the width that the context requires of it. In the process, fix sizing of the width of unary minus is context determined sizes.
2006-06-02 06:48:49 +02:00
unsigned lwid = count_lval_width(lval);
NetExpr*rexp = elab_and_eval(des, scope, expr_, lwid);
Rework of internals to carry vectors through nexus instead of single bits. Make the ivl, tgt-vvp and vvp initial changes down this path.
2004-12-11 03:31:25 +01:00
if (rexp == 0)
Add support for force assignment.
2000-04-22 06:20:19 +02:00
return 0;
More precise about r-value width of constants.
2005-11-26 01:35:42 +01:00
rexp->set_width(lwid, true);
Force r-value padded to width.
2004-12-15 18:09:11 +01:00
rexp = pad_to_width(rexp, lwid);
Rework of internals to carry vectors through nexus instead of single bits. Make the ivl, tgt-vvp and vvp initial changes down this path.
2004-12-11 03:31:25 +01:00
dev = new NetForce(lval, rexp);
Add support for force assignment.
2000-04-22 06:20:19 +02:00
Rework of internals to carry vectors through nexus instead of single bits. Make the ivl, tgt-vvp and vvp initial changes down this path.
2004-12-11 03:31:25 +01:00
if (debug_elaborate) {
Spelling fixes comments, documentation, a variable name, and a couple of messages
2008-06-24 17:46:16 +02:00
cerr << get_fileline() << ": debug: Elaborate force,"
Rework of internals to carry vectors through nexus instead of single bits. Make the ivl, tgt-vvp and vvp initial changes down this path.
2004-12-11 03:31:25 +01:00
<< " lval width=" << lval->lwidth()
<< " rval width=" << rexp->expr_width()
<< " rval=" << *rexp
<< endl;
}
Add support for force assignment.
2000-04-22 06:20:19 +02:00
Rework of internals to carry vectors through nexus instead of single bits. Make the ivl, tgt-vvp and vvp initial changes down this path.
2004-12-11 03:31:25 +01:00
dev->set_line(*this);
Add support for force assignment.
2000-04-22 06:20:19 +02:00
return dev;
}
Add procedural while loops, Parse procedural for loops, Add procedural wait statements, Add constant nodes, Add XNOR logic gate, Make vvm output look a bit prettier.
1998-11-09 19:55:33 +01:00
/*
Fixup spelling and some error messages. <LRDoolittle@lbl.gov>
1999-08-18 06:00:02 +02:00
* elaborate the for loop as the equivalent while loop. This eases the
Add procedural while loops, Parse procedural for loops, Add procedural wait statements, Add constant nodes, Add XNOR logic gate, Make vvm output look a bit prettier.
1998-11-09 19:55:33 +01:00
* task for the target code generator. The structure is:
*
report non-constant part select expressions.
1999-09-18 04:51:35 +02:00
* begin : top
Add procedural while loops, Parse procedural for loops, Add procedural wait statements, Add constant nodes, Add XNOR logic gate, Make vvm output look a bit prettier.
1998-11-09 19:55:33 +01:00
* name1_ = expr1_;
report non-constant part select expressions.
1999-09-18 04:51:35 +02:00
* while (cond_) begin : body
Add procedural while loops, Parse procedural for loops, Add procedural wait statements, Add constant nodes, Add XNOR logic gate, Make vvm output look a bit prettier.
1998-11-09 19:55:33 +01:00
* statement_;
* name2_ = expr2_;
* end
* end
*/
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
NetProc* PForStatement::elaborate(Design*des, NetScope*scope) const
Add procedural while loops, Parse procedural for loops, Add procedural wait statements, Add constant nodes, Add XNOR logic gate, Make vvm output look a bit prettier.
1998-11-09 19:55:33 +01:00
{
Fix expression widths for rvalues and parameters (PR#131,132)
2001-02-07 22:47:13 +01:00
NetExpr*etmp;
Redesign the implementation of scopes and parameters. I now generate the scopes and notice the parameters in a separate pass over the pform. Once the scopes are generated, I can process overrides and evalutate paremeters before elaboration begins.
2000-03-08 05:36:53 +01:00
assert(scope);
Parse and elaborate the concatenate operator in structural contexts, Replace vector<PExpr*> and list<PExpr*> with svector<PExpr*>, evaluate constant expressions with parameters, handle memories as lvalues. Parse task declarations, integer types.
1999-05-10 02:16:57 +02:00
const PEIdent*id1 = dynamic_cast<const PEIdent*>(name1_);
assert(id1);
const PEIdent*id2 = dynamic_cast<const PEIdent*>(name2_);
assert(id2);
Support carrying the scope of named begin-end blocks down to the code generator, and have the vvp code generator use that to support disable.
2002-05-27 02:08:45 +02:00
NetBlock*top = new NetBlock(NetBlock::SEQU, 0);
Attach line number information to for loop parts.
2003-10-26 05:49:51 +01:00
top->set_line(*this);
report non-constant part select expressions.
1999-09-18 04:51:35 +02:00
/* make the expression, and later the initial assignment to
the condition variable. The statement in the for loop is
very specifically an assignment. */
Parser and pform use hierarchical names as hname_t objects instead of encoded strings.
2001-12-03 05:47:14 +01:00
NetNet*sig = des->find_signal(scope, id1->path());
Add parse and elaboration of non-blocking assignments, Replace list<PCase::Item*> with an svector version, Add integer support.
1999-06-06 22:45:38 +02:00
if (sig == 0) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << id1->get_fileline() << ": register ``" << id1->path()
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
<< "'' unknown in " << scope_path(scope) << "." << endl;
Add parse and elaboration of non-blocking assignments, Replace list<PCase::Item*> with an svector version, Add integer support.
1999-06-06 22:45:38 +02:00
des->errors += 1;
return 0;
}
Add procedural while loops, Parse procedural for loops, Add procedural wait statements, Add constant nodes, Add XNOR logic gate, Make vvm output look a bit prettier.
1998-11-09 19:55:33 +01:00
assert(sig);
Change the NetAssign_ class to refer to the signal instead of link into the netlist. This is faster and uses less space. Make the NetAssignNB carry the delays instead of the NetAssign_ lval objects. Change the vvp code generator to support multiple l-values, i.e. concatenations of part selects.
2001-08-26 01:50:02 +02:00
NetAssign_*lv = new NetAssign_(sig);
Fix expression widths for rvalues and parameters (PR#131,132)
2001-02-07 22:47:13 +01:00
Remove last bits of relax_width methods, and use test_width to calculate the width of an r-value expression that may contain unsized numbers.
2006-11-04 07:19:24 +01:00
/* Calculate the width of the initialization as if this were
any other assignment statement. */
unsigned use_width = lv->lwidth();
bool unsized_flag = false;
Include a calculation of the expression type in test_width methods. The type of the sub-expression is sometimes needed by clients of the test_width methods, so add that as an output.
2008-09-27 07:20:11 +02:00
ivl_variable_type_t expr1_type = IVL_VT_NO_TYPE;
use_width = expr1_->test_width(des, scope, use_width, use_width, expr1_type, unsized_flag);
Remove last bits of relax_width methods, and use test_width to calculate the width of an r-value expression that may contain unsized numbers.
2006-11-04 07:19:24 +01:00
Fix expression widths for rvalues and parameters (PR#131,132)
2001-02-07 22:47:13 +01:00
/* Make the r-value of the initial assignment, and size it
properly. Then use it to build the assignment statement. */
Remove last bits of relax_width methods, and use test_width to calculate the width of an r-value expression that may contain unsized numbers.
2006-11-04 07:19:24 +01:00
etmp = elab_and_eval(des, scope, expr1_, use_width);
etmp->set_width(use_width);
etmp = pad_to_width(etmp, use_width);
Parameters cannot have their width changed.
2005-05-17 22:56:55 +02:00
if (debug_elaborate) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": debug: FOR initial assign: "
Parameters cannot have their width changed.
2005-05-17 22:56:55 +02:00
<< sig->name() << " = " << *etmp << endl;
assert(etmp->expr_width() >= lv->lwidth());
}
Fix expression widths for rvalues and parameters (PR#131,132)
2001-02-07 22:47:13 +01:00
Pad the R-value of a for loop initial assign like other assigns. The for loop initial value R-value was not being padded correctly. This code is a copy of the code used in a regular assignment.
2008-03-25 22:06:16 +01:00
/* Based on the specific type of the l-value, do cleanup
processing on the r-value. */
if (etmp->expr_type() != IVL_VT_REAL) {
unsigned wid = count_lval_width(lv);
etmp->set_width(wid);
etmp = pad_to_width(etmp, wid);
assert(etmp->expr_width() >= wid);
}
Fix expression widths for rvalues and parameters (PR#131,132)
2001-02-07 22:47:13 +01:00
NetAssign*init = new NetAssign(lv, etmp);
Attach line number information to for loop parts.
2003-10-26 05:49:51 +01:00
init->set_line(*this);
Unify the NetAssign constructors a bit.
1999-06-13 18:30:06 +02:00
Add procedural while loops, Parse procedural for loops, Add procedural wait statements, Add constant nodes, Add XNOR logic gate, Make vvm output look a bit prettier.
1998-11-09 19:55:33 +01:00
top->append(init);
Support carrying the scope of named begin-end blocks down to the code generator, and have the vvp code generator use that to support disable.
2002-05-27 02:08:45 +02:00
NetBlock*body = new NetBlock(NetBlock::SEQU, 0);
Attach line number information to for loop parts.
2003-10-26 05:49:51 +01:00
body->set_line(*this);
Add procedural while loops, Parse procedural for loops, Add procedural wait statements, Add constant nodes, Add XNOR logic gate, Make vvm output look a bit prettier.
1998-11-09 19:55:33 +01:00
report non-constant part select expressions.
1999-09-18 04:51:35 +02:00
/* Elaborate the statement that is contained in the for
loop. If there is an error, this will return 0 and I should
skip the append. No need to worry, the error has been
reported so it's OK that the netlist is bogus. */
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
NetProc*tmp = statement_->elaborate(des, scope);
report non-constant part select expressions.
1999-09-18 04:51:35 +02:00
if (tmp)
body->append(tmp);
Add procedural while loops, Parse procedural for loops, Add procedural wait statements, Add constant nodes, Add XNOR logic gate, Make vvm output look a bit prettier.
1998-11-09 19:55:33 +01:00
report non-constant part select expressions.
1999-09-18 04:51:35 +02:00
/* Elaborate the increment assignment statement at the end of
the for loop. This is also a very specific assignment
statement. Put this into the "body" block. */
Parser and pform use hierarchical names as hname_t objects instead of encoded strings.
2001-12-03 05:47:14 +01:00
sig = des->find_signal(scope, id2->path());
Error message for invalid for-loop index variable.
2005-09-27 06:51:37 +02:00
if (sig == 0) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: Unable to find variable "
Spelling fixes Mostly comments, but includes quite a few user-visible error, debug, and help messages.
2008-06-12 19:04:29 +02:00
<< id2->path() << " in for-loop increment expression." << endl;
Error message for invalid for-loop index variable.
2005-09-27 06:51:37 +02:00
des->errors += 1;
return body;
}
Add procedural while loops, Parse procedural for loops, Add procedural wait statements, Add constant nodes, Add XNOR logic gate, Make vvm output look a bit prettier.
1998-11-09 19:55:33 +01:00
assert(sig);
Change the NetAssign_ class to refer to the signal instead of link into the netlist. This is faster and uses less space. Make the NetAssignNB carry the delays instead of the NetAssign_ lval objects. Change the vvp code generator to support multiple l-values, i.e. concatenations of part selects.
2001-08-26 01:50:02 +02:00
lv = new NetAssign_(sig);
Fix expression widths for rvalues and parameters (PR#131,132)
2001-02-07 22:47:13 +01:00
/* Make the rvalue of the increment expression, and size it
for the lvalue. */
Clean up elaboration of for-loop increment expression.
2007-01-21 05:26:36 +01:00
etmp = elab_and_eval(des, scope, expr2_, lv->lwidth());
Fix expression widths for rvalues and parameters (PR#131,132)
2001-02-07 22:47:13 +01:00
NetAssign*step = new NetAssign(lv, etmp);
Attach line number information to for loop parts.
2003-10-26 05:49:51 +01:00
step->set_line(*this);
Unify the NetAssign constructors a bit.
1999-06-13 18:30:06 +02:00
Add procedural while loops, Parse procedural for loops, Add procedural wait statements, Add constant nodes, Add XNOR logic gate, Make vvm output look a bit prettier.
1998-11-09 19:55:33 +01:00
body->append(step);
Detect constant lessthen-equal expressions.
1999-09-18 03:53:08 +02:00
/* Elaborate the condition expression. Try to evaluate it too,
in case it is a constant. This is an interesting case
worthy of a warning. */
Make elaborate_expr methods aware of the width that the context requires of it. In the process, fix sizing of the width of unary minus is context determined sizes.
2006-06-02 06:48:49 +02:00
NetExpr*ce = elab_and_eval(des, scope, cond_, -1);
Catch unindexed memory reference.
1999-10-18 02:02:21 +02:00
if (ce == 0) {
delete top;
return 0;
}
MOre thorough use of elab_and_eval function.
2004-03-07 21:04:10 +01:00
if (dynamic_cast<NetEConst*>(ce)) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": warning: condition expression "
MOre thorough use of elab_and_eval function.
2004-03-07 21:04:10 +01:00
"of for-loop is constant." << endl;
Detect constant lessthen-equal expressions.
1999-09-18 03:53:08 +02:00
}
/* All done, build up the loop. */
NetWhile*loop = new NetWhile(ce, body);
Attach line number information to for loop parts.
2003-10-26 05:49:51 +01:00
loop->set_line(*this);
Add procedural while loops, Parse procedural for loops, Add procedural wait statements, Add constant nodes, Add XNOR logic gate, Make vvm output look a bit prettier.
1998-11-09 19:55:33 +01:00
top->append(loop);
return top;
}
Handle recursive functions and arbitrary function references to other functions, properly pass function parameters and save function results.
1999-09-01 22:46:19 +02:00
/*
Move signal tables to the NetScope class.
2000-05-02 02:58:11 +02:00
* (See the PTask::elaborate methods for basic common stuff.)
*
* The return value of a function is represented as a reg variable
* within the scope of the function that has the name of the
* function. So for example with the function:
*
* function [7:0] incr;
* input [7:0] in1;
* incr = in1 + 1;
* endfunction
Redesign the implementation of scopes and parameters. I now generate the scopes and notice the parameters in a separate pass over the pform. Once the scopes are generated, I can process overrides and evalutate paremeters before elaboration begins.
2000-03-08 05:36:53 +01:00
*
Move signal tables to the NetScope class.
2000-05-02 02:58:11 +02:00
* The scope of the function is <parent>.incr and there is a reg
* variable <parent>.incr.incr. The elaborate_1 method is called with
* the scope of the function, so the return reg is easily located.
*
* The function parameters are all inputs, except for the synthetic
* output parameter that is the return value. The return value goes
* into port 0, and the parameters are all the remaining ports.
Handle recursive functions and arbitrary function references to other functions, properly pass function parameters and save function results.
1999-09-01 22:46:19 +02:00
*/
Elaborate and emit to vvm procedural functions.
1999-09-01 00:38:29 +02:00
Rearrange task and function elaboration so that the NetTaskDef and NetFuncDef functions are created during signal enaboration, and carry these objects in the NetScope class instead of the extra, useless map in the Design class.
2000-07-30 20:25:43 +02:00
void PFunction::elaborate(Design*des, NetScope*scope) const
Handle recursive functions and arbitrary function references to other functions, properly pass function parameters and save function results.
1999-09-01 22:46:19 +02:00
{
Parser and pform use hierarchical names as hname_t objects instead of encoded strings.
2001-12-03 05:47:14 +01:00
NetFuncDef*def = scope->func_def();
Rewire/generalize parsing an elaboration of function return values to allow for better speed and more type support.
2004-06-01 01:34:36 +02:00
if (def == 0) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": internal error: "
Rewire/generalize parsing an elaboration of function return values to allow for better speed and more type support.
2004-06-01 01:34:36 +02:00
<< "No function definition for function "
Properly evaluate scope path expressions.
2007-06-02 05:42:12 +02:00
<< scope_path(scope) << endl;
elaborate_sig for generated case items Handle elaborate_sig for scopes that are within a case-generated scheme.
2008-02-28 05:54:47 +01:00
des->errors += 1;
Rewire/generalize parsing an elaboration of function return values to allow for better speed and more type support.
2004-06-01 01:34:36 +02:00
return;
}
Handle recursive functions and arbitrary function references to other functions, properly pass function parameters and save function results.
1999-09-01 22:46:19 +02:00
assert(def);
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
NetProc*st = statement_->elaborate(des, scope);
Handle recursive functions and arbitrary function references to other functions, properly pass function parameters and save function results.
1999-09-01 22:46:19 +02:00
if (st == 0) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << statement_->get_fileline() << ": error: Unable to elaborate "
Properly evaluate scope path expressions.
2007-06-02 05:42:12 +02:00
"statement in function " << scope->basename() << "." << endl;
Handle recursive functions and arbitrary function references to other functions, properly pass function parameters and save function results.
1999-09-01 22:46:19 +02:00
des->errors += 1;
return;
}
def->set_proc(st);
}
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
NetProc* PRelease::elaborate(Design*des, NetScope*scope) const
Add support for force assignment.
2000-04-22 06:20:19 +02:00
{
Add support for the procedural release statement.
2000-04-23 05:45:24 +02:00
assert(scope);
Unify elaboration of l-values for all proceedural assignments, including assing, cassign and force. Generate NetConcat devices for gate outputs that feed into a vector results. Use this to hande gate arrays. Also let gate arrays handle vectors of gates when the outputs allow for it.
2004-12-30 00:55:43 +01:00
NetAssign_*lval = lval_->elaborate_lval(des, scope, true);
Add support for the procedural release statement.
2000-04-23 05:45:24 +02:00
if (lval == 0)
return 0;
NetRelease*dev = new NetRelease(lval);
dev->set_line( *this );
return dev;
Add support for force assignment.
2000-04-22 06:20:19 +02:00
}
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
NetProc* PRepeat::elaborate(Design*des, NetScope*scope) const
Elaborate and supprort to vvm the forever and repeat statements.
1999-06-19 23:06:16 +02:00
{
Redesign the implementation of scopes and parameters. I now generate the scopes and notice the parameters in a separate pass over the pform. Once the scopes are generated, I can process overrides and evalutate paremeters before elaboration begins.
2000-03-08 05:36:53 +01:00
assert(scope);
Make elaborate_expr methods aware of the width that the context requires of it. In the process, fix sizing of the width of unary minus is context determined sizes.
2006-06-02 06:48:49 +02:00
NetExpr*expr = elab_and_eval(des, scope, expr_, -1);
Elaborate and supprort to vvm the forever and repeat statements.
1999-06-19 23:06:16 +02:00
if (expr == 0) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": Unable to elaborate"
Elaborate and supprort to vvm the forever and repeat statements.
1999-06-19 23:06:16 +02:00
" repeat expression." << endl;
des->errors += 1;
return 0;
}
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
NetProc*stat = statement_->elaborate(des, scope);
Elaborate and supprort to vvm the forever and repeat statements.
1999-06-19 23:06:16 +02:00
if (stat == 0) return 0;
// If the expression is a constant, handle certain special
// iteration counts.
if (NetEConst*ce = dynamic_cast<NetEConst*>(expr)) {
Add blocking repeat event control, make repeat sign aware This patch adds blocking repeat event controls and also makes the base repeat statement sign aware. If the argument to repeat is negative (it must be a signed variable) then this is treated just like an argument of 0 (there is no looping). Doing this allows us to model the repeat event control as follows. lhs = repeat(count) @(event) rhs; is translated to: begin temp = rhs; repeat (count) @(event); lhs = temp; end This patch also pushes the non-blocking event control information to the elaboration phase where it will report they are not currently supported.
2008-09-04 01:05:12 +02:00
long val = ce->value().as_long();
if (val <= 0) {
Elaborate and supprort to vvm the forever and repeat statements.
1999-06-19 23:06:16 +02:00
delete expr;
delete stat;
Support carrying the scope of named begin-end blocks down to the code generator, and have the vvp code generator use that to support disable.
2002-05-27 02:08:45 +02:00
return new NetBlock(NetBlock::SEQU, 0);
Add blocking repeat event control, make repeat sign aware This patch adds blocking repeat event controls and also makes the base repeat statement sign aware. If the argument to repeat is negative (it must be a signed variable) then this is treated just like an argument of 0 (there is no looping). Doing this allows us to model the repeat event control as follows. lhs = repeat(count) @(event) rhs; is translated to: begin temp = rhs; repeat (count) @(event); lhs = temp; end This patch also pushes the non-blocking event control information to the elaboration phase where it will report they are not currently supported.
2008-09-04 01:05:12 +02:00
} else if (val == 1) {
Elaborate and supprort to vvm the forever and repeat statements.
1999-06-19 23:06:16 +02:00
delete expr;
return stat;
}
}
NetRepeat*proc = new NetRepeat(expr, stat);
return proc;
}
Elaborate user defined tasks.
1999-07-03 04:12:51 +02:00
/*
* A task definition is elaborated by elaborating the statement that
Elaborate task input ports.
1999-07-24 04:11:19 +02:00
* it contains, and connecting its ports to NetNet objects. The
* netlist doesn't really need the array of parameters once elaboration
* is complete, but this is the best place to store them.
Move signal tables to the NetScope class.
2000-05-02 02:58:11 +02:00
*
* The first elaboration pass finds the reg objects that match the
* port names, and creates the NetTaskDef object. The port names are
* in the form task.port.
*
* task foo;
* output blah;
* begin <body> end
* endtask
*
* So in the foo example, the PWire objects that represent the ports
* of the task will include a foo.blah for the blah port. This port is
Rearrange task and function elaboration so that the NetTaskDef and NetFuncDef functions are created during signal enaboration, and carry these objects in the NetScope class instead of the extra, useless map in the Design class.
2000-07-30 20:25:43 +02:00
* bound to a NetNet object by looking up the name. All of this is
* handled by the PTask::elaborate_sig method and the results stashed
Spelling fixes.
2003-01-27 06:09:17 +01:00
* in the created NetTaskDef attached to the scope.
Move signal tables to the NetScope class.
2000-05-02 02:58:11 +02:00
*
* Elaboration pass 2 for the task definition causes the statement of
* the task to be elaborated and attached to the NetTaskDef object
* created in pass 1.
*
* NOTE: I am not sure why I bothered to prepend the task name to the
* port name when making the port list. It is not really useful, but
* that is what I did in pform_make_task_ports, so there it is.
Elaborate user defined tasks.
1999-07-03 04:12:51 +02:00
*/
Catch memory word parameters to tasks.
2000-04-28 18:50:53 +02:00
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
void PTask::elaborate(Design*des, NetScope*task) const
Handle mutual reference of tasks by elaborating task definitions in two passes, like functions.
1999-09-30 23:28:34 +02:00
{
Keep processes in proper lexical scope Normally processes are found in the lexical scope of a module, but there are special cases where processes (other then task/function definitions) are in other lexical scopes. The most likely case is initilizations that are in the lexical scope where the assigned variable is declared. In the process, the behaviors list is kept in the base PScope class instead of the Module or any other derived lexical scope class.
2008-03-04 05:49:52 +01:00
// Elaborate any processes that are part of this scope that
// aren't the definition itself. This can happen, for example,
// with variable initialization statements in this scope.
elaborate_behaviors_(des, task);
Generate code for task calls.
2001-04-02 04:28:12 +02:00
NetTaskDef*def = task->task_def();
Handle mutual reference of tasks by elaborating task definitions in two passes, like functions.
1999-09-30 23:28:34 +02:00
assert(def);
Elaborate ~^ and ~| operators.
1999-09-30 04:43:01 +02:00
NetProc*st;
if (statement_ == 0) {
Support carrying the scope of named begin-end blocks down to the code generator, and have the vvp code generator use that to support disable.
2002-05-27 02:08:45 +02:00
st = new NetBlock(NetBlock::SEQU, 0);
Elaborate ~^ and ~| operators.
1999-09-30 04:43:01 +02:00
} else {
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
st = statement_->elaborate(des, task);
Elaborate ~^ and ~| operators.
1999-09-30 04:43:01 +02:00
if (st == 0) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << statement_->get_fileline() << ": Unable to elaborate "
Properly evaluate scope path expressions.
2007-06-02 05:42:12 +02:00
"statement in task " << scope_path(task)
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
<< " at " << get_fileline() << "." << endl;
Elaborate ~^ and ~| operators.
1999-09-30 04:43:01 +02:00
return;
}
Elaborate user defined tasks.
1999-07-03 04:12:51 +02:00
}
Handle mutual reference of tasks by elaborating task definitions in two passes, like functions.
1999-09-30 23:28:34 +02:00
def->set_proc(st);
Elaborate user defined tasks.
1999-07-03 04:12:51 +02:00
}
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
NetProc* PTrigger::elaborate(Design*des, NetScope*scope) const
Named events as far as the pform.
2000-04-01 21:31:57 +02:00
{
Simulate named event trigger and waits.
2000-04-04 05:20:15 +02:00
assert(scope);
Obsolete find_symbol and find_event from the Design class.
2003-09-20 03:05:35 +02:00
NetNet* sig = 0;
const NetExpr*par = 0;
NetEvent* eve = 0;
NetScope*found_in = symbol_search(des, scope, event_,
Major rework of array handling. Memories are replaced with the more general concept of arrays. The NetMemory and NetEMemory classes are removed from the ivl core program, and the IVL_LPM_RAM lpm type is removed from the ivl_target API.
2007-01-16 06:44:14 +01:00
sig, par, eve);
Obsolete find_symbol and find_event from the Design class.
2003-09-20 03:05:35 +02:00
if (found_in == 0) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: event <" << event_ << ">"
Simulate named event trigger and waits.
2000-04-04 05:20:15 +02:00
<< " not found." << endl;
des->errors += 1;
return 0;
}
Obsolete find_symbol and find_event from the Design class.
2003-09-20 03:05:35 +02:00
if (eve == 0) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: <" << event_ << ">"
Obsolete find_symbol and find_event from the Design class.
2003-09-20 03:05:35 +02:00
<< " is not a named event." << endl;
des->errors += 1;
return 0;
}
NetEvTrig*trig = new NetEvTrig(eve);
Simulate named event trigger and waits.
2000-04-04 05:20:15 +02:00
trig->set_line(*this);
return trig;
Named events as far as the pform.
2000-04-01 21:31:57 +02:00
}
Handle while loops.
1998-11-11 04:13:04 +01:00
/*
* The while loop is fairly directly represented in the netlist.
*/
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
NetProc* PWhile::elaborate(Design*des, NetScope*scope) const
Handle while loops.
1998-11-11 04:13:04 +01:00
{
Make elaborate_expr methods aware of the width that the context requires of it. In the process, fix sizing of the width of unary minus is context determined sizes.
2006-06-02 06:48:49 +02:00
NetWhile*loop = new NetWhile(elab_and_eval(des, scope, cond_, -1),
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
statement_->elaborate(des, scope));
Handle while loops.
1998-11-11 04:13:04 +01:00
return loop;
}
Handle processes within generate loops.
2007-03-05 06:59:10 +01:00
bool PProcess::elaborate(Design*des, NetScope*scope) const
{
NetProc*cur = statement_->elaborate(des, scope);
if (cur == 0) {
return false;
}
NetProcTop*top=0;
switch (type()) {
case PProcess::PR_INITIAL:
top = new NetProcTop(scope, NetProcTop::KINITIAL, cur);
break;
case PProcess::PR_ALWAYS:
top = new NetProcTop(scope, NetProcTop::KALWAYS, cur);
break;
}
ivl_assert(*this, top);
// Evaluate the attributes for this process, if there
// are any. These attributes are to be attached to the
// NetProcTop object.
struct attrib_list_t*attrib_list = 0;
unsigned attrib_list_n = 0;
attrib_list = evaluate_attributes(attributes, attrib_list_n, des, scope);
for (unsigned adx = 0 ; adx < attrib_list_n ; adx += 1)
top->attribute(attrib_list[adx].key,
attrib_list[adx].val);
delete[]attrib_list;
top->set_line(*this);
des->add_process(top);
/* Detect the special case that this is a combinational
always block. We want to attach an _ivl_schedule_push
attribute to this process so that it starts up and
gets into its wait statement before non-combinational
code is executed. */
do {
if (top->type() != NetProcTop::KALWAYS)
break;
NetEvWait*st = dynamic_cast<NetEvWait*>(top->statement());
if (st == 0)
break;
if (st->nevents() != 1)
break;
NetEvent*ev = st->event(0);
if (ev->nprobe() == 0)
break;
bool anyedge_test = true;
for (unsigned idx = 0 ; anyedge_test && (idx<ev->nprobe())
; idx += 1) {
const NetEvProbe*pr = ev->probe(idx);
if (pr->edge() != NetEvProbe::ANYEDGE)
anyedge_test = false;
}
if (! anyedge_test)
break;
top->attribute(perm_string::literal("_ivl_schedule_push"),
verinum(1));
} while (0);
return true;
}
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
void PSpecPath::elaborate(Design*des, NetScope*scope) const
{
uint64_t delay_value[12];
unsigned ndelays = 0;
Support selective control of specify and xtypes features.
2006-09-28 06:35:18 +02:00
/* Do not elaborate specify delay paths if this feature is
turned off. */
if (!gn_specify_blocks_flag)
return;
Parse all specify paths to pform.
2007-02-12 02:52:21 +01:00
ivl_assert(*this, conditional || (condition==0));
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
ndelays = delays.size();
if (ndelays > 12)
ndelays = 12;
Support real valued specify delays, properly scaled.
2006-10-03 07:06:00 +02:00
int shift = scope->time_unit() - des->get_precision();
/* Elaborate the delay values themselves. Remember to scale
them for the timescale/precision of the scope. */
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
for (unsigned idx = 0 ; idx < ndelays ; idx += 1) {
PExpr*exp = delays[idx];
NetExpr*cur = elab_and_eval(des, scope, exp, 0);
if (NetEConst*cur_con = dynamic_cast<NetEConst*> (cur)) {
delay_value[idx] = cur_con->value().as_ulong();
Support real valued specify delays, properly scaled.
2006-10-03 07:06:00 +02:00
for (int tmp = 0 ; tmp < shift ; tmp += 1)
delay_value[idx] *= 10;
} else if (NetECReal*cur_rcon = dynamic_cast<NetECReal*>(cur)) {
delay_value[idx] = cur_rcon->value().as_long(shift);
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
} else {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: Path delay value "
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
<< "must be constant." << endl;
delay_value[idx] = 0;
des->errors += 1;
}
delete cur;
}
Check delay expressions correctly and give a better message. This patch uses the true delay expression count not the truncated one to check that the number of delay expressions is correct. It also prints the actual number of expressions it found when printing the error message.
2008-04-19 00:18:27 +02:00
switch (delays.size()) {
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
case 1:
case 2:
case 3:
case 6:
case 12:
break;
default:
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: Incorrect delay configuration."
Check delay expressions correctly and give a better message. This patch uses the true delay expression count not the truncated one to check that the number of delay expressions is correct. It also prints the actual number of expressions it found when printing the error message.
2008-04-19 00:18:27 +02:00
<< " Given " << delays.size() << " delay expressions." << endl;
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
ndelays = 1;
des->errors += 1;
break;
}
Add support for conditional specify delay paths.
2007-03-01 07:19:38 +01:00
NetNet*condit_sig = 0;
Add ifnone functionality. This patch adds ifnone functionality. It does not produce an error when both an ifnone and an unconditional simple module path are given. For this case the ifnone delays are ignored.
2008-04-29 04:00:29 +02:00
if (conditional && condition) {
Add support for conditional specify delay paths.
2007-03-01 07:19:38 +01:00
NetExpr*tmp = elab_and_eval(des, scope, condition, -1);
ivl_assert(*condition, tmp);
// FIXME: Look for constant expressions here?
// Get a net form.
Shuffle the argument list for the synthesize method. In preparation for using the synthesize method to replace the elaborate_net method of PExpr, rework the interface to the synthesize() method. This changes no fnctionality, but does set up the infrastructure for the next step.
2008-08-11 03:22:34 +02:00
condit_sig = tmp->synthesize(des, scope);
Add support for conditional specify delay paths.
2007-03-01 07:19:38 +01:00
ivl_assert(*condition, condit_sig);
}
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
/* Create all the various paths from the path specifier. */
typedef std::vector<perm_string>::const_iterator str_vector_iter;
for (str_vector_iter cur = dst.begin()
; cur != dst.end() ; cur ++) {
if (debug_elaborate) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": debug: Path to " << (*cur);
Add support for conditional specify delay paths.
2007-03-01 07:19:38 +01:00
if (condit_sig)
cerr << " if " << condit_sig->name();
Add ifnone functionality. This patch adds ifnone functionality. It does not produce an error when both an ifnone and an unconditional simple module path are given. For this case the ifnone delays are ignored.
2008-04-29 04:00:29 +02:00
else if (conditional)
cerr << " ifnone";
cerr << " from ";
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
}
NetNet*dst_sig = scope->find_signal(*cur);
if (dst_sig == 0) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: No such wire "
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
<< *cur << " in this module." << endl;
des->errors += 1;
continue;
}
Check that path source/destination are ports.
2007-03-03 06:56:55 +01:00
if (dst_sig->port_type() != NetNet::POUTPUT
&& dst_sig->port_type() != NetNet::PINOUT) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: Path destination "
Check that path source/destination are ports.
2007-03-03 06:56:55 +01:00
<< *cur << " must be an output or inout port." << endl;
des->errors += 1;
}
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
NetDelaySrc*path = new NetDelaySrc(scope, scope->local_symbol(),
Add ifnone functionality. This patch adds ifnone functionality. It does not produce an error when both an ifnone and an unconditional simple module path are given. For this case the ifnone delays are ignored.
2008-04-29 04:00:29 +02:00
src.size(), condit_sig,
conditional);
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
path->set_line(*this);
Parse edge sensitive paths without edge specifier.
2007-04-13 04:34:35 +02:00
// The presence of the data_source_expression indicates
// that this is an edge sensitive path. If so, then set
// the edges. Note that edge==0 is BOTH edges.
if (data_source_expression) {
if (edge >= 0) path->set_posedge();
if (edge <= 0) path->set_negedge();
}
Add support for edge sensitive spec paths.
2007-03-02 07:13:22 +01:00
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
switch (ndelays) {
case 12:
path->set_delays(delay_value[0], delay_value[1],
delay_value[2], delay_value[3],
delay_value[4], delay_value[5],
delay_value[6], delay_value[7],
delay_value[8], delay_value[9],
delay_value[10], delay_value[11]);
break;
case 6:
path->set_delays(delay_value[0], delay_value[1],
delay_value[2], delay_value[3],
delay_value[4], delay_value[5]);
break;
case 3:
path->set_delays(delay_value[0], delay_value[1],
delay_value[2]);
break;
case 2:
path->set_delays(delay_value[0], delay_value[1]);
break;
case 1:
path->set_delays(delay_value[0]);
break;
}
unsigned idx = 0;
for (str_vector_iter cur_src = src.begin()
; cur_src != src.end() ; cur_src ++) {
NetNet*src_sig = scope->find_signal(*cur_src);
assert(src_sig);
Add ifnone functionality. This patch adds ifnone functionality. It does not produce an error when both an ifnone and an unconditional simple module path are given. For this case the ifnone delays are ignored.
2008-04-29 04:00:29 +02:00
if (debug_elaborate) {
if (cur_src != src.begin()) cerr << " and ";
cerr << src_sig->name();
}
remove lint flagged by gcc-4.3 watch for possible behavior changes in elaborate.cc:3409 vvp/vvp_net.cc:600
2008-01-05 04:21:26 +01:00
if ( (src_sig->port_type() != NetNet::PINPUT)
&& (src_sig->port_type() != NetNet::PINOUT) ) {
Check that path source/destination are ports.
2007-03-03 06:56:55 +01:00
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": error: Path source "
Check that path source/destination are ports.
2007-03-03 06:56:55 +01:00
<< *cur_src << " must be an input or inout port."
<< endl;
des->errors += 1;
}
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
connect(src_sig->pin(0), path->pin(idx));
idx += 1;
}
Add ifnone functionality. This patch adds ifnone functionality. It does not produce an error when both an ifnone and an unconditional simple module path are given. For this case the ifnone delays are ignored.
2008-04-29 04:00:29 +02:00
if (debug_elaborate) {
cerr << endl;
}
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
Add support for conditional specify delay paths.
2007-03-01 07:19:38 +01:00
if (condit_sig)
connect(condit_sig->pin(0), path->pin(idx));
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
dst_sig->add_delay_path(path);
}
}
Allow generate schemes to generate task/function definitions. Generating task/function definitions involves getting the functions to put themselves into the generate scheme instead of the module, and getting elaboration to elaborate those definitions in the generate scheme.
2008-06-19 06:54:58 +02:00
static void elaborate_functions(Design*des, NetScope*scope,
const map<perm_string,PFunction*>&funcs)
{
typedef map<perm_string,PFunction*>::const_iterator mfunc_it_t;
for (mfunc_it_t cur = funcs.begin()
; cur != funcs.end() ; cur ++) {
hname_t use_name ( (*cur).first );
NetScope*fscope = scope->child(use_name);
assert(fscope);
(*cur).second->elaborate(des, fscope);
}
}
static void elaborate_tasks(Design*des, NetScope*scope,
const map<perm_string,PTask*>&tasks)
{
typedef map<perm_string,PTask*>::const_iterator mtask_it_t;
for (mtask_it_t cur = tasks.begin()
; cur != tasks.end() ; cur ++) {
hname_t use_name ( (*cur).first );
NetScope*tscope = scope->child(use_name);
assert(tscope);
(*cur).second->elaborate(des, tscope);
}
}
Simulate named event trigger and waits.
2000-04-04 05:20:15 +02:00
/*
* When a module is instantiated, it creates the scope then uses this
* method to elaborate the contents of the module.
*/
Redesign the implementation of scopes and parameters. I now generate the scopes and notice the parameters in a separate pass over the pform. Once the scopes are generated, I can process overrides and evalutate paremeters before elaboration begins.
2000-03-08 05:36:53 +01:00
bool Module::elaborate(Design*des, NetScope*scope) const
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
{
Add the LineInfo class to carry the source file location of things. PGate, Statement and PProcess. elaborate handles module parameter mismatches, missing or incorrect lvalues for procedural assignment, and errors are propogated to the top of the elaboration call tree. Attach line numbers to processes, gates and assignment statements.
1999-01-25 06:45:56 +01:00
bool result_flag = true;
Allow elaborate_expr to handle implicit nets. When the elaborate_expr code is used for expressions of continuous assignments, it needs to be able to create implicit nets.
2008-08-17 17:22:42 +02:00
error_implicit = true;
Add the LineInfo class to carry the source file location of things. PGate, Statement and PProcess. elaborate handles module parameter mismatches, missing or incorrect lvalues for procedural assignment, and errors are propogated to the top of the elaboration call tree. Attach line numbers to processes, gates and assignment statements.
1999-01-25 06:45:56 +01:00
no-specify turns of specparam elaboration.
2006-10-03 17:33:49 +02:00
if (gn_specify_blocks_flag) {
// Elaborate specparams
typedef map<perm_string,PExpr*>::const_iterator specparam_it_t;
for (specparam_it_t cur = specparams.begin()
; cur != specparams.end() ; cur ++ ) {
Missing PSpec.cc file.
2006-09-26 21:48:40 +02:00
no-specify turns of specparam elaboration.
2006-10-03 17:33:49 +02:00
NetExpr*val = elab_and_eval(des, scope, (*cur).second, -1);
NetScope::spec_val_t value;
Support real valued specify delays, properly scaled.
2006-10-03 07:06:00 +02:00
no-specify turns of specparam elaboration.
2006-10-03 17:33:49 +02:00
if (NetECReal*val_c = dynamic_cast<NetECReal*> (val)) {
Support real valued specify delays, properly scaled.
2006-10-03 07:06:00 +02:00
no-specify turns of specparam elaboration.
2006-10-03 17:33:49 +02:00
value.type = IVL_VT_REAL;
value.real_val = val_c->value().as_double();
Support real valued specify delays, properly scaled.
2006-10-03 07:06:00 +02:00
no-specify turns of specparam elaboration.
2006-10-03 17:33:49 +02:00
if (debug_elaborate)
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": debug: Elaborate "
no-specify turns of specparam elaboration.
2006-10-03 17:33:49 +02:00
<< "specparam " << (*cur).first
<< " value=" << value.real_val << endl;
Support real valued specify delays, properly scaled.
2006-10-03 07:06:00 +02:00
no-specify turns of specparam elaboration.
2006-10-03 17:33:49 +02:00
} else if (NetEConst*val_c = dynamic_cast<NetEConst*> (val)) {
Support real valued specify delays, properly scaled.
2006-10-03 07:06:00 +02:00
no-specify turns of specparam elaboration.
2006-10-03 17:33:49 +02:00
value.type = IVL_VT_BOOL;
value.integer = val_c->value().as_long();
Support real valued specify delays, properly scaled.
2006-10-03 07:06:00 +02:00
no-specify turns of specparam elaboration.
2006-10-03 17:33:49 +02:00
if (debug_elaborate)
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": debug: Elaborate "
no-specify turns of specparam elaboration.
2006-10-03 17:33:49 +02:00
<< "specparam " << (*cur).first
<< " value=" << value.integer << endl;
Missing PSpec.cc file.
2006-09-26 21:48:40 +02:00
no-specify turns of specparam elaboration.
2006-10-03 17:33:49 +02:00
} else {
Fix an uninitialized variable warning.
2006-12-09 02:59:35 +01:00
value.type = IVL_VT_NO_TYPE;
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << (*cur).second->get_fileline() << ": error: "
no-specify turns of specparam elaboration.
2006-10-03 17:33:49 +02:00
<< "specparam " << (*cur).first << " value"
<< " is not constant: " << *val << endl;
des->errors += 1;
}
Missing PSpec.cc file.
2006-09-26 21:48:40 +02:00
no-specify turns of specparam elaboration.
2006-10-03 17:33:49 +02:00
assert(val);
delete val;
scope->specparams[(*cur).first] = value;
}
Missing PSpec.cc file.
2006-09-26 21:48:40 +02:00
}
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
// Elaborate within the generate blocks.
typedef list<PGenerate*>::const_iterator generate_it_t;
for (generate_it_t cur = generate_schemes.begin()
; cur != generate_schemes.end() ; cur ++ ) {
Add support for conditional generate. In the process, fix bugs related to generate used multiple times by multiple scopes causing spurious generation results. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-06-22 04:04:48 +02:00
(*cur)->elaborate(des, scope);
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
}
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
elaborate some aspects of functions.
1999-08-26 00:22:41 +02:00
// Elaborate functions.
Allow generate schemes to generate task/function definitions. Generating task/function definitions involves getting the functions to put themselves into the generate scheme instead of the module, and getting elaboration to elaborate those definitions in the generate scheme.
2008-06-19 06:54:58 +02:00
elaborate_functions(des, scope, funcs);
elaborate some aspects of functions.
1999-08-26 00:22:41 +02:00
Elaborate user defined tasks.
1999-07-03 04:12:51 +02:00
// Elaborate the task definitions. This is done before the
// behaviors so that task calls may reference these, and after
// the signals so that the tasks can reference them.
Allow generate schemes to generate task/function definitions. Generating task/function definitions involves getting the functions to put themselves into the generate scheme instead of the module, and getting elaboration to elaborate those definitions in the generate scheme.
2008-06-19 06:54:58 +02:00
elaborate_tasks(des, scope, tasks);
Elaborate user defined tasks.
1999-07-03 04:12:51 +02:00
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
// Get all the gates of the module and elaborate them by
// connecting them to the signals. The gate may be simple or
// complex.
const list<PGate*>&gl = get_gates();
Allow elaborate_expr to handle implicit nets. When the elaborate_expr code is used for expressions of continuous assignments, it needs to be able to create implicit nets.
2008-08-17 17:22:42 +02:00
error_implicit = false;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
for (list<PGate*>::const_iterator gt = gl.begin()
; gt != gl.end()
; gt ++ ) {
Use NetScope instead of string for scope path.
2001-11-22 07:20:59 +01:00
(*gt)->elaborate(des, scope);
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
Allow elaborate_expr to handle implicit nets. When the elaborate_expr code is used for expressions of continuous assignments, it needs to be able to create implicit nets.
2008-08-17 17:22:42 +02:00
error_implicit = true;
Carry Verilog 2001 attributes with processes, all the way through to the ivl_target API. Divide signal reference counts between rval and lval references.
2002-05-26 03:39:02 +02:00
// Elaborate the behaviors, making processes out of them. This
// involves scanning the PProcess* list, creating a NetProcTop
// for each process.
Keep processes in proper lexical scope Normally processes are found in the lexical scope of a module, but there are special cases where processes (other then task/function definitions) are in other lexical scopes. The most likely case is initilizations that are in the lexical scope where the assigned variable is declared. In the process, the behaviors list is kept in the base PScope class instead of the Module or any other derived lexical scope class.
2008-03-04 05:49:52 +01:00
result_flag &= elaborate_behaviors_(des, scope);
Add the LineInfo class to carry the source file location of things. PGate, Statement and PProcess. elaborate handles module parameter mismatches, missing or incorrect lvalues for procedural assignment, and errors are propogated to the top of the elaboration call tree. Attach line numbers to processes, gates and assignment statements.
1999-01-25 06:45:56 +01:00
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
// Elaborate the specify paths of the module.
for (list<PSpecPath*>::const_iterator sp = specify_paths.begin()
; sp != specify_paths.end() ; sp ++) {
(*sp)->elaborate(des, scope);
}
Add the LineInfo class to carry the source file location of things. PGate, Statement and PProcess. elaborate handles module parameter mismatches, missing or incorrect lvalues for procedural assignment, and errors are propogated to the top of the elaboration call tree. Attach line numbers to processes, gates and assignment statements.
1999-01-25 06:45:56 +01:00
return result_flag;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
Add support for conditional generate. In the process, fix bugs related to generate used multiple times by multiple scopes causing spurious generation results. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-06-22 04:04:48 +02:00
bool PGenerate::elaborate(Design*des, NetScope*container) const
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
{
bool flag = true;
Add support for generate case Generate case is a complex generate scheme where the items are sub-schemes of the case generate itself. The parser handles them something like nested generate statements, but storing the case guards as the test expression. Then the elaborator notes the case scheme and reaches into the case item schemes inside to make up tests, select the generate item, and elaborate.
2008-02-10 07:19:42 +01:00
// Handle the special case that this is a CASE scheme. In this
// case the PGenerate itself does not have the generated
// item. Look instead for the case ITEM that has a scope
// generated for it.
if (scheme_type == PGenerate::GS_CASE) {
if (debug_elaborate)
cerr << get_fileline() << ": debug: generate case"
<< " elaborating in scope "
<< scope_path(container) << "." << endl;
typedef list<PGenerate*>::const_iterator generate_it_t;
Elaborate block scopes burried in generate schemes. Named begin/end blocks burried within generate schemes need to be elaborated. Handle this by remembering to elaborate_scope on the statements within the generate scheme. In the process, clean up/regularize some of the member names and methods.
2008-06-18 06:45:37 +02:00
for (generate_it_t cur = generate_schemes.begin()
; cur != generate_schemes.end() ; cur ++) {
Add support for generate case Generate case is a complex generate scheme where the items are sub-schemes of the case generate itself. The parser handles them something like nested generate statements, but storing the case guards as the test expression. Then the elaborator notes the case scheme and reaches into the case item schemes inside to make up tests, select the generate item, and elaborate.
2008-02-10 07:19:42 +01:00
PGenerate*item = *cur;
if (! item->scope_list_.empty()) {
flag &= item->elaborate(des, container);
}
}
return flag;
}
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
typedef list<NetScope*>::const_iterator scope_list_it_t;
for (scope_list_it_t cur = scope_list_.begin()
; cur != scope_list_.end() ; cur ++ ) {
Add support for conditional generate. In the process, fix bugs related to generate used multiple times by multiple scopes causing spurious generation results. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-06-22 04:04:48 +02:00
NetScope*scope = *cur;
// Check that this scope is one that is contained in the
// container that the caller passed in.
if (scope->parent() != container)
continue;
Correct naming of unnamed generate blocks. This patch causes unnamed generate blocks to be automatically named using the naming scheme defined in the Verilog-2005 standard. This is a fix for the problem discussed in pr1821610.
2007-11-17 19:17:23 +01:00
// If this was an unnamed generate block, replace its
// temporary name with a name generated using the naming
// scheme defined in the Verilog-2005 standard.
const char*name = scope_name.str();
if (name[0] == '$') {
if (!scope->auto_name("genblk", '0', name + 4)) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": warning: Couldn't build"
Correct naming of unnamed generate blocks. This patch causes unnamed generate blocks to be automatically named using the naming scheme defined in the Verilog-2005 standard. This is a fix for the problem discussed in pr1821610.
2007-11-17 19:17:23 +01:00
<< " unique name for unnamed generate block"
<< " - using internal name " << name << endl;
}
}
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
if (debug_elaborate)
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << get_fileline() << ": debug: Elaborate in "
Add support for conditional generate. In the process, fix bugs related to generate used multiple times by multiple scopes causing spurious generation results. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-06-22 04:04:48 +02:00
<< "scope " << scope_path(scope) << endl;
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
Add support for conditional generate. In the process, fix bugs related to generate used multiple times by multiple scopes causing spurious generation results. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-06-22 04:04:48 +02:00
flag = elaborate_(des, scope) & flag;
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
}
return flag;
}
bool PGenerate::elaborate_(Design*des, NetScope*scope) const
{
Allow generate schemes to generate task/function definitions. Generating task/function definitions involves getting the functions to put themselves into the generate scheme instead of the module, and getting elaboration to elaborate those definitions in the generate scheme.
2008-06-19 06:54:58 +02:00
elaborate_functions(des, scope, funcs);
elaborate_tasks(des, scope, tasks);
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
typedef list<PGate*>::const_iterator gates_it_t;
Handle processes within generate loops.
2007-03-05 06:59:10 +01:00
for (gates_it_t cur = gates.begin() ; cur != gates.end() ; cur ++ )
(*cur)->elaborate(des, scope);
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
Handle processes within generate loops.
2007-03-05 06:59:10 +01:00
typedef list<PProcess*>::const_iterator proc_it_t;
for (proc_it_t cur = behaviors.begin(); cur != behaviors.end(); cur++)
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
(*cur)->elaborate(des, scope);
Support nested generate schemes. This patch adds support for nested loops and if-else decisions in generate statements.
2007-10-28 13:07:25 +01:00
typedef list<PGenerate*>::const_iterator generate_it_t;
Elaborate block scopes burried in generate schemes. Named begin/end blocks burried within generate schemes need to be elaborated. Handle this by remembering to elaborate_scope on the statements within the generate scheme. In the process, clean up/regularize some of the member names and methods.
2008-06-18 06:45:37 +02:00
for (generate_it_t cur = generate_schemes.begin()
; cur != generate_schemes.end() ; cur ++ ) {
Support nested generate schemes. This patch adds support for nested loops and if-else decisions in generate statements.
2007-10-28 13:07:25 +01:00
(*cur)->elaborate(des, scope);
}
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
return true;
}
Keep processes in proper lexical scope Normally processes are found in the lexical scope of a module, but there are special cases where processes (other then task/function definitions) are in other lexical scopes. The most likely case is initilizations that are in the lexical scope where the assigned variable is declared. In the process, the behaviors list is kept in the base PScope class instead of the Module or any other derived lexical scope class.
2008-03-04 05:49:52 +01:00
bool PScope::elaborate_behaviors_(Design*des, NetScope*scope) const
{
bool result_flag = true;
// Elaborate the behaviors, making processes out of them. This
// involves scanning the PProcess* list, creating a NetProcTop
// for each process.
for (list<PProcess*>::const_iterator st = behaviors.begin()
; st != behaviors.end() ; st ++ ) {
result_flag &= (*st)->elaborate(des, scope);
}
return result_flag;
}
Support multiple root modules (Philip Blundell)
2001-10-19 23:53:24 +02:00
struct root_elem {
Module *mod;
NetScope *scope;
};
run scope elaboration as queued work items. Putting scope elaboration into work queue items allows for handling more complex processing order. The elaboration_work_list queue drives the processing of elaborate_scope and parameter evaluation.
2008-06-25 05:28:08 +02:00
class elaborate_root_scope_t : public elaborator_work_item_t {
public:
elaborate_root_scope_t(Design*des, NetScope*scope, Module*rmod)
: elaborator_work_item_t(des), scope_(scope), rmod_(rmod)
{ }
~elaborate_root_scope_t() { }
virtual void elaborate_runrun()
{
Module::replace_t stub;
if (! rmod_->elaborate_scope(des, scope_, stub))
des->errors += 1;
}
private:
NetScope*scope_;
Module*rmod_;
};
class top_defparams : public elaborator_work_item_t {
public:
top_defparams(Design*des)
: elaborator_work_item_t(des)
{ }
~top_defparams() { }
virtual void elaborate_runrun()
{
// This method recurses through the scopes, looking for
// defparam assignments to apply to the parameters in the
// various scopes. This needs to be done after all the scopes
// and basic parameters are taken care of because the defparam
// can assign to a parameter declared *after* it.
des->run_defparams();
// At this point, all parameter overrides are done. Scan the
// scopes and evaluate the parameters all the way down to
// constants.
des->evaluate_parameters();
}
};
Handle multiple passes of scope and defparam elaboration. When generate schems and instance arrays are nested, it takes multiple iterations of elaborate scope, defparams and evaluate parameters before everything is worked out. Rework the work item processing so that the loop elaborates scopes and runs defparams in phases. The phases are needed so that we can tell when the remaining defparams are orphaned.
2008-06-30 03:46:46 +02:00
class later_defparams : public elaborator_work_item_t {
public:
later_defparams(Design*des)
: elaborator_work_item_t(des)
{ }
~later_defparams() { }
virtual void elaborate_runrun()
{
list<NetScope*>tmp_list;
for (set<NetScope*>::iterator cur = des->defparams_later.begin()
; cur != des->defparams_later.end() ; cur ++ )
tmp_list.push_back(*cur);
des->defparams_later.clear();
while (! tmp_list.empty()) {
NetScope*cur = tmp_list.front();
tmp_list.pop_front();
cur->run_defparams_later(des);
}
des->evaluate_parameters();
}
};
Fix the always zero delay check to happen after elaboration. This patch moves the always zero or possibly zero delay checks to a point after the circuit is full elaborated. Before it could try to check tasks that had not already been evaluated resulting in a crash.
2008-08-29 00:05:19 +02:00
bool Design::check_always_delay() const
{
bool result_flag = true;
for (const NetProcTop*pr = procs_ ; pr ; pr = pr->next_) {
/* If this is an always block and we have no or zero delay then
* a runtime infinite loop will happen. If we possible have some
* delay then print a warning that an infinite loop is possible.
*/
if (pr->type() == NetProcTop::KALWAYS) {
DelayType dly_type = pr->statement()->delay_type();
if (dly_type == NO_DELAY || dly_type == ZERO_DELAY) {
cerr << pr->get_fileline() << ": error: always"
<< " statement does not have any delay." << endl;
cerr << pr->get_fileline() << ": : A runtime"
<< " infinite loop will occur." << endl;
result_flag = false;
} else if (dly_type == POSSIBLE_DELAY && warn_inf_loop) {
cerr << pr->get_fileline() << ": warning: always"
<< " statement may not have any delay." << endl;
cerr << pr->get_fileline() << ": : A runtime"
<< " infinite loop may be possible." << endl;
}
}
}
return result_flag;
}
Minor cleanup and comments. The initial elaboration needs better comments/documentation.
2008-06-22 03:36:46 +02:00
/*
* This function is the root of all elaboration. The input is the list
* of root module names. The function locates the Module definitions
* for each root, does the whole elaboration sequence, and fills in
* the resulting Design.
*/
Use perm_strings for named langiage items.
2004-02-18 18:11:54 +01:00
Design* elaborate(list<perm_string>roots)
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
{
Support multiple root modules (Philip Blundell)
2001-10-19 23:53:24 +02:00
svector<root_elem*> root_elems(roots.size());
bool rc = true;
unsigned i = 0;
Elaborate UDP devices, Support UDP type attributes, and pass those attributes to nodes that are instantiated by elaboration, Put modules into a map instead of a simple list.
1998-12-01 01:42:13 +01:00
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
// This is the output design. I fill it in as I scan the root
// module and elaborate what I find.
Design*des = new Design;
Minor cleanup and comments. The initial elaboration needs better comments/documentation.
2008-06-22 03:36:46 +02:00
// Scan the root modules by name, and elaborate their scopes.
Use perm_strings for named langiage items.
2004-02-18 18:11:54 +01:00
for (list<perm_string>::const_iterator root = roots.begin()
Add automatic module libraries.
2001-10-21 01:02:39 +02:00
; root != roots.end()
; root++) {
Redesign the implementation of scopes and parameters. I now generate the scopes and notice the parameters in a separate pass over the pform. Once the scopes are generated, I can process overrides and evalutate paremeters before elaboration begins.
2000-03-08 05:36:53 +01:00
Add automatic module libraries.
2001-10-21 01:02:39 +02:00
// Look for the root module in the list.
Use perm_strings for named langiage items.
2004-02-18 18:11:54 +01:00
map<perm_string,Module*>::const_iterator mod = pform_modules.find(*root);
Add automatic module libraries.
2001-10-21 01:02:39 +02:00
if (mod == pform_modules.end()) {
Better error message for mising root module.
2001-10-23 01:26:37 +02:00
cerr << "error: Unable to find the root module \""
Clean up spurious trailing white space.
2004-10-04 03:10:51 +02:00
<< (*root) << "\" in the Verilog source." << endl;
Better error message for mising root module.
2001-10-23 01:26:37 +02:00
cerr << " : Perhaps ``-s " << (*root)
<< "'' is incorrect?" << endl;
Support multiple root modules (Philip Blundell)
2001-10-19 23:53:24 +02:00
des->errors++;
continue;
}
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
// Get the module definition for this root instance.
Support multiple root modules (Philip Blundell)
2001-10-19 23:53:24 +02:00
Module *rmod = (*mod).second;
Clean up spurious trailing white space.
2004-10-04 03:10:51 +02:00
Spelling fixes Comments only, no code changes
2008-08-28 18:01:43 +02:00
// Make the root scope. This makes a NetScope object and
Minor cleanup and comments. The initial elaboration needs better comments/documentation.
2008-06-22 03:36:46 +02:00
// pushes it into the list of root scopes in the Design.
Support multiple root modules (Philip Blundell)
2001-10-19 23:53:24 +02:00
NetScope*scope = des->make_root_scope(*root);
Minor cleanup and comments. The initial elaboration needs better comments/documentation.
2008-06-22 03:36:46 +02:00
// Collect some basic properties of this scope from the
// Module definition.
Push file and line information for scopes to the runtime. This patch adds code to push the file and line information for scope objects (modules, functions, tasks, etc.) to the runtime. For modules, this includes the definition fields.
2008-04-30 03:58:25 +02:00
scope->set_line(rmod);
Support multiple root modules (Philip Blundell)
2001-10-19 23:53:24 +02:00
scope->time_unit(rmod->time_unit);
scope->time_precision(rmod->time_precision);
Add support for the default_nettype directive.
2004-06-13 06:56:53 +02:00
scope->default_nettype(rmod->default_nettype);
Support multiple root modules (Philip Blundell)
2001-10-19 23:53:24 +02:00
des->set_precision(rmod->time_precision);
Fix instance arrays indexed by overridden parameters.
2006-03-30 03:49:07 +02:00
Support multiple root modules (Philip Blundell)
2001-10-19 23:53:24 +02:00
Spelling fixes Comments only, no code changes
2008-08-28 18:01:43 +02:00
// Save this scope, along with its definition, in the
Minor cleanup and comments. The initial elaboration needs better comments/documentation.
2008-06-22 03:36:46 +02:00
// "root_elems" list for later passes.
Support multiple root modules (Philip Blundell)
2001-10-19 23:53:24 +02:00
struct root_elem *r = new struct root_elem;
r->mod = rmod;
r->scope = scope;
root_elems[i++] = r;
Redesign the implementation of scopes and parameters. I now generate the scopes and notice the parameters in a separate pass over the pform. Once the scopes are generated, I can process overrides and evalutate paremeters before elaboration begins.
2000-03-08 05:36:53 +01:00
run scope elaboration as queued work items. Putting scope elaboration into work queue items allows for handling more complex processing order. The elaboration_work_list queue drives the processing of elaborate_scope and parameter evaluation.
2008-06-25 05:28:08 +02:00
// Arrange for these scopes to be elaborated as root
// scopes. Create an "elaborate_root_scope" object to
// contain the work item, and append it to the scope
// elaborations work list.
elaborator_work_item_t*es = new elaborate_root_scope_t(des, scope, rmod);
des->elaboration_work_list.push_back(es);
}
// After the work items for the root scope elaboration, push a
// work item to process the defparams.
des->elaboration_work_list.push_back(new top_defparams(des));
// Run the work list of scope elaborations until the list is
// empty. This list is initially populated above where the
// initial root scopes are primed.
while (! des->elaboration_work_list.empty()) {
Handle multiple passes of scope and defparam elaboration. When generate schems and instance arrays are nested, it takes multiple iterations of elaborate scope, defparams and evaluate parameters before everything is worked out. Rework the work item processing so that the loop elaborates scopes and runs defparams in phases. The phases are needed so that we can tell when the remaining defparams are orphaned.
2008-06-30 03:46:46 +02:00
// Transfer the queue to a temporary queue.
list<elaborator_work_item_t*> cur_queue;
while (! des->elaboration_work_list.empty()) {
cur_queue.push_back(des->elaboration_work_list.front());
des->elaboration_work_list.pop_front();
}
// Run from the temporary queue. If the temporary queue
// items create new work queue items, they will show up
// in the elaboration_work_list and then we get to run
// through them in the next pass.
while (! cur_queue.empty()) {
elaborator_work_item_t*tmp = cur_queue.front();
cur_queue.pop_front();
tmp->elaborate_runrun();
delete tmp;
}
if (! des->elaboration_work_list.empty()) {
des->elaboration_work_list.push_back(new later_defparams(des));
}
Minor cleanup and comments. The initial elaboration needs better comments/documentation.
2008-06-22 03:36:46 +02:00
}
Handle multiple passes of scope and defparam elaboration. When generate schems and instance arrays are nested, it takes multiple iterations of elaborate scope, defparams and evaluate parameters before everything is worked out. Rework the work item processing so that the loop elaborates scopes and runs defparams in phases. The phases are needed so that we can tell when the remaining defparams are orphaned.
2008-06-30 03:46:46 +02:00
// Look for residual defparams (that point to a non-existent
// scope) and clean them out.
des->residual_defparams();
Give up if roots are missing.
2001-10-31 04:22:31 +01:00
// Errors already? Probably missing root modules. Just give up
// now and return nothing.
Summary list of missing modules.
2003-09-25 02:25:14 +02:00
if (des->errors > 0)
return des;
Give up if roots are missing.
2001-10-31 04:22:31 +01:00
Handle activating tasks in another root.
2001-10-22 04:05:20 +02:00
// With the parameters evaluated down to constants, we have
// what we need to elaborate signals and memories. This pass
// creates all the NetNet and NetMemory objects for declared
// objects.
Support multiple root modules (Philip Blundell)
2001-10-19 23:53:24 +02:00
for (i = 0; i < root_elems.count(); i++) {
Module *rmod = root_elems[i]->mod;
NetScope *scope = root_elems[i]->scope;
Handle defparam to partial hierarchical names.
2000-03-10 07:20:48 +01:00
Support multiple root modules (Philip Blundell)
2001-10-19 23:53:24 +02:00
if (! rmod->elaborate_sig(des, scope)) {
delete des;
return 0;
}
Handle activating tasks in another root.
2001-10-22 04:05:20 +02:00
}
// Now that the structure and parameters are taken care of,
// run through the pform again and generate the full netlist.
for (i = 0; i < root_elems.count(); i++) {
Module *rmod = root_elems[i]->mod;
NetScope *scope = root_elems[i]->scope;
Support multiple root modules (Philip Blundell)
2001-10-19 23:53:24 +02:00
rc &= rmod->elaborate(des, scope);
Move signal elaboration to a seperate pass.
2000-05-02 18:27:38 +02:00
}
Add the LineInfo class to carry the source file location of things. PGate, Statement and PProcess. elaborate handles module parameter mismatches, missing or incorrect lvalues for procedural assignment, and errors are propogated to the top of the elaboration call tree. Attach line numbers to processes, gates and assignment statements.
1999-01-25 06:45:56 +01:00
if (rc == false) {
Fix the always zero delay check to happen after elaboration. This patch moves the always zero or possibly zero delay checks to a point after the circuit is full elaborated. Before it could try to check tasks that had not already been evaluated resulting in a crash.
2008-08-29 00:05:19 +02:00
delete des;
return 0;
}
// Now that everything is fully elaborated verify that we do
// not have an always block with no delay (an infinite loop).
if (des->check_always_delay() == false) {
Add the LineInfo class to carry the source file location of things. PGate, Statement and PProcess. elaborate handles module parameter mismatches, missing or incorrect lvalues for procedural assignment, and errors are propogated to the top of the elaboration call tree. Attach line numbers to processes, gates and assignment statements.
1999-01-25 06:45:56 +01:00
delete des;
des = 0;
}
Redesign the implementation of scopes and parameters. I now generate the scopes and notice the parameters in a separate pass over the pform. Once the scopes are generated, I can process overrides and evalutate paremeters before elaboration begins.
2000-03-08 05:36:53 +01:00
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
return des;
}