Fixup spelling and some error messages. <LRDoolittle@lbl.gov>
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steve
parent
f1fdce78be
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031d91f813
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@ -289,6 +289,7 @@ I have received aid in the form of fixes, Verilog guidance, and
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especially testing from many people, including (in alphabetical order):
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Ed Carter <r47652@email.sps.mot.com>
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Larry Doolittle <LRDoolittle@lbl.gov>
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Ales Hvezda <ahvezda@seul.org>
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James Lee <jml@seva.com>
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Stefan Petersen <spe@geda.seul.org>
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15
elaborate.cc
15
elaborate.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: elaborate.cc,v 1.70 1999/08/08 20:06:06 steve Exp $"
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#ident "$Id: elaborate.cc,v 1.71 1999/08/18 04:00:02 steve Exp $"
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#endif
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/*
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@ -1025,7 +1025,7 @@ NetExpr* PEString::elaborate_expr(Design*des, const string&path) const
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return tmp;
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}
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NetExpr*PEIdent::elaborate_expr(Design*des, const string&path) const
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NetExpr* PEIdent::elaborate_expr(Design*des, const string&path) const
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{
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// System identifiers show up in the netlist as identifiers.
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if (text_[0] == '$')
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@ -1033,7 +1033,7 @@ NetExpr*PEIdent::elaborate_expr(Design*des, const string&path) const
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string name = path+"."+text_;
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// If the identifier name a paramter name, then return
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// If the identifier name a parameter name, then return
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// the expression that it represents.
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if (const NetExpr*ex = des->find_parameter(path, text_))
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return ex->dup_expr();
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@ -1304,7 +1304,7 @@ NetProc* PAssign::elaborate(Design*des, const string&path) const
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This rewriting of the expression allows me to not bother to
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actually and literally represent the delayed assign in the
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netlist. The compound statement is exactly equivilent. */
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netlist. The compound statement is exactly equivalent. */
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if (dex) {
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string n = des->local_symbol(path);
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@ -1808,7 +1808,7 @@ NetProc* PForever::elaborate(Design*des, const string&path) const
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}
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/*
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* elaborate the for loop as the equivilent while loop. This eases the
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* elaborate the for loop as the equivalent while loop. This eases the
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* task for the target code generator. The structure is:
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*
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* begin
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@ -2051,6 +2051,9 @@ Design* elaborate(const map<string,Module*>&modules,
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/*
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* $Log: elaborate.cc,v $
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* Revision 1.71 1999/08/18 04:00:02 steve
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* Fixup spelling and some error messages. <LRDoolittle@lbl.gov>
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*
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* Revision 1.70 1999/08/08 20:06:06 steve
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* Uninitialized low and high indices for single gate syntax
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*
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@ -2106,7 +2109,7 @@ Design* elaborate(const map<string,Module*>&modules,
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* part select in expressions.
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*
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* Revision 1.54 1999/07/13 04:08:26 steve
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* Construct delayed assignment as an equivilent block.
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* Construct delayed assignment as an equivalent block.
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*
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* Revision 1.53 1999/07/12 00:59:36 steve
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* procedural blocking assignment delays.
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: netlist.h,v 1.55 1999/08/06 04:05:28 steve Exp $"
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#ident "$Id: netlist.h,v 1.56 1999/08/18 04:00:02 steve Exp $"
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#endif
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/*
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@ -438,7 +438,7 @@ class NetLogic : public NetNode {
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* expand it out any further then this in the netlist, as this can be
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* used to represent target device primitives.
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*
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* The UDP can be combinational or sequential. The sequentianl UDP
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* The UDP can be combinational or sequential. The sequential UDP
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* includes the current output in the truth table, and supports edges,
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* whereas the combinational does not and is entirely level sensitive.
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* In any case, pin 0 is an output, and all the remaining pins are
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@ -1440,6 +1440,9 @@ extern ostream& operator << (ostream&, NetNet::Type);
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/*
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* $Log: netlist.h,v $
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* Revision 1.56 1999/08/18 04:00:02 steve
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* Fixup spelling and some error messages. <LRDoolittle@lbl.gov>
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*
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* Revision 1.55 1999/08/06 04:05:28 steve
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* Handle scope of parameters.
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*
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7
t-xnf.cc
7
t-xnf.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: t-xnf.cc,v 1.7 1999/07/17 03:39:11 steve Exp $"
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#ident "$Id: t-xnf.cc,v 1.8 1999/08/18 04:00:02 steve Exp $"
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#endif
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/* XNF BACKEND
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@ -82,7 +82,7 @@ class target_xnf : public target_t {
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};
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/*
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* This function takes a signal name and mangles it into an equivilent
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* This function takes a signal name and mangles it into an equivalent
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* name that is suitable to the XNF format.
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*/
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string target_xnf::mangle(const string&name)
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@ -333,6 +333,9 @@ extern const struct target tgt_xnf = { "xnf", &target_xnf_obj };
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/*
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* $Log: t-xnf.cc,v $
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* Revision 1.8 1999/08/18 04:00:02 steve
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* Fixup spelling and some error messages. <LRDoolittle@lbl.gov>
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*
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* Revision 1.7 1999/07/17 03:39:11 steve
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* simplified process scan for targets.
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*
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14
target.cc
14
target.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: target.cc,v 1.15 1999/07/17 19:51:00 steve Exp $"
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#ident "$Id: target.cc,v 1.16 1999/08/18 04:00:02 steve Exp $"
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#endif
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# include "target.h"
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@ -79,16 +79,18 @@ void target_t::net_const(ostream&os, const NetConst*)
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"Unhandled CONSTANT node." << endl;
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}
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void target_t::net_esignal(ostream&os, const NetESignal*)
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void target_t::net_esignal(ostream&os, const NetESignal*net)
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{
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cerr << "target (" << typeid(*this).name() << "): "
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"Unhandled Expression Signal node." << endl;
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net->dump_node(cerr, 4);
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}
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void target_t::net_event(ostream&os, const NetNEvent*)
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void target_t::net_event(ostream&os, const NetNEvent*net)
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{
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cerr << "target (" << typeid(*this).name() << "): "
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"Unhandled EVENT net node." << endl;
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net->dump_node(cerr, 4);
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}
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void target_t::process(ostream&os, const NetProcTop*top)
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@ -140,10 +142,11 @@ void target_t::proc_delay(ostream&os, const NetPDelay*)
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"Unhandled proc_delay." << endl;
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}
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void target_t::proc_event(ostream&os, const NetPEvent*)
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void target_t::proc_event(ostream&os, const NetPEvent*net)
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{
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cerr << "target (" << typeid(*this).name() << "): "
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"Unhandled proc_event." << endl;
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net->dump(cerr, 4);
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}
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void target_t::proc_forever(ostream&os, const NetForever*)
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@ -241,6 +244,9 @@ void expr_scan_t::expr_binary(const NetEBinary*ex)
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/*
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* $Log: target.cc,v $
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* Revision 1.16 1999/08/18 04:00:02 steve
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* Fixup spelling and some error messages. <LRDoolittle@lbl.gov>
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*
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* Revision 1.15 1999/07/17 19:51:00 steve
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* netlist support for ternary operator.
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*
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16
xnfsyn.cc
16
xnfsyn.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: xnfsyn.cc,v 1.2 1999/07/18 21:17:51 steve Exp $"
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#ident "$Id: xnfsyn.cc,v 1.3 1999/08/18 04:00:02 steve Exp $"
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#endif
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/*
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@ -136,13 +136,16 @@ void xnfsyn_f::proc_casn_(class Design*des)
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// ... and the rval must be a simple signal.
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NetESignal*sig = dynamic_cast<NetESignal*>(asn_->rval());
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if (sig == 0)
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if (sig == 0) {
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cerr << "Noted complex rval in DFF, name " << asn_->name() <<
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", not yet implemented" << endl;
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return ;
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}
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// The signal and the assignment must be the same width...
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assert(asn_->pin_count() == sig->pin_count());
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// Geneate enough DFF objects to handle the entire width.
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// Generate enough DFF objects to handle the entire width.
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for (unsigned idx = 0 ; idx < asn_->pin_count() ; idx += 1) {
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// XXXX FIXME: Objects need unique names!
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@ -170,7 +173,7 @@ void xnfsyn_f::proc_casn_(class Design*des)
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}
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/*
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* The process si far has been matches as:
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* The process so far has been matched as:
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*
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* always @(posedge nclk_) if ...;
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* always @(negedge nclk_) if ...;
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@ -197,7 +200,7 @@ void xnfsyn_f::proc_ccon_(class Design*des)
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if (ce->pin_count() != 1)
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return;
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// Geneate enough DFF objects to handle the entire width.
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// Generate enough DFF objects to handle the entire width.
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for (unsigned idx = 0 ; idx < asn_->pin_count() ; idx += 1) {
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// XXXX FIXME: Objects need unique names!
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@ -233,6 +236,9 @@ void xnfsyn(Design*des)
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/*
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* $Log: xnfsyn.cc,v $
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* Revision 1.3 1999/08/18 04:00:02 steve
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* Fixup spelling and some error messages. <LRDoolittle@lbl.gov>
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*
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* Revision 1.2 1999/07/18 21:17:51 steve
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* Add support for CE input to XNF DFF, and do
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* complete cleanup of replaced design nodes.
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