Unify the NetAssign constructors a bit.
This commit is contained in:
steve
parent
988e4f0d3d
commit
6a823cde59
20
elaborate.cc
20
elaborate.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: elaborate.cc,v 1.41 1999/06/13 04:46:54 steve Exp $"
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#ident "$Id: elaborate.cc,v 1.42 1999/06/13 16:30:06 steve Exp $"
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#endif
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/*
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@ -1056,7 +1056,10 @@ NetProc* PAssign::elaborate(Design*des, const string&path) const
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}
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assert(rval);
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NetAssign*cur = new NetAssign(des, reg, rval);
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NetAssign*cur = new NetAssign("@assign", des, reg, rval);
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for (unsigned idx = 0 ; idx < cur->pin_count() ; idx += 1)
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connect(cur->pin(idx), reg->pin(idx));
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cur->set_line(*this);
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des->add_node(cur);
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@ -1369,8 +1372,11 @@ NetProc* PForStatement::elaborate(Design*des, const string&path) const
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return 0;
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}
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assert(sig);
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NetAssign*init = new NetAssign(des, sig,
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NetAssign*init = new NetAssign("@for-assign", des, sig,
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expr1_->elaborate_expr(des, path));
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for (unsigned idx = 0 ; idx < init->pin_count() ; idx += 1)
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connect(init->pin(idx), sig->pin(idx));
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top->append(init);
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NetBlock*body = new NetBlock(NetBlock::SEQU);
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@ -1379,8 +1385,11 @@ NetProc* PForStatement::elaborate(Design*des, const string&path) const
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sig = des->find_signal(path+"."+id2->name());
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assert(sig);
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NetAssign*step = new NetAssign(des, sig,
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NetAssign*step = new NetAssign("@for-assign", des, sig,
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expr2_->elaborate_expr(des, path));
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for (unsigned idx = 0 ; idx < step->pin_count() ; idx += 1)
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connect(step->pin(idx), sig->pin(idx));
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body->append(step);
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NetWhile*loop = new NetWhile(cond_->elaborate_expr(des, path), body);
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@ -1498,6 +1507,9 @@ Design* elaborate(const map<string,Module*>&modules,
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/*
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* $Log: elaborate.cc,v $
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* Revision 1.42 1999/06/13 16:30:06 steve
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* Unify the NetAssign constructors a bit.
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*
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* Revision 1.41 1999/06/13 04:46:54 steve
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* Add part select lvalues to AssignNB.
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*
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34
netlist.cc
34
netlist.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: netlist.cc,v 1.35 1999/06/10 05:33:28 steve Exp $"
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#ident "$Id: netlist.cc,v 1.36 1999/06/13 16:30:06 steve Exp $"
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#endif
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# include <cassert>
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@ -273,14 +273,21 @@ NetProc::~NetProc()
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{
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}
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NetAssign::NetAssign(Design*des, NetNet*lv, NetExpr*rv)
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: NetNode("@assign", lv->pin_count()), rval_(rv)
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NetAssign_::NetAssign_(const string&n, unsigned w)
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: NetNode(n, w)
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{
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for (unsigned idx = 0 ; idx < pin_count() ; idx += 1) {
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for (unsigned idx = 0 ; idx < pin_count() ; idx += 1)
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pin(idx).set_dir(NetObj::Link::OUTPUT);
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connect(pin(idx), lv->pin(idx));
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}
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}
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NetAssign_::~NetAssign_()
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{
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}
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NetAssign::NetAssign(const string&n, Design*des, NetNet*lv, NetExpr*rv)
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: NetAssign_(n, lv->pin_count()), rval_(rv)
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{
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bool flag = rval_->set_width(lv->pin_count());
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if (flag == false) {
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cerr << rv->get_line() << ": Expression bit width" <<
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@ -294,12 +301,8 @@ NetAssign::~NetAssign()
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}
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NetAssignNB::NetAssignNB(const string&n, Design*des, unsigned w, NetExpr*rv)
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: NetNode(n, w), rval_(rv), bmux_(0)
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: NetAssign_(n, w), rval_(rv), bmux_(0)
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{
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for (unsigned idx = 0 ; idx < pin_count() ; idx += 1) {
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pin(idx).set_dir(NetObj::Link::OUTPUT);
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}
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bool flag = rval_->set_width(w);
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if (flag == false) {
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cerr << rv->get_line() << ": Expression bit width" <<
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@ -310,12 +313,8 @@ NetAssignNB::NetAssignNB(const string&n, Design*des, unsigned w, NetExpr*rv)
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NetAssignNB::NetAssignNB(const string&n, Design*des, unsigned w,
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NetExpr*mu, NetExpr*rv)
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: NetNode(n, w), rval_(rv), bmux_(mu)
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: NetAssign_(n, w), rval_(rv), bmux_(mu)
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{
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for (unsigned idx = 0 ; idx < pin_count() ; idx += 1) {
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pin(idx).set_dir(NetObj::Link::OUTPUT);
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}
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bool flag = rval_->set_width(1);
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if (flag == false) {
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cerr << rv->get_line() << ": Expression bit width" <<
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@ -1203,6 +1202,9 @@ NetNet* Design::find_signal(bool (*func)(const NetNet*))
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/*
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* $Log: netlist.cc,v $
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* Revision 1.36 1999/06/13 16:30:06 steve
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* Unify the NetAssign constructors a bit.
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*
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* Revision 1.35 1999/06/10 05:33:28 steve
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* Handle a few more operator bit widths.
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*
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19
netlist.h
19
netlist.h
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: netlist.h,v 1.37 1999/06/09 03:00:06 steve Exp $"
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#ident "$Id: netlist.h,v 1.38 1999/06/13 16:30:06 steve Exp $"
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#endif
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/*
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@ -566,9 +566,17 @@ class NetProc {
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* appears as a procedural statement AND a structural node. The
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* LineInfo is the location of the assignment statement in the source.
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*/
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class NetAssign : public NetProc, public NetNode, public LineInfo {
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class NetAssign_ : public NetProc, public NetNode, public LineInfo {
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protected:
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NetAssign_(const string&n, unsigned w);
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virtual ~NetAssign_() =0;
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};
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class NetAssign : public NetAssign_ {
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public:
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explicit NetAssign(Design*des, NetNet*lv, NetExpr*rv);
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explicit NetAssign(const string&, Design*des, NetNet*lv, NetExpr*rv);
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~NetAssign();
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const NetExpr*rval() const { return rval_; }
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@ -588,7 +596,7 @@ class NetAssign : public NetProc, public NetNode, public LineInfo {
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/*
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* ... and this is a non-blocking version of above.
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*/
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class NetAssignNB : public NetProc, public NetNode, public LineInfo {
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class NetAssignNB : public NetAssign_ {
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public:
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explicit NetAssignNB(const string&, Design*des, unsigned w, NetExpr*rv);
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explicit NetAssignNB(const string&, Design*des, unsigned w,
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@ -1237,6 +1245,9 @@ extern ostream& operator << (ostream&, NetNet::Type);
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/*
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* $Log: netlist.h,v $
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* Revision 1.38 1999/06/13 16:30:06 steve
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* Unify the NetAssign constructors a bit.
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*
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* Revision 1.37 1999/06/09 03:00:06 steve
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* Add support for procedural concatenation expression.
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*
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32
t-verilog.cc
32
t-verilog.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: t-verilog.cc,v 1.4 1999/05/01 02:57:53 steve Exp $"
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#ident "$Id: t-verilog.cc,v 1.5 1999/06/13 16:30:06 steve Exp $"
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#endif
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/*
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@ -43,7 +43,6 @@ class target_verilog : public target_t {
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virtual void logic(ostream&os, const NetLogic*);
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virtual void bufz(ostream&os, const NetBUFZ*);
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virtual void start_process(ostream&os, const NetProcTop*);
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virtual void proc_assign(ostream&os, const NetAssign*);
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virtual void proc_block(ostream&os, const NetBlock*);
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virtual void proc_delay(ostream&os, const NetPDelay*);
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virtual void proc_event(ostream&os, const NetPEvent*);
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@ -152,32 +151,6 @@ void target_verilog::start_process(ostream&os, const NetProcTop*proc)
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indent_ = 6;
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}
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void target_verilog::proc_assign(ostream&os, const NetAssign*net)
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{
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os << setw(indent_) << "";
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const NetNet*lval;
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unsigned msb, lsb;
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net->find_lval_range(lval, msb, lsb);
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if ((lsb == 0) && (msb == (lval->pin_count()-1))) {
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os << mangle(lval->name());
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} else if (msb == lsb) {
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os << mangle(lval->name()) << "[" << msb << "]";
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} else {
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os << mangle(lval->name()) << "[" << msb << ":" << lsb <<
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"]";
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}
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os << " = ";
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emit_expr_(os, net->rval());
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os << ";" << endl;
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}
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void target_verilog::emit_expr_(ostream&os, const NetExpr*expr)
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{
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@ -298,6 +271,9 @@ const struct target tgt_verilog = {
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/*
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* $Log: t-verilog.cc,v $
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* Revision 1.5 1999/06/13 16:30:06 steve
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* Unify the NetAssign constructors a bit.
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*
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* Revision 1.4 1999/05/01 02:57:53 steve
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* Handle much more complex event expressions.
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*
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