AngeloJacobo
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d5f1d600ea
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resolve verilator warnings and add option YOSYS for not using input real in functions
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2023-07-24 17:27:17 +08:00 |
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AngeloJacobo
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47ba90962a
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delete this later
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2023-07-23 10:16:19 +08:00 |
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AngeloJacobo
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234c587229
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working txt for autofpga
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2023-07-19 18:58:51 +08:00 |
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AngeloJacobo
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5486aa4429
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removed old
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2023-07-19 18:58:31 +08:00 |
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AngeloJacobo
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487b026f6c
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add test to wb2
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2023-07-19 18:50:23 +08:00 |
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AngeloJacobo
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c885e3286c
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update wcfg
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2023-07-19 18:48:59 +08:00 |
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AngeloJacobo
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60e40f9d35
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less simulation warning
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2023-07-19 18:48:31 +08:00 |
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AngeloJacobo
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e38859ef78
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resolved warning from vivado on IOBDELAY
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2023-07-19 18:47:24 +08:00 |
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AngeloJacobo
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7142dd9cdb
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added more registers and formal assertions to wb2
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2023-07-19 18:46:36 +08:00 |
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AngeloJacobo
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137e30ba36
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resolve vivado warnings
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2023-07-17 21:39:07 +08:00 |
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AngeloJacobo
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97e740139f
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resolved vivado warnings
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2023-07-17 21:38:20 +08:00 |
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AngeloJacobo
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983919d9df
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removed unneeded .* files
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2023-07-16 08:52:10 +08:00 |
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AngeloJacobo
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12c947afb1
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Merge branch 'main' of https://github.com/AngeloJacobo/DDR3_Controller into main
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2023-07-16 08:46:27 +08:00 |
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AngeloJacobo
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4f857e08f4
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add files back after git rm -r cached .
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2023-07-16 08:46:16 +08:00 |
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AngeloJacobo
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4e61060927
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update wcfg
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2023-07-16 08:40:04 +08:00 |
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AngeloJacobo
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b16c4d56cd
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fixed error due to missing port dm and incorrect IO type for aux
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2023-07-16 08:39:24 +08:00 |
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AngeloJacobo
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b80bda4a46
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resolve warning from verilator linting
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2023-07-16 08:38:20 +08:00 |
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AngeloJacobo
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019722bc70
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resolve warnings and errors from verilator linting
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2023-07-16 08:17:55 +08:00 |
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Angelo Jacobo
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9a29fba26b
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Update formal.gtkw
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2023-07-13 19:35:18 +08:00 |
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Angelo Jacobo
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c45fd85ee4
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Update formal_wb2.gtkw
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2023-07-13 19:34:56 +08:00 |
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Angelo Jacobo
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bd23827864
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delete, replace with much cleaner xsim/
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2023-07-13 19:29:20 +08:00 |
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AngeloJacobo
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352205c970
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test test
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2023-07-13 19:26:36 +08:00 |
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AngeloJacobo
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bad4ca3086
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delete
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2023-07-13 19:25:51 +08:00 |
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AngeloJacobo
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fb7f48b3b8
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add git ignore
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2023-07-13 19:19:43 +08:00 |
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AngeloJacobo
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b2fd0bf4fe
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add formal gtkw files
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2023-07-13 19:18:35 +08:00 |
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AngeloJacobo
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ac3af7f23f
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deleted
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2023-07-13 19:17:25 +08:00 |
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AngeloJacobo
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17e7040626
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set different FLY_BY_DELAY for each lanes
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2023-07-13 19:04:43 +08:00 |
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AngeloJacobo
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4273a172f5
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add wishbone 2 interface
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2023-07-13 18:57:35 +08:00 |
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AngeloJacobo
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29ef663d87
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set parameter FLY_BY_DELAY for each instantiated ddr3, the delay value is retrieved from 8192Mb_ddr3_parameters.vh
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2023-07-13 18:55:57 +08:00 |
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AngeloJacobo
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6655959514
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set different fly_by_delays for each lanes
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2023-07-13 18:54:25 +08:00 |
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AngeloJacobo
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ecb4cb5b2c
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moved FLY_BY_DELAY to this module so multiple instantiated ddr3 can have different set FLY_BY_DELAY
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2023-07-13 18:52:43 +08:00 |
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AngeloJacobo
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ee3d9d4be7
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moved phy to TOP and controller to MAIN, removed constraints for xdc file
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2023-07-13 18:50:56 +08:00 |
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AngeloJacobo
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ee83028986
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make stall and accessible outside, removed added assumptions with i_slave_busy
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2023-07-13 18:48:34 +08:00 |
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AngeloJacobo
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2541d0afcc
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added wishbone 2 ports
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2023-07-13 18:45:43 +08:00 |
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AngeloJacobo
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6fef8081ce
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delete copy
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2023-07-13 18:45:00 +08:00 |
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AngeloJacobo
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89c2b8fbd7
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set depth to 7 (minimum)
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2023-07-13 18:43:47 +08:00 |
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AngeloJacobo
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47766cb8e8
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added wishbone 2 and formally verified it
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2023-07-13 18:41:25 +08:00 |
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AngeloJacobo
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5904a4910d
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shortened formal depth from 9 to 7
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2023-07-09 09:34:03 +08:00 |
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AngeloJacobo
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b03ca1864f
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shortened formal depth from 17 to 9
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2023-07-08 10:19:58 +08:00 |
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AngeloJacobo
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25d7f3bffd
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update gtkw
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2023-07-06 20:33:48 +08:00 |
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AngeloJacobo
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a4d4e3a099
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change all to non-blocking
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2023-07-06 20:32:12 +08:00 |
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AngeloJacobo
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b3c9bdb650
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pass test for timing params with depth of 9
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2023-07-06 20:29:50 +08:00 |
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AngeloJacobo
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69c34dbf8f
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update logs
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2023-07-05 19:48:14 +08:00 |
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AngeloJacobo
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1881e059bc
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add summary log of regression test (not yet complete)
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2023-07-05 19:47:00 +08:00 |
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AngeloJacobo
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10c290f9f8
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temp newest version
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2023-07-05 19:46:18 +08:00 |
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AngeloJacobo
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122e2a2d3c
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exported simulation scripts from Vivado
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2023-07-05 16:50:40 +08:00 |
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AngeloJacobo
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ec6488f68f
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gtkw for testing time parameters
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2023-07-05 16:48:40 +08:00 |
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AngeloJacobo
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ab17b8012b
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add average rate in report
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2023-07-05 16:44:31 +08:00 |
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AngeloJacobo
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7af3358162
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update vivado wcfg file
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2023-07-05 16:42:48 +08:00 |
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AngeloJacobo
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3250d8d368
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write dqs toggles for half slow clk cycle at the end, needed when DQ is set to be delayed (non-zero flyby delay)
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2023-07-05 16:41:55 +08:00 |