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UberDDR3
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This commit is contained in:
AngeloJacobo 2023-07-13 19:17:25 +08:00
parent 17e7040626
commit ac3af7f23f
18 changed files with 0 additions and 124282 deletions
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141
formal_cover.gtkw
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@ -1,141 +0,0 @@
[*]
[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
[*] Thu Apr 6 11:31:18 2023
[*]
[dumpfile] "/home/angelo/Videos/DDR3_Controller/ddr3_controller/engine_0/trace0.vcd"
[dumpfile_mtime] "Thu Apr 6 11:30:02 2023"
[dumpfile_size] 69448
[savefile] "/home/angelo/Videos/DDR3_Controller/formal_cover.gtkw"
[timestart] 0
[size] 1848 1126
[pos] -51 -51
*-5.094873 174 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[sst_width] 43
[signals_width] 468
[sst_expanded] 0
[sst_vpaned_height] 743
@28
ddr3_controller.i_clk
ddr3_controller.i_rst_n
ddr3_controller.i_wb_cyc
ddr3_controller.o_wb_stall
ddr3_controller.i_wb_stb
ddr3_controller.i_wb_we
@c00022
ddr3_controller.f_index[4:0]
@28
(0)ddr3_controller.f_index[4:0]
(1)ddr3_controller.f_index[4:0]
(2)ddr3_controller.f_index[4:0]
(3)ddr3_controller.f_index[4:0]
(4)ddr3_controller.f_index[4:0]
@1401200
-group_end
@200
-
@22
ddr3_controller.i_wb_addr[23:0]
ddr3_controller.i_wb_data[511:0]
ddr3_controller.i_wb_sel[63:0]
@28
ddr3_controller.o_wb_ack
@200
-
@28
ddr3_controller.bank_status_q[7:0]
@22
ddr3_controller.bank_active_row_q<0>[13:0]
ddr3_controller.bank_active_row_q<1>[13:0]
@24
ddr3_controller.bank_active_row_q<2>[13:0]
@22
ddr3_controller.bank_active_row_q<3>[13:0]
ddr3_controller.bank_active_row_q<4>[13:0]
ddr3_controller.bank_active_row_q<5>[13:0]
ddr3_controller.bank_active_row_q<6>[13:0]
ddr3_controller.bank_active_row_q<7>[13:0]
@200
-
-[0] = WR , [1] = ACT, [2] = RD, [3] = PRE
@22
ddr3_controller.cmd_q<0>[20:0]
ddr3_controller.cmd_q<1>[20:0]
ddr3_controller.cmd_q<2>[20:0]
ddr3_controller.cmd_q<3>[20:0]
@200
-
@28
ddr3_controller.stage1_pending
ddr3_controller.stage1_bank[2:0]
@22
ddr3_controller.stage1_row[13:0]
ddr3_controller.stage1_col[9:0]
@28
ddr3_controller.stage1_next_bank[2:0]
@22
ddr3_controller.stage1_next_row[13:0]
@28
ddr3_controller.stage1_we
@200
-
@28
ddr3_controller.stage2_pending
ddr3_controller.stage2_bank[2:0]
@22
ddr3_controller.stage2_row[13:0]
ddr3_controller.stage2_col[9:0]
@28
ddr3_controller.stage2_we
@200
-
@28
ddr3_controller.reset_done
@200
-
-DELAYS
@22
ddr3_controller.delay_before_precharge_counter_q<0>[3:0]
ddr3_controller.delay_before_precharge_counter_q<1>[3:0]
ddr3_controller.delay_before_precharge_counter_q<2>[3:0]
ddr3_controller.delay_before_precharge_counter_q<3>[3:0]
ddr3_controller.delay_before_precharge_counter_q<4>[3:0]
ddr3_controller.delay_before_precharge_counter_q<5>[3:0]
ddr3_controller.delay_before_precharge_counter_q<6>[3:0]
ddr3_controller.delay_before_precharge_counter_q<7>[3:0]
@200
-
@22
ddr3_controller.delay_before_activate_counter_q<0>[3:0]
ddr3_controller.delay_before_activate_counter_q<1>[3:0]
ddr3_controller.delay_before_activate_counter_q<2>[3:0]
ddr3_controller.delay_before_activate_counter_q<3>[3:0]
ddr3_controller.delay_before_activate_counter_q<4>[3:0]
ddr3_controller.delay_before_activate_counter_q<5>[3:0]
ddr3_controller.delay_before_activate_counter_q<6>[3:0]
ddr3_controller.delay_before_activate_counter_q<7>[3:0]
@200
-
@22
ddr3_controller.delay_before_read_counter_q<0>[3:0]
ddr3_controller.delay_before_read_counter_q<1>[3:0]
ddr3_controller.delay_before_read_counter_q<2>[3:0]
ddr3_controller.delay_before_read_counter_q<3>[3:0]
ddr3_controller.delay_before_read_counter_q<4>[3:0]
ddr3_controller.delay_before_read_counter_q<5>[3:0]
ddr3_controller.delay_before_read_counter_q<6>[3:0]
ddr3_controller.delay_before_read_counter_q<7>[3:0]
@200
-
@22
ddr3_controller.delay_before_write_counter_q<0>[3:0]
ddr3_controller.delay_before_write_counter_q<1>[3:0]
ddr3_controller.delay_before_write_counter_q<2>[3:0]
ddr3_controller.delay_before_write_counter_q<3>[3:0]
ddr3_controller.delay_before_write_counter_q<4>[3:0]
ddr3_controller.delay_before_write_counter_q<5>[3:0]
ddr3_controller.delay_before_write_counter_q<6>[3:0]
ddr3_controller.delay_before_write_counter_q<7>[3:0]
@200
-
[pattern_trace] 1
[pattern_trace] 0

1049
formal_cover_3.gtkw
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File diff suppressed because it is too large Load Diff

278
formal_test_time.gtkw
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@ -1,278 +0,0 @@
[*]
[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
[*] Thu Jul 6 11:33:00 2023
[*]
[dumpfile] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/ddr3_controller/engine_0/trace_induct.vcd"
[dumpfile_mtime] "Thu Jul 6 11:26:58 2023"
[dumpfile_size] 118405
[savefile] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/formal_test_time.gtkw"
[timestart] 0
[size] 1848 1126
[pos] -1 -1
*-4.455849 76 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] ddr3_controller.
[sst_width] 391
[signals_width] 419
[sst_expanded] 1
[sst_vpaned_height] 743
@420
smt_step
@28
ddr3_controller.i_controller_clk
ddr3_controller.i_rst_n
ddr3_controller.reset_done
@24
ddr3_controller.state_calibrate[4:0]
ddr3_controller.instruction_address[4:0]
@28
ddr3_controller.instruction[27:0]
@24
ddr3_controller.delay_counter[15:0]
@28
ddr3_controller.o_wb_stall_q
@29
ddr3_controller.o_wb_stall_d
@28
ddr3_controller.o_wb_stall
ddr3_controller.delay_counter_is_zero
ddr3_controller.pause_counter
@200
-
-
@28
+{ddr3_controller.[ACT] cmd_d<0>[23:0]} ddr3_controller.cmd_d<0>[23:0]
@c00028
+{ddr3_controller.[PRE] cmd_d<1>[23:0]} ddr3_controller.cmd_d<1>[23:0]
@28
(0)ddr3_controller.cmd_d<1>[23:0]
(1)ddr3_controller.cmd_d<1>[23:0]
(2)ddr3_controller.cmd_d<1>[23:0]
(3)ddr3_controller.cmd_d<1>[23:0]
(4)ddr3_controller.cmd_d<1>[23:0]
(5)ddr3_controller.cmd_d<1>[23:0]
(6)ddr3_controller.cmd_d<1>[23:0]
(7)ddr3_controller.cmd_d<1>[23:0]
(8)ddr3_controller.cmd_d<1>[23:0]
(9)ddr3_controller.cmd_d<1>[23:0]
(10)ddr3_controller.cmd_d<1>[23:0]
(11)ddr3_controller.cmd_d<1>[23:0]
(12)ddr3_controller.cmd_d<1>[23:0]
(13)ddr3_controller.cmd_d<1>[23:0]
(14)ddr3_controller.cmd_d<1>[23:0]
(15)ddr3_controller.cmd_d<1>[23:0]
(16)ddr3_controller.cmd_d<1>[23:0]
(17)ddr3_controller.cmd_d<1>[23:0]
(18)ddr3_controller.cmd_d<1>[23:0]
(19)ddr3_controller.cmd_d<1>[23:0]
(20)ddr3_controller.cmd_d<1>[23:0]
(21)ddr3_controller.cmd_d<1>[23:0]
(22)ddr3_controller.cmd_d<1>[23:0]
(23)ddr3_controller.cmd_d<1>[23:0]
@1401200
-group_end
@c00028
+{ddr3_controller.[RD] cmd_d<2>[23:0]} ddr3_controller.cmd_d<2>[23:0]
@28
(0)ddr3_controller.cmd_d<2>[23:0]
(1)ddr3_controller.cmd_d<2>[23:0]
(2)ddr3_controller.cmd_d<2>[23:0]
(3)ddr3_controller.cmd_d<2>[23:0]
(4)ddr3_controller.cmd_d<2>[23:0]
(5)ddr3_controller.cmd_d<2>[23:0]
(6)ddr3_controller.cmd_d<2>[23:0]
(7)ddr3_controller.cmd_d<2>[23:0]
(8)ddr3_controller.cmd_d<2>[23:0]
(9)ddr3_controller.cmd_d<2>[23:0]
(10)ddr3_controller.cmd_d<2>[23:0]
(11)ddr3_controller.cmd_d<2>[23:0]
(12)ddr3_controller.cmd_d<2>[23:0]
(13)ddr3_controller.cmd_d<2>[23:0]
(14)ddr3_controller.cmd_d<2>[23:0]
(15)ddr3_controller.cmd_d<2>[23:0]
(16)ddr3_controller.cmd_d<2>[23:0]
(17)ddr3_controller.cmd_d<2>[23:0]
(18)ddr3_controller.cmd_d<2>[23:0]
(19)ddr3_controller.cmd_d<2>[23:0]
(20)ddr3_controller.cmd_d<2>[23:0]
(21)ddr3_controller.cmd_d<2>[23:0]
(22)ddr3_controller.cmd_d<2>[23:0]
(23)ddr3_controller.cmd_d<2>[23:0]
@1401200
-group_end
@28
+{ddr3_controller.[WR] cmd_d<3>[23:0]} ddr3_controller.cmd_d<3>[23:0]
@200
-
@28
ddr3_controller.bank_status_q[7:0]
@200
-
@28
ddr3_controller.stage1_pending
ddr3_controller.stage2_pending
ddr3_controller.stage2_update
@200
-
@24
ddr3_controller.bank_const[2:0]
ddr3_controller.f_timer[6:0]
ddr3_controller.f_activate_time_stamp<0>[6:0]
ddr3_controller.f_activate_time_stamp<1>[6:0]
ddr3_controller.f_activate_time_stamp<2>[6:0]
ddr3_controller.f_activate_time_stamp<3>[6:0]
ddr3_controller.f_activate_time_stamp<4>[6:0]
ddr3_controller.f_activate_time_stamp<5>[6:0]
ddr3_controller.f_activate_time_stamp<6>[6:0]
ddr3_controller.f_activate_time_stamp<7>[6:0]
@22
ddr3_controller.delay_before_precharge_counter_q<0>[3:0]
@24
ddr3_controller.f_precharge_time_stamp<0>[6:0]
@22
ddr3_controller.f_precharge_time_stamp<1>[6:0]
ddr3_controller.f_precharge_time_stamp<2>[6:0]
ddr3_controller.f_precharge_time_stamp<3>[6:0]
ddr3_controller.f_precharge_time_stamp<4>[6:0]
ddr3_controller.f_precharge_time_stamp<5>[6:0]
ddr3_controller.f_precharge_time_stamp<6>[6:0]
ddr3_controller.f_precharge_time_stamp<7>[6:0]
@24
ddr3_controller.f_read_time_stamp<0>[6:0]
ddr3_controller.f_read_time_stamp<1>[6:0]
ddr3_controller.f_read_time_stamp<2>[6:0]
ddr3_controller.f_read_time_stamp<3>[6:0]
ddr3_controller.f_read_time_stamp<4>[6:0]
ddr3_controller.f_read_time_stamp<5>[6:0]
ddr3_controller.f_read_time_stamp<6>[6:0]
ddr3_controller.f_read_time_stamp<7>[6:0]
ddr3_controller.f_write_time_stamp<0>[6:0]
ddr3_controller.f_write_time_stamp<1>[6:0]
ddr3_controller.f_write_time_stamp<2>[6:0]
ddr3_controller.f_write_time_stamp<3>[6:0]
ddr3_controller.f_write_time_stamp<4>[6:0]
ddr3_controller.f_write_time_stamp<5>[6:0]
ddr3_controller.f_write_time_stamp<6>[6:0]
ddr3_controller.f_write_time_stamp<7>[6:0]
@28
ddr3_controller.i_wb_stb
ddr3_controller.o_wb_stall
ddr3_controller.i_wb_cyc
ddr3_controller.o_wb_ack
ddr3_controller.o_wb_stall_d
ddr3_controller.o_wb_stall_q
ddr3_controller.delay_counter_is_zero
@200
-
@28
ddr3_controller.stage1_stall
ddr3_controller.stage1_pending
ddr3_controller.stage1_we
@22
ddr3_controller.stage1_aux[15:0]
@24
ddr3_controller.stage1_bank[2:0]
@22
ddr3_controller.stage1_col[9:0]
ddr3_controller.stage1_row[13:0]
@200
-
@28
ddr3_controller.stage2_stall
ddr3_controller.stage2_pending
ddr3_controller.stage2_update
ddr3_controller.stage2_we
@c00022
ddr3_controller.stage2_aux[15:0]
@28
(0)ddr3_controller.stage2_aux[15:0]
(1)ddr3_controller.stage2_aux[15:0]
(2)ddr3_controller.stage2_aux[15:0]
(3)ddr3_controller.stage2_aux[15:0]
(4)ddr3_controller.stage2_aux[15:0]
(5)ddr3_controller.stage2_aux[15:0]
(6)ddr3_controller.stage2_aux[15:0]
(7)ddr3_controller.stage2_aux[15:0]
(8)ddr3_controller.stage2_aux[15:0]
(9)ddr3_controller.stage2_aux[15:0]
(10)ddr3_controller.stage2_aux[15:0]
(11)ddr3_controller.stage2_aux[15:0]
(12)ddr3_controller.stage2_aux[15:0]
(13)ddr3_controller.stage2_aux[15:0]
(14)ddr3_controller.stage2_aux[15:0]
(15)ddr3_controller.stage2_aux[15:0]
@1401200
-group_end
@24
ddr3_controller.stage2_bank[2:0]
@22
ddr3_controller.stage2_col[9:0]
ddr3_controller.stage2_row[13:0]
@200
-
@28
+{ddr3_controller.[ACT] cmd_d<0>[23:0]} ddr3_controller.cmd_d<0>[23:0]
@c00028
+{ddr3_controller.[PRE] cmd_d<1>[23:0]} ddr3_controller.cmd_d<1>[23:0]
@28
(0)ddr3_controller.cmd_d<1>[23:0]
(1)ddr3_controller.cmd_d<1>[23:0]
(2)ddr3_controller.cmd_d<1>[23:0]
(3)ddr3_controller.cmd_d<1>[23:0]
(4)ddr3_controller.cmd_d<1>[23:0]
(5)ddr3_controller.cmd_d<1>[23:0]
(6)ddr3_controller.cmd_d<1>[23:0]
(7)ddr3_controller.cmd_d<1>[23:0]
(8)ddr3_controller.cmd_d<1>[23:0]
(9)ddr3_controller.cmd_d<1>[23:0]
(10)ddr3_controller.cmd_d<1>[23:0]
(11)ddr3_controller.cmd_d<1>[23:0]
(12)ddr3_controller.cmd_d<1>[23:0]
(13)ddr3_controller.cmd_d<1>[23:0]
(14)ddr3_controller.cmd_d<1>[23:0]
(15)ddr3_controller.cmd_d<1>[23:0]
(16)ddr3_controller.cmd_d<1>[23:0]
(17)ddr3_controller.cmd_d<1>[23:0]
(18)ddr3_controller.cmd_d<1>[23:0]
(19)ddr3_controller.cmd_d<1>[23:0]
(20)ddr3_controller.cmd_d<1>[23:0]
(21)ddr3_controller.cmd_d<1>[23:0]
(22)ddr3_controller.cmd_d<1>[23:0]
(23)ddr3_controller.cmd_d<1>[23:0]
@1401200
-group_end
@c00028
+{ddr3_controller.[RD] cmd_d<2>[23:0]} ddr3_controller.cmd_d<2>[23:0]
@28
(0)ddr3_controller.cmd_d<2>[23:0]
(1)ddr3_controller.cmd_d<2>[23:0]
(2)ddr3_controller.cmd_d<2>[23:0]
(3)ddr3_controller.cmd_d<2>[23:0]
(4)ddr3_controller.cmd_d<2>[23:0]
(5)ddr3_controller.cmd_d<2>[23:0]
(6)ddr3_controller.cmd_d<2>[23:0]
(7)ddr3_controller.cmd_d<2>[23:0]
(8)ddr3_controller.cmd_d<2>[23:0]
(9)ddr3_controller.cmd_d<2>[23:0]
(10)ddr3_controller.cmd_d<2>[23:0]
(11)ddr3_controller.cmd_d<2>[23:0]
(12)ddr3_controller.cmd_d<2>[23:0]
(13)ddr3_controller.cmd_d<2>[23:0]
(14)ddr3_controller.cmd_d<2>[23:0]
(15)ddr3_controller.cmd_d<2>[23:0]
(16)ddr3_controller.cmd_d<2>[23:0]
(17)ddr3_controller.cmd_d<2>[23:0]
(18)ddr3_controller.cmd_d<2>[23:0]
(19)ddr3_controller.cmd_d<2>[23:0]
(20)ddr3_controller.cmd_d<2>[23:0]
(21)ddr3_controller.cmd_d<2>[23:0]
(22)ddr3_controller.cmd_d<2>[23:0]
(23)ddr3_controller.cmd_d<2>[23:0]
@1401200
-group_end
@28
+{ddr3_controller.[WR] cmd_d<3>[23:0]} ddr3_controller.cmd_d<3>[23:0]
@200
-
-
[pattern_trace] 1
[pattern_trace] 0

106
log_regression_test.log
View File

@ -1,106 +0,0 @@
BUS_DELAY: 0 ps
FLY_BY_DELAY: 0 ps
Log File: sim_busdelay0_flybydelay0.log
------- SUMMARY -------
Number of Writes = 4608
Number of Reads = 4608
Number of Success = 4604
Number of Fails = 4
Number of Injected Errors = 4
$stop called at time : 250810 ns : File "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" Line 456
run: Time (s): cpu = 00:00:16 ; elapsed = 00:47:46 . Memory (MB): peak = 2833.148 ; gain = 8.004 ; free physical = 1332 ; free virtual = 24744
## quit
INFO: xsimkernel Simulation Memory Usage: 305696 KB (Peak: 371232 KB), Simulation CPU Usage: 2805770 ms
INFO: [Common 17-206] Exiting xsim at Wed Jul 5 14:58:39 2023...
BUS_DELAY: 625 ps
FLY_BY_DELAY: 0 ps
Log File: sim_busdelay625_flybydelay0.log
------- SUMMARY -------
Number of Writes = 4608
Number of Reads = 4608
Number of Success = 4604
Number of Fails = 4
Number of Injected Errors = 4
$stop called at time : 234810 ns : File "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" Line 456
run: Time (s): cpu = 00:00:15 ; elapsed = 00:44:56 . Memory (MB): peak = 2833.148 ; gain = 8.004 ; free physical = 1358 ; free virtual = 24780
## quit
INFO: xsimkernel Simulation Memory Usage: 305696 KB (Peak: 371232 KB), Simulation CPU Usage: 2640970 ms
INFO: [Common 17-206] Exiting xsim at Wed Jul 5 15:46:48 2023...
BUS_DELAY: 1250 ps
FLY_BY_DELAY: 600 ps
Log File: sim_busdelay1250_flybydelay600.log
------- SUMMARY -------
Number of Writes = 4608
Number of Reads = 4608
Number of Success = 4604
Number of Fails = 4
Number of Injected Errors = 4
$stop called at time : 284 us : File "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" Line 456
run: Time (s): cpu = 00:00:17 ; elapsed = 00:53:20 . Memory (MB): peak = 2833.148 ; gain = 8.004 ; free physical = 1238 ; free virtual = 24677
## quit
INFO: xsimkernel Simulation Memory Usage: 305696 KB (Peak: 371232 KB), Simulation CPU Usage: 3147150 ms
INFO: [Common 17-206] Exiting xsim at Wed Jul 5 16:43:17 2023...
BUS_DELAY: 1875 ps
FLY_BY_DELAY: 1000 ps
Log File: sim_busdelay1875_flybydelay1000.log
------- SUMMARY -------
Number of Writes = 4608
Number of Reads = 4608
Number of Success = 4604
Number of Fails = 4
Number of Injected Errors = 4
$stop called at time : 261610 ns : File "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" Line 456
run: Time (s): cpu = 00:00:17 ; elapsed = 00:57:38 . Memory (MB): peak = 2833.148 ; gain = 8.004 ; free physical = 174 ; free virtual = 23702
## quit
INFO: xsimkernel Simulation Memory Usage: 305696 KB (Peak: 371232 KB), Simulation CPU Usage: 2965430 ms
INFO: [Common 17-206] Exiting xsim at Wed Jul 5 17:44:52 2023...
BUS_DELAY: 2500 ps
FLY_BY_DELAY: 1500 ps
Log File: sim_busdelay2500_flybydelay1500.log
------- SUMMARY -------
Number of Writes = 4608
Number of Reads = 4608
Number of Success = 4604
Number of Fails = 4
Number of Injected Errors = 4
$stop called at time : 277970 ns : File "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" Line 456
run: Time (s): cpu = 00:00:18 ; elapsed = 00:59:53 . Memory (MB): peak = 2833.148 ; gain = 476.559 ; free physical = 1580 ; free virtual = 24408
## quit
INFO: xsimkernel Simulation Memory Usage: 305696 KB (Peak: 371232 KB), Simulation CPU Usage: 3147790 ms
INFO: [Common 17-206] Exiting xsim at Wed Jul 5 18:48:36 2023...
BUS_DELAY: 5000 ps
FLY_BY_DELAY: 2200 ps
Log File: sim_busdelay5000_flybydelay2200.log
------- SUMMARY -------
Number of Writes = 4608
Number of Reads = 4608
Number of Success = 4604
Number of Fails = 4
Number of Injected Errors = 4
$stop called at time : 273380 ns : File "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" Line 456
run: Time (s): cpu = 00:00:16 ; elapsed = 00:52:07 . Memory (MB): peak = 2833.148 ; gain = 8.004 ; free physical = 1814 ; free virtual = 24675
## quit
INFO: xsimkernel Simulation Memory Usage: 305696 KB (Peak: 371232 KB), Simulation CPU Usage: 3030440 ms
INFO: [Common 17-206] Exiting xsim at Wed Jul 5 19:44:03 2023...
BUS_DELAY: 10000 ps
FLY_BY_DELAY: 3000 ps
Log File: sim_busdelay10000_flybydelay3000.log

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new_formal.gtkw
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[*]
[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
[*] Tue Jun 27 09:57:53 2023
[*]
[dumpfile] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/ddr3_controller/engine_0/trace0.vcd"
[dumpfile_mtime] "Tue Jun 27 08:16:33 2023"
[dumpfile_size] 370354
[savefile] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/new_formal.gtkw"
[timestart] 167
[size] 1848 1126
[pos] -51 -51
*-4.943873 244 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[sst_width] 369
[signals_width] 430
[sst_expanded] 1
[sst_vpaned_height] 743
@420
smt_step
@28
ddr3_controller.i_controller_clk
ddr3_controller.i_rst_n
@24
ddr3_controller.state_calibrate[3:0]
ddr3_controller.instruction_address[4:0]
@28
ddr3_controller.reset_done
@200
-
-WB Interface
@28
ddr3_controller.i_wb_cyc
ddr3_controller.o_wb_stall
ddr3_controller.i_wb_stb
ddr3_controller.i_wb_we
@22
ddr3_controller.i_wb_addr[23:0]
ddr3_controller.i_wb_data[511:0]
ddr3_controller.i_wb_sel[63:0]
@28
ddr3_controller.o_wb_ack
@200
-
-Internals
@28
ddr3_controller.stage1_pending
ddr3_controller.stage1_we
@24
ddr3_controller.stage1_bank[2:0]
ddr3_controller.stage1_col[9:0]
@25
ddr3_controller.stage1_row[13:0]
@24
ddr3_controller.stage1_stall
@204
-
@24
ddr3_controller.stage2_pending
ddr3_controller.stage2_we
ddr3_controller.stage2_bank[2:0]
ddr3_controller.stage2_col[9:0]
ddr3_controller.stage2_row[13:0]
ddr3_controller.stage2_stall
@200
-
@28
ddr3_controller.bank_status_q[7:0]
@22
ddr3_controller.delay_before_precharge_counter_q<1>[3:0]
ddr3_controller.delay_before_precharge_counter_q<2>[3:0]
ddr3_controller.delay_before_activate_counter_q<1>[3:0]
ddr3_controller.delay_before_activate_counter_q<2>[3:0]
ddr3_controller.delay_before_read_counter_q<1>[3:0]
ddr3_controller.delay_before_read_counter_q<2>[3:0]
ddr3_controller.delay_before_write_counter_q<1>[3:0]
ddr3_controller.delay_before_write_counter_q<2>[3:0]
@200
-
-CMD
@28
+{ddr3_controller.[ACT] cmd_d<0>[23:0]} ddr3_controller.cmd_d<0>[23:0]
+{ddr3_controller.[PRE] cmd_d<1>[23:0]} ddr3_controller.cmd_d<1>[23:0]
+{ddr3_controller.[RD] cmd_d<2>[23:0]} ddr3_controller.cmd_d<2>[23:0]
+{ddr3_controller.[WR] cmd_d<3>[23:0]} ddr3_controller.cmd_d<3>[23:0]
@200
-
-Formal
@24
ddr3_controller.f_index[4:0]
[pattern_trace] 1
[pattern_trace] 0

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xsim/.sim.py.swp
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xsim/sim_busdelay0.log
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ddr3_dimm_micron_sim.sh - Script generated by export_simulation (Vivado v2021.2 (64-bit)-id)
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr3
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr3_dimm
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr3_dimm_micron_sim
Vivado Simulator v2021.2
Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
Running: /tools/Xilinx/Vivado/2021.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt auto -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:204]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:135]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:156]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:157]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:158]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 5 for port 'CNTVALUEIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:159]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:160]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LD' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:161]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:163]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:165]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:250]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:275]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:276]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:281]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:283]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:319]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:325]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:326]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:374]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:375]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'TCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:426]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:427]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:452]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:453]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:458]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:460]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:497]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:498]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:499]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:501]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:504]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:506]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:536]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:575]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:576]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:580]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:582]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:583]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:631]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:632]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:700]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:701]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:747]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:163]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:164]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'cke' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:165]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 's_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:166]
WARNING: [VRFC 10-3091] actual bit length 14 differs from formal bit length 16 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:171]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'odt' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:172]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:173]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:174]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:203]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:204]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:205]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:206]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:207]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:208]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:209]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:210]
WARNING: [VRFC 10-5021] port 'scl' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:161]
WARNING: [VRFC 10-5021] port 'i_controller_dm' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v:119]
Completed static elaboration
Starting simulation data flow analysis
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale.
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.ddr3_controller(CONTROLLER_CLK_P...
Compiling module unisims_ver.OSERDESE2(DATA_RATE_OQ="SDR",DAT...
Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="...
Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="SDR",DAT...
Compiling module unisims_ver.OBUFDS
Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT...
Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="...
Compiling module unisims_ver.IOBUF(IOSTANDARD="SSTL15",SLEW="...
Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="...
Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE...
Compiling module unisims_ver.OBUF(SLEW="FAST")
Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="...
Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT...
Compiling module unisims_ver.IOBUFDS(IOSTANDARD="DIFF_SSTL15"...
Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="...
Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE...
Compiling module unisims_ver.IDELAYCTRL_default
Compiling module xil_defaultlib.ddr3_phy(CONTROLLER_CLK_PERIOD=1...
Compiling module xil_defaultlib.ddr3_top(CONTROLLER_CLK_PERIOD=1...
Compiling module xil_defaultlib.ddr3_default
Compiling module xil_defaultlib.ddr3_dimm_default
Compiling module xil_defaultlib.ddr3_dimm_micron_sim
Compiling module xil_defaultlib.glbl
Built simulation snapshot ddr3_dimm_micron_sim
****** xsim v2021.2 (64-bit)
**** SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
**** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
source xsim.dir/ddr3_dimm_micron_sim/xsim_script.tcl
# xsim {ddr3_dimm_micron_sim} -autoloadwcfg -tclbatch {cmd.tcl} -key {Behavioral:sim_1:Functional:ddr3_dimm_micron_sim}
Time resolution is 1 ps
source cmd.tcl
## set curr_wave [current_wave_config]
## if { [string length $curr_wave] == 0 } {
## if { [llength [get_objects]] > 0} {
## add_wave /
## set_property needs_save false [current_wave_config]
## } else {
## send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
## }
## }
## run -all
Test ns_to_cycles() function:
ns_to_cycles(15) = 3 = 2 [exact]
ns_to_cycles(14.5) = 3 = 2 [round-off]
ns_to_cycles(11) = 3 = 2 [round-up]
Test nCK_to_cycles() function:
ns_to_cycles(16) = 4 = 4 [exact]
ns_to_cycles(15) = 4 = 4 [round-off]
ns_to_cycles(13) = 4 = 4 [round-up]
Test ns_to_nCK() function:
ns_to_cycles(15) = 12 = 6 [exact]
ns_to_cycles(14.875) = 12 = 6 [round-off]
ns_to_cycles(13.875) = 12 = 6 [round-up]
ns_to_nCK(tRCD) = 11 = 6 [WRONG]
tRTP = 7.5 = 10.000000
ns_to_nCK(tRTP) = 6= 4.000000 [WRONG]
Test nCK_to_ns() function:
ns_to_cycles(4) = 5 = 10 [exact]
ns_to_cycles(14.875) = 4 = 8 [round-off]
ns_to_cycles(13.875) = 7 = 13 [round-up]
Test nCK_to_ns() function:
ns_to_cycles(4) = 5 = 10 [exact]
ns_to_cycles(14.875) = 4 = 8 [round-off]
ns_to_cycles(13.875) = 7 = 13 [round-up]
Test $floor() function:
$floor(5/2) = 2.5 = 2
$floor(9/4) = 2.25 = 2
$floor(9/4) = 2 = 2
$floor(9/5) = 1.8 = 1
DELAY_COUNTER_WIDTH = 16
DELAY_SLOT_WIDTH = 19
serdes_ratio = 4
wb_addr_bits = 24
wb_data_bits = 512
wb_sel_bits = 64
READ_SLOT = 2
WRITE_SLOT = 3
ACTIVATE_SLOT = 0
PRECHARGE_SLOT = 1
DELAYS:
ns_to_nCK(tRCD): 6
ns_to_nCK(tRP): 6
ns_to_nCK(tRTP): 4
tCCD: 4
(CL_nCK + tCCD + 3'd2 - CWL_nCK): 7
(CWL_nCK + 3'd4 + ns_to_nCK(tWR)): 15
(CWL_nCK + 3'd4 + ns_to_nCK(tWTR)): 13
$signed(4'b1100)>>>4: 1111
PRECHARGE_TO_ACTIVATE_DELAY = 3 = 1
ACTIVATE_TO_WRITE_DELAY = 3 = 0
ACTIVATE_TO_READ_DELAY = 2 = 0
READ_TO_WRITE_DELAY = 2 = 1
READ_TO_READ_DELAY = 0 = 0
READ_TO_PRECHARGE_DELAY = 1 =1
WRITE_TO_WRITE_DELAY = 0 = 0
WRITE_TO_READ_DELAY = 4 = 3
WRITE_TO_PRECHARGE_DELAY = 5 = 4
STAGE2_DATA_DEPTH = 2 = 2
READ_ACK_PIPE_WIDTH = 6
ddr3_dimm_micron_sim.ddr3_dimm.U1.file_io_open: at time 0 WARNING: no +model_data option specified, using /tmp.
ddr3_dimm_micron_sim.ddr3_dimm.U2.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
ddr3_dimm_micron_sim.ddr3_dimm.U3.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
ddr3_dimm_micron_sim.ddr3_dimm.U4.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
ddr3_dimm_micron_sim.ddr3_dimm.U6.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
ddr3_dimm_micron_sim.ddr3_dimm.U7.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
ddr3_dimm_micron_sim.ddr3_dimm.U8.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
ddr3_dimm_micron_sim.ddr3_dimm.U9.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
[x ps] MRS -> [ 7500 ps] MRS -> [195000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.reset at time 314324.0 ps WARNING: 200 us is required before RST_N goes inactive.
ddr3_dimm_micron_sim.ddr3_dimm.U2.reset at time 314324.0 ps WARNING: 200 us is required before RST_N goes inactive.
ddr3_dimm_micron_sim.ddr3_dimm.U3.reset at time 314324.0 ps WARNING: 200 us is required before RST_N goes inactive.
ddr3_dimm_micron_sim.ddr3_dimm.U4.reset at time 314324.0 ps WARNING: 200 us is required before RST_N goes inactive.
ddr3_dimm_micron_sim.ddr3_dimm.U6.reset at time 314324.0 ps WARNING: 200 us is required before RST_N goes inactive.
ddr3_dimm_micron_sim.ddr3_dimm.U7.reset at time 314324.0 ps WARNING: 200 us is required before RST_N goes inactive.
ddr3_dimm_micron_sim.ddr3_dimm.U8.reset at time 314324.0 ps WARNING: 200 us is required before RST_N goes inactive.
ddr3_dimm_micron_sim.ddr3_dimm.U9.reset at time 314324.0 ps WARNING: 200 us is required before RST_N goes inactive.
[510000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task at time 825600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task at time 825600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task at time 825600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task at time 825600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task at time 825600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task at time 825600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task at time 825600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task at time 825600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
[370000 ps] MRS ->
[10000 ps] MRS -> ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1198100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1198100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1198100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1198100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1198100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1198100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1198100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1198100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
[10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP -> [40000 ps] ZQC ->
[1290000 ps] PRE @ (0) -> [30000 ps] MRS -> [10000 ps] NOP -> [40000 ps] NOP -> [262500 ps] RD @ (0, 0) ->
[220000 ps] RD @ (0, 0) -> [220000 ps] RD @ (0, 0) -> [230000 ps] RD @ (0, 0) -> [220000 ps] RD @ (0, 0) ->

11475
xsim/sim_busdelay1250_flybydelay600.log
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12673
xsim/sim_busdelay1875_flybydelay1000.log
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5129
xsim/sim_busdelay2500_flybydelay1500.log
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7620
xsim/sim_busdelay5000_flybydelay2200.log
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@ -1,262 +0,0 @@
ddr3_dimm_micron_sim.sh - Script generated by export_simulation (Vivado v2021.2 (64-bit)-id)
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr3_controller
WARNING: [VRFC 10-3380] identifier 'WRITE_TO_PRECHARGE_DELAY' is used before its declaration [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v:190]
WARNING: [VRFC 10-3380] identifier 'stage2_update' is used before its declaration [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v:705]
INFO: [VRFC 10-311] analyzing module mini_fifo
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr3_phy
WARNING: [VRFC 10-3401] illegal argument of type reg [packed dim count:1] in math function 'floor()', expected real type [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:279]
WARNING: [VRFC 10-3401] illegal argument of type reg [packed dim count:1] in math function 'floor()', expected real type [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:324]
WARNING: [VRFC 10-3401] illegal argument of type reg [packed dim count:1] in math function 'floor()', expected real type [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:367]
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr3_top
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr3
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr3_dimm
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr3_dimm_micron_sim
Vivado Simulator v2021.2
Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
Running: /tools/Xilinx/Vivado/2021.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt auto -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:204]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:135]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:156]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:157]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:158]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 5 for port 'CNTVALUEIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:159]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:160]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LD' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:161]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:163]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:165]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:250]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:275]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:276]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:281]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:283]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:319]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:325]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:326]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:374]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:375]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'TCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:426]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:427]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:452]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:453]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:458]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:460]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:497]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:498]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:499]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:501]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:504]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:506]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:536]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:575]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:576]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:580]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:582]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:583]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:631]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:632]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:700]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:701]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:747]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:163]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:164]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'cke' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:165]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 's_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:166]
WARNING: [VRFC 10-3091] actual bit length 14 differs from formal bit length 16 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:171]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'odt' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:172]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:173]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:174]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:203]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:204]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:205]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:206]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:207]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:208]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:209]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:210]
WARNING: [VRFC 10-5021] port 'scl' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:161]
WARNING: [VRFC 10-5021] port 'i_controller_dm' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v:119]
Completed static elaboration
Starting simulation data flow analysis
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale.
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.ddr3_controller(CONTROLLER_CLK_P...
Compiling module unisims_ver.OSERDESE2(DATA_RATE_OQ="SDR",DAT...
Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="...
Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="SDR",DAT...
Compiling module unisims_ver.OBUFDS
Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT...
Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="...
Compiling module unisims_ver.IOBUF(IOSTANDARD="SSTL15",SLEW="...
Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="...
Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE...
Compiling module unisims_ver.OBUF(SLEW="FAST")
Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="...
Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT...
Compiling module unisims_ver.IOBUFDS(IOSTANDARD="DIFF_SSTL15"...
Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="...
Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE...
Compiling module unisims_ver.IDELAYCTRL_default
Compiling module xil_defaultlib.ddr3_phy(CONTROLLER_CLK_PERIOD=1...
Compiling module xil_defaultlib.ddr3_top(CONTROLLER_CLK_PERIOD=1...
Compiling module xil_defaultlib.ddr3_default
Compiling module xil_defaultlib.ddr3_dimm_default
Compiling module xil_defaultlib.ddr3_dimm_micron_sim
Compiling module xil_defaultlib.glbl
Built simulation snapshot ddr3_dimm_micron_sim
****** xsim v2021.2 (64-bit)
**** SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
**** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
source xsim.dir/ddr3_dimm_micron_sim/xsim_script.tcl
# xsim {ddr3_dimm_micron_sim} -autoloadwcfg -tclbatch {cmd.tcl} -key {Behavioral:sim_1:Functional:ddr3_dimm_micron_sim}
Time resolution is 1 ps
source cmd.tcl
## set curr_wave [current_wave_config]
## if { [string length $curr_wave] == 0 } {
## if { [llength [get_objects]] > 0} {
## add_wave /
## set_property needs_save false [current_wave_config]
## } else {
## send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
## }
## }
## run -all
Test ns_to_cycles() function:
ns_to_cycles(15) = 3 = 2 [exact]
ns_to_cycles(14.5) = 3 = 2 [round-off]
ns_to_cycles(11) = 3 = 2 [round-up]
Test nCK_to_cycles() function:
ns_to_cycles(16) = 4 = 4 [exact]
ns_to_cycles(15) = 4 = 4 [round-off]
ns_to_cycles(13) = 4 = 4 [round-up]
Test ns_to_nCK() function:
ns_to_cycles(15) = 12 = 6 [exact]
ns_to_cycles(14.875) = 12 = 6 [round-off]
ns_to_cycles(13.875) = 12 = 6 [round-up]
ns_to_nCK(tRCD) = 11 = 6 [WRONG]
tRTP = 7.5 = 10.000000
ns_to_nCK(tRTP) = 6= 4.000000 [WRONG]
Test nCK_to_ns() function:
ns_to_cycles(4) = 5 = 10 [exact]
ns_to_cycles(14.875) = 4 = 8 [round-off]
ns_to_cycles(13.875) = 7 = 13 [round-up]
Test nCK_to_ns() function:
ns_to_cycles(4) = 5 = 10 [exact]
ns_to_cycles(14.875) = 4 = 8 [round-off]
ns_to_cycles(13.875) = 7 = 13 [round-up]
Test $floor() function:
$floor(5/2) = 2.5 = 2
$floor(9/4) = 2.25 = 2
$floor(9/4) = 2 = 2
$floor(9/5) = 1.8 = 1
DELAY_COUNTER_WIDTH = 16
DELAY_SLOT_WIDTH = 19
serdes_ratio = 4
wb_addr_bits = 24
wb_data_bits = 512
wb_sel_bits = 64
READ_SLOT = 2
WRITE_SLOT = 3
ACTIVATE_SLOT = 0
PRECHARGE_SLOT = 1
DELAYS:
ns_to_nCK(tRCD): 6
ns_to_nCK(tRP): 6
ns_to_nCK(tRTP): 4
tCCD: 4
(CL_nCK + tCCD + 3'd2 - CWL_nCK): 7
(CWL_nCK + 3'd4 + ns_to_nCK(tWR)): 15
(CWL_nCK + 3'd4 + ns_to_nCK(tWTR)): 13
$signed(4'b1100)>>>4: 1111
PRECHARGE_TO_ACTIVATE_DELAY = 3 = 1
ACTIVATE_TO_WRITE_DELAY = 3 = 0
ACTIVATE_TO_READ_DELAY = 2 = 0
READ_TO_WRITE_DELAY = 2 = 1
READ_TO_READ_DELAY = 0 = 0
READ_TO_PRECHARGE_DELAY = 1 =1
WRITE_TO_WRITE_DELAY = 0 = 0
WRITE_TO_READ_DELAY = 4 = 3
WRITE_TO_PRECHARGE_DELAY = 5 = 4
STAGE2_DATA_DEPTH = 2 = 2
READ_ACK_PIPE_WIDTH = 6
ddr3_dimm_micron_sim.ddr3_dimm.U1.file_io_open: at time 0 WARNING: no +model_data option specified, using /tmp.
ddr3_dimm_micron_sim.ddr3_dimm.U2.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
ddr3_dimm_micron_sim.ddr3_dimm.U3.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
ddr3_dimm_micron_sim.ddr3_dimm.U4.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
ddr3_dimm_micron_sim.ddr3_dimm.U6.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
ddr3_dimm_micron_sim.ddr3_dimm.U7.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
ddr3_dimm_micron_sim.ddr3_dimm.U8.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
ddr3_dimm_micron_sim.ddr3_dimm.U9.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
[x ps] MRS -> [ 7500 ps] MRS -> ddr3_dimm_micron_sim.ddr3_dimm.U1.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive.
ddr3_dimm_micron_sim.ddr3_dimm.U2.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive.
ddr3_dimm_micron_sim.ddr3_dimm.U3.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive.
ddr3_dimm_micron_sim.ddr3_dimm.U4.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive.
ddr3_dimm_micron_sim.ddr3_dimm.U6.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive.
ddr3_dimm_micron_sim.ddr3_dimm.U7.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive.
ddr3_dimm_micron_sim.ddr3_dimm.U8.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive.
ddr3_dimm_micron_sim.ddr3_dimm.U9.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive.
[195000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
[510000 ps] NOP -> [370000 ps] MRS ->
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
[10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP -> [40000 ps] ZQC ->
[1290000 ps] PRE @ (0) -> [30000 ps] MRS -> [10000 ps] NOP -> [40000 ps] NOP -> [262500 ps] RD @ (0, 0) ->
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
[130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
[480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> INFO: [Common 17-41] Interrupt caught. Command should exit soon.
run: Time (s): cpu = 00:00:03 ; elapsed = 00:01:46 . Memory (MB): peak = 2833.148 ; gain = 8.004 ; free physical = 1466 ; free virtual = 24759
INFO: [Common 17-344] 'run' was cancelled
xsim: Time (s): cpu = 00:00:04 ; elapsed = 00:01:48 . Memory (MB): peak = 2833.148 ; gain = 844.395 ; free physical = 1466 ; free virtual = 24759
INFO: [Common 17-344] 'source' was cancelled
xsim% adssss

14263
xsim/sim_busdelay625_flybydelay0.log
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