exported simulation scripts from Vivado
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AngeloJacobo
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################################################################################
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# Vivado (TM) v2021.2 (64-bit)
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#
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# README.txt: Please read the sections below to understand the steps required to
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# run the exported script and information about the source files.
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#
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# Generated by export_simulation on Tue Jul 04 17:40:00 PST 2023
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#
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################################################################################
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1. How to run the generated simulation script:-
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From the shell prompt in the current directory, issue the following command:-
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./ddr3_dimm_micron_sim.sh
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This command will launch the 'compile', 'elaborate' and 'simulate' functions
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implemented in the script file for the 3-step flow. These functions are called
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from the main 'run' function in the script file.
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The 'run' function first executes the 'setup' function, the purpose of which is to
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create simulator specific setup files, create design library mappings and library
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directories and copy 'glbl.v' from the Vivado software install location into the
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current directory.
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The 'setup' function is also used for removing the simulator generated data in
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order to reset the current directory to the original state when export_simulation
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was launched from Vivado. This generated data can be removed by specifying the
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'-reset_run' switch to the './ddr3_dimm_micron_sim.sh' script.
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./ddr3_dimm_micron_sim.sh -reset_run
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To keep the generated data from the previous run but regenerate the setup files and
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library directories, use the '-noclean_files' switch.
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./ddr3_dimm_micron_sim.sh -noclean_files
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For more information on the script, please type './ddr3_dimm_micron_sim.sh -help'.
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2. Additional design information files:-
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export_simulation generates following additional file that can be used for fetching
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the design files information or for integrating with external custom scripts.
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Name : file_info.txt
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Purpose: This file contains detail design file information based on the compile order
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when export_simulation was executed from Vivado. The file contains information
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about the file type, name, whether it is part of the IP, associated library
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and the file path information.
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set curr_wave [current_wave_config]
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if { [string length $curr_wave] == 0 } {
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if { [llength [get_objects]] > 0} {
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add_wave /
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set_property needs_save false [current_wave_config]
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} else {
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send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
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}
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}
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run -all
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quit
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ddr3
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ddr3_dimm
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ddr3_dimm_micron_sim
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#!/bin/bash -f
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#*********************************************************************************************************
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# Vivado (TM) v2021.2 (64-bit)
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#
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# Filename : ddr3_dimm_micron_sim.sh
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# Simulator : Xilinx Vivado Simulator
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# Description : Simulation script for compiling, elaborating and verifying the project source files.
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# The script will automatically create the design libraries sub-directories in the run
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# directory, add the library logical mappings in the simulator setup file, create default
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# 'do/prj' file, execute compilation, elaboration and simulation steps.
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#
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# Generated by Vivado on Tue Jul 04 17:40:00 PST 2023
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# SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
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#
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# Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
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#
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# usage: ddr3_dimm_micron_sim.sh [-help]
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# usage: ddr3_dimm_micron_sim.sh [-lib_map_path]
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# usage: ddr3_dimm_micron_sim.sh [-noclean_files]
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# usage: ddr3_dimm_micron_sim.sh [-reset_run]
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#
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#*********************************************************************************************************
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# Set xvlog options
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xvlog_opts="--incr --relax -L uvm"
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# Script info
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echo -e "ddr3_dimm_micron_sim.sh - Script generated by export_simulation (Vivado v2021.2 (64-bit)-id)\n"
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# Main steps
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run()
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{
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check_args $# $1
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setup $1 $2
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compile
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elaborate
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simulate
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}
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# RUN_STEP: <compile>
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compile()
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{
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xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log
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}
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# RUN_STEP: <elaborate>
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elaborate()
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{
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xelab --incr --debug typical --relax --mt auto -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log
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}
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# RUN_STEP: <simulate>
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simulate()
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{
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xsim ddr3_dimm_micron_sim -key {Behavioral:sim_1:Functional:ddr3_dimm_micron_sim} -tclbatch cmd.tcl -log simulate.log
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}
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# STEP: setup
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setup()
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{
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case $1 in
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"-lib_map_path" )
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if [[ ($2 == "") ]]; then
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echo -e "ERROR: Simulation library directory path not specified (type \"./ddr3_dimm_micron_sim.sh -help\" for more information)\n"
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exit 1
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fi
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;;
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"-reset_run" )
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reset_run
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echo -e "INFO: Simulation run files deleted.\n"
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exit 0
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;;
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"-noclean_files" )
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# do not remove previous data
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;;
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* )
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esac
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# Add any setup/initialization commands here:-
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# <user specific commands>
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}
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# Delete generated data from the previous run
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reset_run()
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{
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files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb ddr3_dimm_micron_sim.wdb xsim.dir)
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for (( i=0; i<${#files_to_remove[*]}; i++ )); do
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file="${files_to_remove[i]}"
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if [[ -e $file ]]; then
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rm -rf $file
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fi
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done
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}
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# Check command line arguments
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check_args()
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{
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if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
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echo -e "ERROR: Unknown option specified '$2' (type \"./ddr3_dimm_micron_sim.sh -help\" for more information)\n"
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exit 1
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fi
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if [[ ($2 == "-help" || $2 == "-h") ]]; then
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usage
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fi
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}
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# Script usage
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usage()
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{
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msg="Usage: ddr3_dimm_micron_sim.sh [-help]\n\
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Usage: ddr3_dimm_micron_sim.sh [-lib_map_path]\n\
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Usage: ddr3_dimm_micron_sim.sh [-reset_run]\n\
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Usage: ddr3_dimm_micron_sim.sh [-noclean_files]\n\n\
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[-help] -- Print help information for this script\n\n\
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[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
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using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
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[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
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from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
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-noclean_files switch.\n\n\
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[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
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echo -e $msg
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exit 1
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}
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# Launch script
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run $1 $2
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Vivado Simulator v2021.2
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Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
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Running: /tools/Xilinx/Vivado/2021.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt auto -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log
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Starting static elaboration
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Pass Through NonSizing Optimizer
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:204]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:135]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:156]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:157]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:158]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 5 for port 'CNTVALUEIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:159]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:160]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LD' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:161]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:163]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:165]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:250]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:275]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:276]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:281]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:283]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:319]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:325]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:326]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:374]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:375]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'TCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:426]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:427]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:452]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:453]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:458]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:460]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:497]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:498]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:499]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:501]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:504]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:506]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:536]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:575]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:576]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:580]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:582]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:583]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:631]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:632]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:700]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:701]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:747]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:163]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:164]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'cke' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:165]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 's_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:166]
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WARNING: [VRFC 10-3091] actual bit length 14 differs from formal bit length 16 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:171]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'odt' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:172]
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WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:173]
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WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:174]
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WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:203]
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WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:204]
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WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:205]
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WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:206]
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WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:207]
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WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:208]
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WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:209]
|
||||
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:210]
|
||||
WARNING: [VRFC 10-5021] port 'scl' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:161]
|
||||
WARNING: [VRFC 10-5021] port 'i_controller_dm' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v:119]
|
||||
Completed static elaboration
|
||||
Starting simulation data flow analysis
|
||||
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
|
||||
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
|
||||
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale.
|
||||
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
|
||||
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
|
||||
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale.
|
||||
Completed simulation data flow analysis
|
||||
Time Resolution for simulation is 1ps
|
||||
Compiling module xil_defaultlib.ddr3_controller(CONTROLLER_CLK_P...
|
||||
Compiling module unisims_ver.OSERDESE2(DATA_RATE_OQ="SDR",DAT...
|
||||
Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="...
|
||||
Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="SDR",DAT...
|
||||
Compiling module unisims_ver.OBUFDS
|
||||
Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT...
|
||||
Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="...
|
||||
Compiling module unisims_ver.IOBUF(IOSTANDARD="SSTL15",SLEW="...
|
||||
Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="...
|
||||
Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE...
|
||||
Compiling module unisims_ver.OBUF(SLEW="FAST")
|
||||
Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="...
|
||||
Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT...
|
||||
Compiling module unisims_ver.IOBUFDS(IOSTANDARD="DIFF_SSTL15"...
|
||||
Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="...
|
||||
Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE...
|
||||
Compiling module unisims_ver.IDELAYCTRL_default
|
||||
Compiling module xil_defaultlib.ddr3_phy(CONTROLLER_CLK_PERIOD=1...
|
||||
Compiling module xil_defaultlib.ddr3_top(CONTROLLER_CLK_PERIOD=1...
|
||||
Compiling module xil_defaultlib.ddr3_default
|
||||
Compiling module xil_defaultlib.ddr3_dimm_default
|
||||
Compiling module xil_defaultlib.ddr3_dimm_micron_sim
|
||||
Compiling module xil_defaultlib.glbl
|
||||
Built simulation snapshot ddr3_dimm_micron_sim
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
ddr3_controller.v,verilog,xil_defaultlib,/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v,incdir="/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/rtl"incdir="/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench"
|
||||
ddr3_phy.v,verilog,xil_defaultlib,/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v,incdir="/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/rtl"incdir="/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench"
|
||||
ddr3_top.v,verilog,xil_defaultlib,/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v,incdir="/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/rtl"incdir="/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench"
|
||||
ddr3.v,systemverilog,xil_defaultlib,/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3.v,incdir="/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/rtl"incdir="/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench"
|
||||
ddr3_dimm.v,systemverilog,xil_defaultlib,/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v,incdir="/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/rtl"incdir="/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench"
|
||||
ddr3_dimm_micron_sim.v,systemverilog,xil_defaultlib,/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v,incdir="/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/rtl"incdir="/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench"
|
||||
glbl.v,Verilog,xil_defaultlib,/home/angelo/incdir="/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench"/glbl.v
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
parameter GRES_WIDTH = 10000;
|
||||
parameter GRES_START = 10000;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
wire GRESTORE;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
reg GRESTORE_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GRESTORE_int = 1'b0;
|
||||
#(GRES_START);
|
||||
GRESTORE_int = 1'b1;
|
||||
#(GRES_WIDTH);
|
||||
GRESTORE_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
ddr3_dimm_micron_sim.sh - Script generated by export_simulation (Vivado v2021.2 (64-bit)-id)
|
||||
|
||||
Vivado Simulator v2021.2
|
||||
Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
|
||||
Running: /tools/Xilinx/Vivado/2021.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt auto -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log
|
||||
Starting static elaboration
|
||||
Pass Through NonSizing Optimizer
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:204]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:135]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:156]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:157]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:158]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 5 for port 'CNTVALUEIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:159]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:160]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LD' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:161]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:163]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:165]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:250]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:275]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:276]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:281]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:283]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:319]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:325]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:326]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:374]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:375]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'TCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:426]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:427]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:452]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:453]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:458]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:460]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:497]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:498]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:499]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:501]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:504]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:506]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:536]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:575]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:576]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:580]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:582]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:583]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:631]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:632]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:700]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:701]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:747]
|
||||
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:163]
|
||||
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:164]
|
||||
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'cke' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:165]
|
||||
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 's_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:166]
|
||||
WARNING: [VRFC 10-3091] actual bit length 14 differs from formal bit length 16 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:171]
|
||||
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'odt' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:172]
|
||||
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:173]
|
||||
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:174]
|
||||
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:203]
|
||||
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:204]
|
||||
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:205]
|
||||
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:206]
|
||||
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:207]
|
||||
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:208]
|
||||
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:209]
|
||||
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:210]
|
||||
WARNING: [VRFC 10-5021] port 'scl' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:161]
|
||||
WARNING: [VRFC 10-5021] port 'i_controller_dm' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v:119]
|
||||
Completed static elaboration
|
||||
Starting simulation data flow analysis
|
||||
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
|
||||
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
|
||||
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale.
|
||||
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
|
||||
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
|
||||
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale.
|
||||
Completed simulation data flow analysis
|
||||
ERROR: [XSIM 43-3315] Signal SIGINT received.
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
#!/bin/bash
|
||||
|
||||
# Define the path to the .vh file
|
||||
vh_file="../testbench/8192Mb_ddr3_parameters.vh"
|
||||
|
||||
# Function to modify BUS_DELAY and execute the simulation command
|
||||
run_simulation() {
|
||||
local bus_delay=$1
|
||||
local flyby_delay=$2
|
||||
local log_file=$3
|
||||
|
||||
# Modify BUS_DELAY in the .vh file
|
||||
sed -i "s/parameter BUS_DELAY.*/parameter BUS_DELAY = $bus_delay; \/\/ delay in picoseconds/" "$vh_file"
|
||||
|
||||
# Modify FLY_BY_DELAY in the .vh file
|
||||
sed -i "s/parameter FLY_BY_DELAY.*/parameter FLY_BY_DELAY = $flyby_delay; \/\/ delay in picoseconds/" "$vh_file"
|
||||
|
||||
# Print BUS_DELAY and log file name
|
||||
echo "BUS_DELAY: $bus_delay ps"
|
||||
echo "FLY_BY_DELAY: $flyby_delay ps"
|
||||
echo "Log File: $log_file"
|
||||
|
||||
# Execute the simulation command and redirect the output to the log file
|
||||
./ddr3_dimm_micron_sim.sh >| "$log_file"
|
||||
|
||||
# Print log contents starting from "------- SUMMARY -------"
|
||||
sed -n '/^------- SUMMARY -------/,$p' "$log_file"
|
||||
echo ""
|
||||
echo ""
|
||||
}
|
||||
|
||||
# Run simulations with different BUS_DELAY values
|
||||
run_simulation 0 0 "sim_busdelay0_flybydelay0.log"
|
||||
run_simulation 625 0 "sim_busdelay625_flybydelay0.log"
|
||||
run_simulation 1250 600 "sim_busdelay1250_flybydelay600.log"
|
||||
run_simulation 1875 1000 "sim_busdelay1875_flybydelay1000.log"
|
||||
run_simulation 2500 1500 "sim_busdelay2500_flybydelay1500.log"
|
||||
run_simulation 5000 2200 "sim_busdelay5000_flybydelay2200.log"
|
||||
run_simulation 10000 3000 "sim_busdelay10000_flybydelay3000.log"
|
||||
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
|
||||
|
||||
import fileinput
|
||||
import subprocess
|
||||
|
||||
# Define the path to the .vh file
|
||||
vh_file = "../testbench/8192Mb_ddr3_parameters.vh"
|
||||
|
||||
# Modify BUS_DELAY and execute the simulation command
|
||||
def run_simulation(delay, log_file):
|
||||
with fileinput.FileInput(vh_file, inplace=True) as file:
|
||||
for line in file:
|
||||
if line.startswith(" parameter BUS_DELAY"):
|
||||
line = f" parameter BUS_DELAY = {delay}; // delay in nanoseconds\n"
|
||||
print(line, end="")
|
||||
|
||||
# Print BUS_DELAY and log file name
|
||||
print(f"BUS_DELAY: {delay} ps")
|
||||
print(f"Log File: {log_file}")
|
||||
|
||||
with open(log_file, "a") as log:
|
||||
print("")
|
||||
subprocess.call(["./ddr3_dimm_micron_sim.sh"], stdout=log, shell=True)
|
||||
|
||||
# Print log contents starting from "------- SUMMARY -------"
|
||||
print_log_summary(log_file)
|
||||
print("")
|
||||
|
||||
# Function to print log contents from "------- SUMMARY -------" section
|
||||
def print_log_summary(log_file):
|
||||
with open(log_file, "r") as log:
|
||||
summary_reached = False
|
||||
for line in log:
|
||||
if line.startswith("------- SUMMARY -------"):
|
||||
summary_reached = True
|
||||
if summary_reached:
|
||||
print(line.strip())
|
||||
|
||||
# Run simulations with different BUS_DELAY values
|
||||
run_simulation(0, "sim_test_busdelay0ps.log")
|
||||
run_simulation(1000, "sim_busdelay1000ps.log")
|
||||
run_simulation(5000, "sim_busdelay5000ps.log")
|
||||
run_simulation(10000, "sim_busdelay10000ps.log")
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,252 @@
|
|||
ddr3_dimm_micron_sim.sh - Script generated by export_simulation (Vivado v2021.2 (64-bit)-id)
|
||||
|
||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module ddr3
|
||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module ddr3_dimm
|
||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module ddr3_dimm_micron_sim
|
||||
Vivado Simulator v2021.2
|
||||
Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
|
||||
Running: /tools/Xilinx/Vivado/2021.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt auto -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log
|
||||
Starting static elaboration
|
||||
Pass Through NonSizing Optimizer
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:204]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:135]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:156]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:157]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:158]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 5 for port 'CNTVALUEIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:159]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:160]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LD' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:161]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:163]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:165]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:250]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:275]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:276]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:281]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:283]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:319]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:325]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:326]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:374]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:375]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'TCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:426]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:427]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:452]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:453]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:458]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:460]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:497]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:498]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:499]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:501]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:504]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:506]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:536]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:575]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:576]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:580]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:582]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:583]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:631]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:632]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:700]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:701]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:747]
|
||||
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:163]
|
||||
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:164]
|
||||
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'cke' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:165]
|
||||
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 's_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:166]
|
||||
WARNING: [VRFC 10-3091] actual bit length 14 differs from formal bit length 16 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:171]
|
||||
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'odt' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:172]
|
||||
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:173]
|
||||
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:174]
|
||||
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:203]
|
||||
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:204]
|
||||
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:205]
|
||||
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:206]
|
||||
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:207]
|
||||
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:208]
|
||||
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:209]
|
||||
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:210]
|
||||
WARNING: [VRFC 10-5021] port 'scl' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:161]
|
||||
WARNING: [VRFC 10-5021] port 'i_controller_dm' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v:119]
|
||||
Completed static elaboration
|
||||
Starting simulation data flow analysis
|
||||
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
|
||||
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
|
||||
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale.
|
||||
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
|
||||
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
|
||||
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale.
|
||||
Completed simulation data flow analysis
|
||||
Time Resolution for simulation is 1ps
|
||||
Compiling module xil_defaultlib.ddr3_controller(CONTROLLER_CLK_P...
|
||||
Compiling module unisims_ver.OSERDESE2(DATA_RATE_OQ="SDR",DAT...
|
||||
Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="...
|
||||
Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="SDR",DAT...
|
||||
Compiling module unisims_ver.OBUFDS
|
||||
Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT...
|
||||
Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="...
|
||||
Compiling module unisims_ver.IOBUF(IOSTANDARD="SSTL15",SLEW="...
|
||||
Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="...
|
||||
Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE...
|
||||
Compiling module unisims_ver.OBUF(SLEW="FAST")
|
||||
Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="...
|
||||
Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT...
|
||||
Compiling module unisims_ver.IOBUFDS(IOSTANDARD="DIFF_SSTL15"...
|
||||
Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="...
|
||||
Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE...
|
||||
Compiling module unisims_ver.IDELAYCTRL_default
|
||||
Compiling module xil_defaultlib.ddr3_phy(CONTROLLER_CLK_PERIOD=1...
|
||||
Compiling module xil_defaultlib.ddr3_top(CONTROLLER_CLK_PERIOD=1...
|
||||
Compiling module xil_defaultlib.ddr3_default
|
||||
Compiling module xil_defaultlib.ddr3_dimm_default
|
||||
Compiling module xil_defaultlib.ddr3_dimm_micron_sim
|
||||
Compiling module xil_defaultlib.glbl
|
||||
Built simulation snapshot ddr3_dimm_micron_sim
|
||||
|
||||
****** xsim v2021.2 (64-bit)
|
||||
**** SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
|
||||
**** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
|
||||
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
source xsim.dir/ddr3_dimm_micron_sim/xsim_script.tcl
|
||||
# xsim {ddr3_dimm_micron_sim} -autoloadwcfg -tclbatch {cmd.tcl} -key {Behavioral:sim_1:Functional:ddr3_dimm_micron_sim}
|
||||
Time resolution is 1 ps
|
||||
source cmd.tcl
|
||||
## set curr_wave [current_wave_config]
|
||||
## if { [string length $curr_wave] == 0 } {
|
||||
## if { [llength [get_objects]] > 0} {
|
||||
## add_wave /
|
||||
## set_property needs_save false [current_wave_config]
|
||||
## } else {
|
||||
## send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
||||
## }
|
||||
## }
|
||||
## run -all
|
||||
Test ns_to_cycles() function:
|
||||
ns_to_cycles(15) = 3 = 2 [exact]
|
||||
ns_to_cycles(14.5) = 3 = 2 [round-off]
|
||||
ns_to_cycles(11) = 3 = 2 [round-up]
|
||||
|
||||
Test nCK_to_cycles() function:
|
||||
ns_to_cycles(16) = 4 = 4 [exact]
|
||||
ns_to_cycles(15) = 4 = 4 [round-off]
|
||||
ns_to_cycles(13) = 4 = 4 [round-up]
|
||||
|
||||
Test ns_to_nCK() function:
|
||||
ns_to_cycles(15) = 12 = 6 [exact]
|
||||
ns_to_cycles(14.875) = 12 = 6 [round-off]
|
||||
ns_to_cycles(13.875) = 12 = 6 [round-up]
|
||||
ns_to_nCK(tRCD) = 11 = 6 [WRONG]
|
||||
tRTP = 7.5 = 10.000000
|
||||
ns_to_nCK(tRTP) = 6= 4.000000 [WRONG]
|
||||
|
||||
Test nCK_to_ns() function:
|
||||
ns_to_cycles(4) = 5 = 10 [exact]
|
||||
ns_to_cycles(14.875) = 4 = 8 [round-off]
|
||||
ns_to_cycles(13.875) = 7 = 13 [round-up]
|
||||
|
||||
Test nCK_to_ns() function:
|
||||
ns_to_cycles(4) = 5 = 10 [exact]
|
||||
ns_to_cycles(14.875) = 4 = 8 [round-off]
|
||||
ns_to_cycles(13.875) = 7 = 13 [round-up]
|
||||
|
||||
Test $floor() function:
|
||||
$floor(5/2) = 2.5 = 2
|
||||
$floor(9/4) = 2.25 = 2
|
||||
$floor(9/4) = 2 = 2
|
||||
$floor(9/5) = 1.8 = 1
|
||||
|
||||
|
||||
DELAY_COUNTER_WIDTH = 16
|
||||
DELAY_SLOT_WIDTH = 19
|
||||
serdes_ratio = 4
|
||||
wb_addr_bits = 24
|
||||
wb_data_bits = 512
|
||||
wb_sel_bits = 64
|
||||
|
||||
|
||||
READ_SLOT = 2
|
||||
WRITE_SLOT = 3
|
||||
ACTIVATE_SLOT = 0
|
||||
PRECHARGE_SLOT = 1
|
||||
|
||||
|
||||
DELAYS:
|
||||
ns_to_nCK(tRCD): 6
|
||||
ns_to_nCK(tRP): 6
|
||||
ns_to_nCK(tRTP): 4
|
||||
tCCD: 4
|
||||
(CL_nCK + tCCD + 3'd2 - CWL_nCK): 7
|
||||
(CWL_nCK + 3'd4 + ns_to_nCK(tWR)): 15
|
||||
(CWL_nCK + 3'd4 + ns_to_nCK(tWTR)): 13
|
||||
$signed(4'b1100)>>>4: 1111
|
||||
|
||||
|
||||
PRECHARGE_TO_ACTIVATE_DELAY = 3 = 1
|
||||
ACTIVATE_TO_WRITE_DELAY = 3 = 0
|
||||
ACTIVATE_TO_READ_DELAY = 2 = 0
|
||||
READ_TO_WRITE_DELAY = 2 = 1
|
||||
READ_TO_READ_DELAY = 0 = 0
|
||||
READ_TO_PRECHARGE_DELAY = 1 =1
|
||||
WRITE_TO_WRITE_DELAY = 0 = 0
|
||||
WRITE_TO_READ_DELAY = 4 = 3
|
||||
WRITE_TO_PRECHARGE_DELAY = 5 = 4
|
||||
STAGE2_DATA_DEPTH = 2 = 2
|
||||
READ_ACK_PIPE_WIDTH = 6
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U1.file_io_open: at time 0 WARNING: no +model_data option specified, using /tmp.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U2.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U3.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U4.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U6.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U7.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U8.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U9.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
||||
[x ps] MRS -> [ 7500 ps] MRS -> ddr3_dimm_micron_sim.ddr3_dimm.U1.reset at time 304199.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U2.reset at time 304199.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U3.reset at time 304199.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U4.reset at time 304199.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U6.reset at time 304199.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U7.reset at time 304199.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U8.reset at time 304199.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U9.reset at time 304199.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
||||
[195000 ps] NOP -> [510000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task at time 815475.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task at time 815475.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task at time 815475.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task at time 815475.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task at time 815475.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task at time 815475.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task at time 815475.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task at time 815475.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
||||
[370000 ps] MRS ->
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1187975.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1187975.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1187975.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1187975.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1187975.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1187975.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1187975.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1187975.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
||||
[10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP -> [40000 ps] ZQC ->
|
||||
[1290000 ps] PRE @ (0) -> [30000 ps] MRS -> [10000 ps] NOP -> [40000 ps] NOP -> [262500 ps] RD @ (0, 0) ->
|
||||
[140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
|
||||
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
|
||||
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
|
||||
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
|
||||
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
|
||||
[580000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
|
||||
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
|
||||
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
|
||||
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
|
||||
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
|
||||
[150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [580000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
|
||||
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
|
||||
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
|
||||
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
|
||||
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
|
||||
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
|
||||
[150000 ps] RD @ (0, 0) -> [580000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
|
||||
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
|
||||
|
|
@ -0,0 +1,262 @@
|
|||
ddr3_dimm_micron_sim.sh - Script generated by export_simulation (Vivado v2021.2 (64-bit)-id)
|
||||
|
||||
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module ddr3_controller
|
||||
WARNING: [VRFC 10-3380] identifier 'WRITE_TO_PRECHARGE_DELAY' is used before its declaration [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v:190]
|
||||
WARNING: [VRFC 10-3380] identifier 'stage2_update' is used before its declaration [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v:705]
|
||||
INFO: [VRFC 10-311] analyzing module mini_fifo
|
||||
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module ddr3_phy
|
||||
WARNING: [VRFC 10-3401] illegal argument of type reg [packed dim count:1] in math function 'floor()', expected real type [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:279]
|
||||
WARNING: [VRFC 10-3401] illegal argument of type reg [packed dim count:1] in math function 'floor()', expected real type [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:324]
|
||||
WARNING: [VRFC 10-3401] illegal argument of type reg [packed dim count:1] in math function 'floor()', expected real type [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:367]
|
||||
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module ddr3_top
|
||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module ddr3
|
||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module ddr3_dimm
|
||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module ddr3_dimm_micron_sim
|
||||
Vivado Simulator v2021.2
|
||||
Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
|
||||
Running: /tools/Xilinx/Vivado/2021.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt auto -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log
|
||||
Starting static elaboration
|
||||
Pass Through NonSizing Optimizer
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:204]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:135]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:156]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:157]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:158]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 5 for port 'CNTVALUEIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:159]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:160]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LD' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:161]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:163]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:165]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:250]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:275]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:276]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:281]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:283]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:319]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:325]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:326]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:374]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:375]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'TCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:426]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:427]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:452]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:453]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:458]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:460]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:497]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:498]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:499]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:501]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:504]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:506]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:536]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:575]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:576]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:580]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:582]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:583]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:631]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:632]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:700]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:701]
|
||||
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:747]
|
||||
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:163]
|
||||
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:164]
|
||||
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'cke' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:165]
|
||||
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 's_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:166]
|
||||
WARNING: [VRFC 10-3091] actual bit length 14 differs from formal bit length 16 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:171]
|
||||
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'odt' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:172]
|
||||
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:173]
|
||||
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:174]
|
||||
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:203]
|
||||
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:204]
|
||||
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:205]
|
||||
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:206]
|
||||
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:207]
|
||||
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:208]
|
||||
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:209]
|
||||
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:210]
|
||||
WARNING: [VRFC 10-5021] port 'scl' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:161]
|
||||
WARNING: [VRFC 10-5021] port 'i_controller_dm' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v:119]
|
||||
Completed static elaboration
|
||||
Starting simulation data flow analysis
|
||||
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
|
||||
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
|
||||
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale.
|
||||
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
|
||||
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
|
||||
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale.
|
||||
Completed simulation data flow analysis
|
||||
Time Resolution for simulation is 1ps
|
||||
Compiling module xil_defaultlib.ddr3_controller(CONTROLLER_CLK_P...
|
||||
Compiling module unisims_ver.OSERDESE2(DATA_RATE_OQ="SDR",DAT...
|
||||
Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="...
|
||||
Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="SDR",DAT...
|
||||
Compiling module unisims_ver.OBUFDS
|
||||
Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT...
|
||||
Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="...
|
||||
Compiling module unisims_ver.IOBUF(IOSTANDARD="SSTL15",SLEW="...
|
||||
Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="...
|
||||
Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE...
|
||||
Compiling module unisims_ver.OBUF(SLEW="FAST")
|
||||
Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="...
|
||||
Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT...
|
||||
Compiling module unisims_ver.IOBUFDS(IOSTANDARD="DIFF_SSTL15"...
|
||||
Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="...
|
||||
Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE...
|
||||
Compiling module unisims_ver.IDELAYCTRL_default
|
||||
Compiling module xil_defaultlib.ddr3_phy(CONTROLLER_CLK_PERIOD=1...
|
||||
Compiling module xil_defaultlib.ddr3_top(CONTROLLER_CLK_PERIOD=1...
|
||||
Compiling module xil_defaultlib.ddr3_default
|
||||
Compiling module xil_defaultlib.ddr3_dimm_default
|
||||
Compiling module xil_defaultlib.ddr3_dimm_micron_sim
|
||||
Compiling module xil_defaultlib.glbl
|
||||
Built simulation snapshot ddr3_dimm_micron_sim
|
||||
|
||||
****** xsim v2021.2 (64-bit)
|
||||
**** SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
|
||||
**** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
|
||||
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
source xsim.dir/ddr3_dimm_micron_sim/xsim_script.tcl
|
||||
# xsim {ddr3_dimm_micron_sim} -autoloadwcfg -tclbatch {cmd.tcl} -key {Behavioral:sim_1:Functional:ddr3_dimm_micron_sim}
|
||||
Time resolution is 1 ps
|
||||
source cmd.tcl
|
||||
## set curr_wave [current_wave_config]
|
||||
## if { [string length $curr_wave] == 0 } {
|
||||
## if { [llength [get_objects]] > 0} {
|
||||
## add_wave /
|
||||
## set_property needs_save false [current_wave_config]
|
||||
## } else {
|
||||
## send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
||||
## }
|
||||
## }
|
||||
## run -all
|
||||
Test ns_to_cycles() function:
|
||||
ns_to_cycles(15) = 3 = 2 [exact]
|
||||
ns_to_cycles(14.5) = 3 = 2 [round-off]
|
||||
ns_to_cycles(11) = 3 = 2 [round-up]
|
||||
|
||||
Test nCK_to_cycles() function:
|
||||
ns_to_cycles(16) = 4 = 4 [exact]
|
||||
ns_to_cycles(15) = 4 = 4 [round-off]
|
||||
ns_to_cycles(13) = 4 = 4 [round-up]
|
||||
|
||||
Test ns_to_nCK() function:
|
||||
ns_to_cycles(15) = 12 = 6 [exact]
|
||||
ns_to_cycles(14.875) = 12 = 6 [round-off]
|
||||
ns_to_cycles(13.875) = 12 = 6 [round-up]
|
||||
ns_to_nCK(tRCD) = 11 = 6 [WRONG]
|
||||
tRTP = 7.5 = 10.000000
|
||||
ns_to_nCK(tRTP) = 6= 4.000000 [WRONG]
|
||||
|
||||
Test nCK_to_ns() function:
|
||||
ns_to_cycles(4) = 5 = 10 [exact]
|
||||
ns_to_cycles(14.875) = 4 = 8 [round-off]
|
||||
ns_to_cycles(13.875) = 7 = 13 [round-up]
|
||||
|
||||
Test nCK_to_ns() function:
|
||||
ns_to_cycles(4) = 5 = 10 [exact]
|
||||
ns_to_cycles(14.875) = 4 = 8 [round-off]
|
||||
ns_to_cycles(13.875) = 7 = 13 [round-up]
|
||||
|
||||
Test $floor() function:
|
||||
$floor(5/2) = 2.5 = 2
|
||||
$floor(9/4) = 2.25 = 2
|
||||
$floor(9/4) = 2 = 2
|
||||
$floor(9/5) = 1.8 = 1
|
||||
|
||||
|
||||
DELAY_COUNTER_WIDTH = 16
|
||||
DELAY_SLOT_WIDTH = 19
|
||||
serdes_ratio = 4
|
||||
wb_addr_bits = 24
|
||||
wb_data_bits = 512
|
||||
wb_sel_bits = 64
|
||||
|
||||
|
||||
READ_SLOT = 2
|
||||
WRITE_SLOT = 3
|
||||
ACTIVATE_SLOT = 0
|
||||
PRECHARGE_SLOT = 1
|
||||
|
||||
|
||||
DELAYS:
|
||||
ns_to_nCK(tRCD): 6
|
||||
ns_to_nCK(tRP): 6
|
||||
ns_to_nCK(tRTP): 4
|
||||
tCCD: 4
|
||||
(CL_nCK + tCCD + 3'd2 - CWL_nCK): 7
|
||||
(CWL_nCK + 3'd4 + ns_to_nCK(tWR)): 15
|
||||
(CWL_nCK + 3'd4 + ns_to_nCK(tWTR)): 13
|
||||
$signed(4'b1100)>>>4: 1111
|
||||
|
||||
|
||||
PRECHARGE_TO_ACTIVATE_DELAY = 3 = 1
|
||||
ACTIVATE_TO_WRITE_DELAY = 3 = 0
|
||||
ACTIVATE_TO_READ_DELAY = 2 = 0
|
||||
READ_TO_WRITE_DELAY = 2 = 1
|
||||
READ_TO_READ_DELAY = 0 = 0
|
||||
READ_TO_PRECHARGE_DELAY = 1 =1
|
||||
WRITE_TO_WRITE_DELAY = 0 = 0
|
||||
WRITE_TO_READ_DELAY = 4 = 3
|
||||
WRITE_TO_PRECHARGE_DELAY = 5 = 4
|
||||
STAGE2_DATA_DEPTH = 2 = 2
|
||||
READ_ACK_PIPE_WIDTH = 6
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U1.file_io_open: at time 0 WARNING: no +model_data option specified, using /tmp.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U2.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U3.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U4.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U6.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U7.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U8.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U9.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
||||
[x ps] MRS -> [ 7500 ps] MRS -> ddr3_dimm_micron_sim.ddr3_dimm.U1.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U2.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U3.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U4.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U6.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U7.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U8.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U9.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
||||
[195000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
||||
[510000 ps] NOP -> [370000 ps] MRS ->
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
||||
[10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP -> [40000 ps] ZQC ->
|
||||
[1290000 ps] PRE @ (0) -> [30000 ps] MRS -> [10000 ps] NOP -> [40000 ps] NOP -> [262500 ps] RD @ (0, 0) ->
|
||||
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
|
||||
[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
||||
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
|
||||
[130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
|
||||
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
|
||||
[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
||||
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
|
||||
[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
||||
[480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
|
||||
[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
||||
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> INFO: [Common 17-41] Interrupt caught. Command should exit soon.
|
||||
run: Time (s): cpu = 00:00:03 ; elapsed = 00:01:46 . Memory (MB): peak = 2833.148 ; gain = 8.004 ; free physical = 1466 ; free virtual = 24759
|
||||
INFO: [Common 17-344] 'run' was cancelled
|
||||
xsim: Time (s): cpu = 00:00:04 ; elapsed = 00:01:48 . Memory (MB): peak = 2833.148 ; gain = 844.395 ; free physical = 1466 ; free virtual = 24759
|
||||
INFO: [Common 17-344] 'source' was cancelled
|
||||
xsim% adssss
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,150 @@
|
|||
#-----------------------------------------------------------
|
||||
# xsim v2021.2 (64-bit)
|
||||
# SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
|
||||
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
|
||||
# Start of session at: Wed Jul 5 16:46:56 2023
|
||||
# Process ID: 11548
|
||||
# Current directory: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim
|
||||
# Command line: xsim -log simulate.log -mode tcl -source {xsim.dir/ddr3_dimm_micron_sim/xsim_script.tcl}
|
||||
# Log file: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim/simulate.log
|
||||
# Journal file: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim/xsim.jou
|
||||
# Running On: angelo-desktop, OS: Linux, CPU Frequency: 3552.564 MHz, CPU Physical cores: 2, Host memory: 7450 MB
|
||||
#-----------------------------------------------------------
|
||||
source xsim.dir/ddr3_dimm_micron_sim/xsim_script.tcl
|
||||
# xsim {ddr3_dimm_micron_sim} -autoloadwcfg -tclbatch {cmd.tcl} -key {Behavioral:sim_1:Functional:ddr3_dimm_micron_sim}
|
||||
Time resolution is 1 ps
|
||||
source cmd.tcl
|
||||
## set curr_wave [current_wave_config]
|
||||
## if { [string length $curr_wave] == 0 } {
|
||||
## if { [llength [get_objects]] > 0} {
|
||||
## add_wave /
|
||||
## set_property needs_save false [current_wave_config]
|
||||
## } else {
|
||||
## send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
||||
## }
|
||||
## }
|
||||
## run -all
|
||||
Test ns_to_cycles() function:
|
||||
ns_to_cycles(15) = 3 = 2 [exact]
|
||||
ns_to_cycles(14.5) = 3 = 2 [round-off]
|
||||
ns_to_cycles(11) = 3 = 2 [round-up]
|
||||
|
||||
Test nCK_to_cycles() function:
|
||||
ns_to_cycles(16) = 4 = 4 [exact]
|
||||
ns_to_cycles(15) = 4 = 4 [round-off]
|
||||
ns_to_cycles(13) = 4 = 4 [round-up]
|
||||
|
||||
Test ns_to_nCK() function:
|
||||
ns_to_cycles(15) = 12 = 6 [exact]
|
||||
ns_to_cycles(14.875) = 12 = 6 [round-off]
|
||||
ns_to_cycles(13.875) = 12 = 6 [round-up]
|
||||
ns_to_nCK(tRCD) = 11 = 6 [WRONG]
|
||||
tRTP = 7.5 = 10.000000
|
||||
ns_to_nCK(tRTP) = 6= 4.000000 [WRONG]
|
||||
|
||||
Test nCK_to_ns() function:
|
||||
ns_to_cycles(4) = 5 = 10 [exact]
|
||||
ns_to_cycles(14.875) = 4 = 8 [round-off]
|
||||
ns_to_cycles(13.875) = 7 = 13 [round-up]
|
||||
|
||||
Test nCK_to_ns() function:
|
||||
ns_to_cycles(4) = 5 = 10 [exact]
|
||||
ns_to_cycles(14.875) = 4 = 8 [round-off]
|
||||
ns_to_cycles(13.875) = 7 = 13 [round-up]
|
||||
|
||||
Test $floor() function:
|
||||
$floor(5/2) = 2.5 = 2
|
||||
$floor(9/4) = 2.25 = 2
|
||||
$floor(9/4) = 2 = 2
|
||||
$floor(9/5) = 1.8 = 1
|
||||
|
||||
|
||||
DELAY_COUNTER_WIDTH = 16
|
||||
DELAY_SLOT_WIDTH = 19
|
||||
serdes_ratio = 4
|
||||
wb_addr_bits = 24
|
||||
wb_data_bits = 512
|
||||
wb_sel_bits = 64
|
||||
|
||||
|
||||
READ_SLOT = 2
|
||||
WRITE_SLOT = 3
|
||||
ACTIVATE_SLOT = 0
|
||||
PRECHARGE_SLOT = 1
|
||||
|
||||
|
||||
DELAYS:
|
||||
ns_to_nCK(tRCD): 6
|
||||
ns_to_nCK(tRP): 6
|
||||
ns_to_nCK(tRTP): 4
|
||||
tCCD: 4
|
||||
(CL_nCK + tCCD + 3'd2 - CWL_nCK): 7
|
||||
(CWL_nCK + 3'd4 + ns_to_nCK(tWR)): 15
|
||||
(CWL_nCK + 3'd4 + ns_to_nCK(tWTR)): 13
|
||||
$signed(4'b1100)>>>4: 1111
|
||||
|
||||
|
||||
PRECHARGE_TO_ACTIVATE_DELAY = 3 = 1
|
||||
ACTIVATE_TO_WRITE_DELAY = 3 = 0
|
||||
ACTIVATE_TO_READ_DELAY = 2 = 0
|
||||
READ_TO_WRITE_DELAY = 2 = 1
|
||||
READ_TO_READ_DELAY = 0 = 0
|
||||
READ_TO_PRECHARGE_DELAY = 1 =1
|
||||
WRITE_TO_WRITE_DELAY = 0 = 0
|
||||
WRITE_TO_READ_DELAY = 4 = 3
|
||||
WRITE_TO_PRECHARGE_DELAY = 5 = 4
|
||||
STAGE2_DATA_DEPTH = 2 = 2
|
||||
READ_ACK_PIPE_WIDTH = 6
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U1.file_io_open: at time 0 WARNING: no +model_data option specified, using /tmp.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U2.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U3.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U4.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U6.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U7.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U8.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U9.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
||||
[x ps] MRS -> [ 7500 ps] MRS -> ddr3_dimm_micron_sim.ddr3_dimm.U1.reset at time 304199.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U2.reset at time 304199.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U3.reset at time 304199.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U4.reset at time 304199.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U6.reset at time 304199.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U7.reset at time 304199.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U8.reset at time 304199.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U9.reset at time 304199.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
||||
[195000 ps] NOP -> [510000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task at time 815475.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task at time 815475.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task at time 815475.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task at time 815475.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task at time 815475.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task at time 815475.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task at time 815475.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task at time 815475.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
||||
[370000 ps] MRS ->
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1187975.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1187975.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1187975.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1187975.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1187975.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1187975.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1187975.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1187975.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
||||
[10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP -> [40000 ps] ZQC ->
|
||||
[1290000 ps] PRE @ (0) -> [30000 ps] MRS -> [10000 ps] NOP -> [40000 ps] NOP -> [262500 ps] RD @ (0, 0) ->
|
||||
[140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
|
||||
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
|
||||
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
|
||||
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
|
||||
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
|
||||
[580000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
|
||||
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
|
||||
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
|
||||
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
|
||||
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
|
||||
[150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [580000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
|
||||
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
|
||||
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
|
||||
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
|
||||
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
|
||||
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
|
||||
[150000 ps] RD @ (0, 0) -> [580000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
|
||||
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,12 @@
|
|||
#-----------------------------------------------------------
|
||||
# xsim v2021.2 (64-bit)
|
||||
# SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
|
||||
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
|
||||
# Start of session at: Wed Jul 5 14:00:53 2023
|
||||
# Process ID: 9594
|
||||
# Current directory: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim
|
||||
# Command line: xsim -log simulate.log -mode tcl -source {xsim.dir/ddr3_dimm_micron_sim/xsim_script.tcl}
|
||||
# Log file: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim/simulate.log
|
||||
# Journal file: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim/xsim.jou
|
||||
# Running On: angelo-desktop, OS: Linux, CPU Frequency: 3299.022 MHz, CPU Physical cores: 2, Host memory: 7450 MB
|
||||
#-----------------------------------------------------------
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
#-----------------------------------------------------------
|
||||
# xsim v2021.2 (64-bit)
|
||||
# SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
|
||||
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
|
||||
# Start of session at: Wed Jul 5 14:01:21 2023
|
||||
# Process ID: 9747
|
||||
# Current directory: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim
|
||||
# Command line: xsim -log simulate.log -mode tcl -source {xsim.dir/ddr3_dimm_micron_sim/xsim_script.tcl}
|
||||
# Log file: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim/simulate.log
|
||||
# Journal file: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim/xsim.jou
|
||||
# Running On: angelo-desktop, OS: Linux, CPU Frequency: 3688.963 MHz, CPU Physical cores: 2, Host memory: 7450 MB
|
||||
#-----------------------------------------------------------
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
verilog xil_defaultlib --include "/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/rtl" --include "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench" \
|
||||
"/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" \
|
||||
"/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" \
|
||||
"/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" \
|
||||
|
||||
sv xil_defaultlib --include "/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/rtl" --include "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench" \
|
||||
"/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3.v" \
|
||||
"/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v" \
|
||||
"/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" \
|
||||
|
||||
verilog xil_defaultlib "/home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim/glbl.v"
|
||||
|
||||
nosort
|
||||
Binary file not shown.
|
|
@ -0,0 +1 @@
|
|||
--incr --debug "typical" --relax --mt "auto" -L "xil_defaultlib" -L "uvm" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "ddr3_dimm_micron_sim" "xil_defaultlib.ddr3_dimm_micron_sim" "xil_defaultlib.glbl" -log "elaborate.log"
|
||||
|
|
@ -0,0 +1 @@
|
|||
Breakpoint File Version 1.0
|
||||
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File diff suppressed because one or more lines are too long
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|
|
@ -0,0 +1,12 @@
|
|||
|
||||
{
|
||||
crc : 8377969200457728890 ,
|
||||
ccp_crc : 0 ,
|
||||
cmdline : " --incr --debug typical --relax --mt auto -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl" ,
|
||||
buildDate : "Oct 19 2021" ,
|
||||
buildTime : "02:56:52" ,
|
||||
linkCmd : "/usr/bin/gcc -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/ddr3_dimm_micron_sim/xsimk\" \"xsim.dir/ddr3_dimm_micron_sim/obj/xsim_0.lnx64.o\" \"xsim.dir/ddr3_dimm_micron_sim/obj/xsim_1.lnx64.o\" \"xsim.dir/ddr3_dimm_micron_sim/obj/xsim_2.lnx64.o\" \"xsim.dir/ddr3_dimm_micron_sim/obj/xsim_3.lnx64.o\" \"xsim.dir/ddr3_dimm_micron_sim/obj/xsim_4.lnx64.o\" \"xsim.dir/ddr3_dimm_micron_sim/obj/xsim_5.lnx64.o\" \"xsim.dir/ddr3_dimm_micron_sim/obj/xsim_6.lnx64.o\" \"xsim.dir/ddr3_dimm_micron_sim/obj/xsim_7.lnx64.o\" \"xsim.dir/ddr3_dimm_micron_sim/obj/xsim_8.lnx64.o\" \"xsim.dir/ddr3_dimm_micron_sim/obj/xsim_9.lnx64.o\" \"xsim.dir/ddr3_dimm_micron_sim/obj/xsim_10.lnx64.o\" \"xsim.dir/ddr3_dimm_micron_sim/obj/xsim_11.lnx64.o\" \"xsim.dir/ddr3_dimm_micron_sim/obj/xsim_12.lnx64.o\" \"xsim.dir/ddr3_dimm_micron_sim/obj/xsim_13.lnx64.o\" \"xsim.dir/ddr3_dimm_micron_sim/obj/xsim_14.lnx64.o\" \"xsim.dir/ddr3_dimm_micron_sim/obj/xsim_15.lnx64.o\" -L\"/tools/Xilinx/Vivado/2021.2/lib/lnx64.o\" -lrdi_simulator_kernel -lrdi_simbridge_kernel" ,
|
||||
aggregate_nets :
|
||||
[
|
||||
]
|
||||
}
|
||||
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|
|
@ -0,0 +1,50 @@
|
|||
[General]
|
||||
ARRAY_DISPLAY_LIMIT=512
|
||||
RADIX=hex
|
||||
TIME_UNIT=ns
|
||||
TRACE_LIMIT=2147483647
|
||||
VHDL_ENTITY_SCOPE_FILTER=true
|
||||
VHDL_PACKAGE_SCOPE_FILTER=false
|
||||
VHDL_BLOCK_SCOPE_FILTER=true
|
||||
VHDL_PROCESS_SCOPE_FILTER=false
|
||||
VHDL_PROCEDURE_SCOPE_FILTER=false
|
||||
VERILOG_MODULE_SCOPE_FILTER=true
|
||||
VERILOG_PACKAGE_SCOPE_FILTER=false
|
||||
VERILOG_BLOCK_SCOPE_FILTER=false
|
||||
VERILOG_TASK_SCOPE_FILTER=false
|
||||
VERILOG_PROCESS_SCOPE_FILTER=false
|
||||
INPUT_OBJECT_FILTER=true
|
||||
OUTPUT_OBJECT_FILTER=true
|
||||
INOUT_OBJECT_FILTER=true
|
||||
INTERNAL_OBJECT_FILTER=true
|
||||
CONSTANT_OBJECT_FILTER=true
|
||||
VARIABLE_OBJECT_FILTER=true
|
||||
INPUT_PROTOINST_FILTER=true
|
||||
OUTPUT_PROTOINST_FILTER=true
|
||||
INOUT_PROTOINST_FILTER=true
|
||||
INTERNAL_PROTOINST_FILTER=true
|
||||
CONSTANT_PROTOINST_FILTER=true
|
||||
VARIABLE_PROTOINST_FILTER=true
|
||||
SCOPE_NAME_COLUMN_WIDTH=0
|
||||
SCOPE_DESIGN_UNIT_COLUMN_WIDTH=0
|
||||
SCOPE_BLOCK_TYPE_COLUMN_WIDTH=0
|
||||
OBJECT_NAME_COLUMN_WIDTH=0
|
||||
OBJECT_VALUE_COLUMN_WIDTH=0
|
||||
OBJECT_DATA_TYPE_COLUMN_WIDTH=0
|
||||
PROCESS_NAME_COLUMN_WIDTH=0
|
||||
PROCESS_TYPE_COLUMN_WIDTH=0
|
||||
FRAME_INDEX_COLUMN_WIDTH=0
|
||||
FRAME_NAME_COLUMN_WIDTH=0
|
||||
FRAME_FILE_NAME_COLUMN_WIDTH=0
|
||||
FRAME_LINE_NUM_COLUMN_WIDTH=0
|
||||
LOCAL_NAME_COLUMN_WIDTH=0
|
||||
LOCAL_VALUE_COLUMN_WIDTH=0
|
||||
LOCAL_DATA_TYPE_COLUMN_WIDTH=0
|
||||
PROTO_NAME_COLUMN_WIDTH=0
|
||||
PROTO_VALUE_COLUMN_WIDTH=0
|
||||
INPUT_LOCAL_FILTER=1
|
||||
OUTPUT_LOCAL_FILTER=1
|
||||
INOUT_LOCAL_FILTER=1
|
||||
INTERNAL_LOCAL_FILTER=1
|
||||
CONSTANT_LOCAL_FILTER=1
|
||||
VARIABLE_LOCAL_FILTER=1
|
||||
|
|
@ -0,0 +1 @@
|
|||
xsim {ddr3_dimm_micron_sim} -autoloadwcfg -tclbatch {cmd.tcl} -key {Behavioral:sim_1:Functional:ddr3_dimm_micron_sim}
|
||||
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|
|
@ -0,0 +1,4 @@
|
|||
Running: xsim.dir/ddr3_dimm_micron_sim/xsimk -simmode gui -wdb ddr3_dimm_micron_sim.wdb -simrunnum 0 -socket 40797
|
||||
Design successfully loaded
|
||||
Design Loading Memory Usage: 158688 KB (Peak: 158688 KB)
|
||||
Design Loading CPU Usage: 680 ms
|
||||
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|
|
@ -0,0 +1,12 @@
|
|||
0.7
|
||||
2020.2
|
||||
Oct 19 2021
|
||||
02:56:52
|
||||
/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v,1688533172,verilog,,/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v,,ddr3_controller;mini_fifo,,uvm,/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench;/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/rtl,,,,,
|
||||
/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v,1688382102,verilog,,/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v,,ddr3_phy,,uvm,/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench;/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/rtl,,,,,
|
||||
/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v,1687245962,verilog,,,,ddr3_top,,uvm,/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench;/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/rtl,,,,,
|
||||
/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/8192Mb_ddr3_parameters.vh,1688546597,verilog,,,,,,,,,,,,
|
||||
/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3.v,1687236268,systemVerilog,,/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v,/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/8192Mb_ddr3_parameters.vh,ddr3,,uvm,/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench;/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/rtl,,,,,
|
||||
/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v,1686204490,systemVerilog,,/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v,/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/8192Mb_ddr3_parameters.vh,ddr3_dimm,,uvm,/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench;/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/rtl,,,,,
|
||||
/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v,1688462732,systemVerilog,,,/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/8192Mb_ddr3_parameters.vh,ddr3_dimm_micron_sim,,uvm,/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench;/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/rtl,,,,,
|
||||
/home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim/glbl.v,1634335545,verilog,,,,glbl,,uvm,,,,,,
|
||||
|
|
@ -0,0 +1 @@
|
|||
xil_defaultlib=xsim.dir/xil_defaultlib
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
#-----------------------------------------------------------
|
||||
# xsim v2021.2 (64-bit)
|
||||
# SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
|
||||
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
|
||||
# Start of session at: Wed Jul 5 16:46:56 2023
|
||||
# Process ID: 11548
|
||||
# Current directory: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim
|
||||
# Command line: xsim -log simulate.log -mode tcl -source {xsim.dir/ddr3_dimm_micron_sim/xsim_script.tcl}
|
||||
# Log file: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim/simulate.log
|
||||
# Journal file: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim/xsim.jou
|
||||
# Running On: angelo-desktop, OS: Linux, CPU Frequency: 3552.564 MHz, CPU Physical cores: 2, Host memory: 7450 MB
|
||||
#-----------------------------------------------------------
|
||||
source xsim.dir/ddr3_dimm_micron_sim/xsim_script.tcl
|
||||
source cmd.tcl
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
#-----------------------------------------------------------
|
||||
# xsim v2021.2 (64-bit)
|
||||
# SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
|
||||
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
|
||||
# Start of session at: Wed Jul 5 14:10:39 2023
|
||||
# Process ID: 10147
|
||||
# Current directory: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim
|
||||
# Command line: xsim -log simulate.log -mode tcl -source {xsim.dir/ddr3_dimm_micron_sim/xsim_script.tcl}
|
||||
# Log file: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim/simulate.log
|
||||
# Journal file: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim/xsim.jou
|
||||
# Running On: angelo-desktop, OS: Linux, CPU Frequency: 3689.401 MHz, CPU Physical cores: 2, Host memory: 7450 MB
|
||||
#-----------------------------------------------------------
|
||||
source xsim.dir/ddr3_dimm_micron_sim/xsim_script.tcl
|
||||
source cmd.tcl
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
#-----------------------------------------------------------
|
||||
# xsim v2021.2 (64-bit)
|
||||
# SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
|
||||
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
|
||||
# Start of session at: Wed Jul 5 15:01:38 2023
|
||||
# Process ID: 10611
|
||||
# Current directory: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim
|
||||
# Command line: xsim -log simulate.log -mode tcl -source {xsim.dir/ddr3_dimm_micron_sim/xsim_script.tcl}
|
||||
# Log file: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim/simulate.log
|
||||
# Journal file: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim/xsim.jou
|
||||
# Running On: angelo-desktop, OS: Linux, CPU Frequency: 3667.243 MHz, CPU Physical cores: 2, Host memory: 7450 MB
|
||||
#-----------------------------------------------------------
|
||||
source xsim.dir/ddr3_dimm_micron_sim/xsim_script.tcl
|
||||
source cmd.tcl
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
#-----------------------------------------------------------
|
||||
# xsim v2021.2 (64-bit)
|
||||
# SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
|
||||
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
|
||||
# Start of session at: Wed Jul 5 15:49:42 2023
|
||||
# Process ID: 11039
|
||||
# Current directory: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim
|
||||
# Command line: xsim -log simulate.log -mode tcl -source {xsim.dir/ddr3_dimm_micron_sim/xsim_script.tcl}
|
||||
# Log file: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim/simulate.log
|
||||
# Journal file: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim/xsim.jou
|
||||
# Running On: angelo-desktop, OS: Linux, CPU Frequency: 3693.322 MHz, CPU Physical cores: 2, Host memory: 7450 MB
|
||||
#-----------------------------------------------------------
|
||||
source xsim.dir/ddr3_dimm_micron_sim/xsim_script.tcl
|
||||
source cmd.tcl
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
#-----------------------------------------------------------
|
||||
# xsim v2021.2 (64-bit)
|
||||
# SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
|
||||
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
|
||||
# Start of session at: Wed Jul 5 14:00:53 2023
|
||||
# Process ID: 9594
|
||||
# Current directory: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim
|
||||
# Command line: xsim -log simulate.log -mode tcl -source {xsim.dir/ddr3_dimm_micron_sim/xsim_script.tcl}
|
||||
# Log file: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim/simulate.log
|
||||
# Journal file: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim/xsim.jou
|
||||
# Running On: angelo-desktop, OS: Linux, CPU Frequency: 3299.022 MHz, CPU Physical cores: 2, Host memory: 7450 MB
|
||||
#-----------------------------------------------------------
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
#-----------------------------------------------------------
|
||||
# xsim v2021.2 (64-bit)
|
||||
# SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
|
||||
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
|
||||
# Start of session at: Wed Jul 5 14:01:21 2023
|
||||
# Process ID: 9747
|
||||
# Current directory: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim
|
||||
# Command line: xsim -log simulate.log -mode tcl -source {xsim.dir/ddr3_dimm_micron_sim/xsim_script.tcl}
|
||||
# Log file: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim/simulate.log
|
||||
# Journal file: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim/xsim.jou
|
||||
# Running On: angelo-desktop, OS: Linux, CPU Frequency: 3688.963 MHz, CPU Physical cores: 2, Host memory: 7450 MB
|
||||
#-----------------------------------------------------------
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module ddr3
|
||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module ddr3_dimm
|
||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module ddr3_dimm_micron_sim
|
||||
Binary file not shown.
Loading…
Reference in New Issue