resolve warning from verilator linting

2023-07-16 08:38:20 +08:00 · 2023-07-16 08:38:20 +08:00 · b80bda4a46
parent 019722bc70
commit b80bda4a46
1 changed files with 1 additions and 1 deletions
--- a/rtl/ddr3_phy.v
+++ b/rtl/ddr3_phy.v
@ -99,7 +99,7 @@ module ddr3_phy #(
    always @(posedge i_controller_clk, negedge i_rst_n) begin
        if(!i_rst_n) begin
            sync_rst <= 1'b1;
-            delay_before_release_reset <= SYNC_RESET_DELAY;
+            delay_before_release_reset <= SYNC_RESET_DELAY[$clog2(SYNC_RESET_DELAY):0];
            toggle_dqs_q <= 0;
        end
        else begin