moved FLY_BY_DELAY to this module so multiple instantiated ddr3 can have different set FLY_BY_DELAY

2023-07-13 18:52:43 +08:00 · 2023-07-13 18:52:43 +08:00 · ecb4cb5b2c
parent ee3d9d4be7
commit ecb4cb5b2c
1 changed files with 1 additions and 0 deletions
--- a/testbench/ddr3.v
+++ b/testbench/ddr3.v
@ -138,6 +138,7 @@ module ddr3 (
    parameter feature_truebl4 = 0;
    parameter feature_odt_hi = 0;
    parameter PERTCKAVG=TDLLK;
+    parameter FLY_BY_DELAY = 0;
   
    // text macros
    `define DQ_PER_DQS DQ_BITS/DQS_BITS