resolve vivado warnings
This commit is contained in:
AngeloJacobo
parent
97e740139f
commit
137e30ba36
214
rtl/ddr3_phy.v
214
rtl/ddr3_phy.v
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@ -1,5 +1,6 @@
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`default_nettype none
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`timescale 1ps / 1ps
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module ddr3_phy #(
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parameter ROW_BITS = 14,
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BA_BITS = 3,
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@ -132,8 +133,30 @@ module ddr3_phy #(
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.D2(i_controller_cmd[cmd_len*1 + gen_index]),
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.D3(i_controller_cmd[cmd_len*2 + gen_index]),
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.D4(i_controller_cmd[cmd_len*3 + gen_index]),
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.OCE(1), // 1-bit input: Output data clock enable
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.RST(sync_rst) // 1-bit input: Reset
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.OCE(1'b1), // 1-bit input: Output data clock enable
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.RST(sync_rst), // 1-bit input: Reset
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// unused signals but were added here to make vivado happy
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.SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
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.SHIFTOUT2(),
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.TBYTEOUT(), // 1-bit output: Byte group tristate
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.TFB(), // 1-bit output: 3-state control
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.TQ(), // 1-bit output: 3-state control
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.D5(),
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.D6(),
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.D7(),
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.D8(),
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// SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
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.SHIFTIN1(0),
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.SHIFTIN2(0),
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// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
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.T1(0),
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.T2(0),
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.T3(0),
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.T4(0),
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.TBYTEIN(0),
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// 1-bit input: Byte group tristate
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.TCE(0)
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// 1-bit input: 3-state clock enable
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);
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// End of OSERDESE2_inst instantiation
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@ -153,16 +176,16 @@ module ddr3_phy #(
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.CNTVALUEOUT(), // 5-bit output: Counter value output
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.DATAOUT(cmd[gen_index]), // 1-bit output: Delayed data/clock output
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.C(i_controller_clk), // 1-bit input: Clock input, when using OSERDESE2, C is connected to CLKDIV
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.CE(0), // 1-bit input: Active high enable increment/decrement input
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.CINVCTRL(0), // 1-bit input: Dynamic clock inversion input
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.CLKIN(0), // 1-bit input: Clock delay input
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.CNTVALUEIN(0), // 5-bit input: Counter value input
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.INC(0), // 1-bit input: Increment / Decrement tap delay input
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.LD(0), // 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode, in VAR_LOAD or
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.CE(1'b0), // 1-bit input: Active high enable increment/decrement input
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.CINVCTRL(1'b0), // 1-bit input: Dynamic clock inversion input
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.CLKIN(1'b0), // 1-bit input: Clock delay input
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.CNTVALUEIN(5'd0), // 5-bit input: Counter value input
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.INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
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.LD(1'b0), // 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode, in VAR_LOAD or
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// VAR_LOAD_PIPE mode, loads the value of CNTVALUEIN
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.LDPIPEEN(0), // 1-bit input: Enables the pipeline register to load data
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.LDPIPEEN(1'b0), // 1-bit input: Enables the pipeline register to load data
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.ODATAIN(oserdes_cmd[gen_index]), // 1-bit input: Output delay data input
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.REGRST(0) // 1-bit input: Active-high reset tap-delay input
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.REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input
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);
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end
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endgenerate
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@ -201,8 +224,26 @@ module ddr3_phy #(
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.D6(1'b0),
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.D7(1'b1),
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.D8(1'b0),
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.OCE(1), // 1-bit input: Output data clock enable
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.RST(sync_rst) // 1-bit input: Reset
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.OCE(1'b1), // 1-bit input: Output data clock enable
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.RST(sync_rst), // 1-bit input: Reset
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// unused signals but were added here to make vivado happy
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.SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
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.SHIFTOUT2(),
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.TBYTEOUT(), // 1-bit output: Byte group tristate
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.TFB(), // 1-bit output: 3-state control
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.TQ(), // 1-bit output: 3-state control
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// SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
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.SHIFTIN1(0),
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.SHIFTIN2(0),
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// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
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.T1(0),
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.T2(0),
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.T3(0),
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.T4(0),
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.TBYTEIN(0),
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// 1-bit input: Byte group tristate
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.TCE(0)
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// 1-bit input: 3-state clock enable
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);
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// End of OSERDESE2_inst instantiation
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@ -247,8 +288,22 @@ module ddr3_phy #(
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.D8(i_controller_data[gen_index + (DQ_BITS*LANES)*7]),
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.T1(i_controller_dq_tri_control),
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.TCE(1'b1),
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.OCE(1), // 1-bit input: Output data clock enable
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.RST(sync_rst) // 1-bit input: Reset
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.OCE(1'b1), // 1-bit input: Output data clock enable
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.RST(sync_rst), // 1-bit input: Reset
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// unused signals but were added here to make vivado happy
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.SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
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.SHIFTOUT2(),
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.TBYTEOUT(), // 1-bit output: Byte group tristate
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.TFB(), // 1-bit output: 3-state control
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// SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
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.SHIFTIN1(0),
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.SHIFTIN2(0),
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// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
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.T2(0),
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.T3(0),
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.T4(0),
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.TBYTEIN(0)
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// 1-bit input: Byte group tristate
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);
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// End of OSERDESE2_inst instantiation
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@ -272,15 +327,15 @@ module ddr3_phy #(
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.DATAOUT(odelay_data[gen_index]), // 1-bit output: Delayed data/clock output
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.C(i_controller_clk), // 1-bit input: Clock input, when using OSERDESE2, C is connected to CLKDIV
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.CE(1'b0), // 1-bit input: Active high enable increment/decrement input
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.CINVCTRL(0), // 1-bit input: Dynamic clock inversion input
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.CLKIN(0), // 1-bit input: Clock delay input
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.CINVCTRL(1'b0), // 1-bit input: Dynamic clock inversion input
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.CLKIN(1'b0), // 1-bit input: Clock delay input
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.CNTVALUEIN(i_controller_odelay_data_cntvaluein), // 5-bit input: Counter value input
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.INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
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.LD(i_controller_odelay_data_ld[$rtoi($floor(gen_index/8))]), // 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode, in VAR_LOAD or
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.LD(i_controller_odelay_data_ld[gen_index/8]), // 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode, in VAR_LOAD or
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// VAR_LOAD_PIPE mode, loads the value of CNTVALUEIN
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.LDPIPEEN(0), // 1-bit input: Enables the pipeline register to load data
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.LDPIPEEN(1'b0), // 1-bit input: Enables the pipeline register to load data
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.ODATAIN(oserdes_data[gen_index]), // 1-bit input: Output delay data input
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.REGRST(0) // 1-bit input: Active-high reset tap-delay input
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.REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input
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);
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// IOBUF: Single-ended Bi-directional Buffer
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@ -316,14 +371,14 @@ module ddr3_phy #(
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.DATAOUT(idelay_data[gen_index]), // 1-bit output: Delayed data output
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.C(i_controller_clk), // 1-bit input: Clock input
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.CE(1'b0), // 1-bit input: Active high enable increment/decrement input
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.CINVCTRL(0),// 1-bit input: Dynamic clock inversion input
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.CINVCTRL(1'b0),// 1-bit input: Dynamic clock inversion input
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.CNTVALUEIN(i_controller_idelay_data_cntvaluein), // 5-bit input: Counter value input
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.DATAIN(), //1-bit input: Internal delay data input
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.IDATAIN(read_dq[gen_index]), // 1-bit input: Data input from the I/O
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.INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
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.LD(i_controller_idelay_data_ld[$rtoi($floor(gen_index/8))]), // 1-bit input: Load IDELAY_VALUE input
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.LDPIPEEN(0), // 1-bit input: Enable PIPELINE register to load data input
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.REGRST(0) // 1-bit input: Active-high reset tap-delay input
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.LD(i_controller_idelay_data_ld[gen_index/8]), // 1-bit input: Load IDELAY_VALUE input
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.LDPIPEEN(1'b0), // 1-bit input: Enable PIPELINE register to load data input
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.REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input
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);
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// End of IDELAYE2_inst instantiation
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@ -364,15 +419,15 @@ module ddr3_phy #(
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// SHIFTOUT1-SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
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.SHIFTOUT1(),
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.SHIFTOUT2(),
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.BITSLIP(i_controller_bitslip[$rtoi($floor(gen_index/8))]),
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.BITSLIP(i_controller_bitslip[gen_index/8]),
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// 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to
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// CLKDIV when asserted (active High). Subsequently, the data seen on the Q1
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// to Q8 output ports will shift, as in a barrel-shifter operation, one
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// position every time Bitslip is invoked (DDR operation is different from
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// SDR).
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// CE1, CE2: 1-bit (each) input: Data register clock enable inputs
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.CE1(1),
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.CE2(1),
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.CE1(1'b1),
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.CE2(1'b1),
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.CLKDIVP(), // 1-bit input: TBD
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// Clocks: 1-bit (each) input: ISERDESE2 clock input ports
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.CLK(i_ddr3_clk), // 1-bit input: High-speed clock
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@ -411,7 +466,6 @@ module ddr3_phy #(
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OSERDESE2_dm(
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.OFB(oserdes_dm[gen_index]), // 1-bit output: Feedback path for data
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.OQ(), // 1-bit output: Data path output
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.TQ(),
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.CLK(i_ddr3_clk), // 1-bit input: High speed clock
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.CLKDIV(i_controller_clk), // 1-bit input: Divided clock
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// D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
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@ -423,9 +477,25 @@ module ddr3_phy #(
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.D6(i_controller_dm[gen_index + LANES*5]),
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.D7(i_controller_dm[gen_index + LANES*6]),
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.D8(i_controller_dm[gen_index + LANES*7]),
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.TCE(0),
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.OCE(1), // 1-bit input: Output data clock enable
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.RST(sync_rst) // 1-bit input: Reset
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.TCE(1'b0),
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.OCE(1'b1), // 1-bit input: Output data clock enable
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.RST(sync_rst), // 1-bit input: Reset
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// unused signals but were added here to make vivado happy
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.SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
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.SHIFTOUT2(),
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.TBYTEOUT(), // 1-bit output: Byte group tristate
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.TFB(), // 1-bit output: 3-state control
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.TQ(), // 1-bit output: 3-state control
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// SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
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.SHIFTIN1(0),
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.SHIFTIN2(0),
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// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
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.T1(0),
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.T2(0),
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.T3(0),
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.T4(0),
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.TBYTEIN(0)
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// 1-bit input: Byte group tristate
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);
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// End of OSERDESE2_inst instantiation
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@ -449,15 +519,15 @@ module ddr3_phy #(
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.DATAOUT(odelay_dm[gen_index]), // 1-bit output: Delayed data/clock output
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.C(i_controller_clk), // 1-bit input: Clock input, when using OSERDESE2, C is connected to CLKDIV
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.CE(1'b0), // 1-bit input: Active high enable increment/decrement input
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.CINVCTRL(0), // 1-bit input: Dynamic clock inversion input
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.CLKIN(0), // 1-bit input: Clock delay input
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.CINVCTRL(1'b0), // 1-bit input: Dynamic clock inversion input
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.CLKIN(1'b0), // 1-bit input: Clock delay input
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.CNTVALUEIN(i_controller_odelay_data_cntvaluein), // 5-bit input: Counter value input
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.INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
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.LD(i_controller_odelay_data_ld[gen_index]), // 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode, in VAR_LOAD or
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// VAR_LOAD_PIPE mode, loads the value of CNTVALUEIN
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.LDPIPEEN(0), // 1-bit input: Enables the pipeline register to load data
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.LDPIPEEN(1'b0), // 1-bit input: Enables the pipeline register to load data
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.ODATAIN(oserdes_dm[gen_index]), // 1-bit input: Output delay data input
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.REGRST(0) // 1-bit input: Active-high reset tap-delay input
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.REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input
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);
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// OBUF: Single-ended Output Buffer
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@ -494,16 +564,16 @@ module ddr3_phy #(
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.CNTVALUEOUT(), // 5-bit output: Counter value output
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.DATAOUT(odelay_dqs[gen_index]), // 1-bit output: Delayed data/clock output
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.C(i_controller_clk), // 1-bit input: Clock input, when using OSERDESE2, C is connected to CLKDIV
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.CE(0), // 1-bit input: Active high enable increment/decrement input
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.CINVCTRL(0), // 1-bit input: Dynamic clock inversion input
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.CLKIN(0), // 1-bit input: Clock delay input
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.CE(1'b0), // 1-bit input: Active high enable increment/decrement input
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.CINVCTRL(1'b0), // 1-bit input: Dynamic clock inversion input
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.CLKIN(1'b0), // 1-bit input: Clock delay input
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.CNTVALUEIN(i_controller_odelay_dqs_cntvaluein), // 5-bit input: Counter value input
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.INC(0), // 1-bit input: Increment / Decrement tap delay input
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.INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
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.LD(i_controller_odelay_dqs_ld[gen_index]), // 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode, in VAR_LOAD or
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// VAR_LOAD_PIPE mode, loads the value of CNTVALUEIN
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.LDPIPEEN(0), // 1-bit input: Enables the pipeline register to load data
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.LDPIPEEN(1'b0), // 1-bit input: Enables the pipeline register to load data
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.ODATAIN(oserdes_dqs[gen_index]), // 1-bit input: Output delay data input
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.REGRST(0) // 1-bit input: Active-high reset tap-delay input
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.REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input
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);
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// OSERDESE2: Output SERial/DESerializer with bitslip
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@ -533,8 +603,22 @@ module ddr3_phy #(
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.D8(1'b0 && i_controller_toggle_dqs),
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.T1(i_controller_dqs_tri_control),
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.TCE(1'b1),
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.OCE(1), // 1-bit input: Output data clock enable
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.RST(sync_rst) // 1-bit input: Reset
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.OCE(1'b1), // 1-bit input: Output data clock enable
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.RST(sync_rst), // 1-bit input: Reset
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// unused signals but were added here to make vivado happy
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.SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
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.SHIFTOUT2(),
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.TBYTEOUT(), // 1-bit output: Byte group tristate
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.TFB(), // 1-bit output: 3-state control
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// SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
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.SHIFTIN1(0),
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.SHIFTIN2(0),
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// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
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.T2(0),
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.T3(0),
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.T4(0),
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.TBYTEIN(0)
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// 1-bit input: Byte group tristate
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);
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// End of OSERDESE2_inst instantiation
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@ -572,15 +656,15 @@ module ddr3_phy #(
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.CNTVALUEOUT(), // 5-bit output: Counter value output
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.DATAOUT(idelay_dqs[gen_index]), // 1-bit output: Delayed data output
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.C(i_controller_clk), // 1-bit input: Clock input
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.CE(0), // 1-bit input: Active high enable increment/decrement input
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.CINVCTRL(0),// 1-bit input: Dynamic clock inversion input
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.CE(1'b0), // 1-bit input: Active high enable increment/decrement input
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.CINVCTRL(1'b0),// 1-bit input: Dynamic clock inversion input
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.CNTVALUEIN(i_controller_idelay_dqs_cntvaluein), // 5-bit input: Counter value input
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.DATAIN(), //1-bit input: Internal delay data input
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.IDATAIN(read_dqs[gen_index]), // 1-bit input: Data input from the I/O
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.INC(0), // 1-bit input: Increment / Decrement tap delay input
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.INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
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.LD(i_controller_idelay_dqs_ld[gen_index]), // 1-bit input: Load IDELAY_VALUE input
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.LDPIPEEN(0), // 1-bit input: Enable PIPELINE register to load data input
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.REGRST(0) // 1-bit input: Active-high reset tap-delay input
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.LDPIPEEN(1'b0), // 1-bit input: Enable PIPELINE register to load data input
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.REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input
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);
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// End of IDELAYE2_inst instantiation
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@ -628,8 +712,8 @@ module ddr3_phy #(
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// position every time Bitslip is invoked (DDR operation is different from
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// SDR).
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// CE1, CE2: 1-bit (each) input: Data register clock enable inputs
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.CE1(1),
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.CE2(1),
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.CE1(1'b1),
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.CE2(1'b1),
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.CLKDIVP(), // 1-bit input: TBD
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// Clocks: 1-bit (each) input: ISERDESE2 clock input ports
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.CLK(i_ddr3_clk), // 1-bit input: High-speed clock
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@ -697,8 +781,8 @@ module ddr3_phy #(
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// position every time Bitslip is invoked (DDR operation is different from
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// SDR).
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// CE1, CE2: 1-bit (each) input: Data register clock enable inputs
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.CE1(1),
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.CE2(1),
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.CE1(1'b1),
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.CE2(1'b1),
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.CLKDIVP(), // 1-bit input: TBD
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// Clocks: 1-bit (each) input: ISERDESE2 clock input ports
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.CLK(i_ddr3_clk), // 1-bit input: High-speed clock
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@ -744,8 +828,26 @@ module ddr3_phy #(
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.D6(1'b1),
|
||||
.D7(1'b1),
|
||||
.D8(1'b1),
|
||||
.OCE(1), // 1-bit input: Output data clock enable
|
||||
.RST(sync_rst) // 1-bit input: Reset
|
||||
.OCE(1'b1), // 1-bit input: Output data clock enable
|
||||
.RST(sync_rst), // 1-bit input: Reset
|
||||
// unused signals but were added here to make vivado happy
|
||||
.SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
|
||||
.SHIFTOUT2(),
|
||||
.TBYTEOUT(), // 1-bit output: Byte group tristate
|
||||
.TFB(), // 1-bit output: 3-state control
|
||||
.TQ(), // 1-bit output: 3-state control
|
||||
// SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
|
||||
.SHIFTIN1(0),
|
||||
.SHIFTIN2(0),
|
||||
// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
|
||||
.T1(0),
|
||||
.T2(0),
|
||||
.T3(0),
|
||||
.T4(0),
|
||||
.TBYTEIN(0),
|
||||
// 1-bit input: Byte group tristate
|
||||
.TCE(0)
|
||||
// 1-bit input: 3-state clock enable
|
||||
);
|
||||
// End of OSERDESE2_inst instantiation
|
||||
|
||||
|
|
@ -776,7 +878,7 @@ module ddr3_phy #(
|
|||
.D6(1'b1),
|
||||
.D7(1'b1),
|
||||
.D8(1'b1),
|
||||
.OCE(1), // 1-bit input: Output data clock enable
|
||||
.OCE(1'b1), // 1-bit input: Output data clock enable
|
||||
.RST(sync_rst) // 1-bit input: Reset
|
||||
);
|
||||
// End of OSERDESE2_inst instantiation
|
||||
|
|
@ -804,7 +906,7 @@ module ddr3_phy #(
|
|||
.D6(1'b0 && i_controller_toggle_dqs),
|
||||
.D7(1'b1 && i_controller_toggle_dqs),
|
||||
.D8(1'b0 && i_controller_toggle_dqs),
|
||||
.OCE(1), // 1-bit input: Output data clock enable
|
||||
.OCE(1'b1), // 1-bit input: Output data clock enable
|
||||
.RST(sync_rst) // 1-bit input: Reset
|
||||
);
|
||||
// End of OSERDESE2_inst instantiation
|
||||
|
|
|
|||
Loading…
Reference in New Issue