This commit is contained in:
AngeloJacobo 2023-07-13 19:25:51 +08:00
parent fb7f48b3b8
commit bad4ca3086
1 changed files with 0 additions and 16 deletions

16
run.sh
View File

@ -1,16 +0,0 @@
if [ "$1" == "" ]
then
yosys -q -p "
read_verilog -sv ./rtl/ddr3_top.v;
read_verilog -sv ./rtl/ddr3_controller.v;
read_verilog -sv ./rtl/ddr3_phy.v;
synth -top ddr3_top"
elif [ "$1" == "iverilog" ]
then
iverilog ./rtl/ddr3_top.v ./rtl/ddr3_controller.v ./rtl/ddr3_phy.v -o .out
vvp .out
fi
# :set fileformat=unix