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set parameter FLY_BY_DELAY for each instantiated ddr3, the delay value is retrieved from 8192Mb_ddr3_parameters.vh

This commit is contained in:
AngeloJacobo 2023-07-13 18:55:57 +08:00
parent 6655959514
commit 29ef663d87
1 changed files with 10 additions and 9 deletions
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19
testbench/ddr3_dimm.v
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@ -55,7 +55,8 @@ module ddr3_dimm (
sa ,
sda
);
//added delay for each lane (in referenced to the DQ line) due to the fly-by configuration
`ifdef den1024Mb
`include "1024Mb_ddr3_parameters.vh"
`elsif den2048Mb
@ -200,14 +201,14 @@ module ddr3_dimm (
`endif
`else `ifdef x8
initial if (DEBUG) $display("%m: Component Width = x8");
ddr3 U1 (reset_n, rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[ 9] , rba, raddr[ADDR_BITS-1:0], dq[ 7: 0], dqs[ 0], dqs_n[ 0], dqs_n[ 9], rodt[0]);
ddr3 U2 (reset_n, rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[10] , rba, raddr[ADDR_BITS-1:0], dq[15: 8], dqs[ 1], dqs_n[ 1], dqs_n[10], rodt[0]);
ddr3 U3 (reset_n, rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[11] , rba, raddr[ADDR_BITS-1:0], dq[23:16], dqs[ 2], dqs_n[ 2], dqs_n[11], rodt[0]);
ddr3 U4 (reset_n, rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[12] , rba, raddr[ADDR_BITS-1:0], dq[31:24], dqs[ 3], dqs_n[ 3], dqs_n[12], rodt[0]);
ddr3 U6 (reset_n, rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[13] , rba, raddr[ADDR_BITS-1:0], dq[39:32], dqs[ 4], dqs_n[ 4], dqs_n[13], rodt[0]);
ddr3 U7 (reset_n, rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[14] , rba, raddr[ADDR_BITS-1:0], dq[47:40], dqs[ 5], dqs_n[ 5], dqs_n[14], rodt[0]);
ddr3 U8 (reset_n, rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[15] , rba, raddr[ADDR_BITS-1:0], dq[55:48], dqs[ 6], dqs_n[ 6], dqs_n[15], rodt[0]);
ddr3 U9 (reset_n, rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[16] , rba, raddr[ADDR_BITS-1:0], dq[63:56], dqs[ 7], dqs_n[ 7], dqs_n[16], rodt[0]);
ddr3 #(.FLY_BY_DELAY(FLY_BY_DELAY_LANE_0)) U1 (reset_n, rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[ 9] , rba, raddr[ADDR_BITS-1:0], dq[ 7: 0], dqs[ 0], dqs_n[ 0], dqs_n[ 9], rodt[0]);
ddr3 #(.FLY_BY_DELAY(FLY_BY_DELAY_LANE_1)) U2 (reset_n, rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[10] , rba, raddr[ADDR_BITS-1:0], dq[15: 8], dqs[ 1], dqs_n[ 1], dqs_n[10], rodt[0]);
ddr3 #(.FLY_BY_DELAY(FLY_BY_DELAY_LANE_2)) U3 (reset_n, rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[11] , rba, raddr[ADDR_BITS-1:0], dq[23:16], dqs[ 2], dqs_n[ 2], dqs_n[11], rodt[0]);
ddr3 #(.FLY_BY_DELAY(FLY_BY_DELAY_LANE_3)) U4 (reset_n, rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[12] , rba, raddr[ADDR_BITS-1:0], dq[31:24], dqs[ 3], dqs_n[ 3], dqs_n[12], rodt[0]);
ddr3 #(.FLY_BY_DELAY(FLY_BY_DELAY_LANE_4)) U6 (reset_n, rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[13] , rba, raddr[ADDR_BITS-1:0], dq[39:32], dqs[ 4], dqs_n[ 4], dqs_n[13], rodt[0]);
ddr3 #(.FLY_BY_DELAY(FLY_BY_DELAY_LANE_5)) U7 (reset_n, rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[14] , rba, raddr[ADDR_BITS-1:0], dq[47:40], dqs[ 5], dqs_n[ 5], dqs_n[14], rodt[0]);
ddr3 #(.FLY_BY_DELAY(FLY_BY_DELAY_LANE_6)) U8 (reset_n, rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[15] , rba, raddr[ADDR_BITS-1:0], dq[55:48], dqs[ 6], dqs_n[ 6], dqs_n[15], rodt[0]);
ddr3 #(.FLY_BY_DELAY(FLY_BY_DELAY_LANE_7)) U9 (reset_n, rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[16] , rba, raddr[ADDR_BITS-1:0], dq[63:56], dqs[ 7], dqs_n[ 7], dqs_n[16], rodt[0]);
`ifdef ECC
ddr3 U5 (reset_n, rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[17] , rba, raddr[ADDR_BITS-1:0], cb[ 7: 0], dqs[ 8], dqs_n[ 8], dqs_n[17], rodt[0]);
`endif