update logs
This commit is contained in:
AngeloJacobo
parent
1881e059bc
commit
69c34dbf8f
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ddr3_dimm_micron_sim.sh - Script generated by export_simulation (Vivado v2021.2 (64-bit)-id)
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ddr3
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ddr3_dimm
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ddr3_dimm_micron_sim
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Vivado Simulator v2021.2
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Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
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Running: /tools/Xilinx/Vivado/2021.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt auto -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log
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Starting static elaboration
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Pass Through NonSizing Optimizer
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:204]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:135]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:156]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:157]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:158]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 5 for port 'CNTVALUEIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:159]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:160]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LD' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:161]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:163]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:165]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:250]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:275]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:276]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:281]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:283]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:319]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:325]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:326]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:374]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:375]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'TCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:426]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:427]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:452]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:453]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:458]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:460]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:497]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:498]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:499]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:501]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:504]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:506]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:536]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:575]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:576]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:580]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:582]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:583]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:631]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:632]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:700]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:701]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:747]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:163]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:164]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'cke' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:165]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 's_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:166]
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WARNING: [VRFC 10-3091] actual bit length 14 differs from formal bit length 16 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:171]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'odt' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:172]
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WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:173]
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WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:174]
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WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:203]
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WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:204]
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WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:205]
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WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:206]
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WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:207]
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WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:208]
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WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:209]
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WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:210]
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WARNING: [VRFC 10-5021] port 'scl' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:161]
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WARNING: [VRFC 10-5021] port 'i_controller_dm' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v:119]
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Completed static elaboration
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Starting simulation data flow analysis
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WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
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WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
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WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale.
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WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
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WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
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WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale.
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Completed simulation data flow analysis
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Time Resolution for simulation is 1ps
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Compiling module xil_defaultlib.ddr3_controller(CONTROLLER_CLK_P...
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Compiling module unisims_ver.OSERDESE2(DATA_RATE_OQ="SDR",DAT...
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Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="...
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Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="SDR",DAT...
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Compiling module unisims_ver.OBUFDS
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Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT...
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Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="...
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Compiling module unisims_ver.IOBUF(IOSTANDARD="SSTL15",SLEW="...
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Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="...
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Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE...
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Compiling module unisims_ver.OBUF(SLEW="FAST")
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Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="...
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Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT...
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Compiling module unisims_ver.IOBUFDS(IOSTANDARD="DIFF_SSTL15"...
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Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="...
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Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE...
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Compiling module unisims_ver.IDELAYCTRL_default
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Compiling module xil_defaultlib.ddr3_phy(CONTROLLER_CLK_PERIOD=1...
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Compiling module xil_defaultlib.ddr3_top(CONTROLLER_CLK_PERIOD=1...
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Compiling module xil_defaultlib.ddr3_default
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Compiling module xil_defaultlib.ddr3_dimm_default
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Compiling module xil_defaultlib.ddr3_dimm_micron_sim
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Compiling module xil_defaultlib.glbl
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Built simulation snapshot ddr3_dimm_micron_sim
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****** xsim v2021.2 (64-bit)
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**** SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
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**** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
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** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
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source xsim.dir/ddr3_dimm_micron_sim/xsim_script.tcl
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# xsim {ddr3_dimm_micron_sim} -autoloadwcfg -tclbatch {cmd.tcl} -key {Behavioral:sim_1:Functional:ddr3_dimm_micron_sim}
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Time resolution is 1 ps
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source cmd.tcl
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## set curr_wave [current_wave_config]
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## if { [string length $curr_wave] == 0 } {
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## if { [llength [get_objects]] > 0} {
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## add_wave /
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## set_property needs_save false [current_wave_config]
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## } else {
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## send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
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## }
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## }
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## run -all
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Test ns_to_cycles() function:
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ns_to_cycles(15) = 3 = 2 [exact]
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ns_to_cycles(14.5) = 3 = 2 [round-off]
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ns_to_cycles(11) = 3 = 2 [round-up]
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Test nCK_to_cycles() function:
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ns_to_cycles(16) = 4 = 4 [exact]
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ns_to_cycles(15) = 4 = 4 [round-off]
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ns_to_cycles(13) = 4 = 4 [round-up]
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Test ns_to_nCK() function:
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ns_to_cycles(15) = 12 = 6 [exact]
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ns_to_cycles(14.875) = 12 = 6 [round-off]
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ns_to_cycles(13.875) = 12 = 6 [round-up]
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ns_to_nCK(tRCD) = 11 = 6 [WRONG]
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tRTP = 7.5 = 10.000000
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ns_to_nCK(tRTP) = 6= 4.000000 [WRONG]
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Test nCK_to_ns() function:
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ns_to_cycles(4) = 5 = 10 [exact]
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ns_to_cycles(14.875) = 4 = 8 [round-off]
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ns_to_cycles(13.875) = 7 = 13 [round-up]
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Test nCK_to_ns() function:
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ns_to_cycles(4) = 5 = 10 [exact]
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ns_to_cycles(14.875) = 4 = 8 [round-off]
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ns_to_cycles(13.875) = 7 = 13 [round-up]
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Test $floor() function:
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$floor(5/2) = 2.5 = 2
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$floor(9/4) = 2.25 = 2
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$floor(9/4) = 2 = 2
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$floor(9/5) = 1.8 = 1
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DELAY_COUNTER_WIDTH = 16
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DELAY_SLOT_WIDTH = 19
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serdes_ratio = 4
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wb_addr_bits = 24
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wb_data_bits = 512
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wb_sel_bits = 64
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READ_SLOT = 2
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WRITE_SLOT = 3
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ACTIVATE_SLOT = 0
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PRECHARGE_SLOT = 1
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DELAYS:
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ns_to_nCK(tRCD): 6
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ns_to_nCK(tRP): 6
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ns_to_nCK(tRTP): 4
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tCCD: 4
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(CL_nCK + tCCD + 3'd2 - CWL_nCK): 7
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(CWL_nCK + 3'd4 + ns_to_nCK(tWR)): 15
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(CWL_nCK + 3'd4 + ns_to_nCK(tWTR)): 13
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$signed(4'b1100)>>>4: 1111
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PRECHARGE_TO_ACTIVATE_DELAY = 3 = 1
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ACTIVATE_TO_WRITE_DELAY = 3 = 0
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ACTIVATE_TO_READ_DELAY = 2 = 0
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READ_TO_WRITE_DELAY = 2 = 1
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READ_TO_READ_DELAY = 0 = 0
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READ_TO_PRECHARGE_DELAY = 1 =1
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WRITE_TO_WRITE_DELAY = 0 = 0
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WRITE_TO_READ_DELAY = 4 = 3
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WRITE_TO_PRECHARGE_DELAY = 5 = 4
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STAGE2_DATA_DEPTH = 2 = 2
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READ_ACK_PIPE_WIDTH = 6
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ddr3_dimm_micron_sim.ddr3_dimm.U1.file_io_open: at time 0 WARNING: no +model_data option specified, using /tmp.
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ddr3_dimm_micron_sim.ddr3_dimm.U2.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
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ddr3_dimm_micron_sim.ddr3_dimm.U3.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U4.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U6.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U7.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U8.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U9.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
||||
[x ps] MRS -> [ 7500 ps] MRS -> [195000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.reset at time 314324.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U2.reset at time 314324.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U3.reset at time 314324.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U4.reset at time 314324.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U6.reset at time 314324.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U7.reset at time 314324.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U8.reset at time 314324.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U9.reset at time 314324.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
||||
[510000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task at time 825600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task at time 825600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task at time 825600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task at time 825600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task at time 825600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task at time 825600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task at time 825600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task at time 825600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
||||
[370000 ps] MRS ->
|
||||
[10000 ps] MRS -> ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1198100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1198100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1198100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1198100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1198100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1198100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1198100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
||||
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1198100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
||||
[10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP -> [40000 ps] ZQC ->
|
||||
[1290000 ps] PRE @ (0) -> [30000 ps] MRS -> [10000 ps] NOP -> [40000 ps] NOP -> [262500 ps] RD @ (0, 0) ->
|
||||
[220000 ps] RD @ (0, 0) -> [220000 ps] RD @ (0, 0) -> [230000 ps] RD @ (0, 0) -> [220000 ps] RD @ (0, 0) ->
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue