AngeloJacobo
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efc194a633
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add instantiation template
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2023-11-18 13:35:38 +08:00 |
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AngeloJacobo
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292f94c530
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make 2nd wishbone removable via cyc line
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2023-11-18 13:34:27 +08:00 |
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AngeloJacobo
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c2fc70fb6c
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changed to picosecond-based instead of nanoseconds
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2023-11-14 14:14:16 +08:00 |
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AngeloJacobo
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29ec2d0714
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changed to picosecond-based instead of nanoseconds
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2023-11-14 14:13:41 +08:00 |
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AngeloJacobo
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c514d492f1
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changed to picosecond-based instead of nanoseconds
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2023-11-14 14:11:40 +08:00 |
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AngeloJacobo
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c4a03632ff
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change param to picoseconds, opt_200MHz is not passing due to very high depth required thus removed for now
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2023-11-14 14:07:02 +08:00 |
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AngeloJacobo
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0cfd8243ab
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remove all IODELAY_GROUP lines
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2023-11-11 11:32:14 +08:00 |
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AngeloJacobo
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62f2088d0b
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fix bug when running multiple verification tasks
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2023-11-11 11:20:57 +08:00 |
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AngeloJacobo
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33ec101b79
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resolve bug "Conflicting initialization values for \index"
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2023-11-11 10:18:15 +08:00 |
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AngeloJacobo
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b9b49d67ab
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add xdc file used to test controller in Arty-S7
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2023-11-09 14:16:46 +08:00 |
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AngeloJacobo
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0b7d07e133
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delete old bit and debug files
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2023-11-09 14:14:27 +08:00 |
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AngeloJacobo
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2037044fb4
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fixed reset logic of _top, changed address accessed by ~
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2023-11-09 14:13:08 +08:00 |
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AngeloJacobo
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896d3f4f23
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clean description,and added missing parameters
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2023-11-09 13:49:41 +08:00 |
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AngeloJacobo
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20953ee65f
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fixed bug when ODELAY is not supported, clean file header and description
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2023-11-09 13:25:39 +08:00 |
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Angelo Jacobo
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a1e6ca6656
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Update README.md
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2023-09-21 21:27:53 +08:00 |
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Angelo Jacobo
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72b249a862
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Update README.md
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2023-09-21 06:07:03 +08:00 |
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Angelo Jacobo
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87fa29fcfe
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Update README.md
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2023-09-21 06:04:41 +08:00 |
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AngeloJacobo
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d640e52221
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add wbscope
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2023-09-15 20:05:31 +08:00 |
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AngeloJacobo
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57e9f1b3f9
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update simulation files
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2023-09-15 20:04:55 +08:00 |
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AngeloJacobo
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0ba4f433e5
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add delay option to misalign dq from dqs
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2023-09-15 20:02:05 +08:00 |
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AngeloJacobo
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d834a4d67d
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update wave files
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2023-09-15 20:00:29 +08:00 |
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AngeloJacobo
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a80bacb718
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add reset control from controller to phy
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2023-09-15 19:59:39 +08:00 |
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AngeloJacobo
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922d185643
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now passes internal test calibration on klusterboard
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2023-09-15 19:58:36 +08:00 |
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AngeloJacobo
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8c5c5e30cc
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now passes internal test calibration on klusterboard
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2023-09-15 19:58:12 +08:00 |
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AngeloJacobo
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98b22f79f4
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delete extra xdc file
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2023-09-15 19:56:01 +08:00 |
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AngeloJacobo
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43939ba837
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update autodata files and xdc file
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2023-09-15 19:51:21 +08:00 |
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AngeloJacobo
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20db6352e2
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added write read test after calibration
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2023-09-08 17:15:34 +08:00 |
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AngeloJacobo
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de4fb994b4
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add debug lines and update wb2 registers
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2023-09-05 20:17:10 +08:00 |
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AngeloJacobo
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92c25f394f
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add wire for cue when write leveling starts
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2023-09-05 18:33:20 +08:00 |
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AngeloJacobo
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2ee7e35bc5
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add dci reset and optional DCIEN IO buffers
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2023-09-05 18:32:30 +08:00 |
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AngeloJacobo
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03a1da2ce7
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add calibration when DQS toggles early than DQ
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2023-09-05 18:31:10 +08:00 |
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AngeloJacobo
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4fa30574ef
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not yet working when real parameter is used
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2023-08-24 18:03:12 +08:00 |
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AngeloJacobo
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dc641c188b
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copied settings from litedram
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2023-08-24 18:01:58 +08:00 |
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AngeloJacobo
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47e68d05e1
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added xdc file that uses DCI
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2023-08-24 18:01:24 +08:00 |
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AngeloJacobo
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8f3d673e3d
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fixed bug when issue write calibration has to be repeated
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2023-08-22 16:40:44 +08:00 |
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AngeloJacobo
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fd443ddefd
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add wb2 width
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2023-08-20 13:23:48 +08:00 |
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AngeloJacobo
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83b7b95af4
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pass verilator warning
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2023-08-20 12:32:51 +08:00 |
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AngeloJacobo
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a8aec13ed9
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using different address now finally works!
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2023-08-20 11:52:54 +08:00 |
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AngeloJacobo
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00757338da
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update wcfg
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2023-08-20 11:21:16 +08:00 |
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AngeloJacobo
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5df83b8182
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added working bitfiles for arty s7
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2023-08-20 11:20:41 +08:00 |
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AngeloJacobo
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989e8dd9e7
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use macro for defining the ddr3 config (EIGHT_LANES_x8 or TWO_LANES_x8) and the source of clk (if clock wizard or not)
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2023-08-20 11:13:50 +08:00 |
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AngeloJacobo
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7c68bee5e8
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changed for x8 config
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2023-08-20 11:10:15 +08:00 |
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AngeloJacobo
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e2653d5793
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reset for IO is released only after IDELAYCTRL is ready, added also IODELAY_GROUP
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2023-08-20 11:09:38 +08:00 |
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AngeloJacobo
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9769a7cfaa
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pass formal for 8-lane config and pass verilator linting
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2023-08-20 11:07:22 +08:00 |
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AngeloJacobo
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e839e220c3
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ddr3 model fails when ROW_BITS less than 16 (has Z value in address)
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2023-08-17 11:42:09 +08:00 |
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AngeloJacobo
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ef8b1b84fc
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update wcfg
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2023-08-17 11:41:05 +08:00 |
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AngeloJacobo
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c97e5a8c1f
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added test for testing design in ARTY-S7
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2023-08-17 11:40:41 +08:00 |
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AngeloJacobo
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c9b19ac887
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added uart submodule
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2023-08-17 11:36:15 +08:00 |
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AngeloJacobo
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36c93689e5
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redo read/write calibration if data read is wrong
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2023-08-17 11:27:23 +08:00 |
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AngeloJacobo
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a8bf429bc8
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allow tdqs off and use dm
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2023-08-15 21:17:13 +08:00 |