now passes internal test calibration on klusterboard
This commit is contained in:
AngeloJacobo
parent
8c5c5e30cc
commit
922d185643
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@ -1,5 +1,6 @@
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`default_nettype none
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`timescale 1ps / 1ps
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//`define DEBUG_DQS
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module ddr3_phy #(
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parameter real CONTROLLER_CLK_PERIOD = 12, //ns, period of clock input to this DDR3 controller module
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@ -9,7 +10,7 @@ module ddr3_phy #(
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DQ_BITS = 8,
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LANES = 8,
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parameter[0:0] ODELAY_SUPPORTED = 1, //set to 1 when ODELAYE2 is supported
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USE_IO_TERMINATION = 1, //use IOBUF_DCIEN and IOBUFDS_DCIEN when 1
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USE_IO_TERMINATION = 0, //use IOBUF_DCIEN and IOBUFDS_DCIEN when 1
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// The next parameters act more like a localparam (since user does not have to set this manually) but was added here to simplify port declaration
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parameter serdes_ratio = $rtoi(CONTROLLER_CLK_PERIOD/DDR3_CLK_PERIOD),
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wb_data_bits = DQ_BITS*LANES*serdes_ratio*2,
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@ -21,6 +22,7 @@ module ddr3_phy #(
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input wire i_ddr3_clk_90, //required only when ODELAY_SUPPORTED is zero
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input wire i_rst_n,
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// Controller Interface
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input wire i_controller_reset,
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input wire[cmd_len*serdes_ratio-1:0] i_controller_cmd,
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input wire i_controller_dqs_tri_control, i_controller_dq_tri_control,
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input wire i_controller_toggle_dqs,
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@ -49,7 +51,10 @@ module ddr3_phy #(
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inout wire[(DQ_BITS*LANES)-1:0] io_ddr3_dq,
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inout wire[(DQ_BITS*LANES)/8-1:0] io_ddr3_dqs, io_ddr3_dqs_n,
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output wire[LANES-1:0] o_ddr3_dm,
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output wire o_ddr3_odt // on-die termination
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output wire o_ddr3_odt, // on-die termination
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// DEBUG PHY
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output wire[(DQ_BITS*LANES)/8-1:0] o_ddr3_debug_read_dqs_p,
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output wire[(DQ_BITS*LANES)/8-1:0] o_ddr3_debug_read_dqs_n
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);
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// cmd bit assignment
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@ -62,7 +67,7 @@ module ddr3_phy #(
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CMD_RESET_N = cmd_len - 7,
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CMD_BANK_START = BA_BITS + ROW_BITS - 1,
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CMD_ADDRESS_START = ROW_BITS - 1;
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localparam SYNC_RESET_DELAY = $rtoi($ceil(100/CONTROLLER_CLK_PERIOD)); //52 ns of reset pulse width required for IDELAYCTRL
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localparam SYNC_RESET_DELAY = $rtoi($ceil(1000/CONTROLLER_CLK_PERIOD)); //52 ns of reset pulse width required for IDELAYCTRL
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//cmd needs to be center-aligned to the positive edge of the
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//ddr3_clk. This means cmd needs to be delayed by half the ddr3
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//clk period. Subtract by 600ps to include the IODELAY insertion
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@ -106,10 +111,18 @@ module ddr3_phy #(
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assign o_controller_idelayctrl_rdy = idelayctrl_rdy && dci_locked;
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`ifdef DEBUG_DQS
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assign o_ddr3_debug_read_dqs_p = io_ddr3_dqs;
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assign o_ddr3_debug_read_dqs_n = io_ddr3_dqs_n;
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`else
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assign o_ddr3_debug_read_dqs_p = 0;
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assign o_ddr3_debug_read_dqs_n = 0;
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`endif
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//synchronous reset
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always @(posedge i_controller_clk, negedge i_rst_n) begin
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if(!i_rst_n) begin
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sync_rst <= 1'b0;
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always @(posedge i_controller_clk) begin
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if(!i_rst_n || i_controller_reset) begin
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sync_rst <= 1'b1;
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delay_before_release_reset <= SYNC_RESET_DELAY[$clog2(SYNC_RESET_DELAY):0];
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toggle_dqs_q <= 0;
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end
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@ -144,7 +157,7 @@ module ddr3_phy #(
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.D3(i_controller_cmd[cmd_len*2 + gen_index]),
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.D4(i_controller_cmd[cmd_len*3 + gen_index]),
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.OCE(1'b1), // 1-bit input: Output data clock enable
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.RST(!idelayctrl_rdy), // 1-bit input: Reset
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.RST(sync_rst), // 1-bit input: Reset
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// unused signals but were added here to make vivado happy
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.SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
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.SHIFTOUT2(),
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@ -209,7 +222,7 @@ module ddr3_phy #(
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.D7(1'b1),
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.D8(1'b0),
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.OCE(1'b1), // 1-bit input: Output data clock enable
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.RST(!idelayctrl_rdy), // 1-bit input: Reset
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.RST(sync_rst), // 1-bit input: Reset
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// unused signals but were added here to make vivado happy
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.SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
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.SHIFTOUT2(),
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@ -314,7 +327,7 @@ module ddr3_phy #(
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.T1(i_controller_dq_tri_control),
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.TCE(1'b1),
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.OCE(1'b1), // 1-bit input: Output data clock enable
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.RST(!idelayctrl_rdy), // 1-bit input: Reset
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.RST(sync_rst), // 1-bit input: Reset
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// unused signals but were added here to make vivado happy
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.SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
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.SHIFTOUT2(),
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@ -430,7 +443,7 @@ module ddr3_phy #(
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.T1(i_controller_dq_tri_control),
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.TCE(1'b1),
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.OCE(1'b1), // 1-bit input: Output data clock enable
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.RST(!idelayctrl_rdy), // 1-bit input: Reset
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.RST(sync_rst), // 1-bit input: Reset
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// unused signals but were added here to make vivado happy
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.SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
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.SHIFTOUT2(),
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@ -553,7 +566,7 @@ module ddr3_phy #(
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.DDLY(idelay_data[gen_index]), // 1-bit input: Serial data from IDELAYE2
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.OFB(), // 1-bit input: Data feedback from OSERDESE2
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.OCLKB(), // 1-bit input: High speed negative edge output clock
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.RST(!idelayctrl_rdy), // 1-bit input: Active high asynchronous reset
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.RST(sync_rst), // 1-bit input: Active high asynchronous reset
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// SHIFTIN1-SHIFTIN2: 1-bit (each) input: Data width expansion input ports
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.SHIFTIN1(),
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.SHIFTIN2()
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@ -593,7 +606,7 @@ module ddr3_phy #(
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.D8(i_controller_dm[gen_index + LANES*7]),
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.TCE(1'b0),
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.OCE(1'b1), // 1-bit input: Output data clock enable
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.RST(!idelayctrl_rdy), // 1-bit input: Reset
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.RST(sync_rst), // 1-bit input: Reset
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// unused signals but were added here to make vivado happy
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.SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
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.SHIFTOUT2(),
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@ -683,7 +696,7 @@ module ddr3_phy #(
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.D8(i_controller_dm[gen_index + LANES*7]),
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.TCE(1'b0),
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.OCE(1'b1), // 1-bit input: Output data clock enable
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.RST(!idelayctrl_rdy), // 1-bit input: Reset
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.RST(sync_rst), // 1-bit input: Reset
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// unused signals but were added here to make vivado happy
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.SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
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.SHIFTOUT2(),
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@ -720,8 +733,7 @@ module ddr3_phy #(
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// dqs: odelay -> iobuf
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for(gen_index = 0; gen_index < LANES; gen_index = gen_index + 1) begin
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`ifndef DEBUG_DQS //remove the logic for dqs if needs to be debugged (directed to output instead)
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if(ODELAY_SUPPORTED) begin
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// OSERDESE2: Output SERial/DESerializer with bitslip
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//7 Series
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@ -751,7 +763,7 @@ module ddr3_phy #(
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.T1(i_controller_dqs_tri_control),
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.TCE(1'b1),
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.OCE(1'b1), // 1-bit input: Output data clock enable
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.RST(!idelayctrl_rdy), // 1-bit input: Reset
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.RST(sync_rst), // 1-bit input: Reset
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// unused signals but were added here to make vivado happy
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.SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
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.SHIFTOUT2(),
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@ -861,16 +873,16 @@ module ddr3_phy #(
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// D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
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.D1(1'b1 && (i_controller_toggle_dqs || toggle_dqs_q)), //the last part will still have half dqs series
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.D2(1'b0 && (i_controller_toggle_dqs || toggle_dqs_q)),
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.D3(1'b1 && (i_controller_toggle_dqs || toggle_dqs_q)),
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.D3(1'b1 && (i_controller_toggle_dqs || toggle_dqs_q) && !i_controller_write_leveling_calib),
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.D4(1'b0 && (i_controller_toggle_dqs || toggle_dqs_q)),
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.D5(1'b1 && i_controller_toggle_dqs),
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.D5(1'b1 && i_controller_toggle_dqs && !i_controller_write_leveling_calib),
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.D6(1'b0 && i_controller_toggle_dqs),
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.D7(1'b1 && i_controller_toggle_dqs),
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.D7(1'b1 && i_controller_toggle_dqs && !i_controller_write_leveling_calib),
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.D8(1'b0 && i_controller_toggle_dqs),
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.T1(i_controller_dqs_tri_control),
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.TCE(1'b1),
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.OCE(1'b1), // 1-bit input: Output data clock enable
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.RST(!idelayctrl_rdy), // 1-bit input: Reset
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.RST(sync_rst), // 1-bit input: Reset
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// unused signals but were added here to make vivado happy
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.SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
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.SHIFTOUT2(),
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@ -995,13 +1007,13 @@ module ddr3_phy #(
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.DDLY(idelay_dqs[gen_index]), // 1-bit input: Serial data from IDELAYE2
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.OFB(), // 1-bit input: Data feedback from OSERDESE2
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.OCLKB(), // 1-bit input: High speed negative edge output clock
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.RST(!idelayctrl_rdy), // 1-bit input: Active high asynchronous reset
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.RST(sync_rst), // 1-bit input: Active high asynchronous reset
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// SHIFTIN1-SHIFTIN2: 1-bit (each) input: Data width expansion input ports
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.SHIFTIN1(),
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.SHIFTIN2()
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);
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// End of ISERDESE2_inst instantiation
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`endif
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//ISERDES train
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// End of IOBUF_inst instantiation
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@ -1064,7 +1076,7 @@ module ddr3_phy #(
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.DDLY(), // 1-bit input: Serial data from IDELAYE2
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.OFB(oserdes_bitslip_reference[gen_index]), // 1-bit input: Data feedback from OSERDESE2
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.OCLKB(), // 1-bit input: High speed negative edge output clock
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.RST(!idelayctrl_rdy), // 1-bit input: Active high asynchronous reset
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.RST(sync_rst), // 1-bit input: Active high asynchronous reset
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// SHIFTIN1-SHIFTIN2: 1-bit (each) input: Data width expansion input ports
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.SHIFTIN1(),
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.SHIFTIN2()
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@ -1096,7 +1108,7 @@ module ddr3_phy #(
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.D7(1'b1),
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.D8(1'b1),
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.OCE(1'b1), // 1-bit input: Output data clock enable
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.RST(!idelayctrl_rdy), // 1-bit input: Reset
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.RST(sync_rst), // 1-bit input: Reset
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// unused signals but were added here to make vivado happy
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.SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
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.SHIFTOUT2(),
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