update autodata files and xdc file
This commit is contained in:
AngeloJacobo
parent
20db6352e2
commit
43939ba837
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@ -33,7 +33,6 @@
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################################################################################
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##
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## }}}
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# Wishbone 1
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@PREFIX=ddr3_controller
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@DEVID=DDR3_CONTROLLER
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@ -76,8 +75,8 @@
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@$(DEVID)COL_BITS = 10, // width of column address
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@$(DEVID)BA_BITS = 3, // width of bank address
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@$(DEVID)DQ_BITS = 8, // Size of one octet
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@$(DEVID)LANES = @$(NLANES), //8 lanes of DQ
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@$(DEVID)AUX_WIDTH = 1,
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@$(DEVID)LANES = 8, //@$(NLANES), //8 lanes of DQ
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@$(DEVID)AUX_WIDTH = 8, //must be 8 bits or more (also used in internal test and calibration)
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@$(DEVID)SERDES_RATIO = $rtoi(@$(DEVID)CONTROLLER_CLK_PERIOD/DDR3_CLK_PERIOD),
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//4 is the width of a single ddr3 command {cs_n, ras_n, cas_n, we_n} plus 3 (ck_en, odt, reset_n) plus bank bits plus row bits
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@$(DEVID)CMD_LEN = 4 + 3 + @$(DEVID)BA_BITS + @$(DEVID)ROW_BITS;
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@ -112,13 +111,17 @@
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wire [@$(DEVID)CMD_LEN*@$(DEVID)SERDES_RATIO-1:0] @$(PREFIX)_cmd;
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wire @$(PREFIX)_dqs_tri_control, @$(PREFIX)_dq_tri_control;
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wire @$(PREFIX)_toggle_dqs;
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wire [@$(SLAVE.BUS.WIDTH)-1:0] @$(PREFIX)_data;
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wire [@$(SLAVE.BUS.WIDTH)/8-1:0] @$(PREFIX)_dm;
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wire [@$(DEVID)DQ_BITS*@$(DEVID)LANES*8-1:0] @$(PREFIX)_data;
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wire [(@$(DEVID)DQ_BITS*@$(DEVID)LANES*8)/8-1:0] @$(PREFIX)_dm;
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wire [4:0] @$(PREFIX)_odelay_data_cntvaluein, @$(PREFIX)_odelay_dqs_cntvaluein;
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wire [4:0] @$(PREFIX)_idelay_data_cntvaluein, @$(PREFIX)_idelay_dqs_cntvaluein;
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wire [@$(DEVID)LANES-1:0] @$(PREFIX)_odelay_data_ld, @$(PREFIX)_odelay_dqs_ld;
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wire [@$(DEVID)LANES-1:0] @$(PREFIX)_idelay_data_ld, @$(PREFIX)_idelay_dqs_ld;
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wire [@$(DEVID)LANES-1:0] @$(PREFIX)_bitslip;
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wire @$(PREFIX)_write_leveling_calib;
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wire @$(PREFIX)_reset;
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wire [@$(DEVID)LANES-1:0] @$(PREFIX)_debug_read_dqs_p, @$(PREFIX)_debug_read_dqs_n;
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wire @$(PREFIX)_debug_clk_p, @$(PREFIX)_debug_clk_n;
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// }}}
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@TOP.MAIN=
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// DDR3 Controller-PHY Interface
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@ -132,8 +135,27 @@
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@$(PREFIX)_idelay_data_cntvaluein, @$(PREFIX)_idelay_dqs_cntvaluein,
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@$(PREFIX)_odelay_data_ld, @$(PREFIX)_odelay_dqs_ld,
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@$(PREFIX)_idelay_data_ld, @$(PREFIX)_idelay_dqs_ld,
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@$(PREFIX)_bitslip
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@$(PREFIX)_bitslip,
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@$(PREFIX)_write_leveling_calib,
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@$(PREFIX)_reset
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@TOP.INSERT=
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/*
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wire clk_locked;
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wire controller_clk, ddr3_clk, ref_ddr3_clk, ddr3_clk_90;
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clk_wiz_0 clk_ddr3
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(
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// Clock out ports
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.clk_out1(controller_clk),
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.clk_out2(ddr3_clk),
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.clk_out3(ref_ddr3_clk),
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.clk_out4(ddr3_clk_90),
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// Status and control signals
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.reset(s_reset),
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.locked(clk_locked),
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// Clock in ports
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.clk_in1(s_clk200)
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);
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*/
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// DDR3 PHY Instantiation
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ddr3_phy #(
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.ROW_BITS(@$(DEVID)ROW_BITS), //width of row address
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@ -141,14 +163,17 @@
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.DQ_BITS(@$(DEVID)DQ_BITS), //width of DQ
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.LANES(@$(DEVID)LANES), //8 lanes of DQ
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.CONTROLLER_CLK_PERIOD(@$(DEVID)CONTROLLER_CLK_PERIOD), //ns, period of clock input to this DDR3 controller module
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.DDR3_CLK_PERIOD(DDR3_CLK_PERIOD) //ns, period of clock input to DDR3 RAM device
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.DDR3_CLK_PERIOD(DDR3_CLK_PERIOD), //ns, period of clock input to DDR3 RAM device
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.ODELAY_SUPPORTED(1)
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) ddr3_phy_inst (
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// clock and reset
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.i_controller_clk(s_clk),
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.i_ddr3_clk(s_clk4x),
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.i_ref_clk(s_clk200),
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.i_ddr3_clk_90(0), //required only when ODELAY_SUPPORTED is zero
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.i_rst_n(!s_reset),
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// Controller Interface
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.i_controller_reset(@$(PREFIX)_reset),
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.i_controller_cmd(@$(PREFIX)_cmd),
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.i_controller_dqs_tri_control(@$(PREFIX)_dqs_tri_control),
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.i_controller_dq_tri_control(@$(PREFIX)_dq_tri_control),
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@ -164,6 +189,7 @@
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.i_controller_idelay_data_ld(@$(PREFIX)_idelay_data_ld),
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.i_controller_idelay_dqs_ld(@$(PREFIX)_idelay_dqs_ld),
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.i_controller_bitslip(@$(PREFIX)_bitslip),
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.i_controller_write_leveling_calib(@$(PREFIX)_write_leveling_calib),
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.o_controller_iserdes_data(@$(PREFIX)_iserdes_data),
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.o_controller_iserdes_dqs(@$(PREFIX)_iserdes_dqs),
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.o_controller_iserdes_bitslip_reference(@$(PREFIX)_iserdes_bitslip_reference),
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@ -183,9 +209,12 @@
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.io_ddr3_dqs(io_ddr3_dqs_p),
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.io_ddr3_dqs_n(io_ddr3_dqs_n),
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.o_ddr3_dm(o_ddr3_dm),
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.o_ddr3_odt(o_ddr3_odt[0]) // on-die termination
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.o_ddr3_odt(o_ddr3_odt[0]), // on-die termination
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// DEBUG PHY
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.o_ddr3_debug_read_dqs_p(@$(PREFIX)_debug_read_dqs_p),
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.o_ddr3_debug_read_dqs_n(@$(PREFIX)_debug_read_dqs_n)
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);
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//assign o_tp = {@$(PREFIX)_debug_read_dqs_n[1:0],@$(PREFIX)_debug_read_dqs_p[1:0]};
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assign o_ddr3_s_n[1] = 1; // set to 1 (disabled) since controller only supports single rank
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assign o_ddr3_cke[1] = 0; // set to 0 (disabled) since controller only supports single rank
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assign o_ddr3_odt[1] = 0; // set to 0 (disabled) since controller only supports single rank
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@ -195,7 +224,17 @@
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begin : GEN_UNUSED_@$(DEVID)_ASSIGN
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assign o_ddr3_a[@$(PREFIX)gen_index] = 0;
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end endgenerate
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/*
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// OBUFDS: Differential Output Buffer
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// 7 Series
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// Xilinx HDL Libraries Guide, version 13.4
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OBUFDS OBUFDS_inst (
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.O(o_ddr3_clk_p[1]), // Diff_p output (connect directly to top-level port)
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.OB(o_ddr3_clk_n[1]), // Diff_n output (connect directly to top-level port)
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.I(s_clk4x) // Buffer input
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);
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// End of OBUFDS_inst instantiation
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*/
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@MAIN.PORTLIST=
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// DDR3 Controller Interface
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i_@$(PREFIX)_iserdes_data, i_@$(PREFIX)_iserdes_dqs,
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@ -208,7 +247,9 @@
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o_@$(PREFIX)_idelay_data_cntvaluein, o_@$(PREFIX)_idelay_dqs_cntvaluein,
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o_@$(PREFIX)_odelay_data_ld, o_@$(PREFIX)_odelay_dqs_ld,
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o_@$(PREFIX)_idelay_data_ld, o_@$(PREFIX)_idelay_dqs_ld,
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o_@$(PREFIX)_bitslip
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o_@$(PREFIX)_bitslip,
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o_@$(PREFIX)_leveling_calib,
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o_@$(PREFIX)_reset
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@MAIN.PARAM=@$(TOP.PARAM)
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@MAIN.IODECL=
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// DDR3 Controller I/O declarations
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@ -220,18 +261,20 @@
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output wire [@$(DEVID)CMD_LEN*@$(DEVID)SERDES_RATIO-1:0] o_@$(PREFIX)_cmd;
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output wire o_@$(PREFIX)_dqs_tri_control, o_@$(PREFIX)_dq_tri_control;
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output wire o_@$(PREFIX)_toggle_dqs;
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output wire [@$(SLAVE.BUS.WIDTH)-1:0] o_@$(PREFIX)_data;
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output wire [@$(SLAVE.BUS.WIDTH)/8-1:0] o_@$(PREFIX)_dm;
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output wire [@$(DEVID)DQ_BITS*@$(DEVID)LANES*8-1:0] o_@$(PREFIX)_data;
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output wire [(@$(DEVID)DQ_BITS*@$(DEVID)LANES*8)/8-1:0] o_@$(PREFIX)_dm;
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output wire [4:0] o_@$(PREFIX)_odelay_data_cntvaluein, o_@$(PREFIX)_odelay_dqs_cntvaluein;
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output wire [4:0] o_@$(PREFIX)_idelay_data_cntvaluein, o_@$(PREFIX)_idelay_dqs_cntvaluein;
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output wire [@$(DEVID)LANES-1:0] o_@$(PREFIX)_odelay_data_ld, o_@$(PREFIX)_odelay_dqs_ld;
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output wire [@$(DEVID)LANES-1:0] o_@$(PREFIX)_idelay_data_ld, o_@$(PREFIX)_idelay_dqs_ld;
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output wire [@$(DEVID)LANES-1:0] o_@$(PREFIX)_bitslip;
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output wire o_@$(PREFIX)_leveling_calib;
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output wire o_@$(PREFIX)_reset;
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// }}}
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@MAIN.DEFNS=
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// Verilator lint_off UNUSED
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wire [@$(DEVID)AUX_WIDTH-1:0] @$(PREFIX)_aux_out;
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wire [31:0] @$(PREFIX)_debug1, @$(PREFIX)_debug2;
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wire [31:0] @$(PREFIX)_debug1, @$(PREFIX)_debug2, @$(PREFIX)_debug3;
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// Verilator lint_on UNUSED
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@MAIN.INSERT=
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////////////////////////////////////////////////////////////////////////
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@ -247,6 +290,8 @@
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.DQ_BITS(@$(DEVID)DQ_BITS), //width of DQ
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.LANES(@$(DEVID)LANES), //8 lanes of DQ
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.AUX_WIDTH(@$(DEVID)AUX_WIDTH), //
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.MICRON_SIM(0), //simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
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.ODELAY_SUPPORTED(1), //set to 1 when ODELAYE2 is supported
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.OPT_LOWPOWER(1), //1 = low power, 0 = low logic
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.OPT_BUS_ABORT(1) //1 = can abort bus, 0 = no abort (i_wb_cyc will be ignored, ideal for an AXI implementation which cannot abort transaction)
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) ddr3_controller_inst (
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@ -279,9 +324,12 @@
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.o_phy_idelay_data_ld(o_@$(PREFIX)_idelay_data_ld),
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.o_phy_idelay_dqs_ld(o_@$(PREFIX)_idelay_dqs_ld),
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.o_phy_bitslip(o_@$(PREFIX)_bitslip),
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.o_phy_write_leveling_calib(o_@$(PREFIX)_leveling_calib),
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.o_phy_reset(o_@$(PREFIX)_reset),
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// Debug port
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.o_debug1(@$(PREFIX)_debug1),
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.o_debug2(@$(PREFIX)_debug2)
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.o_debug2(@$(PREFIX)_debug2),
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.o_debug3(@$(PREFIX)_debug3)
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);
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// }}}
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##
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@ -54,3 +54,15 @@
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@INT.DDR3SCOPE2.PIC=altpic
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@INT.DDR3SCOPE2.WIRE=@$(PREFIX)_int
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@MAIN.DEFNS=
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#
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#
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@PREFIX=scope3_ddr3
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@DEVID=DDR3SCOPE3
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@TARGET=ddr3_controller
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@TRIGGER=ddr3_controller_debug3[31]
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@DEBUG=@$(TARGET)_debug3[30:0]
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@$LOG_CAPTURE_SIZE=10
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@INCLUDEFILE=wbscopc.txt
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@INT.DDR3SCOPE2.PIC=altpic
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@INT.DDR3SCOPE2.WIRE=@$(PREFIX)_int
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@MAIN.DEFNS=
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@ -78,17 +78,40 @@ public:
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virtual void define_traces(void) {
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/*
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assign o_debug1 = {debug_trigger, o_wb2_stall, lane[2:0], dqs_start_index_stored[2:0], dqs_target_index[2:0], delay_before_read_data[2:0],
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o_phy_idelay_dqs_ld[lane], state_calibrate[4:0], dqs_store[11:0]};
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*/
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register_trace("o_wb2_stall",1,30);
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register_trace("lane",3,27);
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register_trace("dqs_start_index_stored",3,24);
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register_trace("dqs_target_index",3,21);
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register_trace("delay_before_read_data",3,18);
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register_trace("o_phy_idelay_dqs_ld",1,17);
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register_trace("state_calibrate",5,12);
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register_trace("dqs_store",12,0);
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assign o_debug1 = {debug_trigger, 2'b00, delay_before_read_data[3:0] ,i_phy_idelayctrl_rdy, lane[2:0], dqs_start_index_stored[4:0],
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dqs_target_index[4:0], instruction_address[4:0], state_calibrate[4:0], o_wb2_stall};
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register_trace("delay_before_read_data",4,25);
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register_trace("i_phy_idelayctrl_rdy",1,24);
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register_trace("lane",3,21);
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register_trace("dqs_start_index_stored",5,16);
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register_trace("dqs_target_index",5,11);
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register_trace("instruction_address",5,6);
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register_trace("state_calibrate",5,1);
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register_trace("o_wb2_stall",1,0);
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*/
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/*
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assign o_debug1 = {debug_trigger,stage1_we,stage1_col[5:0],stage1_data[7:0],stage1_dm[15:0]};
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register_trace("stage1_we",1,30);
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register_trace("stage1_col",6,24);
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register_trace("stage1_data",8,16);
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register_trace("stage1_dm",16,0);
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*/
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/*
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assign o_debug1 = {debug_trigger,i_phy_iserdes_dqs[7:0],state_calibrate[4:0], instruction_address[4:0],o_phy_idelay_dqs_ld,o_phy_idelay_data_ld,o_phy_odelay_data_ld,o_phy_odelay_dqs_ld,
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delay_before_read_data[2:0],delay_before_write_level_feedback[4:0],lane};
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assign o_debug1 = {debug_trigger,i_phy_iserdes_dqs[7:0],state_calibrate[4:0], instruction_address[4:0],reset_from_wb2,
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repeat_test, delay_before_read_data[2:0], delay_before_write_level_feedback[4:0],lane[2:0]};
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*/
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register_trace("i_phy_iserdes_dqs",8,23);
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register_trace("state_calibrate",5,18);
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register_trace("instruction_address",5,13);
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register_trace("reset_from_wb2",1,12);
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register_trace("repeat_test",1,11);
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register_trace("delay_before_read_data",3,8);
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register_trace("delay_before_write_level_feedback",5,3);
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register_trace("lane",3,0);
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}
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};
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@ -80,9 +80,9 @@ public:
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/*
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assign o_debug2 = {debug_trigger, idelay_dqs_cntvaluein[lane][4:0], idelay_data_cntvaluein[lane][4:0], i_phy_iserdes_dqs[15:0],
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o_phy_dqs_tri_control, o_phy_dq_tri_control,
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(i_phy_iserdes_data == {(DQ_BITS*LANES*8){1'b0}}), (i_phy_iserdes_data == {(DQ_BITS*LANES*8){1'b1}}), (i_phy_iserdes_data < { {(DQ_BITS*LANES*4){1'b0}}, {(DQ_BITS*LANES*4){1'b1}} } )
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(i_phy_iserdes_data == 0), (i_phy_iserdes_data == {(DQ_BITS*LANES*8){1'b1}}), (i_phy_iserdes_data < { {(DQ_BITS*LANES*4){1'b0}}, {(DQ_BITS*LANES*4){1'b1}} } )
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};
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*/
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register_trace("idelay_dqs_cntvaluein",5,26);
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register_trace("idelay_data_cntvaluein",5,21);
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@ -93,6 +93,11 @@ public:
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register_trace("i_phy_iserdes_data_is_zero",1,2);
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register_trace("i_phy_iserdes_data_all_1s",1,1);
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register_trace("i_phy_iserdes_data_less_than_half",1,0);
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*/
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/*
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assign o_debug2 = {debug_trigger,i_phy_iserdes_data[62:32]};
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*/
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register_trace("i_phy_iserdes_data_62_32",31,0);
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}
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};
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@ -270,121 +270,121 @@ create_clock -period 5.0 -name SYSCLK -waveform { 0.0 2.50 } -add [get_ports i_c
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### Byte lane #0
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### {{{
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#set_property -dict {PACKAGE_PIN AB17 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[0]]
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#set_property -dict {PACKAGE_PIN AC18 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[1]]
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#set_property -dict {PACKAGE_PIN AC17 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[2]]
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#set_property -dict {PACKAGE_PIN AD19 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[3]]
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#set_property -dict {PACKAGE_PIN AA19 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[4]]
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#set_property -dict {PACKAGE_PIN AA20 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[5]]
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#set_property -dict {PACKAGE_PIN AD18 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[6]]
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#set_property -dict {PACKAGE_PIN AC16 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[7]]
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#set_property -dict {PACKAGE_PIN AD20 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_p[0]]
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#set_property -dict {PACKAGE_PIN AE20 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_n[0]]
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#set_property -dict {PACKAGE_PIN AB17 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[0]]
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#set_property -dict {PACKAGE_PIN AC18 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[1]]
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#set_property -dict {PACKAGE_PIN AC17 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[2]]
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#set_property -dict {PACKAGE_PIN AD19 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[3]]
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#set_property -dict {PACKAGE_PIN AA19 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[4]]
|
||||
#set_property -dict {PACKAGE_PIN AA20 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[5]]
|
||||
#set_property -dict {PACKAGE_PIN AD18 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[6]]
|
||||
#set_property -dict {PACKAGE_PIN AC16 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[7]]
|
||||
#set_property -dict {PACKAGE_PIN AD20 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_p[0]]
|
||||
#set_property -dict {PACKAGE_PIN AE20 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_n[0]]
|
||||
#set_property -dict {PACKAGE_PIN AC19 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports o_ddr3_dm[0]]
|
||||
### }}}
|
||||
|
||||
### Byte lane #1
|
||||
### {{{
|
||||
#set_property -dict {PACKAGE_PIN V16 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[8]]
|
||||
#set_property -dict {PACKAGE_PIN V18 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[9]]
|
||||
#set_property -dict {PACKAGE_PIN AB20 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[10]]
|
||||
#set_property -dict {PACKAGE_PIN AB19 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[11]]
|
||||
#set_property -dict {PACKAGE_PIN W15 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[12]]
|
||||
#set_property -dict {PACKAGE_PIN V19 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[13]]
|
||||
#set_property -dict {PACKAGE_PIN W16 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[14]]
|
||||
#set_property -dict {PACKAGE_PIN Y17 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[15]]
|
||||
#set_property -dict {PACKAGE_PIN W18 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_p[1]]
|
||||
#set_property -dict {PACKAGE_PIN W19 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_n[1]]
|
||||
#set_property -dict {PACKAGE_PIN V16 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[8]]
|
||||
#set_property -dict {PACKAGE_PIN V18 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[9]]
|
||||
#set_property -dict {PACKAGE_PIN AB20 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[10]]
|
||||
#set_property -dict {PACKAGE_PIN AB19 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[11]]
|
||||
#set_property -dict {PACKAGE_PIN W15 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[12]]
|
||||
#set_property -dict {PACKAGE_PIN V19 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[13]]
|
||||
#set_property -dict {PACKAGE_PIN W16 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[14]]
|
||||
#set_property -dict {PACKAGE_PIN Y17 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[15]]
|
||||
#set_property -dict {PACKAGE_PIN W18 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_p[1]]
|
||||
#set_property -dict {PACKAGE_PIN W19 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_n[1]]
|
||||
#set_property -dict {PACKAGE_PIN V17 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports o_ddr3_dm[1]]
|
||||
### }}}
|
||||
|
||||
### Byte lane #2
|
||||
### {{{
|
||||
#set_property -dict {PACKAGE_PIN AF19 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[16]]
|
||||
#set_property -dict {PACKAGE_PIN AE17 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[17]]
|
||||
#set_property -dict {PACKAGE_PIN AE15 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[18]]
|
||||
#set_property -dict {PACKAGE_PIN AF15 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[19]]
|
||||
#set_property -dict {PACKAGE_PIN AF20 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[20]]
|
||||
#set_property -dict {PACKAGE_PIN AD16 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[21]]
|
||||
#set_property -dict {PACKAGE_PIN AD15 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[22]]
|
||||
#set_property -dict {PACKAGE_PIN AF14 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[23]]
|
||||
#set_property -dict {PACKAGE_PIN AE18 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_p[2]]
|
||||
#set_property -dict {PACKAGE_PIN AF18 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_n[2]]
|
||||
#set_property -dict {PACKAGE_PIN AF19 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[16]]
|
||||
#set_property -dict {PACKAGE_PIN AE17 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[17]]
|
||||
#set_property -dict {PACKAGE_PIN AE15 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[18]]
|
||||
#set_property -dict {PACKAGE_PIN AF15 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[19]]
|
||||
#set_property -dict {PACKAGE_PIN AF20 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[20]]
|
||||
#set_property -dict {PACKAGE_PIN AD16 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[21]]
|
||||
#set_property -dict {PACKAGE_PIN AD15 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[22]]
|
||||
#set_property -dict {PACKAGE_PIN AF14 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[23]]
|
||||
#set_property -dict {PACKAGE_PIN AE18 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_p[2]]
|
||||
#set_property -dict {PACKAGE_PIN AF18 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_n[2]]
|
||||
#set_property -dict {PACKAGE_PIN AF17 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports o_ddr3_dm[2]]
|
||||
### }}}
|
||||
|
||||
### Byte lane #3
|
||||
### {{{
|
||||
#set_property -dict {PACKAGE_PIN AA15 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[24]]
|
||||
#set_property -dict {PACKAGE_PIN AB16 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[25]]
|
||||
#set_property -dict {PACKAGE_PIN AD14 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[26]]
|
||||
#set_property -dict {PACKAGE_PIN AB14 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[27]]
|
||||
#set_property -dict {PACKAGE_PIN AA18 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[28]]
|
||||
#set_property -dict {PACKAGE_PIN AA17 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[29]]
|
||||
#set_property -dict {PACKAGE_PIN AB15 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[30]]
|
||||
#set_property -dict {PACKAGE_PIN AC14 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[31]]
|
||||
#set_property -dict {PACKAGE_PIN Y15 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_p[3]]
|
||||
#set_property -dict {PACKAGE_PIN Y16 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_n[3]]
|
||||
#set_property -dict {PACKAGE_PIN AA15 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[24]]
|
||||
#set_property -dict {PACKAGE_PIN AB16 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[25]]
|
||||
#set_property -dict {PACKAGE_PIN AD14 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[26]]
|
||||
#set_property -dict {PACKAGE_PIN AB14 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[27]]
|
||||
#set_property -dict {PACKAGE_PIN AA18 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[28]]
|
||||
#set_property -dict {PACKAGE_PIN AA17 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[29]]
|
||||
#set_property -dict {PACKAGE_PIN AB15 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[30]]
|
||||
#set_property -dict {PACKAGE_PIN AC14 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[31]]
|
||||
#set_property -dict {PACKAGE_PIN Y15 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_p[3]]
|
||||
#set_property -dict {PACKAGE_PIN Y16 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_n[3]]
|
||||
#set_property -dict {PACKAGE_PIN AA14 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports o_ddr3_dm[3]]
|
||||
### }}}
|
||||
|
||||
### Byte lane #4
|
||||
### {{{
|
||||
#set_property -dict {PACKAGE_PIN AD6 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[32]]
|
||||
#set_property -dict {PACKAGE_PIN AC6 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[33]]
|
||||
#set_property -dict {PACKAGE_PIN AC3 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[34]]
|
||||
#set_property -dict {PACKAGE_PIN AB4 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[35]]
|
||||
#set_property -dict {PACKAGE_PIN AB6 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[36]]
|
||||
#set_property -dict {PACKAGE_PIN Y6 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[37]]
|
||||
#set_property -dict {PACKAGE_PIN Y5 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[38]]
|
||||
#set_property -dict {PACKAGE_PIN AA4 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[39]]
|
||||
#set_property -dict {PACKAGE_PIN AA5 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_p[4]]
|
||||
#set_property -dict {PACKAGE_PIN AB5 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_n[4]]
|
||||
#set_property -dict {PACKAGE_PIN AD6 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[32]]
|
||||
#set_property -dict {PACKAGE_PIN AC6 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[33]]
|
||||
#set_property -dict {PACKAGE_PIN AC3 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[34]]
|
||||
#set_property -dict {PACKAGE_PIN AB4 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[35]]
|
||||
#set_property -dict {PACKAGE_PIN AB6 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[36]]
|
||||
#set_property -dict {PACKAGE_PIN Y6 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[37]]
|
||||
#set_property -dict {PACKAGE_PIN Y5 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[38]]
|
||||
#set_property -dict {PACKAGE_PIN AA4 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[39]]
|
||||
#set_property -dict {PACKAGE_PIN AA5 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_p[4]]
|
||||
#set_property -dict {PACKAGE_PIN AB5 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_n[4]]
|
||||
#set_property -dict {PACKAGE_PIN AC4 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports o_ddr3_dm[4]]
|
||||
### }}}
|
||||
|
||||
### Byte lane #5
|
||||
### {{{
|
||||
#set_property -dict {PACKAGE_PIN AF3 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[40]]
|
||||
#set_property -dict {PACKAGE_PIN AE3 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[41]]
|
||||
#set_property -dict {PACKAGE_PIN AE2 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[42]]
|
||||
#set_property -dict {PACKAGE_PIN AE1 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[43]]
|
||||
#set_property -dict {PACKAGE_PIN AE6 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[44]]
|
||||
#set_property -dict {PACKAGE_PIN AE5 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[45]]
|
||||
#set_property -dict {PACKAGE_PIN AD4 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[46]]
|
||||
#set_property -dict {PACKAGE_PIN AD1 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[47]]
|
||||
#set_property -dict {PACKAGE_PIN AF5 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_p[5]]
|
||||
#set_property -dict {PACKAGE_PIN AF4 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_n[5]]
|
||||
#set_property -dict {PACKAGE_PIN AF3 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[40]]
|
||||
#set_property -dict {PACKAGE_PIN AE3 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[41]]
|
||||
#set_property -dict {PACKAGE_PIN AE2 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[42]]
|
||||
#set_property -dict {PACKAGE_PIN AE1 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[43]]
|
||||
#set_property -dict {PACKAGE_PIN AE6 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[44]]
|
||||
#set_property -dict {PACKAGE_PIN AE5 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[45]]
|
||||
#set_property -dict {PACKAGE_PIN AD4 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[46]]
|
||||
#set_property -dict {PACKAGE_PIN AD1 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[47]]
|
||||
#set_property -dict {PACKAGE_PIN AF5 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_p[5]]
|
||||
#set_property -dict {PACKAGE_PIN AF4 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_n[5]]
|
||||
#set_property -dict {PACKAGE_PIN AF2 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports o_ddr3_dm[5]]
|
||||
### }}}
|
||||
|
||||
### Byte lane #6
|
||||
### {{{
|
||||
#set_property -dict {PACKAGE_PIN W3 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[48]]
|
||||
#set_property -dict {PACKAGE_PIN V4 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[49]]
|
||||
#set_property -dict {PACKAGE_PIN U2 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[50]]
|
||||
#set_property -dict {PACKAGE_PIN U5 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[51]]
|
||||
#set_property -dict {PACKAGE_PIN V6 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[52]]
|
||||
#set_property -dict {PACKAGE_PIN V3 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[53]]
|
||||
#set_property -dict {PACKAGE_PIN U1 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[54]]
|
||||
#set_property -dict {PACKAGE_PIN U6 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[55]]
|
||||
#set_property -dict {PACKAGE_PIN W6 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_p[6]]
|
||||
#set_property -dict {PACKAGE_PIN W5 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_n[6]]
|
||||
#set_property -dict {PACKAGE_PIN W3 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[48]]
|
||||
#set_property -dict {PACKAGE_PIN V4 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[49]]
|
||||
#set_property -dict {PACKAGE_PIN U2 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[50]]
|
||||
#set_property -dict {PACKAGE_PIN U5 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[51]]
|
||||
#set_property -dict {PACKAGE_PIN V6 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[52]]
|
||||
#set_property -dict {PACKAGE_PIN V3 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[53]]
|
||||
#set_property -dict {PACKAGE_PIN U1 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[54]]
|
||||
#set_property -dict {PACKAGE_PIN U6 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[55]]
|
||||
#set_property -dict {PACKAGE_PIN W6 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_p[6]]
|
||||
#set_property -dict {PACKAGE_PIN W5 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_n[6]]
|
||||
#set_property -dict {PACKAGE_PIN U7 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports o_ddr3_dm[6]]
|
||||
### }}}
|
||||
|
||||
### Byte lane #7
|
||||
### {{{
|
||||
#set_property -dict {PACKAGE_PIN AB2 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[56]]
|
||||
#set_property -dict {PACKAGE_PIN AA3 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[57]]
|
||||
#set_property -dict {PACKAGE_PIN W1 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[58]]
|
||||
#set_property -dict {PACKAGE_PIN V2 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[59]]
|
||||
#set_property -dict {PACKAGE_PIN AC2 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[60]]
|
||||
#set_property -dict {PACKAGE_PIN Y3 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[61]]
|
||||
#set_property -dict {PACKAGE_PIN Y2 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[62]]
|
||||
#set_property -dict {PACKAGE_PIN V1 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[63]]
|
||||
#set_property -dict {PACKAGE_PIN AB1 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_p[7]]
|
||||
#set_property -dict {PACKAGE_PIN AC1 IOSTANDARD DIFF_SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_n[7]]
|
||||
#set_property -dict {PACKAGE_PIN AB2 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[56]]
|
||||
#set_property -dict {PACKAGE_PIN AA3 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[57]]
|
||||
#set_property -dict {PACKAGE_PIN W1 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[58]]
|
||||
#set_property -dict {PACKAGE_PIN V2 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[59]]
|
||||
#set_property -dict {PACKAGE_PIN AC2 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[60]]
|
||||
#set_property -dict {PACKAGE_PIN Y3 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[61]]
|
||||
#set_property -dict {PACKAGE_PIN Y2 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[62]]
|
||||
#set_property -dict {PACKAGE_PIN V1 IOSTANDARD SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dq[63]]
|
||||
#set_property -dict {PACKAGE_PIN AB1 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_p[7]]
|
||||
#set_property -dict {PACKAGE_PIN AC1 IOSTANDARD DIFF_SSTL15_T_DCI SLEW FAST VCCAUX_IO HIGH} [get_ports io_ddr3_dqs_n[7]]
|
||||
#set_property -dict {PACKAGE_PIN Y1 IOSTANDARD SSTL15 SLEW FAST VCCAUX_IO HIGH} [get_ports o_ddr3_dm[7]]
|
||||
### }}}
|
||||
|
||||
|
|
@ -453,8 +453,8 @@ set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
|
|||
set_property INTERNAL_VREF 0.750 [get_iobanks 32]
|
||||
set_property INTERNAL_VREF 0.750 [get_iobanks 33]
|
||||
set_property INTERNAL_VREF 0.750 [get_iobanks 34]
|
||||
#set_property DCI_CASCADE {{32}} [get_iobanks 34]
|
||||
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]
|
||||
set_property BITSTREAM.STARTUP.MATCH_CYCLE 6 [current_design]
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue