fixed bug when ODELAY is not supported, clean file header and description
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AngeloJacobo
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a1e6ca6656
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20953ee65f
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@ -1,57 +1,55 @@
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// Background:
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// This DDR3 controller will be used with a DDR3-1600 with Kintex 7 FPGA Board (XC7K160T-3FFG676E).
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////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: ddr3_controller.v
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// {{{
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// Project: DDR3 Controller
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//
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// Purpose: This DDR3 controller was originally designed to be used on the
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// Network Switch Project (https://github.com/ZipCPU/eth10g). The Network Switch
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// project uses a Kintex 7 FPGA (XC7K160T-3FFG676E).
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// The goal will be to:
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// - Run this at 1600Mbps (Maximum Physical Interface (PHY) Rate for a 4:1
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// memory controller based on "DC and AC Switching Characteristics" for Kintex 7)
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// - Parameterize everything
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// - Interface should be (nearly) bus agnostic
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// - High (sustained) data throughput. Sequential writes should be able to continue without interruption
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//
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// Engineer: Angelo C. Jacobo
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//
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////////////////////////////////////////////////////////////////////////////////
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//`define FORMAL_COVER //change delay in reset sequence to fit in cover statement
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//`define COVER_DELAY 1 //fixed delay used in formal cover for reset sequence
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//`define FORMAL_COVER //skip reset sequence to fit in cover depth
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`default_nettype none
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`timescale 1ps / 1ps
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// THESE DEFINES WILL BE MODIFIED AS PARAMETERS LATER ON
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`define DDR3_1600_11_11_11 // DDR3-1600 (11-11-11) speed bin
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`define RAM_8Gb //DDR3 Capacity
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//
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// speed bin
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`define DDR3_1600_11_11_11
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//
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//DDR3 Capacity
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`define RAM_8Gb
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//`define RAM_2Gb
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//`define RAM_4Gb
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//`define RAM_8Gb
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`define x8 //DDR3 organization (DQ bus width)
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//`define x4
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//`define x16
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//NOTE IN FORMAL INDUCTION: Make formal induction finish in shorter time by lowering the delays between commands.
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//A good basis on the formal depth is the value of PRE_STALL_DELAY.
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//The value of prestall delay is the longest possible
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//clock cycles needed to finish 2 requests. Since the
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//fifo used in the formal induction has 2 locations
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//only (pertains to the request stored on the two
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// pipeline stages of bank access), we need to flush
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// those two requests on the fifo first, and the max
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// time for two request is also the value of
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// PRE_STALL_DELAY
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module ddr3_controller #(
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parameter real CONTROLLER_CLK_PERIOD = 10, //ns, period of clock input to this DDR3 controller module
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DDR3_CLK_PERIOD = 2.5, //ns, period of clock input to DDR3 RAM device
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parameter real CONTROLLER_CLK_PERIOD = 10, //ns, clock period of the controller interface
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DDR3_CLK_PERIOD = 2.5, //ns, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD)
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parameter ROW_BITS = 14, //width of row address
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COL_BITS = 10, //width of column address
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BA_BITS = 3, //width of bank address
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DQ_BITS = 8, //width of DQ
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LANES = 8, //8 lanes of DQ
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AUX_WIDTH = 16,
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WB2_ADDR_BITS = 7,
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WB2_DATA_BITS = 32,
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LANES = 8, //lanes of DQ
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AUX_WIDTH = 4, //width of aux line (must be >= 4)
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WB2_ADDR_BITS = 7, //width of 2nd wishbone address bus
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WB2_DATA_BITS = 32, //width of 2nd wishbone data bus
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/* verilator lint_off UNUSEDPARAM */
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parameter[0:0] OPT_LOWPOWER = 1, //1 = low power, 0 = low logic
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OPT_BUS_ABORT = 1, //1 = can abort bus, 0 = no abort (i_wb_cyc will be ignored, ideal for an AXI implementation which cannot abort transaction)
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/* verilator lint_on UNUSEDPARAM */
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MICRON_SIM = 0, //simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
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TEST_DATAMASK = 0, //Add test to datamask during calibration
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MICRON_SIM = 0, //enable faster simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
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TEST_DATAMASK = 0, //add test to datamask during calibration
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ODELAY_SUPPORTED = 1, //set to 1 when ODELAYE2 is supported
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parameter // The next parameters act more like a localparam (since user does not have to set this manually) but was added here to simplify port declaration
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serdes_ratio = $rtoi(CONTROLLER_CLK_PERIOD/DDR3_CLK_PERIOD),
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@ -1500,8 +1498,10 @@ module ddr3_controller #(
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pause_counter <= 0;
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lane <= 0;
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state_calibrate <= ISSUE_WRITE_1;
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write_calib_odt <= 0;
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o_phy_write_leveling_calib <= 0;
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end
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else if(instruction_address == 17) begin
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else if(instruction_address == 17) begin
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write_calib_dqs <= 1'b1;
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write_calib_odt <= 1'b1;
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delay_before_write_level_feedback <= DELAY_BEFORE_WRITE_LEVEL_FEEDBACK[$clog2(DELAY_BEFORE_WRITE_LEVEL_FEEDBACK):0];
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@ -2030,7 +2030,7 @@ ALTERNATE_WRITE_READ: if(!o_wb_stall_calib) begin
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end
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//added read pipe delay for lanes 0-to-3 (4 bits each lane the max is just 1 for each)
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end
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/*
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6: if(!wb2_we) begin
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o_wb2_data <= dqs_store[31:0]; //show last 4 sets of received 8-bit DQS during MPR (repeated 4 times, must have a value of 10'b01_01_01_01_00 somewhere)
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end
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@ -2061,7 +2061,7 @@ ALTERNATE_WRITE_READ: if(!o_wb_stall_calib) begin
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end
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14: if(!wb2_we) begin //0x30
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o_wb2_data <= wrong_data[255:224]; //lane 1
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end
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end*/
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15: if(!wb2_we) begin //0x30
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o_wb2_data <= correct_read_data; //lane 1
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end
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@ -2107,8 +2107,9 @@ ALTERNATE_WRITE_READ: if(!o_wb_stall_calib) begin
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i_phy_iserdes_data[256 +: 3], i_phy_iserdes_data[192 +: 3], i_phy_iserdes_data[128 +: 3], i_phy_iserdes_data[64 +: 3], i_phy_iserdes_data[0 +: 3]};*/
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//assign o_debug3 = {debug_trigger, i_phy_iserdes_data[192 +: 7], i_phy_iserdes_data[128 +: 8], i_phy_iserdes_data[64 +: 8], i_phy_iserdes_data[0 +: 8]};
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//assign o_debug3 = {debug_trigger, i_phy_iserdes_data[48 +: 7], i_phy_iserdes_data[32 +: 8], i_phy_iserdes_data[16 +: 8], i_phy_iserdes_data[0 +: 8]};
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assign o_debug1 = {debug_trigger,i_phy_iserdes_dqs[7:0],state_calibrate[4:0], instruction_address[4:0],reset_from_wb2,
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repeat_test, delay_before_read_data[2:0], delay_before_write_level_feedback[4:0],lane[2:0]};
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//assign o_debug1 = {debug_trigger,i_phy_iserdes_dqs[7:0],state_calibrate[4:0], instruction_address[4:0],reset_from_wb2,
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// repeat_test, delay_before_read_data[2:0], delay_before_write_level_feedback[4:0],lane[2:0]};
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assign o_debug1 = {27'd0, state_calibrate[4:0]};
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assign o_debug2 = {debug_trigger,i_phy_iserdes_data[62:32]};
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assign o_debug3 = {debug_trigger,i_phy_iserdes_data[30:0]};
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assign debug_trigger = repeat_test /*o_wb_ack_read_q[0][0]*/;
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