add wbscope
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AngeloJacobo
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57e9f1b3f9
commit
d640e52221
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////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: ddr3scope.cpp
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// {{{
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// Project: 10Gb Ethernet switch
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//
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// Purpose: This file decodes the debug bits produced by the SMI IP and
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// stored in a (compressed) WB scope. It is useful for determining
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// if the SMI IP is working, or even if/how the RPi is toggling the
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// associated SMI bits.
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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// }}}
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// Copyright (C) 2023, Gisselquist Technology, LLC
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// {{{
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// This file is part of the ETH10G project.
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//
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// The ETH10G project contains free software and gateware, licensed under the
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// Apache License, Version 2.0 (the "License"). You may not use this project,
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// or this file, except in compliance with the License. You may obtain a copy
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// of the License at
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// }}}
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// http://www.apache.org/licenses/LICENSE-2.0
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// {{{
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// Unless required by applicable law or agreed to in writing, files
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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// License for the specific language governing permissions and limitations
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// under the License.
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// }}}
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#include <stdio.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include <strings.h>
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#include <ctype.h>
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#include <string.h>
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#include <signal.h>
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#include <assert.h>
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#include "regdefs.h"
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#include "devbus.h"
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#include "scopecls.h"
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#ifndef R_DDR3SCOPE3
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int main(int argc, char **argv) {
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printf("This design was not built with a NET scope within it.\n");
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}
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#else
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#define WBSCOPE R_DDR3SCOPE3
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#define WBSCOPEDATA R_DDR3SCOPE3D
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DEVBUS *m_fpga;
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void closeup(int v) {
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m_fpga->kill();
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exit(0);
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}
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class DDR3SCOPE3 : public SCOPE {
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public:
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DDR3SCOPE3(DEVBUS *fpga, unsigned addr, bool vecread = true)
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: SCOPE(fpga, addr, true, vecread) {};
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~DDR3SCOPE3(void) {}
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virtual void decode(DEVBUS::BUSW val) const {
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int trigger;
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trigger = (val>>31)&1;
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printf("%6s", (trigger) ? "TRIGGERED at state_calibrate == MPR_READ! ":"");
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}
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virtual void define_traces(void) {
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/*
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assign o_debug3 = {debug_trigger, delay_before_write_level_feedback[4:0], odelay_data_cntvaluein[lane][4:0], odelay_dqs_cntvaluein[lane][4:0],
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state_calibrate[4:0], prev_write_level_feedback, i_phy_iserdes_data[48], i_phy_iserdes_data[40], i_phy_iserdes_data[32], i_phy_iserdes_data[24]
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, i_phy_iserdes_data[16], i_phy_iserdes_data[8], i_phy_iserdes_data[0], lane[2:0] };
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register_trace("delay_before_write_level_feedback",5,26);
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register_trace("odelay_data_cntvaluein",5,21);
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register_trace("odelay_dqs_cntvaluein",5,16);
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register_trace("state_calibrate",5,11);
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register_trace("prev_write_level_feedback",1,10);
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register_trace("i_phy_iserdes_data_lane6",1,9);
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register_trace("i_phy_iserdes_data_lane5",1,8);
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register_trace("i_phy_iserdes_data_lane4",1,7);
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register_trace("i_phy_iserdes_data_lane3",1,6);
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register_trace("i_phy_iserdes_data_lane2",1,5);
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register_trace("i_phy_iserdes_data_lane1",1,4);
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register_trace("i_phy_iserdes_data_lane0",1,3);
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register_trace("lane",3,0);
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*/
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/*
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assign o_debug3 = {debug_trigger, lane[2:0], delay_before_read_data[3:0], i_phy_iserdes_data[448 +: 3], i_phy_iserdes_data[384 +: 3], i_phy_iserdes_data[320 +: 3],
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i_phy_iserdes_data[256 +: 3], i_phy_iserdes_data[192 +: 3], i_phy_iserdes_data[128 +: 3], i_phy_iserdes_data[64 +: 3], i_phy_iserdes_data[0 +: 3]};
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register_trace("lane",3,28);
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register_trace("delay_before_read_data",4,24);
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register_trace("i_phy_iserdes_data_burst7",3,21);
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register_trace("i_phy_iserdes_data_burst6",3,18);
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register_trace("i_phy_iserdes_data_burst5",3,15);
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register_trace("i_phy_iserdes_data_burst4",3,12);
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register_trace("i_phy_iserdes_data_burst3",3,9);
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register_trace("i_phy_iserdes_data_burst2",3,6);
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register_trace("i_phy_iserdes_data_burst1",3,3);
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register_trace("i_phy_iserdes_data_burst0",3,0);
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*/
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/*
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assign o_debug3 = {debug_trigger, i_phy_iserdes_data[128 +: 7], i_phy_iserdes_data[128 +: 8], i_phy_iserdes_data[64 +: 8], i_phy_iserdes_data[0 +: 8]};
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register_trace("i_phy_iserdes_data_burst3",7,24);
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register_trace("i_phy_iserdes_data_burst2",8,16);
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register_trace("i_phy_iserdes_data_burst1",8,8);
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register_trace("i_phy_iserdes_data_burst0",8,0);
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*/
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/*
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assign o_debug3 = {debug_trigger,i_phy_iserdes_data[30:0]};
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*/
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register_trace("i_phy_iserdes_data_30_0",31,0);
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}
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};
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int main(int argc, char **argv) {
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m_fpga = connect_devbus(NULL);
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signal(SIGSTOP, closeup);
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signal(SIGHUP, closeup);
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DDR3SCOPE3 *scope = new DDR3SCOPE3(m_fpga, WBSCOPE);
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// scope->set_clkfreq_hz(ENETCLKFREQHZ);
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scope->set_clkfreq_hz(100000000);
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if (!scope->ready()) {
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printf("Scope is not yet ready:\n");
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scope->decode_control();
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} else {
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scope->print();
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scope->writevcd("ddr3scope3.vcd");
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}
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}
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#endif
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