Commit Graph

163 Commits

Author SHA1 Message Date
AngeloJacobo 4e61060927 update wcfg 2023-07-16 08:40:04 +08:00
AngeloJacobo b16c4d56cd fixed error due to missing port dm and incorrect IO type for aux 2023-07-16 08:39:24 +08:00
AngeloJacobo b80bda4a46 resolve warning from verilator linting 2023-07-16 08:38:20 +08:00
AngeloJacobo 019722bc70 resolve warnings and errors from verilator linting 2023-07-16 08:17:55 +08:00
AngeloJacobo 352205c970 test test 2023-07-13 19:26:36 +08:00
AngeloJacobo bad4ca3086 delete 2023-07-13 19:25:51 +08:00
AngeloJacobo fb7f48b3b8 add git ignore 2023-07-13 19:19:43 +08:00
AngeloJacobo b2fd0bf4fe add formal gtkw files 2023-07-13 19:18:35 +08:00
AngeloJacobo ac3af7f23f deleted 2023-07-13 19:17:25 +08:00
AngeloJacobo 17e7040626 set different FLY_BY_DELAY for each lanes 2023-07-13 19:04:43 +08:00
AngeloJacobo 4273a172f5 add wishbone 2 interface 2023-07-13 18:57:35 +08:00
AngeloJacobo 29ef663d87 set parameter FLY_BY_DELAY for each instantiated ddr3, the delay value is retrieved from 8192Mb_ddr3_parameters.vh 2023-07-13 18:55:57 +08:00
AngeloJacobo 6655959514 set different fly_by_delays for each lanes 2023-07-13 18:54:25 +08:00
AngeloJacobo ecb4cb5b2c moved FLY_BY_DELAY to this module so multiple instantiated ddr3 can have different set FLY_BY_DELAY 2023-07-13 18:52:43 +08:00
AngeloJacobo ee3d9d4be7 moved phy to TOP and controller to MAIN, removed constraints for xdc file 2023-07-13 18:50:56 +08:00
AngeloJacobo ee83028986 make stall and accessible outside, removed added assumptions with i_slave_busy 2023-07-13 18:48:34 +08:00
AngeloJacobo 2541d0afcc added wishbone 2 ports 2023-07-13 18:45:43 +08:00
AngeloJacobo 6fef8081ce delete copy 2023-07-13 18:45:00 +08:00
AngeloJacobo 89c2b8fbd7 set depth to 7 (minimum) 2023-07-13 18:43:47 +08:00
AngeloJacobo 47766cb8e8 added wishbone 2 and formally verified it 2023-07-13 18:41:25 +08:00
AngeloJacobo 5904a4910d shortened formal depth from 9 to 7 2023-07-09 09:34:03 +08:00
AngeloJacobo b03ca1864f shortened formal depth from 17 to 9 2023-07-08 10:19:58 +08:00
AngeloJacobo 25d7f3bffd update gtkw 2023-07-06 20:33:48 +08:00
AngeloJacobo a4d4e3a099 change all to non-blocking 2023-07-06 20:32:12 +08:00
AngeloJacobo b3c9bdb650 pass test for timing params with depth of 9 2023-07-06 20:29:50 +08:00
AngeloJacobo 69c34dbf8f update logs 2023-07-05 19:48:14 +08:00
AngeloJacobo 1881e059bc add summary log of regression test (not yet complete) 2023-07-05 19:47:00 +08:00
AngeloJacobo 10c290f9f8 temp newest version 2023-07-05 19:46:18 +08:00
AngeloJacobo 122e2a2d3c exported simulation scripts from Vivado 2023-07-05 16:50:40 +08:00
AngeloJacobo ec6488f68f gtkw for testing time parameters 2023-07-05 16:48:40 +08:00
AngeloJacobo ab17b8012b add average rate in report 2023-07-05 16:44:31 +08:00
AngeloJacobo 7af3358162 update vivado wcfg file 2023-07-05 16:42:48 +08:00
AngeloJacobo 3250d8d368 write dqs toggles for half slow clk cycle at the end, needed when DQ is set to be delayed (non-zero flyby delay) 2023-07-05 16:41:55 +08:00
AngeloJacobo ce3ca7e158 pre-refresh delay is now flexible and not fixed. Separated formal properties for testing time parameters 2023-07-05 16:35:57 +08:00
AngeloJacobo 217770b977 verified precharge and activate cmds, fixed bug in write_calib cmd 2023-07-02 06:38:33 +08:00
AngeloJacobo 3c32501ffd log before passing fwb_slave 2023-06-29 19:37:49 +08:00
AngeloJacobo bf7f9142b8 log after passing fwb_slave 2023-06-29 19:24:06 +08:00
AngeloJacobo d6f9614295 update gtkw 2023-06-29 13:03:08 +08:00
AngeloJacobo 3251dda112 added gtkw for cover 2023-06-29 13:00:52 +08:00
AngeloJacobo ba00cb9063 changed to non-blocking simulation 2023-06-29 12:59:57 +08:00
AngeloJacobo 188b26ee12 assume no request when slave busy (calibration or at refresh) 2023-06-29 12:58:41 +08:00
AngeloJacobo 2ca5a15c30 add cover 2023-06-29 12:56:58 +08:00
AngeloJacobo 760c75d238 passes optimized pipeline stall control and passed fwb_slave properties 2023-06-29 12:56:24 +08:00
AngeloJacobo 463707a07c sim log before passing fwb_slave 2023-06-28 21:16:56 +08:00
AngeloJacobo 2cfbba6d28 change ff to unix 2023-06-24 08:04:21 +08:00
AngeloJacobo 6f90bc165c passes all test with no violations 2023-06-24 07:59:05 +08:00
AngeloJacobo 4ecf119454 add error injections and use aux to determine ack request type 2023-06-24 07:56:05 +08:00
AngeloJacobo c9e29935a0 add more pins in gtkw 2023-06-24 07:54:17 +08:00
AngeloJacobo 310f2d5af8 update wcfg 2023-06-24 07:53:28 +08:00
AngeloJacobo a42a13ecab Merge branch 'main' of https://github.com/AngeloJacobo/DDR3_Controller into main 2023-06-24 07:52:02 +08:00