add more pins in gtkw
This commit is contained in:
AngeloJacobo
parent
310f2d5af8
commit
c9e29935a0
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@ -1,15 +1,18 @@
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[*]
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[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
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[*] Wed Jun 14 09:17:49 2023
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[*] Fri Jun 23 13:27:15 2023
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[*]
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[dumpfile] "(null)"
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[dumpfile] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/ddr3_controller/engine_0/trace_induct.vcd"
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[dumpfile_mtime] "Fri Jun 23 13:26:30 2023"
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[dumpfile_size] 318610
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[savefile] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/formal_cover_3.gtkw"
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[timestart] 206
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[timestart] 0
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[size] 1848 1126
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[pos] -1 -1
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*-4.598215 307 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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*-5.917290 156 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] ddr3_controller.
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[sst_width] 391
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[signals_width] 565
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[signals_width] 541
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[sst_expanded] 1
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[sst_vpaned_height] 743
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@420
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@ -20,9 +23,128 @@ ddr3_controller.i_rst_n
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ddr3_controller.reset_done
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@24
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ddr3_controller.state_calibrate[4:0]
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ddr3_controller.instruction_address[4:0]
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@25
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ddr3_controller.delay_counter[15:0]
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@200
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-
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@28
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ddr3_controller.wb_properties.i_wb_cyc
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@24
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ddr3_controller.wb_properties.f_nacks[3:0]
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ddr3_controller.wb_properties.f_nreqs[3:0]
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ddr3_controller.wb_properties.f_outstanding[3:0]
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ddr3_controller.f_sum_of_pending_acks[15:0]
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@28
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ddr3_controller.i_wb_stb
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ddr3_controller.o_wb_stall
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ddr3_controller.i_wb_cyc
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ddr3_controller.o_wb_ack
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@200
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-
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@22
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ddr3_controller.stage1_aux[15:0]
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ddr3_controller.stage2_aux[15:0]
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ddr3_controller.write_calib_aux[15:0]
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@28
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ddr3_controller.write_calib_stb
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ddr3_controller.write_calib_we
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@200
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-
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@28
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ddr3_controller.pipe_stall
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ddr3_controller.stage1_pending
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ddr3_controller.stage2_pending
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ddr3_controller.shift_reg_read_pipe_q<4>[16:0]
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ddr3_controller.shift_reg_read_pipe_q<3>[16:0]
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@c00028
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ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
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@28
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(0)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
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(1)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
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(2)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
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(3)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
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(4)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
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(5)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
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(6)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
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(7)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
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(8)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
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(9)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
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(10)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
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(11)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
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(12)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
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(13)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
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(14)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
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(15)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
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(16)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
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@1401200
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-group_end
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@c00028
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ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
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@28
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(0)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
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(1)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
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(2)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
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(3)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
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(4)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
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(5)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
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(6)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
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(7)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
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(8)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
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(9)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
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(10)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
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(11)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
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(12)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
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(13)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
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(14)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
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(15)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
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(16)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
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@1401200
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-group_end
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@28
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ddr3_controller.shift_reg_read_pipe_q<0>[16:0]
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ddr3_controller.o_wb_ack_read_q<1>[16:0]
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ddr3_controller.o_wb_ack_read_q<0>[16:0]
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@24
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ddr3_controller.added_read_pipe_max[3:0]
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@28
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ddr3_controller.wb_properties.i_check_assert
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@200
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-
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@28
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ddr3_controller.f_read_fifo_2
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ddr3_controller.f_write_fifo_2
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@22
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ddr3_controller.i_aux[15:0]
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ddr3_controller.o_aux[15:0]
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@200
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-
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@22
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ddr3_controller.stage1_aux[15:0]
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ddr3_controller.stage2_aux[15:0]
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ddr3_controller.write_pattern[127:0]
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ddr3_controller.read_ack_width[31:0]
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ddr3_controller.o_wb_ack_read_q<0>[16:0]
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ddr3_controller.o_wb_ack_read_q<1>[16:0]
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ddr3_controller.shift_reg_read_pipe_q<0>[16:0]
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ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
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ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
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ddr3_controller.shift_reg_read_pipe_q<3>[16:0]
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ddr3_controller.shift_reg_read_pipe_q<4>[16:0]
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ddr3_controller.shift_reg_read_pipe_d<0>[16:0]
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ddr3_controller.shift_reg_read_pipe_d<1>[16:0]
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ddr3_controller.shift_reg_read_pipe_d<2>[16:0]
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ddr3_controller.shift_reg_read_pipe_d<3>[16:0]
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@200
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-
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@28
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ddr3_controller.fifo_1.i_rst_n
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ddr3_controller.write_calib_stb
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ddr3_controller.write_calib_we
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@200
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-
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@28
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ddr3_controller.pipe_stall
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ddr3_controller.o_wb_stall
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ddr3_controller.o_wb_stall_d
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ddr3_controller.i_wb_cyc
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@ -30,11 +152,9 @@ ddr3_controller.i_wb_stb
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ddr3_controller.i_wb_we
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@24
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ddr3_controller.o_wb_ack
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@28
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ddr3_controller.o_wb_ack_read_q[15:0]
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@200
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-
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@25
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@24
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ddr3_controller.f_activate_slot[1:0]
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ddr3_controller.f_precharge_slot[1:0]
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ddr3_controller.f_read_slot[1:0]
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@ -42,20 +162,20 @@ ddr3_controller.f_write_slot[1:0]
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@28
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ddr3_controller.f_read_fifo
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ddr3_controller.f_write_fifo
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ddr3_controller.i_wb_cyc
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ddr3_controller.f_empty
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ddr3_controller.fifo_1.empty
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ddr3_controller.f_full
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ddr3_controller.f_read_pointer
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ddr3_controller.f_write_pointer
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ddr3_controller.shift_reg_read_pipe_d[4:0]
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ddr3_controller.shift_reg_read_pipe_q[4:0]
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ddr3_controller.write_calib_stb
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ddr3_controller.write_calib_we
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@200
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-
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@24
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ddr3_controller.delay_counter[15:0]
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@28
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+{ddr3_controller.[PRE] cmd_d<0>[23:0]} ddr3_controller.cmd_d<0>[23:0]
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+{ddr3_controller.[ACT] cmd_d<0>[23:0]} ddr3_controller.cmd_d<0>[23:0]
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@c00028
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+{ddr3_controller.[ACT] cmd_d<1>[23:0]} ddr3_controller.cmd_d<1>[23:0]
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+{ddr3_controller.[PRE] cmd_d<1>[23:0]} ddr3_controller.cmd_d<1>[23:0]
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@28
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(0)ddr3_controller.cmd_d<1>[23:0]
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(1)ddr3_controller.cmd_d<1>[23:0]
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@ -114,6 +234,12 @@ ddr3_controller.write_calib_we
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-group_end
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@28
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+{ddr3_controller.[WR] cmd_d<3>[23:0]} ddr3_controller.cmd_d<3>[23:0]
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@24
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ddr3_controller.stage1_bank[2:0]
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ddr3_controller.stage2_bank[2:0]
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@28
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ddr3_controller.stage1_we
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ddr3_controller.stage2_we
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ddr3_controller.issue_read_command
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ddr3_controller.issue_write_command
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@200
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@ -129,6 +255,40 @@ ddr3_controller.delay_before_write_counter_q<7>[3:0]
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ddr3_controller.delay_before_precharge_counter_q<7>[3:0]
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@200
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-
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@22
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ddr3_controller.delay_before_activate_counter_q<0>[3:0]
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ddr3_controller.delay_before_activate_counter_q<1>[3:0]
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ddr3_controller.delay_before_activate_counter_q<2>[3:0]
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ddr3_controller.delay_before_activate_counter_q<3>[3:0]
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ddr3_controller.delay_before_activate_counter_q<4>[3:0]
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ddr3_controller.delay_before_activate_counter_q<5>[3:0]
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ddr3_controller.delay_before_activate_counter_q<6>[3:0]
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ddr3_controller.delay_before_activate_counter_q<7>[3:0]
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ddr3_controller.delay_before_precharge_counter_q<0>[3:0]
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ddr3_controller.delay_before_precharge_counter_q<1>[3:0]
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ddr3_controller.delay_before_precharge_counter_q<2>[3:0]
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ddr3_controller.delay_before_precharge_counter_q<3>[3:0]
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ddr3_controller.delay_before_precharge_counter_q<4>[3:0]
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ddr3_controller.delay_before_precharge_counter_q<5>[3:0]
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ddr3_controller.delay_before_precharge_counter_q<6>[3:0]
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ddr3_controller.delay_before_precharge_counter_q<7>[3:0]
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ddr3_controller.delay_before_read_counter_q<0>[3:0]
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ddr3_controller.delay_before_read_counter_q<1>[3:0]
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ddr3_controller.delay_before_read_counter_q<2>[3:0]
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ddr3_controller.delay_before_read_counter_q<3>[3:0]
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ddr3_controller.delay_before_read_counter_q<4>[3:0]
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ddr3_controller.delay_before_read_counter_q<5>[3:0]
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ddr3_controller.delay_before_read_counter_q<6>[3:0]
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ddr3_controller.delay_before_read_counter_q<7>[3:0]
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ddr3_controller.delay_before_write_counter_q<0>[3:0]
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ddr3_controller.delay_before_write_counter_q<1>[3:0]
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ddr3_controller.delay_before_write_counter_q<2>[3:0]
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ddr3_controller.delay_before_write_counter_q<3>[3:0]
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ddr3_controller.delay_before_write_counter_q<4>[3:0]
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ddr3_controller.delay_before_write_counter_q<5>[3:0]
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ddr3_controller.delay_before_write_counter_q<6>[3:0]
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ddr3_controller.delay_before_write_counter_q<7>[3:0]
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@200
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-
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@22
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ddr3_controller.delay_before_activate_counter_q<4>[3:0]
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@ -155,8 +315,8 @@ ddr3_controller.delay_before_write_counter_q<4>[3:0]
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ddr3_controller.delay_before_read_counter_q<4>[3:0]
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@28
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ddr3_controller.o_wb_stall_d
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ddr3_controller.stage1_col[9:0]
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@24
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ddr3_controller.stage1_col[9:0]
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ddr3_controller.stage1_row[13:0]
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ddr3_controller.stage2_row[13:0]
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ddr3_controller.stage1_next_bank[2:0]
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@ -182,47 +342,18 @@ ddr3_controller.stage1_next_row[13:0]
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@200
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-
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@22
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ddr3_controller.delay_before_write_counter_q<0>[3:0]
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ddr3_controller.delay_before_activate_counter_d<7>[3:0]
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ddr3_controller.delay_before_precharge_counter_q<7>[3:0]
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ddr3_controller.delay_before_activate_counter_q<0>[3:0]
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ddr3_controller.delay_before_activate_counter_q<1>[3:0]
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@200
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-
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@22
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ddr3_controller.delay_before_precharge_counter_q<0>[3:0]
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ddr3_controller.delay_before_precharge_counter_q<1>[3:0]
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ddr3_controller.delay_before_precharge_counter_q<2>[3:0]
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ddr3_controller.delay_before_precharge_counter_q<3>[3:0]
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ddr3_controller.delay_before_precharge_counter_q<4>[3:0]
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ddr3_controller.delay_before_precharge_counter_q<5>[3:0]
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ddr3_controller.delay_before_precharge_counter_q<6>[3:0]
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ddr3_controller.delay_before_precharge_counter_q<7>[3:0]
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@200
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-
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@22
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ddr3_controller.delay_before_read_counter_q<0>[3:0]
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ddr3_controller.delay_before_read_counter_q<1>[3:0]
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ddr3_controller.delay_before_read_counter_q<2>[3:0]
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ddr3_controller.delay_before_read_counter_q<3>[3:0]
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ddr3_controller.delay_before_read_counter_q<4>[3:0]
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ddr3_controller.delay_before_read_counter_q<5>[3:0]
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@c00022
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ddr3_controller.delay_before_read_counter_q<6>[3:0]
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@28
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(0)ddr3_controller.delay_before_read_counter_q<6>[3:0]
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(1)ddr3_controller.delay_before_read_counter_q<6>[3:0]
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(2)ddr3_controller.delay_before_read_counter_q<6>[3:0]
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(3)ddr3_controller.delay_before_read_counter_q<6>[3:0]
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@1401200
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-group_end
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@c00022
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ddr3_controller.delay_before_read_counter_q<7>[3:0]
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@28
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(0)ddr3_controller.delay_before_read_counter_q<7>[3:0]
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(1)ddr3_controller.delay_before_read_counter_q<7>[3:0]
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(2)ddr3_controller.delay_before_read_counter_q<7>[3:0]
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(3)ddr3_controller.delay_before_read_counter_q<7>[3:0]
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@1401200
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-group_end
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@200
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-
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@24
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