AngeloJacobo
|
e5bd0d74c3
|
use SIM_MODEL directive to use models during vivado simulation
|
2025-05-25 09:03:16 +08:00 |
|
AngeloJacobo
|
4be9a30ff8
|
added files needed for icarus simulation (not yet working)
|
2025-05-18 15:24:10 +08:00 |
|
AngeloJacobo
|
157cca28d8
|
fixed late_dq logic
|
2025-05-12 18:27:57 +08:00 |
|
AngeloJacobo
|
90647a70e0
|
resolved (again) the verilator lint
|
2025-05-12 16:28:07 +08:00 |
|
AngeloJacobo
|
50c0a6488d
|
verilator now passing lint even with older verilator version
|
2025-05-11 20:02:13 +08:00 |
|
AngeloJacobo
|
c7ec0a54fc
|
set default BIST_MODE to 1 for shorter bring up
|
2025-04-19 13:37:58 +08:00 |
|
AngeloJacobo
|
b990372663
|
added support for DLL_OFF and Lattice ECP5 PHY
|
2025-04-19 13:24:20 +08:00 |
|
AngeloJacobo
|
b02e66b7d8
|
revert changes in shiftin and iodelay_group string name since openxc7 now works on them
|
2025-03-16 12:29:48 +08:00 |
|
AngeloJacobo
|
7f801b1f1d
|
add uart_tx to top
|
2025-03-02 19:05:30 +08:00 |
|
AngeloJacobo
|
c0bc4ca48a
|
removed extra semicolon
|
2025-03-02 18:46:07 +08:00 |
|
AngeloJacobo
|
e8444fb379
|
fix flagged errors from openxc7 (shiftin grounded, iodelay_group string)
|
2025-03-02 18:40:18 +08:00 |
|
AngeloJacobo
|
94b4e0866b
|
added UART for debugging, DQ now support 1 cycle late
|
2025-03-02 14:15:44 +08:00 |
|
AngeloJacobo
|
5c52351bce
|
uncommented default_nettype
|
2025-03-01 19:32:35 +08:00 |
|
AngeloJacobo
|
e19c6023c4
|
remove wb2 related logic when SECOND_WISHBONE == 0 to pass DDR3-1600 timing
|
2025-03-01 15:51:48 +08:00 |
|
AngeloJacobo
|
99eaa7d103
|
added IODELAY_GROUP for ODELAY,IDELAY,and IDELAYCTRL
|
2025-03-01 14:41:00 +08:00 |
|
AngeloJacobo
|
74f68760a4
|
removed mark_debug
|
2025-03-01 14:40:21 +08:00 |
|
Angelo Jacobo
|
3898b1e762
|
Merge branch 'main' into higher_speed_feature
|
2025-02-22 11:31:54 +08:00 |
|
AngeloJacobo
|
1db41ad9e1
|
add xdc for microblaze run, and minor fixes in params
|
2025-02-22 11:23:24 +08:00 |
|
AngeloJacobo
|
d6f50b3a6a
|
update UberDDR3 AXI for Vivado custom IP
|
2025-02-16 14:53:05 +08:00 |
|
AngeloJacobo
|
d4ecfee105
|
improve latency of ack after write
|
2025-02-09 16:16:42 +08:00 |
|
AngeloJacobo
|
7ada4bcbab
|
add support for BIST_MODE = 0,1,and 2 , write data is also randomized
|
2025-02-09 09:48:46 +08:00 |
|
AngeloJacobo
|
058da90bfc
|
changed SKIP_INTERNAL_TEST to BIST_MODE (0,1, or 2)
|
2025-02-09 09:45:30 +08:00 |
|
AngeloJacobo
|
c81f9044d8
|
add activate-to-activate delay, calibrate-able for both late-write-dq and early-read-dq, simulation passing for ddr3-1600!
|
2025-01-30 19:07:09 +08:00 |
|
AngeloJacobo
|
760979db27
|
hardware runs on ddr3-1333! Now working on ddr3-1600
|
2025-01-19 17:15:40 +08:00 |
|
AngeloJacobo
|
339adfe8d6
|
added simulation and project demo with XADC
|
2025-01-12 14:55:43 +08:00 |
|
AngeloJacobo
|
d8cb6d16d9
|
update copyright date
|
2025-01-02 13:18:42 +08:00 |
|
AngeloJacobo
|
c11d90440e
|
fixed mtb computation
|
2024-12-29 22:11:26 +08:00 |
|
AngeloJacobo
|
1afd06542f
|
make mtb mcp to meet timing
|
2024-12-29 21:58:26 +08:00 |
|
AngeloJacobo
|
ab1a5b9f81
|
make spd read display better
|
2024-12-29 21:40:53 +08:00 |
|
AngeloJacobo
|
6ead81ba48
|
fixed stuck on addr 21, and fixed dual rank
|
2024-12-29 21:33:58 +08:00 |
|
AngeloJacobo
|
f636dcbd2e
|
bring all timing parameters to top
|
2024-12-29 21:22:52 +08:00 |
|
AngeloJacobo
|
d424bcdf4e
|
add option to debug all registers in ILA
|
2024-12-29 20:59:57 +08:00 |
|
AngeloJacobo
|
7acaf34b44
|
added uart to display spd report
|
2024-12-29 20:41:17 +08:00 |
|
AngeloJacobo
|
75857a0af0
|
read bytes 0 to 63 of spd then store (sim passing)
|
2024-12-29 14:47:57 +08:00 |
|
AngeloJacobo
|
fbc4b5ff9a
|
added initial files for spd
|
2024-12-29 12:18:37 +08:00 |
|
AngeloJacobo
|
3b2ef2afa8
|
odt[1] generated by separate oserdes to make it routable
|
2024-12-21 18:24:12 +08:00 |
|
AngeloJacobo
|
7367182640
|
dual rank enabled is now passing formal and simulation!
|
2024-12-20 18:56:21 +08:00 |
|
AngeloJacobo
|
4fdaace899
|
add dual-rank feature (PHY ongoing changes)
|
2024-12-02 11:28:21 +08:00 |
|
AngeloJacobo
|
05589c3f83
|
added self-refresh to vivado IP GUI, tested self-refresh on hardware with microblaze
|
2024-11-24 17:40:21 +08:00 |
|
AngeloJacobo
|
e08612658b
|
self-refresh feature done, passing simulation and formal
|
2024-11-24 14:31:20 +08:00 |
|
AngeloJacobo
|
1078e2ffe0
|
Revert "add self-refresh option, passing Simulation, ongoing formal"
This reverts commit a5e2adf4a4.
|
2024-11-23 11:43:05 +08:00 |
|
AngeloJacobo
|
a5e2adf4a4
|
add self-refresh option, passing Simulation, ongoing formal
|
2024-11-17 20:47:14 +08:00 |
|
AngeloJacobo
|
c58a9d70e6
|
add self-refresh feature (untested)
|
2024-11-03 14:52:32 +08:00 |
|
AngeloJacobo
|
65bcf2f621
|
add option to skip internal test for Microblaze use
|
2024-10-26 09:07:24 +08:00 |
|
AngeloJacobo
|
e89b06defd
|
paremeterized IOSERDES loopback option
|
2024-10-13 16:42:31 +08:00 |
|
Angelo Jacobo
|
95820556c2
|
replace ioserdes loopback with logic
|
2024-10-12 09:43:27 +08:00 |
|
Angelo Jacobo
|
aa68c22169
|
turn off ECC test by default
|
2024-09-01 09:04:45 +08:00 |
|
AngeloJacobo
|
fc963c3c23
|
simulation and formal are now passing for all ECC types
|
2024-07-28 17:36:37 +08:00 |
|
AngeloJacobo
|
f80d4ac21b
|
simulation passing for ECC_ENABLE = 3
|
2024-07-15 18:31:49 +08:00 |
|
AngeloJacobo
|
de85925681
|
add support for ECC_ENABLE = 3
|
2024-07-06 21:24:01 +08:00 |