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add option to skip internal test for Microblaze use

This commit is contained in:
AngeloJacobo 2024-10-26 09:07:24 +08:00
parent 0c41a271d9
commit 65bcf2f621
3 changed files with 56 additions and 34 deletions
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40
rtl/axi/ddr3_top_axi.v
View File

@ -44,6 +44,11 @@ module ddr3_top_axi #(
parameter[0:0] MICRON_SIM = 0, //enable faster simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
ODELAY_SUPPORTED = 0, //set to 1 when ODELAYE2 is supported
SECOND_WISHBONE = 0, //set to 1 if 2nd wishbone for debugging is needed
WB_ERROR = 0, // set to 1 to support Wishbone error (asserts at ECC double bit error)
SKIP_INTERNAL_TEST = 0, // skip built-in self test (would require >2 seconds of internal test right after calibration)
parameter[1:0] ECC_ENABLE = 0, // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC )
parameter[1:0] DIC = 2'b00, //Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms) (only change when you know what you are doing)
parameter[2:0] RTT_NOM = 3'b011, //RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms) (only change when you know what you are doing)
parameter // The next parameters act more like a localparam (since user does not have to set this manually) but was added here to simplify port declaration
DQ_BITS = 8, //device width (fixed to 8, if DDR3 is x16 then BYTE_LANES will be 2 while )
serdes_ratio = 4, // this controller is fixed as a 4:1 memory controller (CONTROLLER_CLK_PERIOD/DDR3_CLK_PERIOD = 4)
@ -121,12 +126,15 @@ module ddr3_top_axi #(
output wire[BYTE_LANES-1:0] o_ddr3_dm,
output wire o_ddr3_odt,
//
// Done Calibration pin
output wire o_calib_complete,
//
// Debug outputs
output wire[31:0] o_debug1,
output wire[31:0] o_debug2,
output wire[31:0] o_debug3,
output wire[(DQ_BITS*BYTE_LANES)/8-1:0] o_ddr3_debug_read_dqs_p,
output wire[(DQ_BITS*BYTE_LANES)/8-1:0] o_ddr3_debug_read_dqs_n
output wire[31:0] o_debug1
// output wire[31:0] o_debug2,
// output wire[31:0] o_debug3,
// output wire[(DQ_BITS*BYTE_LANES)/8-1:0] o_ddr3_debug_read_dqs_p,
// output wire[(DQ_BITS*BYTE_LANES)/8-1:0] o_ddr3_debug_read_dqs_n
);
wire wb_cyc;
@ -152,7 +160,12 @@ ddr3_top #(
.ODELAY_SUPPORTED(ODELAY_SUPPORTED), //set to 1 if ODELAYE2 is supported
.SECOND_WISHBONE(SECOND_WISHBONE), //set to 1 if 2nd wishbone for debugging is needed
.WB2_ADDR_BITS(WB2_ADDR_BITS), //width of 2nd wishbone address bus
.WB2_DATA_BITS(WB2_DATA_BITS) //width of 2nd wishbone data bus
.WB2_DATA_BITS(WB2_DATA_BITS), //width of 2nd wishbone data bus
.WB_ERROR(WB_ERROR), // set to 1 to support Wishbone error (asserts at ECC double bit error)
.SKIP_INTERNAL_TEST(SKIP_INTERNAL_TEST), // skip built-in self test (would require >2 seconds of internal test right after calibration)
.ECC_ENABLE(ECC_ENABLE), // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC )
.DIC(DIC), // Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms) (only change when you know what you are doing)
.RTT_NOM(RTT_NOM) //RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms) (only change when you know what you are doing)
) ddr3_top_inst
(
//clock and reset
@ -205,12 +218,15 @@ ddr3_top #(
.o_ddr3_dm(o_ddr3_dm), // width = BYTE_LANES
.o_ddr3_odt(o_ddr3_odt),
//
// Done Calibration pin
.o_calib_complete(o_calib_complete),
//
// Debug outputs
.o_debug1(o_debug1),
.o_debug2(o_debug2),
.o_debug3(o_debug3),
.o_ddr3_debug_read_dqs_p(o_ddr3_debug_read_dqs_p),
.o_ddr3_debug_read_dqs_n(o_ddr3_debug_read_dqs_n)
.o_debug1(o_debug1)
// .o_debug2(o_debug2),
// .o_debug3(o_debug3),
// .o_ddr3_debug_read_dqs_p(o_ddr3_debug_read_dqs_p),
// .o_ddr3_debug_read_dqs_n(o_ddr3_debug_read_dqs_n)
////////////////////////////////////
);
@ -284,4 +300,4 @@ axim2wbsp #(
endmodule

20
rtl/ddr3_controller.v
View File

@ -67,6 +67,7 @@ module ddr3_controller #(
ODELAY_SUPPORTED = 1, //set to 1 when ODELAYE2 is supported
SECOND_WISHBONE = 0, //set to 1 if 2nd wishbone is needed
WB_ERROR = 0, // set to 1 to support Wishbone error (asserts at ECC double bit error)
SKIP_INTERNAL_TEST = 1, // skip built-in self test (would require >2 seconds of internal test right after calibration)
parameter[1:0] ECC_ENABLE = 0, // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC ) (only change when you know what you are doing)
parameter[1:0] DIC = 2'b00, //Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms) (only change when you know what you are doing)
parameter[2:0] RTT_NOM = 3'b011, //RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms)
@ -131,10 +132,12 @@ module ddr3_controller #(
output reg[LANES-1:0] o_phy_bitslip,
output reg o_phy_write_leveling_calib,
output wire o_phy_reset,
// Done Calibration pin
output wire o_calib_complete,
// Debug port
output wire [31:0] o_debug1,
output wire [31:0] o_debug2,
output wire [31:0] o_debug3
output wire [31:0] o_debug1
// output wire [31:0] o_debug2,
// output wire [31:0] o_debug3
);
@ -554,6 +557,7 @@ module ddr3_controller #(
(* mark_debug = "true" *) reg odelay_cntvalue_halfway = 0;
reg initial_calibration_done = 0;
reg final_calibration_done = 0;
assign o_calib_complete = final_calibration_done;
// Wishbone 2
reg wb2_stb = 0;
reg wb2_update = 0;
@ -2325,7 +2329,7 @@ module ddr3_controller #(
/* verilator lint_off WIDTH */
if(lane == LANES - 1) begin
/* verilator lint_on WIDTH */
state_calibrate <= BURST_WRITE;
state_calibrate <= SKIP_INTERNAL_TEST? FINISH_READ : BURST_WRITE; // go straight to FINISH_READ if SKIP_INTERNAL_TEST high
initial_calibration_done <= 1'b1;
end
else begin
@ -2827,11 +2831,11 @@ ALTERNATE_WRITE_READ: if(!o_wb_stall_calib) begin
end//end of always
// Logic connected to debug port
// Logic connected to debug port
wire debug_trigger;
// wire debug_trigger;
assign o_debug1 = {27'd0, state_calibrate[4:0]};
assign o_debug2 = {debug_trigger,i_phy_iserdes_data[62:32]};
assign o_debug3 = {debug_trigger,i_phy_iserdes_data[30:0]};
assign debug_trigger = repeat_test /*o_wb_ack_read_q[0][0]*/;
// assign o_debug2 = {debug_trigger,i_phy_iserdes_data[62:32]};
// assign o_debug3 = {debug_trigger,i_phy_iserdes_data[30:0]};
// assign debug_trigger = repeat_test /*o_wb_ack_read_q[0][0]*/;
/*********************************************************************************************************************************************/

30
rtl/ddr3_top.v
View File

@ -44,6 +44,7 @@ module ddr3_top #(
ODELAY_SUPPORTED = 0, //set to 1 when ODELAYE2 is supported
SECOND_WISHBONE = 0, //set to 1 if 2nd wishbone for debugging is needed
WB_ERROR = 0, // set to 1 to support Wishbone error (asserts at ECC double bit error)
SKIP_INTERNAL_TEST = 0, // skip built-in self test (would require >2 seconds of internal test right after calibration)
parameter[1:0] ECC_ENABLE = 0, // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC )
parameter[1:0] DIC = 2'b00, //Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms) (only change when you know what you are doing)
parameter[2:0] RTT_NOM = 3'b011, //RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms) (only change when you know what you are doing)
@ -104,12 +105,14 @@ module ddr3_top #(
output wire[BYTE_LANES-1:0] o_ddr3_dm,
output wire o_ddr3_odt, // on-die termination
//
// Done Calibration pin
output wire o_calib_complete,
// Debug outputs
output wire[31:0] o_debug1,
output wire[31:0] o_debug2,
output wire[31:0] o_debug3,
output wire[(DQ_BITS*BYTE_LANES)/8-1:0] o_ddr3_debug_read_dqs_p,
output wire[(DQ_BITS*BYTE_LANES)/8-1:0] o_ddr3_debug_read_dqs_n
output wire[31:0] o_debug1
// output wire[31:0] o_debug2,
// output wire[31:0] o_debug3,
// output wire[(DQ_BITS*BYTE_LANES)/8-1:0] o_ddr3_debug_read_dqs_p,
// output wire[(DQ_BITS*BYTE_LANES)/8-1:0] o_ddr3_debug_read_dqs_n
);
// Instantiation Template (DEFAULT VALUE IS FOR ARTY S7)
@ -182,10 +185,6 @@ ddr3_top #(
.o_ddr3_odt(ddr3_odt),
// Debug outputs
.o_debug1(),
.o_debug2(),
.o_debug3(),
.o_ddr3_debug_read_dqs_p(),
.o_ddr3_debug_read_dqs_n()
////////////////////////////////////
);
*/
@ -225,6 +224,7 @@ ddr3_top #(
.SECOND_WISHBONE(SECOND_WISHBONE), //set to 1 if 2nd wishbone is needed
.ECC_ENABLE(ECC_ENABLE), // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC )
.WB_ERROR(WB_ERROR), // set to 1 to support Wishbone error (asserts at ECC double bit error)
.SKIP_INTERNAL_TEST(SKIP_INTERNAL_TEST), // skip built-in self test (would require >2 seconds of internal test right after calibration)
.DIC(DIC), //Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms)
.RTT_NOM(RTT_NOM) //RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms)
) ddr3_controller_inst (
@ -278,10 +278,12 @@ ddr3_top #(
.o_phy_bitslip(bitslip),
.o_phy_write_leveling_calib(write_leveling_calib),
.o_phy_reset(reset),
// Done Calibration pin
.o_calib_complete(o_calib_complete),
// Debug outputs
.o_debug1(o_debug1),
.o_debug2(o_debug2),
.o_debug3(o_debug3)
.o_debug1(o_debug1)
// .o_debug2(o_debug2),
// .o_debug3(o_debug3)
);
ddr3_phy #(
@ -336,8 +338,8 @@ ddr3_top #(
.io_ddr3_dqs_n(io_ddr3_dqs_n),
.o_ddr3_dm(o_ddr3_dm),
.o_ddr3_odt(o_ddr3_odt), // on-die termination
.o_ddr3_debug_read_dqs_p(o_ddr3_debug_read_dqs_p),
.o_ddr3_debug_read_dqs_n(o_ddr3_debug_read_dqs_n)
.o_ddr3_debug_read_dqs_p(/*o_ddr3_debug_read_dqs_p*/),
.o_ddr3_debug_read_dqs_n(/*o_ddr3_debug_read_dqs_n*/)
);
endmodule