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UberDDR3
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odt[1] generated by separate oserdes to make it routable

This commit is contained in:
AngeloJacobo 2024-12-21 18:24:12 +08:00
parent 7367182640
commit 3b2ef2afa8
2 changed files with 53 additions and 3 deletions
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4
rtl/ddr3_controller.v
View File

@ -406,7 +406,7 @@ module ddr3_controller #(
/************************************************************* Registers and Wires *************************************************************/
integer index;
reg[4:0] instruction_address = 0; //address for accessing rom instruction
(* mark_debug ="true" *) reg[4:0] instruction_address = 0; //address for accessing rom instruction
reg[27:0] instruction = INITIAL_RESET_INSTRUCTION; //instruction retrieved from reset instruction rom
reg[ DELAY_COUNTER_WIDTH - 1:0] delay_counter = INITIAL_RESET_INSTRUCTION[DELAY_COUNTER_WIDTH - 1:0]; //counter used for delays
reg delay_counter_is_zero = (INITIAL_RESET_INSTRUCTION[DELAY_COUNTER_WIDTH - 1:0] == 0); //counter is now zero so retrieve next delay
@ -601,7 +601,7 @@ module ddr3_controller #(
wire db_err_o;
wire[wb_data_bits - 1:0] o_wb_data_q_decoded;
/* verilator lint_on UNDRIVEN */
reg user_self_refresh_q; // registered i_user_self_refresh
(* mark_debug ="true" *) reg user_self_refresh_q; // registered i_user_self_refresh
// initial block for all regs
initial begin

52
rtl/ddr3_phy.v
View File

@ -226,6 +226,55 @@ module ddr3_phy #(
// End of OSERDESE2_inst instantiation
end
if(DUAL_RANK_DIMM) begin // if dual rank enabled, odt_2 and odt_1 will be generated separately
// OSERDESE2: Output SERial/DESerializer with bitslip
//7 Series
// Xilinx HDL Libraries Guide, version 13.4
OSERDESE2 #(
.DATA_RATE_OQ("SDR"), // DDR, SDR
.DATA_RATE_TQ("SDR"), // DDR, SDR
.DATA_WIDTH(4), // Parallel data width (2-8,10,14)
.INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
.TRISTATE_WIDTH(1)
)
OSERDESE2_cmd(
.OFB(), // 1-bit output: Feedback path for data
.OQ(o_ddr3_odt[1]), // 1-bit output: Data path output
.CLK(i_ddr3_clk), // 1-bit input: High speed clock
.CLKDIV(i_controller_clk), // 1-bit input: Divided clock
// D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
.D1(i_controller_cmd[cmd_len*0 + CMD_ODT]),
.D2(i_controller_cmd[cmd_len*1 + CMD_ODT]),
.D3(i_controller_cmd[cmd_len*2 + CMD_ODT]),
.D4(i_controller_cmd[cmd_len*3 + CMD_ODT]),
.OCE(1'b1), // 1-bit input: Output data clock enable
.RST(sync_rst), // 1-bit input: Reset
// unused signals but were added here to make vivado happy
.SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
.SHIFTOUT2(),
.TBYTEOUT(), // 1-bit output: Byte group tristate
.TFB(), // 1-bit output: 3-state control
.TQ(), // 1-bit output: 3-state control
.D5(),
.D6(),
.D7(),
.D8(),
// SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
.SHIFTIN1(0),
.SHIFTIN2(0),
// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
.T1(0),
.T2(0),
.T3(0),
.T4(0),
.TBYTEIN(0),
// 1-bit input: Byte group tristate
.TCE(0)
// 1-bit input: 3-state clock enable
);
// End of OSERDESE2_inst instantiation
end
endgenerate
// cs[1] when DUAL_RANK_DIMM enabled
@ -235,8 +284,9 @@ module ddr3_phy #(
assign o_ddr3_cs_n[0] = oserdes_cmd[CMD_CS_N];
assign o_ddr3_cke[1] = oserdes_cmd[CMD_CKE_2];
assign o_ddr3_cke[0] = oserdes_cmd[CMD_CKE];
assign o_ddr3_odt[1] = oserdes_cmd[CMD_ODT];
assign o_ddr3_odt[0] = oserdes_cmd[CMD_ODT];
// o_ddr3_odt[1] will be generated directly by a separate OSERDES
// if odt[1] and odt[0] uses same output from oserdes, one of them will be unroutable
end
else begin
assign o_ddr3_cs_n = oserdes_cmd[CMD_CS_N];