Angelo Jacobo
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be6b2a3b8d
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Merge pull request #37 from AngeloJacobo/dev_max_freq
Show every modifications done per optimization step
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2026-01-18 12:25:34 +08:00 |
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AngeloJacobo
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e22c2b1c53
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fix whitespaces
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2026-01-18 12:17:36 +08:00 |
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AngeloJacobo
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2226aa4461
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Step 7: Resize registers
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2026-01-18 12:01:58 +08:00 |
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AngeloJacobo
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859963ad20
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Step 6: Optimize wb_stall logic
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2026-01-18 11:55:31 +08:00 |
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AngeloJacobo
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5066c3d280
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Step 5: Optimize stage-1 stall and stage-2 stall logic
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2026-01-18 11:40:26 +08:00 |
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AngeloJacobo
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f724ec0d43
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Step 4: Arrange logic (stage-2 pre/act/wr-rd logic)
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2026-01-18 11:25:47 +08:00 |
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AngeloJacobo
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fad0a7b19a
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Step 3: Register conditions in advance (calibration fsm)
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2026-01-18 11:19:04 +08:00 |
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AngeloJacobo
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282d9596ca
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Step 2: Register conditions in advance (2-stage pipeline)
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2026-01-18 11:06:49 +08:00 |
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AngeloJacobo
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98fe547262
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Step 1: Separate _q (sequential) from _d (combinational) logic
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2026-01-18 10:52:57 +08:00 |
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AngeloJacobo
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a653bbeb35
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revert ddr3_controller to commit a1258e2 (before optimizing)
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2026-01-18 10:19:05 +08:00 |
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Angelo Jacobo
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b46b2ca06d
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Merge pull request #36 from AngeloJacobo/dev_max_freq
Increase max frequency of controller and add CaaS flow
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2026-01-11 13:34:08 +08:00 |
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AngeloJacobo
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30731d1b4c
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add files for caas and linked uberddr3 files
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2026-01-11 13:30:06 +08:00 |
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AngeloJacobo
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df67fc038b
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add files for caas and linked uberddr3 files
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2026-01-11 12:03:03 +08:00 |
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AngeloJacobo
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31b3642fbe
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run @ 133MHz with yosys
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2025-12-31 14:40:04 +08:00 |
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AngeloJacobo
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ad50f79695
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run @ 100MHz with yosys
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2025-12-31 14:39:16 +08:00 |
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AngeloJacobo
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407c1a8115
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update dfu file
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2025-12-31 14:38:32 +08:00 |
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AngeloJacobo
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383e53d647
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run @ 125MHz with yosys
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2025-12-31 14:38:13 +08:00 |
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AngeloJacobo
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b38d9801ba
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run @ 100MHz with yosys
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2025-12-31 14:37:32 +08:00 |
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AngeloJacobo
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3c4c4b9f83
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optimize stage1/2 stall logic, optimize size of registers (delay_before_*, added_read_pipe*, delay_read_pipe), register huge conditions, explicit removal of unused states)
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2025-12-31 14:35:04 +08:00 |
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AngeloJacobo
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3d94fae1e6
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separated sequential from combinational logic for pipeline stage logic
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2025-12-29 14:36:25 +08:00 |
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AngeloJacobo
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a3ffeb670f
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register conditions for anticipate logic; change logic order for stage 2 from r/w-act-pre to pre-act-r/w
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2025-12-29 10:26:32 +08:00 |
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AngeloJacobo
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0b3bb30fae
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added define for UART-debugging of BIST exclusively
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2025-12-27 13:01:19 +08:00 |
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AngeloJacobo
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356c6cc1a2
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run at DDR3-1000 (125MHz controller clock)
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2025-12-26 10:02:16 +08:00 |
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AngeloJacobo
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80da754a64
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achieve >40% increase in max frequency
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2025-12-26 09:50:12 +08:00 |
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AngeloJacobo
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864b8069c3
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fix read_data_store_lane logic
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2025-12-23 10:01:57 +08:00 |
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AngeloJacobo
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a3edea5e00
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add prep state for ANALYZE_DATA to cut timing path due to indexing with lane
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2025-12-22 13:11:20 +08:00 |
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AngeloJacobo
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c605135dd9
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make o_wb_stall/o_wb_stall_calib combinational logic
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2025-12-22 08:50:40 +08:00 |
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AngeloJacobo
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fdf1becc03
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register stage2 if-else conditions (2.4% increase in max freq)
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2025-12-19 17:39:03 +08:00 |
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AngeloJacobo
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ba640ca59c
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optimize wb_stall/wb_stall_calib logic (3.7% increase in max freq)
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2025-12-14 11:53:04 +08:00 |
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AngeloJacobo
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a1258e2eed
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added back main wcfg file
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2025-06-14 11:52:13 +08:00 |
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AngeloJacobo
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a3efc861da
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update bistream files from latest CI run
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2025-06-05 18:55:44 +08:00 |
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AngeloJacobo
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9c3249b8dd
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log files are renamed with PASS_ for easier checking
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2025-06-03 19:26:05 +08:00 |
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Angelo Jacobo
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4d60a19154
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Merge pull request #32 from AngeloJacobo/run_iverilog_sim
Run simulation with Icarus Verilog
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2025-05-25 09:12:59 +08:00 |
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AngeloJacobo
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da4ffebe9b
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update vivado sim log files
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2025-05-25 09:03:28 +08:00 |
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AngeloJacobo
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e5bd0d74c3
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use SIM_MODEL directive to use models during vivado simulation
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2025-05-25 09:03:16 +08:00 |
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AngeloJacobo
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a33560122c
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added icarus simulation scripts (PASSING!)
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2025-05-24 17:35:39 +08:00 |
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AngeloJacobo
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cb5f78b057
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modified vivado simulation files
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2025-05-24 17:33:49 +08:00 |
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AngeloJacobo
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972506bb4b
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moved verilog models to model/
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2025-05-24 17:31:55 +08:00 |
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AngeloJacobo
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8fbb6387ab
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removed UART in example demo for arty s7 to pass openxc7 timing
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2025-05-24 17:31:13 +08:00 |
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AngeloJacobo
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f0b4a15b7c
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icarus verilog simulation now working!
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2025-05-18 17:08:38 +08:00 |
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AngeloJacobo
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4be9a30ff8
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added files needed for icarus simulation (not yet working)
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2025-05-18 15:24:10 +08:00 |
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Angelo Jacobo
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4b159fa03a
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Merge pull request #31 from AngeloJacobo/pass_verilator_lint
Pass verilator lint
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2025-05-12 18:35:28 +08:00 |
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AngeloJacobo
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157cca28d8
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fixed late_dq logic
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2025-05-12 18:27:57 +08:00 |
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AngeloJacobo
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90647a70e0
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resolved (again) the verilator lint
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2025-05-12 16:28:07 +08:00 |
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AngeloJacobo
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5f8f5974b4
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added vivado on makefile (make vivado)
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2025-05-12 16:02:38 +08:00 |
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AngeloJacobo
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fe8563ed65
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update all simulation log files
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2025-05-12 11:05:36 +08:00 |
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AngeloJacobo
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9fd104b566
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updated example demo bitstream files
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2025-05-11 20:11:05 +08:00 |
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AngeloJacobo
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50c0a6488d
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verilator now passing lint even with older verilator version
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2025-05-11 20:02:13 +08:00 |
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Angelo Jacobo
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264801fc99
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Merge pull request #30 from AngeloJacobo/ecp5_phy
added support for lattice ecp5 PHY, now working on orangecrab ECP5
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2025-04-19 14:57:57 +08:00 |
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AngeloJacobo
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5b0c48ca0a
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fixed bug on vivado IP (convert string to long for SELF_REFRESH)
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2025-04-19 13:59:30 +08:00 |