After merging upstream changes, fix all build errors in C++ test files
and regolden Tcl test golden files to match updated code output.
Build fixes:
- dcalc/test/cpp/TestDcalc.cc: Fix const char* loop iterations, use
EXPECT_NEAR for uninitialized subnormal float comparison
- liberty/test/cpp/TestLibertyStaBasicsB.cc: Wrap tests using removed
LibertyBuilder() default constructor in #if 0
- liberty/test/cpp/TestLibertyStaCallbacks.cc: Fix LibertyBuilder()
call to use sta_->debug()/report(); wrap old visitor tests in #if 0
- search/test/cpp/TestSearchStaDesignB.cc: Fix pg->name() nullptr
comparison (now returns std::string&)
- search/test/cpp/TestSearchStaInit.cc: Fix 5 clkPinsInvalid/isIdealClock
tests to expect throw (API now requires linked network)
Tcl test fixes:
- Remove calls to removed APIs: report_path_end_header/footer, report_path_end2
from 6 search test scripts; regolden their .ok files
- Regolden .ok files for liberty (15), graph (1), network (8),
parasitics (3), sdc (3), util (2), verilog (8) modules to reflect
upstream format changes (timing arcs output, pin ordering, spacing)
All 6103 tests now pass.
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Update test code to match API changes from upstream master:
- TestGraph.cc: Fix makeScenes() call to pass reference instead of pointer
- TestLibertyClasses.cc: Fix ScaleFactorType wire_res/wire_cap name mapping;
fix TablePtr usage by calling .get() where const TableModel* is expected
- TestLibertyClasses.cc: Update liberty_read_nangate.ok for new timing arc output
- TestPower.cc: Replace PwrActivityOrigin::defaulted with ::unknown;
fix isSet() expectations (unknown origin returns false)
- TestSdcClasses.cc, TestSdf.cc, TestUtil.cc, TestSpice.cc:
Fix RiseFall::to_string() expected values from short form ("^"/"v")
to long form ("rise"/"fall")
- TestUtil.cc: Remove tests for deleted StringVector/split/TokenParser
and StringSet::deleteContents (removed from master)
- TestSpice.cc: Replace StdStringSeq with StringSeq
- helpers.tcl: Use pwd-based result_dir so module tests write results
to their own test/results/ directory
- verilog_bus.ok: Update golden file for new port ordering from master
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Major upstream refactoring: Corner→Scene, Mode architecture, warning
format change (Warning ID:), command renames, and many API signature
changes. Adapted all C++ test files and TCL test scripts/expected
output files to pass with the new API. 6159/6159 tests pass.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
- Split oversized test files to stay under 5,000 lines per file:
TestSdc.cc → TestSdcClasses.cc, TestSdcStaInit.cc, TestSdcStaDesign.cc
TestSearchStaDesign.cc → TestSearchStaDesign.cc, TestSearchStaDesignB.cc
TestLibertyStaBasics.cc → TestLibertyStaBasics.cc, TestLibertyStaBasicsB.cc
TestNetwork.cc → TestNetwork.cc, TestNetworkB.cc
- Replace ~200+ (void) casts with proper EXPECT_* assertions across all
C++ test files (dcalc, liberty, network, sdc, search, power, spice, util)
- Remove ~55 SUCCEED() and EXPECT_TRUE(true) no-op assertions
- Fix 6 load-only Tcl tests by adding diff_files verification with
22 new .sdcok golden reference files
- Delete 7 orphan .ok files with no matching .tcl tests
- Add how_to_write_good_tests.md and TODO6.md documenting test quality rules
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
- Add diff_files_sorted to test/helpers.tcl for hash-order-independent
SDC comparison (fixes non-deterministic write_sdc output ordering)
- Use diff_files_sorted in sdc_derate_disable_deep and
sdc_port_delay_advanced tests
- Remove stale coverage percentages from test comments (Comment 1)
- Remove unnecessary catch blocks in search property tests (Comment 3)
- Strengthen load-only tests with actual data verification (Comment 8)
- Remove orphan .ok files for deleted monolithic tests (Comment 9)
- Add golden .sdcok/.libok/.vok/.sdfok files for SDC/liberty/verilog
write-and-diff tests
- Add -B (clean rebuild) option to make_coverage_report.sh
- Replace (void) casts and EXPECT_TRUE(true) with real assertions in
TestSdc.cc and TestVerilog.cc
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Add meaningful verification to liberty ECSM, sky130 corners, writer,
and roundtrip tests. Expand verilog specify, escaped-write, remove-cells,
write, and writer tests with content checks, roundtrip validation, and
error guards. Update corresponding .ok golden files.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Strengthen C++ test assertions in TestSdc and TestSearch with actual
value checks. Stabilize verilog_multimodule_write by using clear_sta
for isolated roundtrips. Add report_checks to wireload model tests.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Remove useless empty-body if-blocks that check file size/existence without
doing anything, replacing them with meaningful puts output where appropriate.
Split monolithic verilog test files into individual per-test files with
their own .ok golden files. Update .ok files to match actual output.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Document why each catch block is needed across 48 test files,
covering liberty, search, sdc, spice, network, parasitics, util,
and verilog modules.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Remove unnecessary catch blocks from Tcl test files across all modules,
add report_checks after each set_wire_load_model in liberty_wireload,
rewrite liberty_sky130_corners for actual multi-corner timing analysis
with define_corners, and expand C++ tests (TestSearchIncremental 8→36,
TestPower 71→96, TestSpice 98→126 tests).
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
- Remove stale line-number coverage comments (# Targets: line NNN, hit=0)
- Remove useless file-existence checks from verilog/sdf tests
- Delete 21 orphaned dcalc Tcl tests (C++ tests already cover them)
- Rename liberty_ccsn_ecsm -> liberty_ccsn (no ECSM libs available)
- Fix liberty_sky130_corners to use define_corners/-corner for real multi-corner testing
- Add report_checks per wireload model in liberty_wireload
- Fix test/regression to work from test/ directory (label mismatch)
- Refactor all module CMakeLists.txt with sta_module_tests() macro
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
The Cell may come from LEF which doesn't have internal pins that
Liberty does. This used to work by dumb luck where the extra two
power pins in LEF happened to align to the extra two internal pins
from Liberty. With the change to pg_pins this no longer works.
Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
* Add parser support for specify blocks and specparam
Treated like regular parameters, and so ignored
* Add regression test
* Apply PR feedback
* missed the verilog_lang
* msg: Turn warnings into errors with more explicit meaning and make script returns an error code.
Signed-off-by: Christian Costa <titan.costa@gmail.com>
* msg: Generate messages.txt during build and stop in case of duplicated message ids.
Signed-off-by: Christian Costa <titan.costa@gmail.com>
* msg: Fix duplicate messages ids.
Signed-off-by: Christian Costa <titan.costa@gmail.com>
* msg: Do not fail build on duplicated ids and turn errors into warnings.
Signed-off-by: Christian Costa <titan.costa@gmail.com>
* msg: Remove messages.txt and use full path to it in gitignore.
Signed-off-by: Christian Costa <titan.costa@gmail.com>
---------
Signed-off-by: Christian Costa <titan.costa@gmail.com>
* made module deletion optional in linkNetwork
Signed-off-by: Cho Moon <cmoon@precisioninno.com>
* merged with master
Signed-off-by: Cho Moon <cmoon@precisioninno.com>
---------
Signed-off-by: Cho Moon <cmoon@precisioninno.com>
Jaehyun Kim
Vitor Bandeira
James Cherry
Deepashree Sengupta
Deepashree Sengupta
Matt Liberty
ambd161
Christian Costa
Cho Moon