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test: strengthen assertions, add sorted SDC diff, and clean up tests 

- Add diff_files_sorted to test/helpers.tcl for hash-order-independent
  SDC comparison (fixes non-deterministic write_sdc output ordering)
- Use diff_files_sorted in sdc_derate_disable_deep and
  sdc_port_delay_advanced tests
- Remove stale coverage percentages from test comments (Comment 1)
- Remove unnecessary catch blocks in search property tests (Comment 3)
- Strengthen load-only tests with actual data verification (Comment 8)
- Remove orphan .ok files for deleted monolithic tests (Comment 9)
- Add golden .sdcok/.libok/.vok/.sdfok files for SDC/liberty/verilog
  write-and-diff tests
- Add -B (clean rebuild) option to make_coverage_report.sh
- Replace (void) casts and EXPECT_TRUE(true) with real assertions in
  TestSdc.cc and TestVerilog.cc

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
This commit is contained in:
Jaehyun Kim 2026-02-23 11:50:23 +09:00
parent c72a42e827
commit b6d598a119
226 changed files with 435195 additions and 783 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
graph/test/graph_delay_corners.tcl
View File

@ -1,9 +1,5 @@
# Test graph delay value comparison and multi-corner graph operations.
# Targets: DelayFloat.cc (87.8% -> delayLess with min_max, delayGreater,
# delayGreaterEqual, delayLessEqual, delayRemove, delayRatio, delayZero,
# delayInf, delayInitValue, delayIsInitValue)
# Graph.cc (71.2% -> multi-corner vertex/edge access, clock vertices)
# GraphCmp.cc (90.5% -> sortEdges with multiple edges)
# Targets: DelayFloat.cc/Graph.cc/GraphCmp.cc multi-corner delay paths.
source ../../test/helpers.tcl

5
graph/test/graph_incremental.tcl
View File

@ -1,8 +1,5 @@
# Test graph incremental changes, constant propagation, and level reporting.
# Targets: Graph.cc (71.2% -> constant propagation, remove/add edges,
# setSlew, pinDrvrVertex, pinLoadVertex, hasDownstreamClkPin, etc.)
# GraphCmp.cc (90.5% -> EdgeLess, sortEdges, VertexNameLess)
# DelayFloat.cc (87.8% -> delayLess with min_max, delayGreater, etc.)
# Targets: Graph.cc/GraphCmp.cc/DelayFloat.cc graph update and traversal paths.
source ../../test/helpers.tcl

13
liberty/test/liberty_cell_deep.ok
View File

@ -45,7 +45,6 @@ BUF_X1 dont_use = 0
DFF_X1 dont_use = 0
ANTENNA_X1 dont_use = 1
FILLCELL_X1 dont_use = 1
Warning: liberty_cell_deep.tcl line 1, set_input_delay relative to a clock defined on the same port/pin not allowed.
No paths found.
No paths found.
No paths found.
@ -88,20 +87,20 @@ No paths found.
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
----------------------------------------------------------------
Sequential 1.76e-06 6.90e-09 2.36e-07 2.01e-06 85.9%
Combinational 1.33e-07 7.11e-08 1.25e-07 3.29e-07 14.1%
Sequential 1.52e-06 6.90e-09 2.36e-07 1.76e-06 84.2%
Combinational 1.33e-07 7.11e-08 1.25e-07 3.29e-07 15.8%
Clock 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
Total 1.90e-06 7.80e-08 3.61e-07 2.33e-06 100.0%
81.2% 3.3% 15.5%
Total 1.65e-06 7.80e-08 3.61e-07 2.09e-06 100.0%
79.0% 3.7% 17.3%
Internal Switching Leakage Total
Power Power Power Power (Watts)
--------------------------------------------
5.87e-07 6.90e-09 7.86e-08 6.73e-07 reg1
5.89e-07 0.00e+00 7.84e-08 6.67e-07 reg2
5.87e-07 0.00e+00 7.86e-08 6.65e-07 reg3
3.41e-07 0.00e+00 7.86e-08 4.20e-07 reg3
2.56e-08 2.00e-08 2.51e-08 7.07e-08 and1
2.70e-08 2.01e-08 2.27e-08 6.98e-08 or1
3.04e-08 1.13e-08 2.14e-08 6.31e-08 buf1
@ -280,4 +279,4 @@ File ../../test/sky130hd/sky130hd_tt.lib
S0 input 3.70-4.09
S1 input 2.61-2.74
X output function=((((A0*!S0)*!S1)+((A1*S0)*!S1))+((A2*!S0)*S1))+((A3*S0)*S1)
write_liberty output: 3598559 bytes
No differences found.

6
liberty/test/liberty_cell_deep.tcl
View File

@ -80,7 +80,7 @@ read_verilog ../../sdc/test/sdc_test2.v
link_design sdc_test2
create_clock -name clk1 -period 10 [get_ports clk1]
create_clock -name clk2 -period 20 [get_ports clk2]
set_input_delay -clock clk1 2.0 [all_inputs]
set_input_delay -clock clk1 2.0 [get_ports {in1 in2 in3}]
set_output_delay -clock clk1 3.0 [all_outputs]
set_input_transition 0.1 [all_inputs]
@ -157,5 +157,5 @@ report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__mux4_1
set outfile [make_result_file liberty_cell_deep_write.lib]
sta::write_liberty NangateOpenCellLibrary $outfile
# Verify file was written
puts "write_liberty output: [file size $outfile] bytes"
# Verify file contents against static golden.
diff_files liberty_cell_deep_write.libok $outfile

61250
liberty/test/liberty_cell_deep_write.libok Normal file
View File

File diff suppressed because it is too large Load Diff

40
liberty/test/liberty_read_asap7.tcl
View File

@ -42,9 +42,15 @@ report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/ICGx1_ASAP7_75t_R
# Query all cells in SEQ library
set all_seq_cells [get_lib_cells asap7sc7p5t_SEQ_RVT_FF_nldm_220123/*]
if { [llength $all_seq_cells] == 0 } {
error "expected cells in asap7 SEQ FF library"
}
# Get pins of DFF
set dff_pins [get_lib_pins asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DFFHQNx1_ASAP7_75t_R/*]
if { [llength $dff_pins] < 3 } {
error "expected DFFHQNx1 pins in asap7 SEQ FF library"
}
############################################################
# Read compressed ASAP7 SIMPLE library (.lib.gz)
@ -60,6 +66,9 @@ if { $simple_lib == "" } {
# Query cells in SIMPLE library
set all_simple_cells [get_lib_cells asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120/*]
if { [llength $all_simple_cells] == 0 } {
error "expected cells in asap7 SIMPLE FF library"
}
############################################################
# Read compressed ASAP7 INVBUF library (.lib.gz)
@ -74,6 +83,9 @@ if { $invbuf_lib == "" } {
}
set all_invbuf_cells [get_lib_cells asap7sc7p5t_INVBUF_RVT_FF_nldm_211120/*]
if { [llength $all_invbuf_cells] == 0 } {
error "expected cells in asap7 INVBUF FF library"
}
############################################################
# Read compressed ASAP7 OA library (.lib.gz)
@ -88,6 +100,9 @@ if { $oa_lib == "" } {
}
set all_oa_cells [get_lib_cells asap7sc7p5t_OA_RVT_FF_nldm_211120/*]
if { [llength $all_oa_cells] == 0 } {
error "expected cells in asap7 OA FF library"
}
############################################################
# Read compressed ASAP7 AO library (.lib.gz)
@ -102,6 +117,9 @@ if { $ao_lib == "" } {
}
set all_ao_cells [get_lib_cells asap7sc7p5t_AO_RVT_FF_nldm_211120/*]
if { [llength $all_ao_cells] == 0 } {
error "expected cells in asap7 AO FF library"
}
############################################################
# Read SS corner for different timing
@ -113,17 +131,33 @@ read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120.lib.gz
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_SS_nldm_220122.lib.gz
if { [llength [get_lib_cells asap7sc7p5t_SEQ_RVT_SS_nldm_220123/*]] == 0 } {
error "expected cells in asap7 SEQ SS library"
}
if { [llength [get_lib_cells asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120/*]] == 0 } {
error "expected cells in asap7 SIMPLE SS library"
}
if { [llength [get_lib_cells asap7sc7p5t_INVBUF_RVT_SS_nldm_211120/*]] == 0 } {
error "expected cells in asap7 INVBUF SS library"
}
############################################################
# Read CCSN library (compressed, exercises LibertyReader CCSN)
############################################################
read_liberty ../../test/asap7_ccsn.lib.gz
if { [llength [get_lib_cells asap7sc7p5t_AO_LVT_FF_ccsn_211120/*]] == 0 } {
error "expected cells in asap7 CCSN library"
}
############################################################
# Read latch library (exercises latch-specific parsing)
############################################################
read_liberty ../../test/liberty_latch3.lib
if { [llength [get_lib_cells asap7sc7p5t_lvt_ff/*]] == 0 } {
error "expected cells in latch3 library"
}
############################################################
# Read fakeram (macro library)
@ -132,3 +166,9 @@ read_liberty ../../test/liberty_latch3.lib
read_liberty ../../test/nangate45/fake_macros.lib
read_liberty ../../test/nangate45/fakeram45_256x16.lib
if { [llength [get_lib_cells fake_macros/*]] == 0 } {
error "expected cells in fake_macros library"
}
if { [llength [get_lib_cells fakeram45_256x16/*]] == 0 } {
error "expected cells in fakeram45_256x16 library"
}

18
liberty/test/liberty_read_ihp.tcl
View File

@ -25,6 +25,9 @@ if { $inv == "" } {
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_inv_1
set inv_pins [get_lib_pins sg13g2_stdcell_typ_1p20V_25C/sg13g2_inv_1/*]
if { [llength $inv_pins] != 2 } {
error "expected 2 pins on sg13g2_inv_1, found [llength $inv_pins]"
}
foreach sz {2 4 8 16} {
set cell [get_lib_cells sg13g2_stdcell_typ_1p20V_25C/sg13g2_inv_$sz]
@ -121,6 +124,9 @@ if { $dfrbp == "" } {
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_dfrbp_1
set dfrbp_pins [get_lib_pins sg13g2_stdcell_typ_1p20V_25C/sg13g2_dfrbp_1/*]
if { [llength $dfrbp_pins] < 4 } {
error "expected dfrbp_1 to have at least 4 pins, found [llength $dfrbp_pins]"
}
# Latch cells
set dlhq [get_lib_cells sg13g2_stdcell_typ_1p20V_25C/sg13g2_dlhq_1]
@ -180,10 +186,19 @@ report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_dlygate4sd1_1
############################################################
set all_cells [get_lib_cells sg13g2_stdcell_typ_1p20V_25C/*]
if { [llength $all_cells] < 70 } {
error "expected broad sg13g2 1p20V cell set, found [llength $all_cells]"
}
set all_inv [get_lib_cells sg13g2_stdcell_typ_1p20V_25C/sg13g2_inv_*]
if { [llength $all_inv] < 4 } {
error "expected sg13g2 inverter variants, found [llength $all_inv]"
}
set all_nand [get_lib_cells sg13g2_stdcell_typ_1p20V_25C/sg13g2_nand*]
if { [llength $all_nand] < 3 } {
error "expected sg13g2 nand variants, found [llength $all_nand]"
}
############################################################
# Also read the 1.50V variant
@ -198,3 +213,6 @@ if { $lib_1p5 == "" } {
}
set cells_1p5 [get_lib_cells sg13g2_stdcell_typ_1p50V_25C/*]
if { [llength $cells_1p5] < 70 } {
error "expected broad sg13g2 1p50V cell set, found [llength $cells_1p5]"
}

30
liberty/test/liberty_read_nangate.tcl
View File

@ -24,6 +24,9 @@ if { $inv1 == "" } {
report_lib_cell NangateOpenCellLibrary/INV_X1
set inv_pins [get_lib_pins NangateOpenCellLibrary/INV_X1/*]
if { [llength $inv_pins] != 2 } {
error "expected 2 pins on INV_X1, found [llength $inv_pins]"
}
# Other inverter sizes
foreach sz {X2 X4 X8 X16 X32} {
@ -47,6 +50,9 @@ if { $buf1 == "" } {
report_lib_cell NangateOpenCellLibrary/BUF_X1
set buf_pins [get_lib_pins NangateOpenCellLibrary/BUF_X1/*]
if { [llength $buf_pins] != 2 } {
error "expected 2 pins on BUF_X1, found [llength $buf_pins]"
}
foreach sz {X2 X4 X8 X16 X32} {
set cell [get_lib_cells NangateOpenCellLibrary/BUF_$sz]
@ -69,6 +75,9 @@ if { $nand2 == "" } {
report_lib_cell NangateOpenCellLibrary/NAND2_X1
set nand_pins [get_lib_pins NangateOpenCellLibrary/NAND2_X1/*]
if { [llength $nand_pins] != 3 } {
error "expected 3 pins on NAND2_X1, found [llength $nand_pins]"
}
foreach cell_name {NAND2_X2 NAND2_X4 NAND3_X1 NAND3_X2 NAND4_X1} {
set cell [get_lib_cells NangateOpenCellLibrary/$cell_name]
@ -220,22 +229,43 @@ report_lib_cell NangateOpenCellLibrary/FA_X1
############################################################
set all_inv [get_lib_cells NangateOpenCellLibrary/INV_*]
if { [llength $all_inv] < 6 } {
error "expected multiple INV_* cells, found [llength $all_inv]"
}
set all_buf [get_lib_cells NangateOpenCellLibrary/BUF_*]
if { [llength $all_buf] < 6 } {
error "expected multiple BUF_* cells, found [llength $all_buf]"
}
set all_dff [get_lib_cells NangateOpenCellLibrary/DFF*]
if { [llength $all_dff] < 4 } {
error "expected multiple DFF* cells, found [llength $all_dff]"
}
set all_cells [get_lib_cells NangateOpenCellLibrary/*]
if { [llength $all_cells] < 100 } {
error "expected full Nangate library cell list, found [llength $all_cells]"
}
############################################################
# get_lib_pins with patterns
############################################################
set all_inv_pins [get_lib_pins NangateOpenCellLibrary/INV_X1/*]
if { [llength $all_inv_pins] != 2 } {
error "expected 2 INV_X1 pins from wildcard, found [llength $all_inv_pins]"
}
set all_dff_pins [get_lib_pins NangateOpenCellLibrary/DFF_X1/*]
if { [llength $all_dff_pins] < 4 } {
error "expected DFF_X1 pins to include D/CK/Q(+variants), found [llength $all_dff_pins]"
}
set nand_a1 [get_lib_pins NangateOpenCellLibrary/NAND2_X1/A1]
if { [llength $nand_a1] != 1 } {
error "expected single NAND2_X1/A1 pin match"
}
############################################################
# Clock buffer

19
liberty/test/liberty_read_sky130.tcl
View File

@ -20,6 +20,20 @@ if { [llength $pins] == 0 } {
puts "FAIL: no pins found"
exit 1
}
if { [llength $pins] != 2 } {
error "expected exactly 2 pins on sky130 inv_1, found [llength $pins]"
}
set inv_area [get_property $cell area]
if { $inv_area <= 0.0 } {
error "expected positive area for sky130 inv_1, got $inv_area"
}
set inv_a [get_lib_pins sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__inv_1/A]
set inv_y [get_lib_pins sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__inv_1/Y]
if { $inv_a == "" || $inv_y == "" } {
error "expected both A and Y pins on sky130 inv_1"
}
# Query a 2-input gate
set nand [get_lib_cells sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__nand2_1]
@ -27,3 +41,8 @@ if { $nand == "" } {
puts "FAIL: nand2_1 not found"
exit 1
}
set nand_pins [get_lib_pins sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__nand2_1/*]
if { [llength $nand_pins] != 3 } {
error "expected 3 pins on sky130 nand2_1, found [llength $nand_pins]"
}

2728
liberty/test/liberty_roundtrip_asap7_invbuf.libok Normal file
View File

File diff suppressed because it is too large Load Diff

11647
liberty/test/liberty_roundtrip_asap7_seq.libok Normal file
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File diff suppressed because it is too large Load Diff

12620
liberty/test/liberty_roundtrip_asap7_simple.libok Normal file
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File diff suppressed because it is too large Load Diff

2536
liberty/test/liberty_roundtrip_fakeram.libok Normal file
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File diff suppressed because it is too large Load Diff

13300
liberty/test/liberty_roundtrip_ihp.libok Normal file
View File

File diff suppressed because it is too large Load Diff

61250
liberty/test/liberty_roundtrip_nangate.libok Normal file
View File

File diff suppressed because it is too large Load Diff

90692
liberty/test/liberty_roundtrip_sky130.libok Normal file
View File

File diff suppressed because it is too large Load Diff

14
liberty/test/liberty_write_roundtrip.ok
View File

@ -1,6 +1,6 @@
Nangate45 write: 3598559 bytes
Sky130 write: 4746895 bytes
IHP write: 752459 bytes
No differences found.
No differences found.
No differences found.
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13178, timing group from output port.
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13211, timing group from output port.
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13244, timing group from output port.
@ -11,10 +11,10 @@ Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 1337
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14772, timing group from output port.
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14805, timing group from output port.
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14838, timing group from output port.
ASAP7 SIMPLE write: 795590 bytes
ASAP7 SEQ write: 718373 bytes
ASAP7 INVBUF write: 147219 bytes
fakeram write: 78058 bytes
No differences found.
No differences found.
No differences found.
No differences found.
Warning: ../../test/nangate45/fake_macros.lib line 32, default_max_transition is 0.0.
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120.lib.gz line 13156, timing group from output port.
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120.lib.gz line 13189, timing group from output port.

21
liberty/test/liberty_write_roundtrip.tcl
View File

@ -11,13 +11,12 @@ proc assert_written_liberty {path lib_name} {
if {![file exists $path]} {
error "missing written liberty file: $path"
}
if {[file size $path] <= 0} {
error "written liberty file is empty: $path"
}
set in [open $path r]
set text [read $in]
close $in
if {[string length $text] <= 0} {
error "written liberty file is empty: $path"
}
if {[string first "library (" $text] < 0} {
error "written liberty file has no library block: $path"
@ -41,7 +40,7 @@ set outfile1 [make_result_file liberty_roundtrip_nangate.lib]
sta::write_liberty NangateOpenCellLibrary $outfile1
assert_written_liberty $outfile1 NangateOpenCellLibrary
puts "Nangate45 write: [file size $outfile1] bytes"
diff_files liberty_roundtrip_nangate.libok $outfile1
############################################################
# Read and write Sky130 (large library with different features)
@ -53,7 +52,7 @@ set outfile2 [make_result_file liberty_roundtrip_sky130.lib]
sta::write_liberty sky130_fd_sc_hd__tt_025C_1v80 $outfile2
assert_written_liberty $outfile2 sky130_fd_sc_hd__tt_025C_1v80
puts "Sky130 write: [file size $outfile2] bytes"
diff_files liberty_roundtrip_sky130.libok $outfile2
############################################################
# Read and write IHP (different vendor format)
@ -65,7 +64,7 @@ set outfile3 [make_result_file liberty_roundtrip_ihp.lib]
sta::write_liberty sg13g2_stdcell_typ_1p20V_25C $outfile3
assert_written_liberty $outfile3 sg13g2_stdcell_typ_1p20V_25C
puts "IHP write: [file size $outfile3] bytes"
diff_files liberty_roundtrip_ihp.libok $outfile3
############################################################
# Read and write ASAP7 SIMPLE (compressed input)
@ -77,7 +76,7 @@ set outfile4 [make_result_file liberty_roundtrip_asap7_simple.lib]
sta::write_liberty asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120 $outfile4
assert_written_liberty $outfile4 asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120
puts "ASAP7 SIMPLE write: [file size $outfile4] bytes"
diff_files liberty_roundtrip_asap7_simple.libok $outfile4
############################################################
# Read and write ASAP7 SEQ (sequential cell writing)
@ -89,7 +88,7 @@ set outfile5 [make_result_file liberty_roundtrip_asap7_seq.lib]
sta::write_liberty asap7sc7p5t_SEQ_RVT_FF_nldm_220123 $outfile5
assert_written_liberty $outfile5 asap7sc7p5t_SEQ_RVT_FF_nldm_220123
puts "ASAP7 SEQ write: [file size $outfile5] bytes"
diff_files liberty_roundtrip_asap7_seq.libok $outfile5
############################################################
# Read and write ASAP7 INVBUF (compressed input)
@ -101,7 +100,7 @@ set outfile6 [make_result_file liberty_roundtrip_asap7_invbuf.lib]
sta::write_liberty asap7sc7p5t_INVBUF_RVT_FF_nldm_211120 $outfile6
assert_written_liberty $outfile6 asap7sc7p5t_INVBUF_RVT_FF_nldm_211120
puts "ASAP7 INVBUF write: [file size $outfile6] bytes"
diff_files liberty_roundtrip_asap7_invbuf.libok $outfile6
############################################################
# Read and write ASAP7 AO (AND-OR cells)
@ -133,7 +132,7 @@ set outfile9 [make_result_file liberty_roundtrip_fakeram.lib]
sta::write_liberty fakeram7_256x32 $outfile9
assert_written_liberty $outfile9 fakeram7_256x32
puts "fakeram write: [file size $outfile9] bytes"
diff_files liberty_roundtrip_fakeram.libok $outfile9
############################################################
# Read and write fake_macros

4
liberty/test/liberty_writer_roundtrip.ok
View File

@ -1,5 +1,5 @@
write_liberty rt1: 3598559 bytes
write_liberty sky130: 4746895 bytes
No differences found.
No differences found.
INV_X1: 1 arc sets
rise->fall
fall->rise

4
liberty/test/liberty_writer_roundtrip.tcl
View File

@ -15,7 +15,7 @@ set lib [lindex [get_libs NangateOpenCellLibrary] 0]
set outfile1 [make_result_file liberty_writer_rt1.lib]
sta::write_liberty $lib $outfile1
puts "write_liberty rt1: [file size $outfile1] bytes"
diff_files liberty_writer_rt1.libok $outfile1
############################################################
# Read Sky130 which has tristate, latch, and async cells
@ -27,7 +27,7 @@ set sky_lib [sta::find_liberty "sky130_fd_sc_hd__tt_025C_1v80"]
if {$sky_lib ne "NULL" && $sky_lib ne ""} {
set outfile3 [make_result_file liberty_writer_rt_sky.lib]
sta::write_liberty $sky_lib $outfile3
puts "write_liberty sky130: [file size $outfile3] bytes"
diff_files liberty_writer_rt_sky.libok $outfile3
}

61250
liberty/test/liberty_writer_rt1.libok Normal file
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File diff suppressed because it is too large Load Diff

90692
liberty/test/liberty_writer_rt_sky.libok Normal file
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File diff suppressed because it is too large Load Diff

15
make_coverage_report.sh
View File

@ -1,5 +1,5 @@
#!/bin/bash
# Usage: ./make_coverage_report.sh [--tcl_only] [--O0]
# Usage: ./make_coverage_report.sh [-B] [--tcl_only] [--O0]
# Generates an lcov/genhtml coverage report for OpenSTA tests.
# --O0 Disable optimizations for accurate coverage (no inlining)
# --tcl_only Run only Tcl tests (skip C++ unit tests)
@ -13,6 +13,7 @@ usage() {
echo "an lcov/genhtml coverage report."
echo ""
echo "Options:"
echo " -B Clean rebuild (remove build directory before building)"
echo " --O0 Disable optimizations (-O0) for accurate coverage measurement"
echo " --tcl_only Run only Tcl tests (skip C++ unit tests)"
echo " -h, --help Show this help message"
@ -23,11 +24,13 @@ usage() {
exit 0
}
CLEAN_BUILD=0
TCL_ONLY=0
OPT_LEVEL=""
for arg in "$@"; do
case "$arg" in
-h|--help) usage ;;
-B) CLEAN_BUILD=1 ;;
--tcl_only) TCL_ONLY=1 ;;
--O0) OPT_LEVEL="-O0" ;;
*) echo "Unknown argument: $arg"; echo "Run '$0 --help' for usage."; exit 1 ;;
@ -47,10 +50,15 @@ LCOV_IGNORE="--ignore-errors mismatch,mismatch,gcov,gcov,source,source"
echo "=== OpenSTA Coverage Report ==="
echo "Build directory: $BUILD_DIR"
echo "Report directory: $REPORT_DIR"
echo "Clean build: $CLEAN_BUILD"
echo "TCL only: $TCL_ONLY"
echo "Optimization: ${OPT_LEVEL:-default}"
# Step 1: Configure
if [ "$CLEAN_BUILD" -eq 1 ] && [ -d "$BUILD_DIR" ]; then
echo "Removing $BUILD_DIR for clean rebuild..."
rm -rf "$BUILD_DIR"
fi
mkdir -p "$BUILD_DIR"
cd "$BUILD_DIR"
@ -63,6 +71,11 @@ cmake .. \
# Step 2: Build
make -j$(nproc)
# Step 2.5: Clear stale coverage data before test execution.
# Old .gcda files from previous builds can cause gcov checksum mismatch noise
# that pollutes test logs and leads to false regression diffs.
find . -name '*.gcda' -delete
# Step 3: Run tests
if [ "$TCL_ONLY" -eq 1 ]; then
echo "Running Tcl tests only..."

3
network/test/network_net_cap_query.ok
View File

@ -204,6 +204,8 @@ leaf instances list: 11
library: NangateOpenCellLibrary
library: verilog
total libraries: 2
found library: NangateOpenCellLibrary
found INV_X1 in NangateOpenCellLibrary
BUF* cells in library: 6
all cells in library: 134
--- Test 9: timing reports ---
@ -266,7 +268,6 @@ Path Type: min
0.01 slack (MET)
Warning: network_net_cap_query.tcl line 1, unknown field nets.
Startpoint: in2 (input port clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk

8
network/test/network_net_cap_query.tcl
View File

@ -235,11 +235,17 @@ puts "total libraries: $lib_count"
# Find library by name
set found_lib [sta::find_library NangateOpenCellLibrary]
if { $found_lib != "NULL" } {
puts "found library: [$found_lib name]"
} else {
error "expected NangateOpenCellLibrary to exist"
}
# Find cell in library
set inv_cell [$found_lib find_cell INV_X1]
if { $inv_cell != "NULL" } {
puts "found INV_X1 in NangateOpenCellLibrary"
} else {
error "expected INV_X1 cell in NangateOpenCellLibrary"
}
# find_cells_matching on library
@ -259,7 +265,7 @@ report_checks
report_checks -path_delay min
report_checks -fields {slew cap input_pins nets fanout}
report_checks -fields {slew cap input_pins fanout}
# Check types
report_check_types -max_delay -min_delay

4
parasitics/test/parasitics_spef.ok
View File

@ -8,4 +8,8 @@ Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 1337
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14772, timing group from output port.
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14805, timing group from output port.
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14838, timing group from output port.
r1q total_cap=1.3922564510505161e-14 pin_cap=5.225650124681606e-16 wire_cap=1.3399999392157882e-14
r2q total_cap=1.3977042281540768e-14 pin_cap=5.770419894103802e-16 wire_cap=1.3400000239190829e-14
u1z total_cap=1.3965708133673559e-14 pin_cap=5.65708000361848e-16 wire_cap=1.3400000239190829e-14
u2z total_cap=1.4021215896773027e-14 pin_cap=6.212170340107377e-16 wire_cap=1.3399998545124935e-14
No paths found.

14
parasitics/test/parasitics_spef.tcl
View File

@ -14,4 +14,16 @@ create_clock -name clk1 -period 10 [get_ports clk1]
# Read SPEF
read_spef ../../test/reg1_asap7.spef
report_checks
set corner [sta::cmd_corner]
foreach net_name {r1q r2q u1z u2z} {
set net [get_nets $net_name]
set total_cap [$net capacitance $corner "max"]
set pin_cap [$net pin_capacitance $corner "max"]
set wire_cap [$net wire_capacitance $corner "max"]
puts "$net_name total_cap=$total_cap pin_cap=$pin_cap wire_cap=$wire_cap"
if {$total_cap <= 0.0} {
error "expected positive capacitance on net $net_name after SPEF read"
}
}
report_checks -fields {slew cap input_pins fanout}

11
power/test/power_report.ok
View File

@ -1,11 +0,0 @@
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
----------------------------------------------------------------
Sequential 4.28e-06 0.00e+00 8.44e-12 4.28e-06 97.4%
Combinational 8.52e-08 2.72e-08 1.18e-12 1.12e-07 2.6%
Clock 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
Total 4.36e-06 2.72e-08 9.62e-12 4.39e-06 100.0%
99.4% 0.6% 0.0%

21
power/test/power_report.tcl
View File

@ -5,6 +5,23 @@ link_design power_test1
create_clock -name clk -period 10 [get_ports clk]
set_input_delay -clock clk 0 [get_ports in1]
set_output_delay -clock clk 0 [get_ports out1]
set_input_transition 0.1 [get_ports in1]
# Report power
report_power
set_power_activity -global -activity 0.5 -duty 0.5
# Report power with explicit checks on returned content.
with_output_to_variable pwr_default { report_power }
if {![regexp {Total} $pwr_default]} {
error "report_power output missing Total section"
}
with_output_to_variable pwr_inst { report_power -instances [get_cells reg1] }
if {![regexp {reg1} $pwr_inst]} {
error "instance power report missing reg1 entry"
}
with_output_to_variable pwr_json { report_power -format json }
if {![regexp {"Total"} $pwr_json]} {
error "json power report missing Total field"
}

77
sdc/test/cpp/TestSdc.cc
View File

@ -467,12 +467,11 @@ protected:
};
TEST_F(CycleAcctingTest, CycleAcctingHashAndEqual) {
// Test the hash and equal functors with placeholder data
CycleAcctingHash hasher;
CycleAcctingEqual equal;
// These work on CycleAccting pointers but we can verify the functors exist
// by testing that they compile and are callable
EXPECT_TRUE(true); // Compilation test
(void)hasher;
(void)equal;
EXPECT_TRUE(true);
}
////////////////////////////////////////////////////////////////
@ -565,12 +564,13 @@ protected:
// (actual Clock objects require Sdc which requires full setup)
TEST_F(ClockCmpTest, ClkNameLessInstantiation) {
ClkNameLess less;
// Just verify it compiles
(void)less;
EXPECT_TRUE(true);
}
TEST_F(ClockCmpTest, ClockNameLessInstantiation) {
ClockNameLess less;
(void)less;
EXPECT_TRUE(true);
}
@ -2981,10 +2981,23 @@ TEST_F(SdcInitTest, SdcRemoveNetLoadCaps) {
// CycleAccting hash and equal functors
TEST_F(SdcInitTest, CycleAcctingFunctorsCompile) {
FloatSeq *wave = new FloatSeq;
wave->push_back(0.0);
wave->push_back(4.0);
sta_->makeClock("cycle_functor_clk", nullptr, false, 8.0, wave, nullptr);
Sdc *sdc = sta_->sdc();
Clock *clk = sdc->findClock("cycle_functor_clk");
ASSERT_NE(clk, nullptr);
ClockEdge *rise = clk->edge(RiseFall::rise());
ClockEdge *fall = clk->edge(RiseFall::fall());
ASSERT_NE(rise, nullptr);
ASSERT_NE(fall, nullptr);
CycleAccting ca(rise, fall);
CycleAcctingHash hasher;
CycleAcctingEqual equal;
// Just verify they compile and can be instantiated
EXPECT_TRUE(true);
EXPECT_EQ(hasher(&ca), hasher(&ca));
EXPECT_TRUE(equal(&ca, &ca));
}
// clkCmp, clkEdgeCmp, clkEdgeLess
@ -3232,10 +3245,9 @@ TEST_F(SdcInitTest, ClkEdgeCmpLess) {
ClockEdge *e1 = clk1->edge(RiseFall::rise());
ClockEdge *e2 = clk2->edge(RiseFall::rise());
int cmp_result = clkEdgeCmp(e1, e2);
// Just verify it doesn't crash and returns a value
(void)cmp_result;
bool less_result = clkEdgeLess(e1, e2);
(void)less_result;
EXPECT_NE(cmp_result, 0);
EXPECT_EQ(less_result, cmp_result < 0);
}() ));
}
@ -3319,7 +3331,8 @@ TEST_F(SdcInitTest, ClockIndexLessComparator) {
Clock *clk2 = sdc->findClock("idx_clk2");
ClockIndexLess idx_less;
bool result = idx_less(clk1, clk2);
(void)result;
bool reverse = idx_less(clk2, clk1);
EXPECT_NE(result, reverse);
}() ));
}
@ -3353,11 +3366,13 @@ TEST_F(SdcInitTest, DeratingFactorsIsOneValue) {
DeratingFactors factors;
factors.setFactor(PathClkOrData::clk,
RiseFallBoth::riseFall(), EarlyLate::early(), 1.0f);
factors.setFactor(PathClkOrData::data,
RiseFallBoth::riseFall(), EarlyLate::early(), 1.0f);
bool is_one;
float value;
factors.isOneValue(EarlyLate::early(), is_one, value);
(void)is_one;
(void)value;
EXPECT_TRUE(is_one);
EXPECT_FLOAT_EQ(value, 1.0f);
}() ));
}
@ -3371,8 +3386,8 @@ TEST_F(SdcInitTest, DeratingFactorsIsOneValueClkData) {
bool is_one;
float value;
factors.isOneValue(PathClkOrData::clk, EarlyLate::early(), is_one, value);
(void)is_one;
(void)value;
EXPECT_TRUE(is_one);
EXPECT_FLOAT_EQ(value, 1.0f);
}() ));
}
@ -3422,11 +3437,17 @@ TEST_F(SdcInitTest, DeratingFactorsCellIsOneValue) {
DeratingFactorsCell factors;
factors.setFactor(TimingDerateCellType::cell_delay, PathClkOrData::clk,
RiseFallBoth::riseFall(), EarlyLate::early(), 1.0f);
factors.setFactor(TimingDerateCellType::cell_delay, PathClkOrData::data,
RiseFallBoth::riseFall(), EarlyLate::early(), 1.0f);
factors.setFactor(TimingDerateCellType::cell_check, PathClkOrData::clk,
RiseFallBoth::riseFall(), EarlyLate::early(), 1.0f);
factors.setFactor(TimingDerateCellType::cell_check, PathClkOrData::data,
RiseFallBoth::riseFall(), EarlyLate::early(), 1.0f);
bool is_one;
float value;
factors.isOneValue(EarlyLate::early(), is_one, value);
(void)is_one;
(void)value;
EXPECT_TRUE(is_one);
EXPECT_FLOAT_EQ(value, 1.0f);
}() ));
}
@ -3498,12 +3519,14 @@ TEST_F(SdcInitTest, CycleAcctingHashEqualLess) {
CycleAcctingHash hash;
size_t h1 = hash(&ca1);
size_t h2 = hash(&ca2);
(void)h1; (void)h2;
EXPECT_NE(h1, h2);
EXPECT_EQ(h1, hash(&ca1));
CycleAcctingEqual eq;
EXPECT_TRUE(eq(&ca1, &ca1));
CycleAcctingLess less;
bool r = less(&ca1, &ca2);
(void)r;
bool r2 = less(&ca2, &ca1);
EXPECT_NE(r, r2);
}
// DisabledPorts constructors and methods
@ -3641,12 +3664,12 @@ TEST_F(SdcInitTest, SdcUnsetTimingDerate) {
// PinPairLess
TEST_F(SdcInitTest, PinPairLessConstruct) {
ASSERT_NO_THROW(( [&](){
Network *network = sta_->cmdNetwork();
ASSERT_NE(network, nullptr);
PinPairLess less(network);
// Just construction
}() ));
PinPair p1(nullptr, nullptr);
PinPair p2(nullptr, nullptr);
EXPECT_FALSE(less(p1, p2));
}
// PinPairSet with network
@ -3658,12 +3681,10 @@ TEST_F(SdcInitTest, PinPairSetConstruct) {
// PinPairHash with network
TEST_F(SdcInitTest, PinPairHashConstruct) {
ASSERT_NO_THROW(( [&](){
Network *network = sta_->cmdNetwork();
ASSERT_NE(network, nullptr);
PinPairHash hash(network);
// Just construction
}() ));
(void)hash;
}
// Sdc: dataChecksFrom/dataChecksTo (need Pin* arg)
@ -3978,7 +3999,7 @@ TEST_F(SdcInitTest, ClockDefaultPin) {
Clock *clk = sdc->findClock("dp_clk");
const Pin *dp = clk->defaultPin();
// No default pin for virtual clock
(void)dp;
EXPECT_EQ(dp, nullptr);
}() ));
}

23
sdc/test/sdc_case1.sdcok Normal file
View File

@ -0,0 +1,23 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
set_input_delay 2.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
set_output_delay 3.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
###############################################################################
# Environment
###############################################################################
set_case_analysis 0 [get_ports {in1}]
set_case_analysis 1 [get_ports {in2}]
set_case_analysis rising [get_ports {in3}]
###############################################################################
# Design Rules
###############################################################################

21
sdc/test/sdc_case2.sdcok Normal file
View File

@ -0,0 +1,21 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
set_input_delay 2.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
set_output_delay 3.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
###############################################################################
# Environment
###############################################################################
set_case_analysis falling [get_ports {in1}]
###############################################################################
# Design Rules
###############################################################################

32
sdc/test/sdc_clk_grp_allow.sdcok Normal file
View File

@ -0,0 +1,32 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
create_clock -name vclk1 -period 8.0000
create_clock -name vclk2 -period 12.0000
create_clock -name clk1_2x -add -period 5.0000 [get_ports {clk1}]
create_generated_clock -name gclk1 -source [get_ports {clk1}] -divide_by 2 [get_pins {reg1/Q}]
create_generated_clock -name gclk2 -source [get_ports {clk2}] -multiply_by 2 [get_pins {reg3/Q}]
set_clock_groups -name allow_grp -asynchronous \
-allow_paths \
-group [list [get_clocks {clk2}]\
[get_clocks {gclk2}]]\
-group [list [get_clocks {clk1}]\
[get_clocks {clk1_2x}]\
[get_clocks {gclk1}]]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
set_input_delay 2.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
set_output_delay 3.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
###############################################################################
# Environment
###############################################################################
###############################################################################
# Design Rules
###############################################################################

31
sdc/test/sdc_clk_grp_async.sdcok Normal file
View File

@ -0,0 +1,31 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
create_clock -name vclk1 -period 8.0000
create_clock -name vclk2 -period 12.0000
create_clock -name clk1_2x -add -period 5.0000 [get_ports {clk1}]
create_generated_clock -name gclk1 -source [get_ports {clk1}] -divide_by 2 [get_pins {reg1/Q}]
create_generated_clock -name gclk2 -source [get_ports {clk2}] -multiply_by 2 [get_pins {reg3/Q}]
set_clock_groups -name async_group1 -asynchronous \
-group [list [get_clocks {clk2}]\
[get_clocks {gclk2}]]\
-group [list [get_clocks {clk1}]\
[get_clocks {clk1_2x}]\
[get_clocks {gclk1}]]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
set_input_delay 2.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
set_output_delay 3.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
###############################################################################
# Environment
###############################################################################
###############################################################################
# Design Rules
###############################################################################

43
sdc/test/sdc_clk_grp_final.sdcok Normal file
View File

@ -0,0 +1,43 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
set_propagated_clock [get_clocks {clk2}]
create_clock -name vclk1 -period 8.0000
create_clock -name vclk2 -period 12.0000
create_clock -name clk1_2x -add -period 5.0000 [get_ports {clk1}]
create_generated_clock -name gclk1 -source [get_ports {clk1}] -divide_by 2 [get_pins {reg1/Q}]
create_generated_clock -name gclk2 -source [get_ports {clk2}] -multiply_by 2 [get_pins {reg3/Q}]
set_clock_uncertainty -setup 0.2000 [get_pins {reg2/CK}]
set_clock_uncertainty -rise_from [get_clocks {clk2}] -rise_to [get_clocks {clk1}] -hold 0.1200
set_clock_uncertainty -rise_from [get_clocks {clk2}] -rise_to [get_clocks {clk1}] -setup 0.2500
set_clock_uncertainty -rise_from [get_clocks {clk2}] -fall_to [get_clocks {clk1}] -hold 0.1200
set_clock_uncertainty -rise_from [get_clocks {clk2}] -fall_to [get_clocks {clk1}] -setup 0.2500
set_clock_uncertainty -fall_from [get_clocks {clk2}] -rise_to [get_clocks {clk1}] -hold 0.1200
set_clock_uncertainty -fall_from [get_clocks {clk2}] -rise_to [get_clocks {clk1}] -setup 0.2500
set_clock_uncertainty -fall_from [get_clocks {clk2}] -fall_to [get_clocks {clk1}] -hold 0.1200
set_clock_uncertainty -fall_from [get_clocks {clk2}] -fall_to [get_clocks {clk1}] -setup 0.2500
set_sense -type clock -stop_propagation -clock [get_clocks {clk1}] [get_pins {and1/ZN}]
set_sense -type clock -positive -clock [get_clocks {clk1}] [get_pins {buf1/Z}]
set_sense -type clock -negative -clock [get_clocks {clk2}] [get_pins {inv1/ZN}]
set_clock_groups -name group1 -asynchronous \
-group [list [get_clocks {clk1}]\
[get_clocks {gclk1}]]\
-group [list [get_clocks {clk2}]\
[get_clocks {gclk2}]]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
set_input_delay 2.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
set_output_delay 3.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
###############################################################################
# Environment
###############################################################################
###############################################################################
# Design Rules
###############################################################################

29
sdc/test/sdc_clk_grp_logical.sdcok Normal file
View File

@ -0,0 +1,29 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
create_clock -name vclk1 -period 8.0000
create_clock -name vclk2 -period 12.0000
create_clock -name clk1_2x -add -period 5.0000 [get_ports {clk1}]
create_generated_clock -name gclk1 -source [get_ports {clk1}] -divide_by 2 [get_pins {reg1/Q}]
create_generated_clock -name gclk2 -source [get_ports {clk2}] -multiply_by 2 [get_pins {reg3/Q}]
set_clock_groups -name logical_group1 -logically_exclusive \
-group [get_clocks {vclk1}]\
-group [list [get_clocks {clk1}]\
[get_clocks {clk1_2x}]]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
set_input_delay 2.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
set_output_delay 3.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
###############################################################################
# Environment
###############################################################################
###############################################################################
# Design Rules
###############################################################################

33
sdc/test/sdc_clk_grp_multi.sdcok Normal file
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@ -0,0 +1,33 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
create_clock -name vclk1 -period 8.0000
create_clock -name vclk2 -period 12.0000
create_clock -name clk1_2x -add -period 5.0000 [get_ports {clk1}]
create_generated_clock -name gclk1 -source [get_ports {clk1}] -divide_by 2 [get_pins {reg1/Q}]
create_generated_clock -name gclk2 -source [get_ports {clk2}] -multiply_by 2 [get_pins {reg3/Q}]
set_clock_groups -name mixed1 -asynchronous \
-group [list [get_clocks {clk1}]\
[get_clocks {gclk1}]]\
-group [list [get_clocks {clk2}]\
[get_clocks {gclk2}]]
set_clock_groups -name mixed2 -logically_exclusive \
-group [get_clocks {vclk1}]\
-group [get_clocks {vclk2}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
set_input_delay 2.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
set_output_delay 3.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
###############################################################################
# Environment
###############################################################################
###############################################################################
# Design Rules
###############################################################################

28
sdc/test/sdc_clk_grp_phys.sdcok Normal file
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@ -0,0 +1,28 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
create_clock -name vclk1 -period 8.0000
create_clock -name vclk2 -period 12.0000
create_clock -name clk1_2x -add -period 5.0000 [get_ports {clk1}]
create_generated_clock -name gclk1 -source [get_ports {clk1}] -divide_by 2 [get_pins {reg1/Q}]
create_generated_clock -name gclk2 -source [get_ports {clk2}] -multiply_by 2 [get_pins {reg3/Q}]
set_clock_groups -name phys_group1 -physically_exclusive \
-group [get_clocks {clk1}]\
-group [get_clocks {clk1_2x}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
set_input_delay 2.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
set_output_delay 3.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
###############################################################################
# Environment
###############################################################################
###############################################################################
# Design Rules
###############################################################################

28
sdc/test/sdc_clk_sense.sdcok Normal file
View File

@ -0,0 +1,28 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
create_clock -name vclk1 -period 8.0000
create_clock -name vclk2 -period 12.0000
create_clock -name clk1_2x -add -period 5.0000 [get_ports {clk1}]
create_generated_clock -name gclk1 -source [get_ports {clk1}] -divide_by 2 [get_pins {reg1/Q}]
create_generated_clock -name gclk2 -source [get_ports {clk2}] -multiply_by 2 [get_pins {reg3/Q}]
set_sense -type clock -stop_propagation -clock [get_clocks {clk1}] [get_pins {and1/ZN}]
set_sense -type clock -positive -clock [get_clocks {clk1}] [get_pins {buf1/Z}]
set_sense -type clock -negative -clock [get_clocks {clk2}] [get_pins {inv1/ZN}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
set_input_delay 2.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
set_output_delay 3.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
###############################################################################
# Environment
###############################################################################
###############################################################################
# Design Rules
###############################################################################

53
sdc/test/sdc_clk_uncert.sdcok Normal file
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@ -0,0 +1,53 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
set_propagated_clock [get_clocks {clk2}]
create_clock -name vclk1 -period 8.0000
create_clock -name vclk2 -period 12.0000
create_clock -name clk1_2x -add -period 5.0000 [get_ports {clk1}]
create_generated_clock -name gclk1 -source [get_ports {clk1}] -divide_by 2 [get_pins {reg1/Q}]
create_generated_clock -name gclk2 -source [get_ports {clk2}] -multiply_by 2 [get_pins {reg3/Q}]
set_clock_uncertainty -setup 0.1500 [get_pins {reg1/CK}]
set_clock_uncertainty -hold 0.0800 [get_pins {reg1/CK}]
set_clock_uncertainty -setup 0.2000 [get_pins {reg2/CK}]
set_clock_uncertainty -rise_from [get_clocks {clk1}] -rise_to [get_clocks {clk2}] -hold 0.1500
set_clock_uncertainty -rise_from [get_clocks {clk1}] -rise_to [get_clocks {clk2}] -setup 0.3000
set_clock_uncertainty -rise_from [get_clocks {clk1}] -fall_to [get_clocks {clk2}] -hold 0.1500
set_clock_uncertainty -rise_from [get_clocks {clk1}] -fall_to [get_clocks {clk2}] -setup 0.3000
set_clock_uncertainty -fall_from [get_clocks {clk1}] -rise_to [get_clocks {clk2}] -hold 0.1500
set_clock_uncertainty -fall_from [get_clocks {clk1}] -rise_to [get_clocks {clk2}] -setup 0.3000
set_clock_uncertainty -fall_from [get_clocks {clk1}] -fall_to [get_clocks {clk2}] -hold 0.1500
set_clock_uncertainty -fall_from [get_clocks {clk1}] -fall_to [get_clocks {clk2}] -setup 0.3000
set_clock_uncertainty -rise_from [get_clocks {clk2}] -rise_to [get_clocks {clk1}] -hold 0.1200
set_clock_uncertainty -rise_from [get_clocks {clk2}] -rise_to [get_clocks {clk1}] -setup 0.2500
set_clock_uncertainty -rise_from [get_clocks {clk2}] -fall_to [get_clocks {clk1}] -hold 0.1200
set_clock_uncertainty -rise_from [get_clocks {clk2}] -fall_to [get_clocks {clk1}] -setup 0.2500
set_clock_uncertainty -fall_from [get_clocks {clk2}] -rise_to [get_clocks {clk1}] -hold 0.1200
set_clock_uncertainty -fall_from [get_clocks {clk2}] -rise_to [get_clocks {clk1}] -setup 0.2500
set_clock_uncertainty -fall_from [get_clocks {clk2}] -fall_to [get_clocks {clk1}] -hold 0.1200
set_clock_uncertainty -fall_from [get_clocks {clk2}] -fall_to [get_clocks {clk1}] -setup 0.2500
set_sense -type clock -stop_propagation -clock [get_clocks {clk1}] [get_pins {and1/ZN}]
set_sense -type clock -positive -clock [get_clocks {clk1}] [get_pins {buf1/Z}]
set_sense -type clock -negative -clock [get_clocks {clk2}] [get_pins {inv1/ZN}]
set_clock_groups -name group1 -asynchronous \
-group [list [get_clocks {clk1}]\
[get_clocks {gclk1}]]\
-group [list [get_clocks {clk2}]\
[get_clocks {gclk2}]]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
set_input_delay 2.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
set_output_delay 3.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
###############################################################################
# Environment
###############################################################################
###############################################################################
# Design Rules
###############################################################################

23
sdc/test/sdc_clkgate1.sdcok Normal file
View File

@ -0,0 +1,23 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
set_input_delay 2.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
set_output_delay 3.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
###############################################################################
# Environment
###############################################################################
set_logic_zero [get_ports {in1}]
set_logic_one [get_ports {in2}]
set_logic_dc [get_ports {in3}]
###############################################################################
# Design Rules
###############################################################################

11
sdc/test/sdc_clock_groups_sense.ok
View File

@ -1,3 +1,4 @@
No differences found.
Warning: generated clock gclk1 pin clk1 is in the fanout of multiple clocks.
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1_2x)
Endpoint: out1 (output port clocked by clk1)
@ -79,6 +80,9 @@ Path Type: max
2.00 slack (MET)
No differences found.
No differences found.
No differences found.
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1_2x)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
@ -159,9 +163,8 @@ Path Type: max
2.00 slack (MET)
Warning: sdc_clock_groups_sense.tcl line 1, set_clock_sense is deprecated as of SDC 2.1. Use set_sense -type clock.
Warning: sdc_clock_groups_sense.tcl line 1, set_clock_sense is deprecated as of SDC 2.1. Use set_sense -type clock.
Warning: sdc_clock_groups_sense.tcl line 1, set_clock_sense is deprecated as of SDC 2.1. Use set_sense -type clock.
No differences found.
No differences found.
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1_2x)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
@ -242,6 +245,8 @@ Path Type: max
2.00 slack (MET)
No differences found.
No differences found.
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1_2x)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1

14
sdc/test/sdc_clock_groups_sense.tcl
View File

@ -41,6 +41,7 @@ set_clock_groups -asynchronous -name async_group1 \
# Write SDC with async groups
set sdc_file1 [make_result_file sdc_clk_grp_async.sdc]
write_sdc -no_timestamp $sdc_file1
diff_files sdc_clk_grp_async.sdcok $sdc_file1
report_checks
@ -58,6 +59,7 @@ set_clock_groups -logically_exclusive -name logical_group1 \
# Write SDC with logically exclusive groups
set sdc_file2 [make_result_file sdc_clk_grp_logical.sdc]
write_sdc -no_timestamp $sdc_file2
diff_files sdc_clk_grp_logical.sdcok $sdc_file2
# Remove logically exclusive
unset_clock_groups -logically_exclusive -name logical_group1
@ -73,6 +75,7 @@ set_clock_groups -physically_exclusive -name phys_group1 \
# Write SDC
set sdc_file3 [make_result_file sdc_clk_grp_phys.sdc]
write_sdc -no_timestamp $sdc_file3
diff_files sdc_clk_grp_phys.sdcok $sdc_file3
# Remove physically exclusive
unset_clock_groups -physically_exclusive -name phys_group1
@ -92,6 +95,7 @@ set_clock_groups -logically_exclusive -name mixed2 \
# Write SDC with multiple groups
set sdc_file4 [make_result_file sdc_clk_grp_multi.sdc]
write_sdc -no_timestamp $sdc_file4
diff_files sdc_clk_grp_multi.sdcok $sdc_file4
report_checks
@ -110,6 +114,7 @@ set_clock_groups -asynchronous -name allow_grp \
set sdc_file5 [make_result_file sdc_clk_grp_allow.sdc]
write_sdc -no_timestamp $sdc_file5
diff_files sdc_clk_grp_allow.sdcok $sdc_file5
unset_clock_groups -asynchronous -name allow_grp
@ -118,17 +123,18 @@ unset_clock_groups -asynchronous -name allow_grp
############################################################
# Positive sense
set_clock_sense -positive -clocks [get_clocks clk1] [get_pins buf1/Z]
set_sense -type clock -positive -clocks [get_clocks clk1] [get_pins buf1/Z]
# Negative sense
set_clock_sense -negative -clocks [get_clocks clk2] [get_pins inv1/ZN]
set_sense -type clock -negative -clocks [get_clocks clk2] [get_pins inv1/ZN]
# Stop propagation
set_clock_sense -stop_propagation -clocks [get_clocks clk1] [get_pins and1/ZN]
set_sense -type clock -stop_propagation -clocks [get_clocks clk1] [get_pins and1/ZN]
# Write SDC with clock sense
set sdc_file6 [make_result_file sdc_clk_sense.sdc]
write_sdc -no_timestamp $sdc_file6
diff_files sdc_clk_sense.sdcok $sdc_file6
report_checks
@ -171,6 +177,7 @@ set_clock_uncertainty -from [get_clocks clk2] -to [get_clocks clk1] -hold 0.12
# Write SDC with all uncertainty
set sdc_file7 [make_result_file sdc_clk_uncert.sdc]
write_sdc -no_timestamp $sdc_file7
diff_files sdc_clk_uncert.sdcok $sdc_file7
# Remove inter-clock uncertainty
unset_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -setup
@ -186,5 +193,6 @@ unset_clock_uncertainty -hold [get_pins reg1/CK]
set sdc_final [make_result_file sdc_clk_grp_final.sdc]
write_sdc -no_timestamp $sdc_final
diff_files sdc_clk_grp_final.sdcok $sdc_final
report_checks

26
sdc/test/sdc_cycle_acct.sdcok Normal file
View File

@ -0,0 +1,26 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk_half -period 10.0000 -waveform {0.0000 3.0000} [get_ports {clk1}]
create_clock -name clk_norm -period 10.0000 [get_ports {clk2}]
set_input_delay 1.0000 -clock [get_clocks {clk_half}] -add_delay [get_ports {in1}]
set_input_delay 1.0000 -clock [get_clocks {clk_half}] -add_delay [get_ports {in2}]
set_input_delay 1.0000 -clock [get_clocks {clk_norm}] -add_delay [get_ports {in3}]
set_output_delay 2.0000 -clock [get_clocks {clk_half}] -add_delay [get_ports {out1}]
set_output_delay 2.0000 -clock [get_clocks {clk_norm}] -add_delay [get_ports {out2}]
set_multicycle_path -hold\
-from [get_clocks {clk_half}]\
-to [get_clocks {clk_norm}] 1
set_multicycle_path -setup\
-from [get_clocks {clk_half}]\
-to [get_clocks {clk_norm}] 2
###############################################################################
# Environment
###############################################################################
###############################################################################
# Design Rules
###############################################################################

1
sdc/test/sdc_cycle_acct_clk_relationships.ok
View File

@ -679,6 +679,7 @@ Path Type: min
0.08 slack (MET)
No differences found.
--- report_clock_properties ---
Clock Period Waveform
----------------------------------------------------

1
sdc/test/sdc_cycle_acct_clk_relationships.tcl
View File

@ -128,6 +128,7 @@ report_checks -path_delay min
############################################################
set sdc_out [make_result_file sdc_cycle_acct.sdc]
write_sdc -no_timestamp $sdc_out
diff_files sdc_cycle_acct.sdcok $sdc_out
############################################################
# Phase 10: report_clock_properties

1
sdc/test/sdc_cycle_acct_genclk.ok
View File

@ -853,3 +853,4 @@ Clock Period Waveform
----------------------------------------------------
mclk 10.00 0.00 5.00
edge_clk 20.00 0.00 10.00 (generated)
No differences found.

20
sdc/test/sdc_cycle_acct_genclk.sdcok Normal file
View File

@ -0,0 +1,20 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name mclk -period 10.0000 [get_ports {clk1}]
create_generated_clock -name edge_clk -source [get_ports {clk1}] -edges {1 3 5} [get_ports {clk2}]
set_input_delay 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {in1}]
set_input_delay 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {in2}]
set_input_delay 1.5000 -clock [get_clocks {edge_clk}] -add_delay [get_ports {in3}]
set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {out1}]
set_output_delay 2.5000 -clock [get_clocks {edge_clk}] -add_delay [get_ports {out2}]
###############################################################################
# Environment
###############################################################################
###############################################################################
# Design Rules
###############################################################################

1
sdc/test/sdc_cycle_acct_genclk.tcl
View File

@ -155,3 +155,4 @@ report_clock_properties
############################################################
set sdc_out [make_result_file sdc_cycle_acct_genclk.sdc]
write_sdc -no_timestamp $sdc_out
diff_files sdc_cycle_acct_genclk.sdcok $sdc_out

31
sdc/test/sdc_datacheck1.sdcok Normal file
View File

@ -0,0 +1,31 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
set_input_delay 2.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
set_output_delay 3.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
set_data_check -rise_from [get_pins {reg1/Q}] -rise_to [get_pins {reg2/D}] -hold 0.3000
set_data_check -rise_from [get_pins {reg1/Q}] -fall_to [get_pins {reg2/D}] -hold 0.2500
set_data_check -fall_from [get_pins {reg1/Q}] -rise_to [get_pins {reg2/D}] -hold 0.3000
set_data_check -fall_from [get_pins {reg1/Q}] -fall_to [get_pins {reg2/D}] -hold 0.2500
set_data_check -rise_from [get_pins {reg1/Q}] -rise_to [get_pins {reg2/D}] -setup 0.6000
set_data_check -rise_from [get_pins {reg1/Q}] -fall_to [get_pins {reg2/D}] -setup 0.6000
set_data_check -fall_from [get_pins {reg1/Q}] -rise_to [get_pins {reg2/D}] -setup 0.5000
set_data_check -fall_from [get_pins {reg1/Q}] -fall_to [get_pins {reg2/D}] -setup 0.5000
###############################################################################
# Environment
###############################################################################
set_logic_zero [get_ports {in1}]
set_logic_one [get_ports {in2}]
set_logic_dc [get_ports {in3}]
###############################################################################
# Design Rules
###############################################################################

42
sdc/test/sdc_derate1.sdcok Normal file
View File

@ -0,0 +1,42 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
set_input_delay 2.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
set_output_delay 3.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
###############################################################################
# Environment
###############################################################################
set_timing_derate -cell_delay -early -clock 0.9600
set_timing_derate -cell_delay -data -rise -early 0.9500
set_timing_derate -cell_delay -data -fall -early 0.9600
set_timing_derate -cell_check -early 0.9800
set_timing_derate -net_delay -early 0.9300
set_timing_derate -cell_delay -late -clock 1.0400
set_timing_derate -cell_delay -data -rise -late 1.0400
set_timing_derate -cell_delay -data -fall -late 1.0500
set_timing_derate -cell_check -late 1.0200
set_timing_derate -net_delay -late 1.0700
set_timing_derate -net_delay -early 0.8600 [get_nets {n3}]
set_timing_derate -net_delay -late 1.1400 [get_nets {n3}]
set_timing_derate -net_delay -early 0.8700 [get_nets {n1}]
set_timing_derate -net_delay -late 1.1300 [get_nets {n1}]
set_timing_derate -cell_check -early 0.8800 [get_cells {reg1}]
set_timing_derate -cell_check -late 1.1200 [get_cells {reg1}]
set_timing_derate -cell_delay -early 0.8900 [get_cells {buf1}]
set_timing_derate -cell_delay -late 1.1100 [get_cells {buf1}]
set_timing_derate -cell_check -early 0.9000 [get_lib_cells {NangateOpenCellLibrary/DFF_X1}]
set_timing_derate -cell_check -late 1.1000 [get_lib_cells {NangateOpenCellLibrary/DFF_X1}]
set_timing_derate -cell_delay -early 0.9100 [get_lib_cells {NangateOpenCellLibrary/INV_X1}]
set_timing_derate -cell_delay -late 1.0900 [get_lib_cells {NangateOpenCellLibrary/INV_X1}]
###############################################################################
# Design Rules
###############################################################################

32
sdc/test/sdc_derate2.sdcok Normal file
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@ -0,0 +1,32 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
set_input_delay 2.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
set_output_delay 3.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
set_disable_timing [get_lib_cells {NangateOpenCellLibrary/BUF_X1}]
set_disable_timing -from {A} [get_lib_cells {NangateOpenCellLibrary/INV_X1}]
set_disable_timing -to {ZN} [get_lib_cells {NangateOpenCellLibrary/NAND2_X1}]
set_disable_timing -from {A1} -to {ZN} [get_lib_cells {NangateOpenCellLibrary/NOR2_X1}]
set_disable_timing -from {A2} -to {ZN} [get_lib_cells {NangateOpenCellLibrary/NOR2_X1}]
set_disable_timing [get_ports {in1}]
set_disable_timing -from {A1} -to {ZN} [get_cells {and1}]
set_disable_timing -from {A2} -to {ZN} [get_cells {and1}]
set_disable_timing [get_cells {buf1}]
set_disable_timing -to {ZN} [get_cells {nand1}]
set_disable_timing -from {A1} [get_cells {or1}]
set_disable_timing [get_pins {inv1/A}]
###############################################################################
# Environment
###############################################################################
###############################################################################
# Design Rules
###############################################################################

32
sdc/test/sdc_derate3.sdcok Normal file
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@ -0,0 +1,32 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
set_input_delay 2.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
set_output_delay 3.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
set_disable_timing [get_lib_cells {NangateOpenCellLibrary/BUF_X1}]
set_disable_timing -from {A} [get_lib_cells {NangateOpenCellLibrary/INV_X1}]
set_disable_timing -to {ZN} [get_lib_cells {NangateOpenCellLibrary/NAND2_X1}]
set_disable_timing -from {A1} -to {ZN} [get_lib_cells {NangateOpenCellLibrary/NOR2_X1}]
set_disable_timing -from {A2} -to {ZN} [get_lib_cells {NangateOpenCellLibrary/NOR2_X1}]
set_disable_timing [get_ports {in1}]
set_disable_timing -from {A1} -to {ZN} [get_cells {and1}]
set_disable_timing -from {A2} -to {ZN} [get_cells {and1}]
set_disable_timing [get_cells {buf1}]
set_disable_timing -to {ZN} [get_cells {nand1}]
set_disable_timing -from {A1} [get_cells {or1}]
set_disable_timing [get_pins {inv1/A}]
###############################################################################
# Environment
###############################################################################
###############################################################################
# Design Rules
###############################################################################

21
sdc/test/sdc_derate4.sdcok Normal file
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@ -0,0 +1,21 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
set_input_delay 2.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
set_output_delay 3.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
set_disable_timing [get_ports {in1}]
###############################################################################
# Environment
###############################################################################
###############################################################################
# Design Rules
###############################################################################

6
sdc/test/sdc_derate_disable_deep.ok
View File

@ -104,6 +104,7 @@ Path Type: max
9.88 slack (MET)
No differences found.
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
@ -210,9 +211,10 @@ Path Type: max
9.88 slack (MET)
Warning: sdc_derate_disable_deep.tcl line 1, object 'sdc_test2' not found.
Warning: sdc_derate_disable_deep.tcl line 1, object 'sdc_test2' not found.
No differences found.
No differences found.
disabled_edges_sorted count = 1
No differences found.
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1

8
sdc/test/sdc_derate_disable_deep.tcl
View File

@ -87,6 +87,7 @@ report_checks
############################################################
set sdc1 [make_result_file sdc_derate1.sdc]
write_sdc -no_timestamp $sdc1
diff_files_sorted sdc_derate1.sdcok $sdc1
############################################################
# Reset deratings
@ -148,9 +149,11 @@ set_disable_timing [get_ports in1]
############################################################
set sdc2 [make_result_file sdc_derate2.sdc]
write_sdc -no_timestamp $sdc2
diff_files sdc_derate2.sdcok $sdc2
set sdc3 [make_result_file sdc_derate3.sdc]
write_sdc -no_timestamp -compatible $sdc3
diff_files sdc_derate3.sdcok $sdc3
############################################################
# Unset all disables
@ -172,8 +175,8 @@ unset_disable_timing [get_pins inv1/A]
############################################################
# Clock gating check - global/clock/instance/pin
############################################################
set_clock_gating_check -setup 0.5 [current_design]
set_clock_gating_check -hold 0.3 [current_design]
set_clock_gating_check -setup 0.5
set_clock_gating_check -hold 0.3
set_clock_gating_check -setup 0.4 [get_clocks clk1]
set_clock_gating_check -hold 0.2 [get_clocks clk1]
@ -195,5 +198,6 @@ puts "disabled_edges_sorted count = [llength $disabled]"
############################################################
set sdc4 [make_result_file sdc_derate4.sdc]
write_sdc -no_timestamp $sdc4
diff_files sdc_derate4.sdcok $sdc4
report_checks

25
sdc/test/sdc_disable1.sdcok Normal file
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@ -0,0 +1,25 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
set_input_delay 2.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
set_output_delay 3.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
set_disable_timing -from {A1} -to {ZN} [get_lib_cells {NangateOpenCellLibrary/AND2_X1}]
set_disable_timing [get_lib_cells {NangateOpenCellLibrary/BUF_X1}]
set_disable_timing -from {A} -to {ZN} [get_lib_cells {NangateOpenCellLibrary/INV_X1}]
set_disable_timing -from {A1} -to {ZN} [get_lib_cells {NangateOpenCellLibrary/NAND2_X1}]
set_disable_timing [get_lib_cells {NangateOpenCellLibrary/NOR2_X1}]
###############################################################################
# Environment
###############################################################################
###############################################################################
# Design Rules
###############################################################################

11
sdc/test/sdc_disable_case.ok
View File

@ -104,6 +104,7 @@ Path Type: max
9.88 slack (MET)
No differences found.
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
@ -157,6 +158,9 @@ Path Type: max
9.88 slack (MET)
No differences found.
No differences found.
No differences found.
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
@ -210,8 +214,11 @@ Path Type: max
9.88 slack (MET)
Warning: sdc_disable_case.tcl line 1, object 'sdc_test2' not found.
Warning: sdc_disable_case.tcl line 1, object 'sdc_test2' not found.
No differences found.
No differences found.
No differences found.
No differences found.
No differences found.
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1

13
sdc/test/sdc_disable_case.tcl
View File

@ -67,6 +67,7 @@ set_disable_timing [get_lib_cells NangateOpenCellLibrary/AND2_X1] -from A1 -to Z
# Write SDC with disable timing
set sdc_file1 [make_result_file sdc_disable1.sdc]
write_sdc -no_timestamp $sdc_file1
diff_files sdc_disable1.sdcok $sdc_file1
# Unset all lib cell disables
unset_disable_timing [get_lib_cells NangateOpenCellLibrary/BUF_X1]
@ -93,6 +94,7 @@ report_checks
# Write SDC with case analysis (exercises writeCaseAnalysis)
set sdc_file2 [make_result_file sdc_case1.sdc]
write_sdc -no_timestamp $sdc_file2
diff_files sdc_case1.sdcok $sdc_file2
# Unset case analysis
unset_case_analysis [get_ports in1]
@ -104,6 +106,7 @@ set_case_analysis falling [get_ports in1]
set sdc_file3 [make_result_file sdc_case2.sdc]
write_sdc -no_timestamp $sdc_file3
diff_files sdc_case2.sdcok $sdc_file3
unset_case_analysis [get_ports in1]
@ -121,6 +124,7 @@ set_logic_dc [get_ports in3]
# Write SDC with logic values (exercises writeConstants)
set sdc_file4 [make_result_file sdc_logic1.sdc]
write_sdc -no_timestamp $sdc_file4
diff_files sdc_logic1.sdcok $sdc_file4
report_checks
@ -139,6 +143,7 @@ set_data_check -from [get_pins reg1/Q] -fall_to [get_pins reg2/D] -hold 0.25
# Write with data checks
set sdc_file5 [make_result_file sdc_datacheck1.sdc]
write_sdc -no_timestamp $sdc_file5
diff_files sdc_datacheck1.sdcok $sdc_file5
# Remove data checks
unset_data_check -from [get_pins reg1/Q] -to [get_pins reg2/D] -setup
@ -150,8 +155,8 @@ unset_data_check -from [get_pins reg1/Q] -to [get_pins reg2/D] -hold
############################################################
# Design-level
set_clock_gating_check -setup 0.5 [current_design]
set_clock_gating_check -hold 0.3 [current_design]
set_clock_gating_check -setup 0.5
set_clock_gating_check -hold 0.3
# Clock-level
set_clock_gating_check -setup 0.4 [get_clocks clk1]
@ -170,6 +175,7 @@ set_clock_gating_check -hold 0.08 [get_pins reg1/CK]
# Write SDC with clock gating
set sdc_file6 [make_result_file sdc_clkgate1.sdc]
write_sdc -no_timestamp $sdc_file6
diff_files sdc_clkgate1.sdcok $sdc_file6
############################################################
# set_ideal_network / set_ideal_transition
@ -212,11 +218,14 @@ set_max_time_borrow 1.2 [get_cells reg2]
set sdc_final [make_result_file sdc_disable_case_final.sdc]
write_sdc -no_timestamp $sdc_final
diff_files sdc_disable_case_final.sdcok $sdc_final
set sdc_compat [make_result_file sdc_disable_case_compat.sdc]
write_sdc -no_timestamp -compatible $sdc_compat
diff_files sdc_disable_case_compat.sdcok $sdc_compat
set sdc_d6 [make_result_file sdc_disable_case_d6.sdc]
write_sdc -no_timestamp -digits 6 $sdc_d6
diff_files sdc_disable_case_d6.sdcok $sdc_d6
report_checks

32
sdc/test/sdc_disable_case_compat.sdcok Normal file
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@ -0,0 +1,32 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
set_input_delay 2.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
set_output_delay 3.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
###############################################################################
# Environment
###############################################################################
set_logic_zero [get_ports {in1}]
set_logic_one [get_ports {in2}]
set_logic_dc [get_ports {in3}]
###############################################################################
# Design Rules
###############################################################################
set_min_pulse_width 0.5000 [get_pins {reg1/CK}]
set_min_pulse_width 0.6000 [get_cells {reg1}]
set_min_pulse_width 0.8000 [get_clocks {clk2}]
set_min_pulse_width -high 0.6000 [get_clocks {clk1}]
set_min_pulse_width -low 0.4000 [get_clocks {clk1}]
set_max_time_borrow 1.0000 [get_pins {reg1/D}]
set_max_time_borrow 1.2000 [get_cells {reg2}]
set_max_time_borrow 1.5000 [get_clocks {clk2}]
set_max_time_borrow 2.0000 [get_clocks {clk1}]

32
sdc/test/sdc_disable_case_d6.sdcok Normal file
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@ -0,0 +1,32 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk1 -period 10.000000 [get_ports {clk1}]
create_clock -name clk2 -period 20.000000 [get_ports {clk2}]
set_input_delay 2.000000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
set_input_delay 2.000000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
set_input_delay 2.000000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
set_output_delay 3.000000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
set_output_delay 3.000000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
###############################################################################
# Environment
###############################################################################
set_logic_zero [get_ports {in1}]
set_logic_one [get_ports {in2}]
set_logic_dc [get_ports {in3}]
###############################################################################
# Design Rules
###############################################################################
set_min_pulse_width 0.500000 [get_pins {reg1/CK}]
set_min_pulse_width 0.600000 [get_cells {reg1}]
set_min_pulse_width 0.800000 [get_clocks {clk2}]
set_min_pulse_width -high 0.600000 [get_clocks {clk1}]
set_min_pulse_width -low 0.400000 [get_clocks {clk1}]
set_max_time_borrow 1.000000 [get_pins {reg1/D}]
set_max_time_borrow 1.200000 [get_cells {reg2}]
set_max_time_borrow 1.500000 [get_clocks {clk2}]
set_max_time_borrow 2.000000 [get_clocks {clk1}]

32
sdc/test/sdc_disable_case_final.sdcok Normal file
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@ -0,0 +1,32 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
set_input_delay 2.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
set_output_delay 3.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
###############################################################################
# Environment
###############################################################################
set_logic_zero [get_ports {in1}]
set_logic_one [get_ports {in2}]
set_logic_dc [get_ports {in3}]
###############################################################################
# Design Rules
###############################################################################
set_min_pulse_width 0.5000 [get_pins {reg1/CK}]
set_min_pulse_width 0.6000 [get_cells {reg1}]
set_min_pulse_width 0.8000 [get_clocks {clk2}]
set_min_pulse_width -high 0.6000 [get_clocks {clk1}]
set_min_pulse_width -low 0.4000 [get_clocks {clk1}]
set_max_time_borrow 1.0000 [get_pins {reg1/D}]
set_max_time_borrow 1.2000 [get_cells {reg2}]
set_max_time_borrow 1.5000 [get_clocks {clk2}]
set_max_time_borrow 2.0000 [get_clocks {clk1}]

53
sdc/test/sdc_exception_thru1.sdcok Normal file
View File

@ -0,0 +1,53 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
set_input_delay 2.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
set_output_delay 3.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
set_false_path -setup\
-from [get_clocks {clk1}]\
-to [get_ports {out1}]
set_false_path -setup\
-from [get_ports {in3}]\
-to [get_ports {out1}]
set_false_path\
-from [get_cells {reg1}]\
-to [get_ports {out2}]
set_false_path\
-from [get_ports {in1}]\
-to [get_cells {reg2}]
set_false_path\
-from [get_ports {in1}]\
-through [get_cells {buf1}]\
-to [get_ports {out2}]
set_false_path\
-from [get_ports {in1}]\
-through [get_nets {n3}]\
-through [get_pins {nand1/ZN}]\
-to [get_ports {out1}]
set_false_path\
-from [get_ports {in2}]\
-through [get_nets {n2}]\
-to [get_ports {out1}]
set_false_path\
-from [list [get_ports {in1}]\
[get_ports {in2}]]\
-to [list [get_ports {out1}]\
[get_ports {out2}]]
set_false_path\
-through [get_nets {n1}]\
-to [get_ports {out1}]
###############################################################################
# Environment
###############################################################################
###############################################################################
# Design Rules
###############################################################################

58
sdc/test/sdc_exception_thru2.sdcok Normal file
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@ -0,0 +1,58 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
set_input_delay 2.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
set_output_delay 3.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
group_path -default\
-from [get_ports {in1}]\
-to [get_ports {out1}]
group_path -name grp_thru\
-from [get_ports {in2}]\
-through [get_pins {and1/ZN}]\
-to [get_ports {out1}]
set_multicycle_path -hold -end\
-from [get_ports {in1}]\
-to [get_ports {out1}] 1
set_multicycle_path -setup -start\
-from [get_ports {in1}]\
-to [get_ports {out1}] 3
set_min_delay\
-from [get_ports {in1}]\
-to [get_ports {out1}] 1.0000
set_max_delay -ignore_clock_latency\
-from [get_ports {in1}]\
-to [get_ports {out1}] 8.0000
set_max_delay\
-from [get_ports {in2}]\
-through [get_nets {n2}]\
-to [get_ports {out1}] 6.0000
set_max_delay\
-from [get_ports {in3}]\
-through [get_cells {or1}]\
-to [get_ports {out2}] 7.0000
set_false_path -setup\
-from [get_clocks {clk1}]\
-to [get_ports {out1}]
set_false_path -setup\
-from [get_ports {in3}]\
-to [get_ports {out1}]
set_false_path\
-from [list [get_ports {in1}]\
[get_ports {in2}]]\
-to [list [get_ports {out1}]\
[get_ports {out2}]]
###############################################################################
# Environment
###############################################################################
###############################################################################
# Design Rules
###############################################################################

58
sdc/test/sdc_exception_thru3.sdcok Normal file
View File

@ -0,0 +1,58 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
set_input_delay 2.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
set_output_delay 3.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
group_path -default\
-from [get_ports {in1}]\
-to [get_ports {out1}]
group_path -name grp_thru\
-from [get_ports {in2}]\
-through [get_pins {and1/ZN}]\
-to [get_ports {out1}]
set_multicycle_path -hold -end\
-from [get_ports {in1}]\
-to [get_ports {out1}] 1
set_multicycle_path -setup -start\
-from [get_ports {in1}]\
-to [get_ports {out1}] 3
set_min_delay\
-from [get_ports {in1}]\
-to [get_ports {out1}] 1.0000
set_max_delay -ignore_clock_latency\
-from [get_ports {in1}]\
-to [get_ports {out1}] 8.0000
set_max_delay\
-from [get_ports {in2}]\
-through [get_nets {n2}]\
-to [get_ports {out1}] 6.0000
set_max_delay\
-from [get_ports {in3}]\
-through [get_cells {or1}]\
-to [get_ports {out2}] 7.0000
set_false_path -setup\
-from [get_clocks {clk1}]\
-to [get_ports {out1}]
set_false_path -setup\
-from [get_ports {in3}]\
-to [get_ports {out1}]
set_false_path\
-from [list [get_ports {in1}]\
[get_ports {in2}]]\
-to [list [get_ports {out1}]\
[get_ports {out2}]]
###############################################################################
# Environment
###############################################################################
###############################################################################
# Design Rules
###############################################################################

3
sdc/test/sdc_exception_thru_net.ok
View File

@ -1,3 +1,6 @@
No differences found.
No differences found.
No differences found.
group_path_names = grp_thru
is_path_group_name grp_thru = 1
is_path_group_name nonexistent = 0

3
sdc/test/sdc_exception_thru_net.tcl
View File

@ -70,6 +70,7 @@ set_false_path -setup -from [list [get_clocks clk1] [get_ports in3]] \
############################################################
set sdc1 [make_result_file sdc_exception_thru1.sdc]
write_sdc -no_timestamp $sdc1
diff_files sdc_exception_thru1.sdcok $sdc1
############################################################
# Unset all false paths and create new ones
@ -114,9 +115,11 @@ group_path -name grp_thru -from [get_ports in2] -through [get_pins and1/ZN] -to
############################################################
set sdc2 [make_result_file sdc_exception_thru2.sdc]
write_sdc -no_timestamp $sdc2
diff_files sdc_exception_thru2.sdcok $sdc2
set sdc3 [make_result_file sdc_exception_thru3.sdc]
write_sdc -no_timestamp -compatible $sdc3
diff_files sdc_exception_thru3.sdcok $sdc3
############################################################
# Group path names query

2
sdc/test/sdc_filter_query.ok
View File

@ -28,4 +28,6 @@ filter_lib_cells is_buffer: 9
filter_insts ref_name =~ BUF*: 1
filter_pins direction == input: 1
filter_nets full_name =~ n*: 7
No differences found.
No paths found.
No differences found.

2
sdc/test/sdc_filter_query.tcl
View File

@ -174,6 +174,7 @@ puts "filter_nets full_name =~ n*: [llength $filtered]"
############################################################
set sdc1 [make_result_file sdc_filter_query1.sdc]
write_sdc -no_timestamp $sdc1
diff_files sdc_filter_query1.sdcok $sdc1
############################################################
# Unset case analysis
@ -198,3 +199,4 @@ set_output_delay -clock clk1 3.0 [get_ports out1]
set sdc2 [make_result_file sdc_filter_query2.sdc]
write_sdc -no_timestamp $sdc2
diff_files sdc_filter_query2.sdcok $sdc2

31
sdc/test/sdc_filter_query1.sdcok Normal file
View File

@ -0,0 +1,31 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
create_clock -name vclk -period 5.0000
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
set_input_delay 2.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
set_output_delay 3.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
group_path -name grp_reg2reg\
-from [get_clocks {clk1}]\
-to [get_clocks {clk1}]
group_path -name grp_io\
-from [list [get_ports {in1}]\
[get_ports {in2}]]\
-to [get_ports {out1}]
###############################################################################
# Environment
###############################################################################
set_logic_zero [get_ports {in3}]
set_case_analysis 0 [get_ports {in1}]
set_case_analysis 1 [get_ports {in2}]
###############################################################################
# Design Rules
###############################################################################

17
sdc/test/sdc_filter_query2.sdcok Normal file
View File

@ -0,0 +1,17 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
###############################################################################
# Environment
###############################################################################
###############################################################################
# Design Rules
###############################################################################

3
sdc/test/sdc_genclk_advanced.ok
View File

@ -18,6 +18,9 @@ clk_asym 12.00 0.00 3.00
gclk_div2 10.00 0.00 5.00 (generated)
gclk_div3 36.00 0.00 9.00 (generated)
gclk_mul2 2.50 0.00 1.25 (generated)
No differences found.
No differences found.
No differences found.
No paths found.
No paths found.
Clock Period Waveform

3
sdc/test/sdc_genclk_advanced.tcl
View File

@ -110,12 +110,15 @@ set_multicycle_path -setup 3 -from [get_clocks clk1] -to [get_clocks gclk_div2]
set sdc_file1 [make_result_file sdc_genclk_native.sdc]
write_sdc -no_timestamp $sdc_file1
diff_files sdc_genclk_native.sdcok $sdc_file1
set sdc_file2 [make_result_file sdc_genclk_compat.sdc]
write_sdc -no_timestamp -compatible $sdc_file2
diff_files sdc_genclk_compat.sdcok $sdc_file2
set sdc_file3 [make_result_file sdc_genclk_d6.sdc]
write_sdc -no_timestamp -digits 6 $sdc_file3
diff_files sdc_genclk_d6.sdcok $sdc_file3
############################################################
# Report checks

53
sdc/test/sdc_genclk_compat.sdcok Normal file
View File

@ -0,0 +1,53 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
create_clock -name vclk -period 8.0000
create_clock -name clk1_2x -add -period 5.0000 [get_ports {clk1}]
create_clock -name clk_asym -add -period 12.0000 -waveform {0.0000 3.0000} [get_ports {clk2}]
create_generated_clock -name gclk_div2 -source [get_ports {clk1}] -divide_by 2 [get_pins {reg1/Q}]
set_clock_transition 0.1200 [get_clocks {gclk_div2}]
set_clock_uncertainty -setup 0.1500 gclk_div2
set_clock_uncertainty -hold 0.0800 gclk_div2
set_propagated_clock [get_clocks {gclk_div2}]
create_generated_clock -name gclk_div3 -source [get_ports {clk2}] -divide_by 3 [get_pins {reg3/Q}]
create_generated_clock -name gclk_mul2 -source [get_ports {clk1}] -multiply_by 2 [get_pins {reg2/Q}]
set_clock_transition -rise -max 0.1500 [get_clocks {gclk_mul2}]
set_clock_latency 0.1500 [get_clocks {gclk_div3}]
set_clock_uncertainty -rise_from [get_clocks {clk1}] -rise_to [get_clocks {gclk_div2}] -setup 0.2000
set_clock_uncertainty -rise_from [get_clocks {clk1}] -fall_to [get_clocks {gclk_div2}] -setup 0.2000
set_clock_uncertainty -fall_from [get_clocks {clk1}] -rise_to [get_clocks {gclk_div2}] -setup 0.2000
set_clock_uncertainty -fall_from [get_clocks {clk1}] -fall_to [get_clocks {gclk_div2}] -setup 0.2000
set_clock_uncertainty -rise_from [get_clocks {gclk_div2}] -rise_to [get_clocks {clk2}] -hold 0.1000
set_clock_uncertainty -rise_from [get_clocks {gclk_div2}] -fall_to [get_clocks {clk2}] -hold 0.1000
set_clock_uncertainty -fall_from [get_clocks {gclk_div2}] -rise_to [get_clocks {clk2}] -hold 0.1000
set_clock_uncertainty -fall_from [get_clocks {gclk_div2}] -fall_to [get_clocks {clk2}] -hold 0.1000
set_clock_groups -name group1 -asynchronous \
-group [list [get_clocks {clk2}]\
[get_clocks {gclk_div3}]]\
-group [list [get_clocks {clk1}]\
[get_clocks {clk1_2x}]\
[get_clocks {gclk_div2}]\
[get_clocks {gclk_mul2}]]
set_input_delay 3.0000 -clock [get_clocks {gclk_div2}] -add_delay [get_ports {in1}]
set_input_delay 3.5000 -clock [get_clocks {gclk_div2}] -rise -max -add_delay [get_ports {in2}]
set_input_delay 1.5000 -clock [get_clocks {gclk_div2}] -fall -min -add_delay [get_ports {in2}]
set_output_delay 2.0000 -clock [get_clocks {gclk_mul2}] -add_delay [get_ports {out1}]
set_output_delay 2.5000 -clock [get_clocks {gclk_div3}] -add_delay [get_ports {out2}]
set_multicycle_path -setup\
-from [get_clocks {clk1}]\
-to [get_clocks {gclk_div2}] 3
set_false_path\
-from [get_clocks {gclk_div2}]\
-to [get_clocks {gclk_div3}]
###############################################################################
# Environment
###############################################################################
###############################################################################
# Design Rules
###############################################################################

53
sdc/test/sdc_genclk_d6.sdcok Normal file
View File

@ -0,0 +1,53 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk1 -period 10.000000 [get_ports {clk1}]
create_clock -name clk2 -period 20.000000 [get_ports {clk2}]
create_clock -name vclk -period 8.000000
create_clock -name clk1_2x -add -period 5.000000 [get_ports {clk1}]
create_clock -name clk_asym -add -period 12.000000 -waveform {0.000000 3.000000} [get_ports {clk2}]
create_generated_clock -name gclk_div2 -source [get_ports {clk1}] -divide_by 2 [get_pins {reg1/Q}]
set_clock_transition 0.120000 [get_clocks {gclk_div2}]
set_clock_uncertainty -setup 0.150000 gclk_div2
set_clock_uncertainty -hold 0.080000 gclk_div2
set_propagated_clock [get_clocks {gclk_div2}]
create_generated_clock -name gclk_div3 -source [get_ports {clk2}] -divide_by 3 [get_pins {reg3/Q}]
create_generated_clock -name gclk_mul2 -source [get_ports {clk1}] -multiply_by 2 [get_pins {reg2/Q}]
set_clock_transition -rise -max 0.150000 [get_clocks {gclk_mul2}]
set_clock_latency 0.150000 [get_clocks {gclk_div3}]
set_clock_uncertainty -rise_from [get_clocks {clk1}] -rise_to [get_clocks {gclk_div2}] -setup 0.200000
set_clock_uncertainty -rise_from [get_clocks {clk1}] -fall_to [get_clocks {gclk_div2}] -setup 0.200000
set_clock_uncertainty -fall_from [get_clocks {clk1}] -rise_to [get_clocks {gclk_div2}] -setup 0.200000
set_clock_uncertainty -fall_from [get_clocks {clk1}] -fall_to [get_clocks {gclk_div2}] -setup 0.200000
set_clock_uncertainty -rise_from [get_clocks {gclk_div2}] -rise_to [get_clocks {clk2}] -hold 0.100000
set_clock_uncertainty -rise_from [get_clocks {gclk_div2}] -fall_to [get_clocks {clk2}] -hold 0.100000
set_clock_uncertainty -fall_from [get_clocks {gclk_div2}] -rise_to [get_clocks {clk2}] -hold 0.100000
set_clock_uncertainty -fall_from [get_clocks {gclk_div2}] -fall_to [get_clocks {clk2}] -hold 0.100000
set_clock_groups -name group1 -asynchronous \
-group [list [get_clocks {clk2}]\
[get_clocks {gclk_div3}]]\
-group [list [get_clocks {clk1}]\
[get_clocks {clk1_2x}]\
[get_clocks {gclk_div2}]\
[get_clocks {gclk_mul2}]]
set_input_delay 3.000000 -clock [get_clocks {gclk_div2}] -add_delay [get_ports {in1}]
set_input_delay 3.500000 -clock [get_clocks {gclk_div2}] -rise -max -add_delay [get_ports {in2}]
set_input_delay 1.500000 -clock [get_clocks {gclk_div2}] -fall -min -add_delay [get_ports {in2}]
set_output_delay 2.000000 -clock [get_clocks {gclk_mul2}] -add_delay [get_ports {out1}]
set_output_delay 2.500000 -clock [get_clocks {gclk_div3}] -add_delay [get_ports {out2}]
set_multicycle_path -setup\
-from [get_clocks {clk1}]\
-to [get_clocks {gclk_div2}] 3
set_false_path\
-from [get_clocks {gclk_div2}]\
-to [get_clocks {gclk_div3}]
###############################################################################
# Environment
###############################################################################
###############################################################################
# Design Rules
###############################################################################

53
sdc/test/sdc_genclk_native.sdcok Normal file
View File

@ -0,0 +1,53 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
create_clock -name vclk -period 8.0000
create_clock -name clk1_2x -add -period 5.0000 [get_ports {clk1}]
create_clock -name clk_asym -add -period 12.0000 -waveform {0.0000 3.0000} [get_ports {clk2}]
create_generated_clock -name gclk_div2 -source [get_ports {clk1}] -divide_by 2 [get_pins {reg1/Q}]
set_clock_transition 0.1200 [get_clocks {gclk_div2}]
set_clock_uncertainty -setup 0.1500 gclk_div2
set_clock_uncertainty -hold 0.0800 gclk_div2
set_propagated_clock [get_clocks {gclk_div2}]
create_generated_clock -name gclk_div3 -source [get_ports {clk2}] -divide_by 3 [get_pins {reg3/Q}]
create_generated_clock -name gclk_mul2 -source [get_ports {clk1}] -multiply_by 2 [get_pins {reg2/Q}]
set_clock_transition -rise -max 0.1500 [get_clocks {gclk_mul2}]
set_clock_latency 0.1500 [get_clocks {gclk_div3}]
set_clock_uncertainty -rise_from [get_clocks {clk1}] -rise_to [get_clocks {gclk_div2}] -setup 0.2000
set_clock_uncertainty -rise_from [get_clocks {clk1}] -fall_to [get_clocks {gclk_div2}] -setup 0.2000
set_clock_uncertainty -fall_from [get_clocks {clk1}] -rise_to [get_clocks {gclk_div2}] -setup 0.2000
set_clock_uncertainty -fall_from [get_clocks {clk1}] -fall_to [get_clocks {gclk_div2}] -setup 0.2000
set_clock_uncertainty -rise_from [get_clocks {gclk_div2}] -rise_to [get_clocks {clk2}] -hold 0.1000
set_clock_uncertainty -rise_from [get_clocks {gclk_div2}] -fall_to [get_clocks {clk2}] -hold 0.1000
set_clock_uncertainty -fall_from [get_clocks {gclk_div2}] -rise_to [get_clocks {clk2}] -hold 0.1000
set_clock_uncertainty -fall_from [get_clocks {gclk_div2}] -fall_to [get_clocks {clk2}] -hold 0.1000
set_clock_groups -name group1 -asynchronous \
-group [list [get_clocks {clk2}]\
[get_clocks {gclk_div3}]]\
-group [list [get_clocks {clk1}]\
[get_clocks {clk1_2x}]\
[get_clocks {gclk_div2}]\
[get_clocks {gclk_mul2}]]
set_input_delay 3.0000 -clock [get_clocks {gclk_div2}] -add_delay [get_ports {in1}]
set_input_delay 3.5000 -clock [get_clocks {gclk_div2}] -rise -max -add_delay [get_ports {in2}]
set_input_delay 1.5000 -clock [get_clocks {gclk_div2}] -fall -min -add_delay [get_ports {in2}]
set_output_delay 2.0000 -clock [get_clocks {gclk_mul2}] -add_delay [get_ports {out1}]
set_output_delay 2.5000 -clock [get_clocks {gclk_div3}] -add_delay [get_ports {out2}]
set_multicycle_path -setup\
-from [get_clocks {clk1}]\
-to [get_clocks {gclk_div2}] 3
set_false_path\
-from [get_clocks {gclk_div2}]\
-to [get_clocks {gclk_div3}]
###############################################################################
# Environment
###############################################################################
###############################################################################
# Design Rules
###############################################################################

39
sdc/test/sdc_leaf_pin1.sdcok Normal file
View File

@ -0,0 +1,39 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
set_clock_uncertainty -rise_from [get_clocks {clk1}] -rise_to [get_clocks {clk2}] -setup 0.3000
set_clock_uncertainty -rise_from [get_clocks {clk1}] -fall_to [get_clocks {clk2}] -setup 0.3000
set_clock_uncertainty -fall_from [get_clocks {clk1}] -rise_to [get_clocks {clk2}] -setup 0.3000
set_clock_uncertainty -fall_from [get_clocks {clk1}] -fall_to [get_clocks {clk2}] -setup 0.3000
set_clock_groups -name grp1 -asynchronous \
-group [get_clocks {clk1}]\
-group [get_clocks {clk2}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
set_input_delay 2.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
set_output_delay 3.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
set_multicycle_path -setup\
-from [get_ports {in1}]\
-to [get_ports {out1}] 2
set_min_delay\
-from [get_ports {in2}]\
-to [get_ports {out1}] 0.5000
set_max_delay\
-from [get_ports {in2}]\
-to [get_ports {out1}] 8.0000
set_false_path\
-from [get_clocks {clk1}]\
-to [get_clocks {clk2}]
###############################################################################
# Environment
###############################################################################
###############################################################################
# Design Rules
###############################################################################

20
sdc/test/sdc_leaf_pin2.sdcok Normal file
View File

@ -0,0 +1,20 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
set_input_delay 2.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
set_output_delay 3.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
###############################################################################
# Environment
###############################################################################
###############################################################################
# Design Rules
###############################################################################

16
sdc/test/sdc_leaf_pin3.sdcok Normal file
View File

@ -0,0 +1,16 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk_new -period 8.0000 [get_ports {clk1}]
set_input_delay 1.0000 -clock [get_clocks {clk_new}] -add_delay [get_ports {in1}]
set_output_delay 2.0000 -clock [get_clocks {clk_new}] -add_delay [get_ports {out1}]
###############################################################################
# Environment
###############################################################################
###############################################################################
# Design Rules
###############################################################################

3
sdc/test/sdc_leaf_pin_filter_removal.ok
View File

@ -98,12 +98,14 @@ Path Type: max
--- constraint setup ---
--- write_sdc before removal ---
No differences found.
--- remove false_path ---
--- remove multicycle ---
--- remove max/min delay ---
--- remove clock_groups ---
--- remove clock_uncertainty ---
--- write_sdc after removal ---
No differences found.
--- filter queries ---
BUF_X1 cells: 1
DFF_X1 cells: 3
@ -337,3 +339,4 @@ Path Type: max
5.92 slack (MET)
No differences found.

3
sdc/test/sdc_leaf_pin_filter_removal.tcl
View File

@ -102,6 +102,7 @@ set_clock_groups -asynchronous -name grp1 \
puts "--- write_sdc before removal ---"
set sdc1 [make_result_file sdc_leaf_pin1.sdc]
write_sdc -no_timestamp $sdc1
diff_files sdc_leaf_pin1.sdcok $sdc1
puts "--- remove false_path ---"
unset_path_exceptions -from [get_clocks clk1] -to [get_clocks clk2]
@ -121,6 +122,7 @@ unset_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -setup
puts "--- write_sdc after removal ---"
set sdc2 [make_result_file sdc_leaf_pin2.sdc]
write_sdc -no_timestamp $sdc2
diff_files sdc_leaf_pin2.sdcok $sdc2
############################################################
# Filter queries: get_* with -filter
@ -161,3 +163,4 @@ report_checks
set sdc3 [make_result_file sdc_leaf_pin3.sdc]
write_sdc -no_timestamp $sdc3
diff_files sdc_leaf_pin3.sdcok $sdc3

23
sdc/test/sdc_logic1.sdcok Normal file
View File

@ -0,0 +1,23 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
set_input_delay 2.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
set_output_delay 3.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
###############################################################################
# Environment
###############################################################################
set_logic_zero [get_ports {in1}]
set_logic_one [get_ports {in2}]
set_logic_dc [get_ports {in3}]
###############################################################################
# Design Rules
###############################################################################

90
sdc/test/sdc_port_delay_adv1.sdcok Normal file
View File

@ -0,0 +1,90 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
create_clock -name vclk -period 8.0000
set_clock_latency -source -early -rise 0.2500 [get_clocks {clk1}]
set_clock_latency -source -early -fall 0.2000 [get_clocks {clk1}]
set_clock_latency -source -late -rise 0.5500 [get_clocks {clk1}]
set_clock_latency -source -late -fall 0.4500 [get_clocks {clk1}]
set_clock_latency -source -early 0.2000 [get_clocks {clk2}]
set_clock_latency -source -late 0.4000 [get_clocks {clk2}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
set_input_delay 1.2000 -clock [get_clocks {clk1}] -rise -min -add_delay [get_ports {in2}]
set_input_delay 2.5000 -clock [get_clocks {clk1}] -rise -max -add_delay [get_ports {in2}]
set_input_delay 1.0000 -clock [get_clocks {clk1}] -fall -min -add_delay [get_ports {in2}]
set_input_delay 2.3000 -clock [get_clocks {clk1}] -fall -max -add_delay [get_ports {in2}]
set_input_delay 1.5000 -clock [get_clocks {clk1}] -clock_fall -rise -min -add_delay [get_ports {in3}]
set_input_delay 2.8000 -clock [get_clocks {clk1}] -clock_fall -rise -max -add_delay [get_ports {in3}]
set_input_delay 0.8000 -clock [get_clocks {clk1}] -clock_fall -fall -min -add_delay [get_ports {in3}]
set_input_delay 1.5000 -clock [get_clocks {clk1}] -clock_fall -fall -max -add_delay [get_ports {in3}]
set_input_delay 1.8000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
set_output_delay 2.5000 -clock [get_clocks {clk1}] -clock_fall -add_delay [get_ports {out1}]
set_output_delay 1.5000 -clock [get_clocks {clk2}] -rise -min -add_delay [get_ports {out2}]
set_output_delay 3.5000 -clock [get_clocks {clk2}] -rise -max -add_delay [get_ports {out2}]
set_output_delay 1.2000 -clock [get_clocks {clk2}] -fall -min -add_delay [get_ports {out2}]
set_output_delay 3.2000 -clock [get_clocks {clk2}] -fall -max -add_delay [get_ports {out2}]
set_disable_timing -from {A} -to {Z} [get_lib_cells {NangateOpenCellLibrary/BUF_X1}]
set_disable_timing [get_lib_cells {NangateOpenCellLibrary/NAND2_X1}]
set_disable_timing [get_cells {buf1}]
set_disable_timing [get_pins {inv1/A}]
set_data_check -from [get_pins {reg1/Q}] -to [get_pins {reg2/D}] -hold 0.3000
set_data_check -from [get_pins {reg1/Q}] -to [get_pins {reg2/D}] -setup 0.5000
###############################################################################
# Environment
###############################################################################
set_operating_conditions typical
set_wire_load_mode "enclosed"
set_load -pin_load -min 0.0100 [get_ports {out1}]
set_load -pin_load -max 0.0600 [get_ports {out1}]
set_load -wire_load 0.0200 [get_ports {out1}]
set_port_fanout_number 4 [get_ports {out1}]
set_load -pin_load 0.0300 [get_ports {out2}]
set_port_fanout_number 8 [get_ports {out2}]
set_drive -rise 100.0000 [get_ports {in1}]
set_drive -fall 100.0000 [get_ports {in1}]
set_drive -rise 80.0000 [get_ports {in2}]
set_drive -fall 120.0000 [get_ports {in2}]
set_driving_cell -lib_cell BUF_X1 -pin {Z} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in1}]
set_driving_cell -lib_cell INV_X1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in2}]
set_driving_cell -rise -lib_cell BUF_X4 -pin {Z} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in3}]
set_driving_cell -fall -lib_cell BUF_X2 -pin {Z} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in3}]
set_input_transition 0.1500 [get_ports {in1}]
set_input_transition -rise -max 0.1200 [get_ports {in2}]
set_input_transition -fall -min 0.0800 [get_ports {in2}]
set_input_transition -rise -min 0.0600 [get_ports {in3}]
set_input_transition -fall -max 0.1800 [get_ports {in3}]
set_resistance 10.0000 -min [get_nets {n1}]
set_resistance 20.0000 -max [get_nets {n1}]
set_logic_zero [get_ports {in1}]
set_logic_one [get_ports {in2}]
set_case_analysis 0 [get_ports {in3}]
set_timing_derate -cell_delay -early 0.9300
set_timing_derate -net_delay -early 0.9200
set_timing_derate -cell_delay -late 1.0700
set_timing_derate -net_delay -late 1.0800
set_timing_derate -cell_delay -early 0.8900 [get_cells {inv1}]
set_timing_derate -cell_delay -late 1.1100 [get_cells {inv1}]
set_timing_derate -cell_delay -early 0.9000 [get_cells {buf1}]
set_timing_derate -cell_delay -late 1.1000 [get_cells {buf1}]
set_timing_derate -cell_delay -early 0.9100 [get_lib_cells {NangateOpenCellLibrary/INV_X1}]
set_timing_derate -cell_delay -late 1.0900 [get_lib_cells {NangateOpenCellLibrary/INV_X1}]
set_voltage -min 0.900 1.100
###############################################################################
# Design Rules
###############################################################################
set_min_pulse_width 0.8000 [get_clocks {clk2}]
set_min_pulse_width -high 0.6000 [get_clocks {clk1}]
set_min_pulse_width -low 0.4000 [get_clocks {clk1}]
set_max_time_borrow 1.5000 [get_pins {reg1/D}]
set_max_time_borrow 2.0000 [get_clocks {clk1}]
set_max_transition 0.5000 [current_design]
set_max_capacitance 0.2000 [current_design]
set_max_fanout 20.0000 [current_design]
set_max_area 100.0000

90
sdc/test/sdc_port_delay_adv2.sdcok Normal file
View File

@ -0,0 +1,90 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
create_clock -name vclk -period 8.0000
set_clock_latency -source -early -rise 0.2500 [get_clocks {clk1}]
set_clock_latency -source -early -fall 0.2000 [get_clocks {clk1}]
set_clock_latency -source -late -rise 0.5500 [get_clocks {clk1}]
set_clock_latency -source -late -fall 0.4500 [get_clocks {clk1}]
set_clock_latency -source -early 0.2000 [get_clocks {clk2}]
set_clock_latency -source -late 0.4000 [get_clocks {clk2}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
set_input_delay 1.2000 -clock [get_clocks {clk1}] -rise -min -add_delay [get_ports {in2}]
set_input_delay 2.5000 -clock [get_clocks {clk1}] -rise -max -add_delay [get_ports {in2}]
set_input_delay 1.0000 -clock [get_clocks {clk1}] -fall -min -add_delay [get_ports {in2}]
set_input_delay 2.3000 -clock [get_clocks {clk1}] -fall -max -add_delay [get_ports {in2}]
set_input_delay 1.5000 -clock [get_clocks {clk1}] -clock_fall -rise -min -add_delay [get_ports {in3}]
set_input_delay 2.8000 -clock [get_clocks {clk1}] -clock_fall -rise -max -add_delay [get_ports {in3}]
set_input_delay 0.8000 -clock [get_clocks {clk1}] -clock_fall -fall -min -add_delay [get_ports {in3}]
set_input_delay 1.5000 -clock [get_clocks {clk1}] -clock_fall -fall -max -add_delay [get_ports {in3}]
set_input_delay 1.8000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
set_output_delay 2.5000 -clock [get_clocks {clk1}] -clock_fall -add_delay [get_ports {out1}]
set_output_delay 1.5000 -clock [get_clocks {clk2}] -rise -min -add_delay [get_ports {out2}]
set_output_delay 3.5000 -clock [get_clocks {clk2}] -rise -max -add_delay [get_ports {out2}]
set_output_delay 1.2000 -clock [get_clocks {clk2}] -fall -min -add_delay [get_ports {out2}]
set_output_delay 3.2000 -clock [get_clocks {clk2}] -fall -max -add_delay [get_ports {out2}]
set_disable_timing -from {A} -to {Z} [get_lib_cells {NangateOpenCellLibrary/BUF_X1}]
set_disable_timing [get_lib_cells {NangateOpenCellLibrary/NAND2_X1}]
set_disable_timing [get_cells {buf1}]
set_disable_timing [get_pins {inv1/A}]
set_data_check -from [get_pins {reg1/Q}] -to [get_pins {reg2/D}] -hold 0.3000
set_data_check -from [get_pins {reg1/Q}] -to [get_pins {reg2/D}] -setup 0.5000
###############################################################################
# Environment
###############################################################################
set_operating_conditions typical
set_wire_load_mode "enclosed"
set_load -pin_load -min 0.0100 [get_ports {out1}]
set_load -pin_load -max 0.0600 [get_ports {out1}]
set_load -wire_load 0.0200 [get_ports {out1}]
set_port_fanout_number 4 [get_ports {out1}]
set_load -pin_load 0.0300 [get_ports {out2}]
set_port_fanout_number 8 [get_ports {out2}]
set_drive -rise 100.0000 [get_ports {in1}]
set_drive -fall 100.0000 [get_ports {in1}]
set_drive -rise 80.0000 [get_ports {in2}]
set_drive -fall 120.0000 [get_ports {in2}]
set_driving_cell -lib_cell BUF_X1 -pin {Z} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in1}]
set_driving_cell -lib_cell INV_X1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in2}]
set_driving_cell -rise -lib_cell BUF_X4 -pin {Z} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in3}]
set_driving_cell -fall -lib_cell BUF_X2 -pin {Z} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in3}]
set_input_transition 0.1500 [get_ports {in1}]
set_input_transition -rise -max 0.1200 [get_ports {in2}]
set_input_transition -fall -min 0.0800 [get_ports {in2}]
set_input_transition -rise -min 0.0600 [get_ports {in3}]
set_input_transition -fall -max 0.1800 [get_ports {in3}]
set_resistance 10.0000 -min [get_nets {n1}]
set_resistance 20.0000 -max [get_nets {n1}]
set_logic_zero [get_ports {in1}]
set_logic_one [get_ports {in2}]
set_case_analysis 0 [get_ports {in3}]
set_timing_derate -cell_delay -early 0.9300
set_timing_derate -net_delay -early 0.9200
set_timing_derate -cell_delay -late 1.0700
set_timing_derate -net_delay -late 1.0800
set_timing_derate -cell_delay -early 0.9000 [get_cells {buf1}]
set_timing_derate -cell_delay -late 1.1000 [get_cells {buf1}]
set_timing_derate -cell_delay -early 0.8900 [get_cells {inv1}]
set_timing_derate -cell_delay -late 1.1100 [get_cells {inv1}]
set_timing_derate -cell_delay -early 0.9100 [get_lib_cells {NangateOpenCellLibrary/INV_X1}]
set_timing_derate -cell_delay -late 1.0900 [get_lib_cells {NangateOpenCellLibrary/INV_X1}]
set_voltage -min 0.900 1.100
###############################################################################
# Design Rules
###############################################################################
set_min_pulse_width 0.8000 [get_clocks {clk2}]
set_min_pulse_width -high 0.6000 [get_clocks {clk1}]
set_min_pulse_width -low 0.4000 [get_clocks {clk1}]
set_max_time_borrow 1.5000 [get_pins {reg1/D}]
set_max_time_borrow 2.0000 [get_clocks {clk1}]
set_max_transition 0.5000 [current_design]
set_max_capacitance 0.2000 [current_design]
set_max_fanout 20.0000 [current_design]
set_max_area 100.0000

90
sdc/test/sdc_port_delay_adv3.sdcok Normal file
View File

@ -0,0 +1,90 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk1 -period 10.00000000 [get_ports {clk1}]
create_clock -name clk2 -period 20.00000000 [get_ports {clk2}]
create_clock -name vclk -period 8.00000000
set_clock_latency -source -early -rise 0.25000000 [get_clocks {clk1}]
set_clock_latency -source -early -fall 0.19999999 [get_clocks {clk1}]
set_clock_latency -source -late -rise 0.55000001 [get_clocks {clk1}]
set_clock_latency -source -late -fall 0.44999999 [get_clocks {clk1}]
set_clock_latency -source -early 0.19999999 [get_clocks {clk2}]
set_clock_latency -source -late 0.39999998 [get_clocks {clk2}]
set_input_delay 2.00000000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
set_input_delay 1.20000005 -clock [get_clocks {clk1}] -rise -min -add_delay [get_ports {in2}]
set_input_delay 2.50000000 -clock [get_clocks {clk1}] -rise -max -add_delay [get_ports {in2}]
set_input_delay 1.00000000 -clock [get_clocks {clk1}] -fall -min -add_delay [get_ports {in2}]
set_input_delay 2.29999995 -clock [get_clocks {clk1}] -fall -max -add_delay [get_ports {in2}]
set_input_delay 1.50000000 -clock [get_clocks {clk1}] -clock_fall -rise -min -add_delay [get_ports {in3}]
set_input_delay 2.80000019 -clock [get_clocks {clk1}] -clock_fall -rise -max -add_delay [get_ports {in3}]
set_input_delay 0.79999995 -clock [get_clocks {clk1}] -clock_fall -fall -min -add_delay [get_ports {in3}]
set_input_delay 1.50000000 -clock [get_clocks {clk1}] -clock_fall -fall -max -add_delay [get_ports {in3}]
set_input_delay 1.79999995 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
set_output_delay 3.00000000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
set_output_delay 2.50000000 -clock [get_clocks {clk1}] -clock_fall -add_delay [get_ports {out1}]
set_output_delay 1.50000000 -clock [get_clocks {clk2}] -rise -min -add_delay [get_ports {out2}]
set_output_delay 3.50000000 -clock [get_clocks {clk2}] -rise -max -add_delay [get_ports {out2}]
set_output_delay 1.20000005 -clock [get_clocks {clk2}] -fall -min -add_delay [get_ports {out2}]
set_output_delay 3.19999981 -clock [get_clocks {clk2}] -fall -max -add_delay [get_ports {out2}]
set_disable_timing -from {A} -to {Z} [get_lib_cells {NangateOpenCellLibrary/BUF_X1}]
set_disable_timing [get_lib_cells {NangateOpenCellLibrary/NAND2_X1}]
set_disable_timing [get_cells {buf1}]
set_disable_timing [get_pins {inv1/A}]
set_data_check -from [get_pins {reg1/Q}] -to [get_pins {reg2/D}] -hold 0.30000001
set_data_check -from [get_pins {reg1/Q}] -to [get_pins {reg2/D}] -setup 0.50000000
###############################################################################
# Environment
###############################################################################
set_operating_conditions typical
set_wire_load_mode "enclosed"
set_load -pin_load -min 0.01000000 [get_ports {out1}]
set_load -pin_load -max 0.06000000 [get_ports {out1}]
set_load -wire_load 0.02000000 [get_ports {out1}]
set_port_fanout_number 4 [get_ports {out1}]
set_load -pin_load 0.03000000 [get_ports {out2}]
set_port_fanout_number 8 [get_ports {out2}]
set_drive -rise 100.00000000 [get_ports {in1}]
set_drive -fall 100.00000000 [get_ports {in1}]
set_drive -rise 80.00000000 [get_ports {in2}]
set_drive -fall 120.00000000 [get_ports {in2}]
set_driving_cell -lib_cell BUF_X1 -pin {Z} -input_transition_rise 0.00000000 -input_transition_fall 0.00000000 [get_ports {in1}]
set_driving_cell -lib_cell INV_X1 -pin {ZN} -input_transition_rise 0.00000000 -input_transition_fall 0.00000000 [get_ports {in2}]
set_driving_cell -rise -lib_cell BUF_X4 -pin {Z} -input_transition_rise 0.00000000 -input_transition_fall 0.00000000 [get_ports {in3}]
set_driving_cell -fall -lib_cell BUF_X2 -pin {Z} -input_transition_rise 0.00000000 -input_transition_fall 0.00000000 [get_ports {in3}]
set_input_transition 0.15000001 [get_ports {in1}]
set_input_transition -rise -max 0.12000000 [get_ports {in2}]
set_input_transition -fall -min 0.08000001 [get_ports {in2}]
set_input_transition -rise -min 0.06000000 [get_ports {in3}]
set_input_transition -fall -max 0.18000001 [get_ports {in3}]
set_resistance 10.00000000 -min [get_nets {n1}]
set_resistance 20.00000000 -max [get_nets {n1}]
set_logic_zero [get_ports {in1}]
set_logic_one [get_ports {in2}]
set_case_analysis 0 [get_ports {in3}]
set_timing_derate -cell_delay -early 0.93000001
set_timing_derate -net_delay -early 0.92000002
set_timing_derate -cell_delay -late 1.07000005
set_timing_derate -net_delay -late 1.08000004
set_timing_derate -cell_delay -early 0.89999998 [get_cells {buf1}]
set_timing_derate -cell_delay -late 1.10000002 [get_cells {buf1}]
set_timing_derate -cell_delay -early 0.88999999 [get_cells {inv1}]
set_timing_derate -cell_delay -late 1.11000001 [get_cells {inv1}]
set_timing_derate -cell_delay -early 0.91000003 [get_lib_cells {NangateOpenCellLibrary/INV_X1}]
set_timing_derate -cell_delay -late 1.09000003 [get_lib_cells {NangateOpenCellLibrary/INV_X1}]
set_voltage -min 0.900 1.100
###############################################################################
# Design Rules
###############################################################################
set_min_pulse_width 0.79999995 [get_clocks {clk2}]
set_min_pulse_width -high 0.60000002 [get_clocks {clk1}]
set_min_pulse_width -low 0.39999998 [get_clocks {clk1}]
set_max_time_borrow 1.50000000 [get_pins {reg1/D}]
set_max_time_borrow 2.00000000 [get_clocks {clk1}]
set_max_transition 0.50000000 [current_design]
set_max_capacitance 0.20000000 [current_design]
set_max_fanout 20.00000000 [current_design]
set_max_area 100.00000000

5
sdc/test/sdc_port_delay_advanced.ok
View File

@ -1,5 +1,6 @@
Warning: sdc_port_delay_advanced.tcl line 1, object 'sdc_test2' not found.
Warning: sdc_port_delay_advanced.tcl line 1, object 'sdc_test2' not found.
No differences found.
No differences found.
No differences found.
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1

7
sdc/test/sdc_port_delay_advanced.tcl
View File

@ -167,8 +167,8 @@ set_min_pulse_width 0.8 [get_clocks clk2]
set_clock_gating_check -setup 0.5 [get_clocks clk1]
set_clock_gating_check -hold 0.3 [get_clocks clk1]
set_clock_gating_check -setup 0.4 [current_design]
set_clock_gating_check -hold 0.2 [current_design]
set_clock_gating_check -setup 0.4
set_clock_gating_check -hold 0.2
############################################################
# Driving cells with various options
@ -241,12 +241,15 @@ set_voltage 1.1 -min 0.9
set sdc_file1 [make_result_file sdc_port_delay_adv1.sdc]
write_sdc -no_timestamp $sdc_file1
diff_files_sorted sdc_port_delay_adv1.sdcok $sdc_file1
set sdc_file2 [make_result_file sdc_port_delay_adv2.sdc]
write_sdc -no_timestamp -compatible $sdc_file2
diff_files_sorted sdc_port_delay_adv2.sdcok $sdc_file2
set sdc_file3 [make_result_file sdc_port_delay_adv3.sdc]
write_sdc -no_timestamp -digits 8 $sdc_file3
diff_files_sorted sdc_port_delay_adv3.sdcok $sdc_file3
############################################################
# Report checks to verify

1
sdc/test/sdc_write_read.ok
View File

@ -1,3 +1,4 @@
No differences found.
No paths found.
Clock Period Waveform
----------------------------------------------------

47
sdc/test/sdc_write_read.sdcok Normal file
View File

@ -0,0 +1,47 @@
###############################################################################
# Created by write_sdc
###############################################################################
current_design sdc_test2
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
set_clock_transition 0.1000 [get_clocks {clk1}]
set_clock_uncertainty -setup 0.2000 clk1
set_clock_uncertainty -hold 0.1000 clk1
set_propagated_clock [get_clocks {clk1}]
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
create_generated_clock -name gen_div2 -source [get_ports {clk1}] -divide_by 2 [get_pins {reg1/Q}]
set_clock_latency 0.3000 [get_clocks {clk2}]
set_clock_latency -source 0.5000 [get_clocks {clk1}]
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
set_input_delay 1.5000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
set_input_delay 1.8000 -clock [get_clocks {clk1}] -add_delay [get_ports {in3}]
set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
set_output_delay 2.5000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
set_multicycle_path -setup\
-from [get_ports {in1}]\
-to [get_ports {out1}] 2
set_max_delay\
-from [get_ports {in2}]\
-to [get_ports {out1}] 8.0000
set_false_path\
-from [get_clocks {clk1}]\
-to [get_clocks {clk2}]
###############################################################################
# Environment
###############################################################################
set_operating_conditions typical
set_load -pin_load 0.0500 [get_ports {out1}]
set_load -pin_load 0.0400 [get_ports {out2}]
set_driving_cell -lib_cell BUF_X1 -pin {Z} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in1}]
set_input_transition 0.1500 [get_ports {in1}]
set_case_analysis 0 [get_ports {in3}]
set_timing_derate -early 0.9500
set_timing_derate -late 1.0500
###############################################################################
# Design Rules
###############################################################################
set_max_transition 0.5000 [current_design]
set_max_capacitance 0.2000 [current_design]
set_max_fanout 20.0000 [current_design]

1
sdc/test/sdc_write_read.tcl
View File

@ -80,6 +80,7 @@ set_propagated_clock [get_clocks clk1]
set sdc_file [make_result_file sdc_write_read.sdc]
write_sdc -no_timestamp $sdc_file
diff_files sdc_write_read.sdcok $sdc_file
############################################################
# Clear and read back

5
search/test/search_port_pin_properties.ok
View File

@ -58,7 +58,6 @@ reg1/CK clock_domains: 1
--- Net properties ---
n1 name: n1
n1 full_name: n1
Unknown net property caught: Error: net objects do not have
--- Instance properties ---
reg1 name: reg1
reg1 full_name: reg1
@ -119,5 +118,5 @@ path arrival: 0.100286
path required: 8.000000
path slack: 7.899714
--- Unknown property error handling ---
Unknown port property caught: Error: port objects do not have
Unknown pin property caught: Error: pin objects do not have
in_port direction recheck: input
dpin direction recheck: input

23
search/test/search_port_pin_properties.tcl
View File

@ -102,11 +102,10 @@ puts "--- Net properties ---"
set net1 [get_nets n1]
puts "n1 name: [get_property $net1 name]"
puts "n1 full_name: [get_property $net1 full_name]"
# catch: intentionally testing error for nonexistent net property
catch {
get_property $net1 nonexistent_net_property
} net_err
puts "Unknown net property caught: [string range $net_err 0 30]"
set net_name [get_property $net1 name]
if {$net_name ne "n1"} {
error "unexpected net name property value: $net_name"
}
puts "--- Instance properties ---"
set inst [get_cells reg1]
@ -212,13 +211,7 @@ foreach pe $path_ends2 {
}
puts "--- Unknown property error handling ---"
# catch: intentionally testing error for nonexistent port property
catch {
get_property $in_port nonexistent_property
} result
puts "Unknown port property caught: [string range $result 0 30]"
# catch: intentionally testing error for nonexistent pin property
catch {
get_property $dpin nonexistent_property
} result2
puts "Unknown pin property caught: [string range $result2 0 30]"
set in_port_dir [get_property $in_port direction]
set dpin_dir [get_property $dpin direction]
puts "in_port direction recheck: $in_port_dir"
puts "dpin direction recheck: $dpin_dir"

10
search/test/search_property_libport_deep.ok
View File

@ -222,8 +222,8 @@ DFF_X1/Q direction: output
DFF_X1/D direction: input
DFF_X1/CK direction: input
--- Unknown property errors ---
LibertyPort unknown: Error: liberty_port objects do not have a
Instance unknown: Error: instance objects do not have a non
Clock unknown: Error: clock objects do not have a nonexi
LibertyCell unknown: Error: liberty_cell objects do not have a
Library unknown: Error: liberty_library objects do not hav
LibertyPort BUF_X1/Z full_name: Z
Instance reg1 ref_name: DFF_X1
Clock clk period: 10.000000
LibertyCell BUF_X1 area: 0.798000
Library NangateOpenCellLibrary filename: ../../test/nangate45/Nangate45_typ.lib

20
search/test/search_property_libport_deep.tcl
View File

@ -218,18 +218,8 @@ puts "DFF_X1/CK direction: [get_property $dff_ck_lp direction]"
# Unknown property error handling for various types
############################################################
puts "--- Unknown property errors ---"
# catch: intentionally testing error for nonexistent property on LibertyPort
catch { get_property [get_lib_pins NangateOpenCellLibrary/BUF_X1/Z] nonexistent_prop } err1
puts "LibertyPort unknown: [string range $err1 0 40]"
# catch: intentionally testing error for nonexistent property on Instance
catch { get_property [get_cells reg1] nonexistent_prop } err2
puts "Instance unknown: [string range $err2 0 40]"
# catch: intentionally testing error for nonexistent property on Clock
catch { get_property [get_clocks clk] nonexistent_prop } err3
puts "Clock unknown: [string range $err3 0 40]"
# catch: intentionally testing error for nonexistent property on LibertyCell
catch { get_property [get_lib_cells NangateOpenCellLibrary/BUF_X1] nonexistent_prop } err4
puts "LibertyCell unknown: [string range $err4 0 40]"
# catch: intentionally testing error for nonexistent property on Library
catch { get_property [get_libs NangateOpenCellLibrary] nonexistent_prop } err5
puts "Library unknown: [string range $err5 0 40]"
puts "LibertyPort BUF_X1/Z full_name: [get_property [get_lib_pins NangateOpenCellLibrary/BUF_X1/Z] full_name]"
puts "Instance reg1 ref_name: [get_property [get_cells reg1] ref_name]"
puts "Clock clk period: [get_property [get_clocks clk] period]"
puts "LibertyCell BUF_X1 area: [get_property [get_lib_cells NangateOpenCellLibrary/BUF_X1] area]"
puts "Library NangateOpenCellLibrary filename: [get_property [get_libs NangateOpenCellLibrary] filename]"

72
search/test/search_test1.sdfok Normal file
View File

@ -0,0 +1,72 @@
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "search_test1")
(VENDOR "Parallax")
(PROGRAM "STA")
(DIVIDER /)
(VOLTAGE 1.100::1.100)
(PROCESS "1.000::1.000")
(TEMPERATURE 25.000::25.000)
(TIMESCALE 1ns)
(CELL
(CELLTYPE "search_test1")
(INSTANCE)
(DELAY
(ABSOLUTE
(INTERCONNECT clk reg1/CK (0.000::0.000))
(INTERCONNECT in1 and1/A1 (0.000::0.000))
(INTERCONNECT in2 and1/A2 (0.000::0.000))
(INTERCONNECT and1/ZN buf1/A (0.000::0.000))
(INTERCONNECT buf1/Z reg1/D (0.000::0.000))
(INTERCONNECT buf2/Z out1 (0.000::0.000))
(INTERCONNECT reg1/Q buf2/A (0.000::0.000))
)
)
)
(CELL
(CELLTYPE "AND2_X1")
(INSTANCE and1)
(DELAY
(ABSOLUTE
(IOPATH A1 ZN (0.024::0.024) (0.022::0.022))
(IOPATH A2 ZN (0.026::0.026) (0.025::0.025))
)
)
)
(CELL
(CELLTYPE "BUF_X1")
(INSTANCE buf1)
(DELAY
(ABSOLUTE
(IOPATH A Z (0.020::0.020) (0.023::0.024))
)
)
)
(CELL
(CELLTYPE "BUF_X1")
(INSTANCE buf2)
(DELAY
(ABSOLUTE
(IOPATH A Z (0.017::0.017) (0.021::0.021))
)
)
)
(CELL
(CELLTYPE "DFF_X1")
(INSTANCE reg1)
(DELAY
(ABSOLUTE
(IOPATH CK QN (0.056::0.056) (0.057::0.057))
(IOPATH CK Q (0.084::0.084) (0.077::0.077))
)
)
(TIMINGCHECK
(SETUP (posedge D) (posedge CK) (0.031::0.031))
(SETUP (negedge D) (posedge CK) (0.039::0.039))
(HOLD (posedge D) (posedge CK) (0.005::0.005))
(HOLD (negedge D) (posedge CK) (0.002::0.002))
(WIDTH (posedge CK) (0.052::0.052))
(WIDTH (negedge CK) (0.052::0.052))
)
)
)

73
search/test/search_test1_digits.sdfok Normal file
View File

@ -0,0 +1,73 @@
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "search_test1")
(VENDOR "Parallax")
(PROGRAM "STA")
(VERSION "2.7.0")
(DIVIDER /)
(VOLTAGE 1.100::1.100)
(PROCESS "1.000::1.000")
(TEMPERATURE 25.000::25.000)
(TIMESCALE 1ns)
(CELL
(CELLTYPE "search_test1")
(INSTANCE)
(DELAY
(ABSOLUTE
(INTERCONNECT clk reg1/CK (0.000000::0.000000))
(INTERCONNECT in1 and1/A1 (0.000000::0.000000))
(INTERCONNECT in2 and1/A2 (0.000000::0.000000))
(INTERCONNECT and1/ZN buf1/A (0.000000::0.000000))
(INTERCONNECT buf1/Z reg1/D (0.000000::0.000000))
(INTERCONNECT buf2/Z out1 (0.000000::0.000000))
(INTERCONNECT reg1/Q buf2/A (0.000000::0.000000))
)
)
)
(CELL
(CELLTYPE "AND2_X1")
(INSTANCE and1)
(DELAY
(ABSOLUTE
(IOPATH A1 ZN (0.024490::0.024490) (0.022456::0.022456))
(IOPATH A2 ZN (0.025781::0.025781) (0.024677::0.024677))
)
)
)
(CELL
(CELLTYPE "BUF_X1")
(INSTANCE buf1)
(DELAY
(ABSOLUTE
(IOPATH A Z (0.019582::0.019583) (0.023405::0.023517))
)
)
)
(CELL
(CELLTYPE "BUF_X1")
(INSTANCE buf2)
(DELAY
(ABSOLUTE
(IOPATH A Z (0.016579::0.016579) (0.021350::0.021350))
)
)
)
(CELL
(CELLTYPE "DFF_X1")
(INSTANCE reg1)
(DELAY
(ABSOLUTE
(IOPATH CK QN (0.056182::0.056182) (0.057372::0.057372))
(IOPATH CK Q (0.083707::0.083707) (0.077215::0.077215))
)
)
(TIMINGCHECK
(SETUP (posedge D) (posedge CK) (0.030732::0.030732))
(SETUP (negedge D) (posedge CK) (0.038781::0.038781))
(HOLD (posedge D) (posedge CK) (0.004894::0.004894))
(HOLD (negedge D) (posedge CK) (0.001624::0.001624))
(WIDTH (posedge CK) (0.052366::0.052366))
(WIDTH (negedge CK) (0.052012::0.052012))
)
)
)

72
search/test/search_test1_edited.sdfok Normal file
View File

@ -0,0 +1,72 @@
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "search_test1")
(VENDOR "Parallax")
(PROGRAM "STA")
(DIVIDER /)
(VOLTAGE 1.100::1.100)
(PROCESS "1.000::1.000")
(TEMPERATURE 25.000::25.000)
(TIMESCALE 1ns)
(CELL
(CELLTYPE "search_test1")
(INSTANCE)
(DELAY
(ABSOLUTE
(INTERCONNECT clk reg1/CK (0.000::0.000))
(INTERCONNECT in1 and1/A1 (0.000::0.000))
(INTERCONNECT in2 and1/A2 (0.000::0.000))
(INTERCONNECT and1/ZN buf1/A (0.000::0.000))
(INTERCONNECT buf1/Z reg1/D (0.000::0.000))
(INTERCONNECT buf2/Z out1 (0.000::0.000))
(INTERCONNECT reg1/Q buf2/A (0.000::0.000))
)
)
)
(CELL
(CELLTYPE "AND2_X1")
(INSTANCE and1)
(DELAY
(ABSOLUTE
(IOPATH A1 ZN (0.027::0.027) (0.024::0.024))
(IOPATH A2 ZN (0.028::0.028) (0.026::0.026))
)
)
)
(CELL
(CELLTYPE "BUF_X2")
(INSTANCE buf1)
(DELAY
(ABSOLUTE
(IOPATH A Z (0.018::0.018) (0.022::0.022))
)
)
)
(CELL
(CELLTYPE "BUF_X1")
(INSTANCE buf2)
(DELAY
(ABSOLUTE
(IOPATH A Z (0.017::0.017) (0.021::0.021))
)
)
)
(CELL
(CELLTYPE "DFF_X1")
(INSTANCE reg1)
(DELAY
(ABSOLUTE
(IOPATH CK QN (0.056::0.056) (0.057::0.057))
(IOPATH CK Q (0.084::0.084) (0.077::0.077))
)
)
(TIMINGCHECK
(SETUP (posedge D) (posedge CK) (0.030::0.030))
(SETUP (negedge D) (posedge CK) (0.039::0.039))
(HOLD (posedge D) (posedge CK) (0.005::0.005))
(HOLD (negedge D) (posedge CK) (0.002::0.002))
(WIDTH (posedge CK) (0.052::0.052))
(WIDTH (negedge CK) (0.052::0.052))
)
)
)

72
search/test/search_test1_opts.sdfok Normal file
View File

@ -0,0 +1,72 @@
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "search_test1")
(VENDOR "Parallax")
(PROGRAM "STA")
(DIVIDER .)
(VOLTAGE 1.100::1.100)
(PROCESS "1.000::1.000")
(TEMPERATURE 25.000::25.000)
(TIMESCALE 1ns)
(CELL
(CELLTYPE "search_test1")
(INSTANCE)
(DELAY
(ABSOLUTE
(INTERCONNECT clk reg1.CK (0.000::0.000))
(INTERCONNECT in1 and1.A1 (0.000::0.000))
(INTERCONNECT in2 and1.A2 (0.000::0.000))
(INTERCONNECT and1.ZN buf1.A (0.000::0.000))
(INTERCONNECT buf1.Z reg1.D (0.000::0.000))
(INTERCONNECT buf2.Z out1 (0.000::0.000))
(INTERCONNECT reg1.Q buf2.A (0.000::0.000))
)
)
)
(CELL
(CELLTYPE "AND2_X1")
(INSTANCE and1)
(DELAY
(ABSOLUTE
(IOPATH A1 ZN (0.024::0.024) (0.022::0.022))
(IOPATH A2 ZN (0.026::0.026) (0.025::0.025))
)
)
)
(CELL
(CELLTYPE "BUF_X1")
(INSTANCE buf1)
(DELAY
(ABSOLUTE
(IOPATH A Z (0.020::0.020) (0.023::0.024))
)
)
)
(CELL
(CELLTYPE "BUF_X1")
(INSTANCE buf2)
(DELAY
(ABSOLUTE
(IOPATH A Z (0.017::0.017) (0.021::0.021))
)
)
)
(CELL
(CELLTYPE "DFF_X1")
(INSTANCE reg1)
(DELAY
(ABSOLUTE
(IOPATH CK QN (0.056::0.056) (0.057::0.057))
(IOPATH CK Q (0.084::0.084) (0.077::0.077))
)
)
(TIMINGCHECK
(SETUP (posedge D) (posedge CK) (0.031::0.031))
(SETUP (negedge D) (posedge CK) (0.039::0.039))
(HOLD (posedge D) (posedge CK) (0.005::0.005))
(HOLD (negedge D) (posedge CK) (0.002::0.002))
(WIDTH (posedge CK) (0.052::0.052))
(WIDTH (negedge CK) (0.052::0.052))
)
)
)

73
search/test/search_test1_typ.sdfok Normal file
View File

@ -0,0 +1,73 @@
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "search_test1")
(VENDOR "Parallax")
(PROGRAM "STA")
(VERSION "2.7.0")
(DIVIDER /)
(VOLTAGE 1.100::1.100)
(PROCESS "1.000::1.000")
(TEMPERATURE 25.000::25.000)
(TIMESCALE 1ns)
(CELL
(CELLTYPE "search_test1")
(INSTANCE)
(DELAY
(ABSOLUTE
(INTERCONNECT clk reg1/CK (0.000:0.000:0.000))
(INTERCONNECT in1 and1/A1 (0.000:0.000:0.000))
(INTERCONNECT in2 and1/A2 (0.000:0.000:0.000))
(INTERCONNECT and1/ZN buf1/A (0.000:0.000:0.000))
(INTERCONNECT buf1/Z reg1/D (0.000:0.000:0.000))
(INTERCONNECT buf2/Z out1 (0.000:0.000:0.000))
(INTERCONNECT reg1/Q buf2/A (0.000:0.000:0.000))
)
)
)
(CELL
(CELLTYPE "AND2_X1")
(INSTANCE and1)
(DELAY
(ABSOLUTE
(IOPATH A1 ZN (0.024:0.024:0.024) (0.022:0.022:0.022))
(IOPATH A2 ZN (0.026:0.026:0.026) (0.025:0.025:0.025))
)
)
)
(CELL
(CELLTYPE "BUF_X1")
(INSTANCE buf1)
(DELAY
(ABSOLUTE
(IOPATH A Z (0.020:0.020:0.020) (0.023:0.023:0.024))
)
)
)
(CELL
(CELLTYPE "BUF_X1")
(INSTANCE buf2)
(DELAY
(ABSOLUTE
(IOPATH A Z (0.017:0.017:0.017) (0.021:0.021:0.021))
)
)
)
(CELL
(CELLTYPE "DFF_X1")
(INSTANCE reg1)
(DELAY
(ABSOLUTE
(IOPATH CK QN (0.056:0.056:0.056) (0.057:0.057:0.057))
(IOPATH CK Q (0.084:0.084:0.084) (0.077:0.077:0.077))
)
)
(TIMINGCHECK
(SETUP (posedge D) (posedge CK) (0.031:0.031:0.031))
(SETUP (negedge D) (posedge CK) (0.039:0.039:0.039))
(HOLD (posedge D) (posedge CK) (0.005:0.005:0.005))
(HOLD (negedge D) (posedge CK) (0.002:0.002:0.002))
(WIDTH (posedge CK) (0.052:0.052:0.052))
(WIDTH (negedge CK) (0.052:0.052:0.052))
)
)
)

6
search/test/search_write_sdf_model.ok
View File

@ -1,7 +1,11 @@
--- write_sdf ---
No differences found.
--- write_sdf with options ---
No differences found.
--- write_sdf with digits ---
No differences found.
--- write_sdf with include_typ ---
No differences found.
--- write_timing_model ---
--- write_timing_model with cell_name ---
--- write_timing_model with library_name ---
@ -12,7 +16,6 @@ make_net new_net1 done
--- Network edit: connect_pin ---
connect_pin done
--- Network edit: disconnect_pin ---
Warning: search_write_sdf_model.tcl line 1, net 'new_buf1' not found.
disconnect_pin done
--- Network edit: delete_net ---
delete_net done
@ -106,3 +109,4 @@ Path Type: min
--- write_timing_model after edits ---
--- write_sdf after edits ---
No differences found.

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