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rm using std:: 

Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry 2026-03-02 12:13:13 -08:00
parent 94b8fd8f37
commit 741bf4d561
62 changed files with 794 additions and 958 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
app/Main.cc
View File

@ -39,7 +39,6 @@ namespace sta {
extern const char *tcl_inits[];
}
using std::string;
using sta::stringEq;
using sta::findCmdLineFlag;
using sta::Sta;
@ -129,7 +128,7 @@ staTclAppInit(int argc,
if (!findCmdLineFlag(argc, argv, "-no_init")) {
const char *home = getenv("HOME");
if (home) {
string init_path = home;
std::string init_path = home;
init_path += "/";
init_path += init_filename;
if (std::filesystem::is_regular_file(init_path.c_str()))

6
dcalc/ArcDcalcWaveforms.cc
View File

@ -35,8 +35,6 @@
namespace sta {
using std::make_shared;
Waveform
ArcDcalcWaveforms::inputWaveform(ArcDcalcArg &dcalc_arg,
const Scene *scene,
@ -68,8 +66,8 @@ ArcDcalcWaveforms::inputWaveform(ArcDcalcArg &dcalc_arg,
FloatSeq time_values;
for (float time : in_waveform.axis1()->values())
time_values.push_back(time + dcalc_arg.inputDelay());
TableAxisPtr time_axis = make_shared<TableAxis>(TableAxisVariable::time,
std::move(time_values));
TableAxisPtr time_axis = std::make_shared<TableAxis>(TableAxisVariable::time,
std::move(time_values));
// Scale the waveform from 0:vdd.
FloatSeq *scaled_values = new FloatSeq;
for (float value : *in_waveform.values()) {

46
dcalc/ArnoldiDelayCalc.cc
View File

@ -63,10 +63,6 @@ namespace sta {
// ra_get_r
// ra_get_s
using std::string;
using std::abs;
using std::vector;
struct delay_work;
struct delay_c;
@ -151,15 +147,15 @@ public:
const LoadPinIndexMap &load_pin_index_map,
const Scene *scene,
const MinMax *min_max) override;
string reportGateDelay(const Pin *drvr_pin,
const TimingArc *arc,
const Slew &in_slew,
float load_cap,
const Parasitic *parasitic,
const LoadPinIndexMap &load_pin_index_map,
const Scene *scene,
const MinMax *min_max,
int digits) override;
std::string reportGateDelay(const Pin *drvr_pin,
const TimingArc *arc,
const Slew &in_slew,
float load_cap,
const Parasitic *parasitic,
const LoadPinIndexMap &load_pin_index_map,
const Scene *scene,
const MinMax *min_max,
int digits) override;
void finishDrvrPin() override;
void delay_work_set_thresholds(delay_work *D,
double lo,
@ -240,7 +236,7 @@ private:
int pin_n_;
ArnoldiReduce *reduce_;
delay_work *delay_work_;
vector<rcmodel*> unsaved_parasitics_;
std::vector<rcmodel*> unsaved_parasitics_;
bool pocv_enabled_;
};
@ -469,7 +465,7 @@ ArnoldiDelayCalc::gateDelaySlew(const LibertyCell *drvr_cell,
return dcalc_result;
}
string
std::string
ArnoldiDelayCalc::reportGateDelay(const Pin *drvr_pin,
const TimingArc *arc,
const Slew &in_slew,
@ -690,7 +686,7 @@ tridiagEV(int n,double *din,double *ein,double *d,double **v)
e[0] = 0.0;
for (h=n-1;h>=1;h--) {
iter = 0;
while (abs(e[h])>1e-18) { // 1e-6ps
while (std::abs(e[h])>1e-18) { // 1e-6ps
m=0;
if (m != h) {
if (iter++ == 20)
@ -820,14 +816,14 @@ solve_t_bracketed(double s,int order,double *p,double *rr,
if (0.0<f2) return x2;
if (f1<0.0) return x1;
}
dxold = abs(x2-x1);
dxold = std::abs(x2-x1);
dx = dxold;
get_dv(rts,s,order,p,rr,&f,&df);
f -= val;
double flast = 0.0;
for (j=1;j<10;j++) {
if ((((rts-xh)*df-f)*((rts-xl)*df-f) >= 0.0)
|| (abs(2.0*f) > abs(dxold*df))) {
|| (std::abs(2.0*f) > std::abs(dxold*df))) {
dxold = dx;
dx = 0.5*(xh-xl);
if (flast*f >0.0) {
@ -851,7 +847,7 @@ solve_t_bracketed(double s,int order,double *p,double *rr,
return rts;
}
}
if (abs(dx) < xacc) {
if (std::abs(dx) < xacc) {
return rts;
}
get_dv(rts,s,order,p,rr,&f,&df); f -= val;
@ -860,7 +856,7 @@ solve_t_bracketed(double s,int order,double *p,double *rr,
else
xh = rts;
}
if (abs(f)<1e-6) // 1uV
if (std::abs(f)<1e-6) // 1uV
return rts;
return 0.5*(xl+xh);
}
@ -1266,28 +1262,28 @@ ArnoldiDelayCalc::ra_solve_for_s(delay_work *D,
f = (ptlo-pthi)/p - tlohi;
df = dlo-dhi;
s = s - f/df;
if (abs(f)<.001e-12) return; // .001ps
if (std::abs(f)<.001e-12) return; // .001ps
ra_solve_for_pt(p*s,vlo,&ptlo,&dlo);
ra_solve_for_pt(p*s,vhi,&pthi,&dhi);
f = (ptlo-pthi)/p - tlohi;
df = dlo-dhi;
s = s - f/df;
if (abs(f)<.001e-12) return; // .001ps
if (std::abs(f)<.001e-12) return; // .001ps
ra_solve_for_pt(p*s,vlo,&ptlo,&dlo);
ra_solve_for_pt(p*s,vhi,&pthi,&dhi);
f = (ptlo-pthi)/p - tlohi;
df = dlo-dhi;
s = s - f/df;
if (abs(f)<.001e-12) return; // .001ps
if (std::abs(f)<.001e-12) return; // .001ps
ra_solve_for_pt(p*s,vlo,&ptlo,&dlo);
ra_solve_for_pt(p*s,vhi,&pthi,&dhi);
f = (ptlo-pthi)/p - tlohi;
df = dlo-dhi;
s = s - f/df;
if (abs(f)<.001e-12) return; // .001ps
if (std::abs(f)<.001e-12) return; // .001ps
ra_solve_for_pt(p*s,vlo,&ptlo,&dlo);
ra_solve_for_pt(p*s,vhi,&pthi,&dhi);
@ -1295,7 +1291,7 @@ ArnoldiDelayCalc::ra_solve_for_s(delay_work *D,
df = dlo-dhi;
s = s - f/df;
if (abs(f)>.5e-12) // .5ps
if (std::abs(f)>.5e-12) // .5ps
debugPrint(debug_, "arnoldi", 1, "ra_solve_for_s p %g tlohi %s err %s",
p,
units_->timeUnit()->asString(tlohi),

4
dcalc/ArnoldiReduce.cc
View File

@ -38,8 +38,6 @@
namespace sta {
using std::string;
rcmodel::rcmodel() :
pinV(nullptr)
{
@ -621,7 +619,7 @@ ArnoldiReduce::makeRcmodelFromTs()
report_->reportLine(" d[%d] %s",
h,
units_->timeUnit()->asString(d[h]));
string line = stdstrPrint("U[%d]",h);
std::string line = stdstrPrint("U[%d]",h);
for (i=0;i<nterms;i++)
line += stdstrPrint(" %6.2e",U[h][i]);
report_->reportLineString(line);

30
dcalc/CcsCeffDelayCalc.cc
View File

@ -24,6 +24,8 @@
#include "CcsCeffDelayCalc.hh"
#include <cmath>
#include "Debug.hh"
#include "Units.hh"
#include "Liberty.hh"
@ -38,17 +40,11 @@
namespace sta {
using std::string;
// Implementaion based on:
// "Gate Delay Estimation with Library Compatible Current Source Models
// and Effective Capacitance", D. Garyfallou et al,
// IEEE Transactions on Very Large Scale Integration (VLSI) Systems, March 2021
using std::abs;
using std::exp;
using std::make_shared;
ArcDelayCalc *
makeCcsCeffDelayCalc(StaState *sta)
{
@ -144,7 +140,7 @@ CcsCeffDelayCalc::gateDelaySlew(const LibertyLibrary *drvr_library,
findCsmWaveform();
ref_time_ = output_waveforms_->referenceTime(in_slew_);
gate_delay = region_times_[region_vth_idx_] - ref_time_;
drvr_slew = abs(region_times_[region_vh_idx_] - region_times_[region_vl_idx_]);
drvr_slew = std::abs(region_times_[region_vh_idx_] - region_times_[region_vl_idx_]);
debugPrint(debug_, "ccs_dcalc", 2,
"gate_delay %s drvr_slew %s (initial)",
delayAsString(gate_delay, this),
@ -184,12 +180,12 @@ CcsCeffDelayCalc::gateDelaySlew(const LibertyLibrary *drvr_library,
}
findCsmWaveform();
gate_delay = region_times_[region_vth_idx_] - ref_time_;
drvr_slew = abs(region_times_[region_vh_idx_] - region_times_[region_vl_idx_]);
drvr_slew = std::abs(region_times_[region_vh_idx_] - region_times_[region_vl_idx_]);
debugPrint(debug_, "ccs_dcalc", 2,
"gate_delay %s drvr_slew %s",
delayAsString(gate_delay, this),
delayAsString(drvr_slew, this));
if (abs(delayAsFloat(drvr_slew) - prev_drvr_slew) < .01 * prev_drvr_slew)
if (std::abs(delayAsFloat(drvr_slew) - prev_drvr_slew) < .01 * prev_drvr_slew)
break;
prev_drvr_slew = delayAsFloat(drvr_slew);
}
@ -529,8 +525,8 @@ CcsCeffDelayCalc::drvrWaveform()
drvr_volts->push_back(v);
}
}
TableAxisPtr drvr_time_axis = make_shared<TableAxis>(TableAxisVariable::time,
std::move(*drvr_times));
TableAxisPtr drvr_time_axis = std::make_shared<TableAxis>(TableAxisVariable::time,
std::move(*drvr_times));
delete drvr_times;
Table drvr_table(drvr_volts, drvr_time_axis);
return drvr_table;
@ -561,8 +557,8 @@ CcsCeffDelayCalc::loadWaveform(const Pin *load_pin)
double v1 = (drvr_rf_ == RiseFall::rise()) ? v : vdd_ - v;
load_volts->push_back(v1);
}
TableAxisPtr load_time_axis = make_shared<TableAxis>(TableAxisVariable::time,
std::move(*load_times));
TableAxisPtr load_time_axis = std::make_shared<TableAxis>(TableAxisVariable::time,
std::move(*load_times));
delete load_times;
Table load_table(load_volts, load_time_axis);
return load_table;
@ -606,8 +602,8 @@ CcsCeffDelayCalc::drvrRampWaveform(const Pin *in_pin,
double v1 = (drvr_rf == RiseFall::rise()) ? v : vdd_ - v;
load_volts->push_back(v1);
}
TableAxisPtr load_time_axis = make_shared<TableAxis>(TableAxisVariable::time,
std::move(*load_times));
TableAxisPtr load_time_axis = std::make_shared<TableAxis>(TableAxisVariable::time,
std::move(*load_times));
delete load_times;
Table load_table(load_volts, load_time_axis);
return load_table;
@ -663,7 +659,7 @@ CcsCeffDelayCalc::makeWaveformPreamble(const Pin *in_pin,
////////////////////////////////////////////////////////////////
string
std::string
CcsCeffDelayCalc::reportGateDelay(const Pin *drvr_pin,
const TimingArc *arc,
const Slew &in_slew,
@ -680,7 +676,7 @@ CcsCeffDelayCalc::reportGateDelay(const Pin *drvr_pin,
pi_elmore = parasitics_->reduceToPiElmore(parasitic, drvr_pin_, rf,
scene, min_max);
}
string report = table_dcalc_->reportGateDelay(drvr_pin, arc, in_slew, load_cap,
std::string report = table_dcalc_->reportGateDelay(drvr_pin, arc, in_slew, load_cap,
pi_elmore, load_pin_index_map,
scene, min_max, digits);
parasitics_->deleteDrvrReducedParasitics(drvr_pin);

11
dcalc/DelayCalcBase.cc
View File

@ -38,9 +38,6 @@
namespace sta {
using std::string;
using std::log;
DelayCalcBase::DelayCalcBase(StaState *sta) :
ArcDelayCalc(sta)
{
@ -101,9 +98,9 @@ DelayCalcBase::dspfWireDelaySlew(const Pin *load_pin,
vh = load_library->slewUpperThreshold(rf);
slew_derate = load_library->slewDerateFromLibrary();
}
wire_delay = -elmore * log(1.0 - vth);
load_slew = drvr_slew + elmore * log((1.0 - vl) / (1.0 - vh)) / slew_derate;
load_slew = drvr_slew + elmore * log((1.0 - vl) / (1.0 - vh)) / slew_derate;
wire_delay = -elmore * std::log(1.0 - vth);
load_slew = drvr_slew + elmore * std::log((1.0 - vl) / (1.0 - vh)) / slew_derate;
load_slew = drvr_slew + elmore * std::log((1.0 - vl) / (1.0 - vh)) / slew_derate;
}
void
@ -173,7 +170,7 @@ DelayCalcBase::checkDelay(const Pin *check_pin,
return delay_zero;
}
string
std::string
DelayCalcBase::reportCheckDelay(const Pin *check_pin,
const TimingArc *arc,
const Slew &from_slew,

38
dcalc/DmpCeff.cc
View File

@ -32,8 +32,9 @@
#include "DmpCeff.hh"
#include <algorithm> // abs, min
#include <cmath> // sqrt, log
#include <algorithm>
#include <cmath>
#include <functional>
#include "Report.hh"
#include "Debug.hh"
@ -50,15 +51,6 @@
namespace sta {
using std::string;
using std::abs;
using std::min;
using std::max;
using std::sqrt;
using std::log;
using std::isnan;
using std::function;
// Tolerance (as a scale of value) for driver parameters (Ceff, delta t, t0).
static const double driver_param_tol = .01;
// Waveform threshold crossing time tolerance (1.0 = 100%).
@ -107,7 +99,7 @@ newtonRaphson(const int max_iter,
const int n,
const double x_tol,
// eval(state) is called to fill fvec and fjac.
function<void ()> eval,
std::function<void ()> eval,
// Temporaries supplied by caller.
double *fvec,
double **fjac,
@ -337,7 +329,7 @@ DmpAlg::findDriverParams(double ceff)
gateDelays(ceff, t_vth, t_vl, slew);
// Scale slew to 0-100%
double dt = slew / (vh_ - vl_);
double t0 = t_vth + log(1.0 - vth_) * rd_ * ceff - vth_ * dt;
double t0 = t_vth + std::log(1.0 - vth_) * rd_ * ceff - vth_ * dt;
x_[DmpParam::dt] = dt;
x_[DmpParam::t0] = t0;
newtonRaphson(100, x_, nr_order_, driver_param_tol,
@ -461,7 +453,7 @@ DmpAlg::showFvec()
void
DmpAlg::showJacobian()
{
string line = " ";
std::string line = " ";
for (int j = 0; j < nr_order_; j++)
line += stdstrPrint("%12s", dmp_param_index_strings[j]);
report_->reportLineString(line);
@ -894,7 +886,7 @@ DmpPi::init(const LibertyLibrary *drvr_library,
k0_ = 1.0 / (rd_ * c2_);
double a = rpi_ * rd_ * c1_ * c2_;
double b = rd_ * (c1_ + c2_) + rpi_ * c1_;
double sqrt_ = sqrt(b * b - 4 * a);
double sqrt_ = std::sqrt(b * b - 4 * a);
p1_ = (b + sqrt_) / (2 * a);
p2_ = (b - sqrt_) / (2 * a);
@ -1282,7 +1274,7 @@ newtonRaphson(const int max_iter,
double x[],
const int size,
const double x_tol,
function<void ()> eval,
std::function<void ()> eval,
// Temporaries supplied by caller.
double *fvec,
double **fjac,
@ -1300,7 +1292,7 @@ newtonRaphson(const int max_iter,
bool all_under_x_tol = true;
for (int i = 0; i < size; i++) {
if (abs(p[i]) > abs(x[i]) * x_tol)
if (std::abs(p[i]) > std::abs(x[i]) * x_tol)
all_under_x_tol = false;
x[i] += p[i];
}
@ -1334,7 +1326,7 @@ luDecomp(double **a,
for (int i = 0; i < size; i++) {
double big = 0.0;
for (int j = 0; j < size; j++) {
double temp = abs(a[i][j]);
double temp = std::abs(a[i][j]);
if (temp > big)
big = temp;
}
@ -1363,7 +1355,7 @@ luDecomp(double **a,
for (int k = 0; k < j; k++)
sum -= a[i][k] * a[k][j];
a[i][j] = sum;
double dum = scale[i] * abs(sum);
double dum = scale[i] * std::abs(sum);
if (dum >= big) {
big = dum;
imax = i;
@ -1507,7 +1499,7 @@ DmpCeffDelayCalc::gateDelay(const Pin *drvr_pin,
float in_slew1 = delayAsFloat(in_slew);
float c2, rpi, c1;
parasitics_->piModel(parasitic, c2, rpi, c1);
if (isnan(c2) || isnan(c1) || isnan(rpi))
if (std::isnan(c2) || std::isnan(c1) || std::isnan(rpi))
report_->error(1040, "parasitic Pi model has NaNs.");
setCeffAlgorithm(drvr_library, drvr_cell, pinPvt(drvr_pin, scene, min_max),
table_model, rf, in_slew1, c2, rpi, c1);
@ -1583,7 +1575,7 @@ DmpCeffDelayCalc::setCeffAlgorithm(const LibertyLibrary *drvr_library,
dmp_alg_->name());
}
string
std::string
DmpCeffDelayCalc::reportGateDelay(const Pin *drvr_pin,
const TimingArc *arc,
const Slew &in_slew,
@ -1598,7 +1590,7 @@ DmpCeffDelayCalc::reportGateDelay(const Pin *drvr_pin,
parasitic, load_pin_index_map, scene, min_max);
GateTableModel *model = arc->gateTableModel(scene, min_max);
float c_eff = 0.0;
string result;
std::string result;
const LibertyCell *drvr_cell = arc->to()->libertyCell();
const LibertyLibrary *drvr_library = drvr_cell->libertyLibrary();
const Units *units = drvr_library->units();
@ -1653,7 +1645,7 @@ gateModelRd(const LibertyCell *cell,
gate_model->gateDelay(pvt, in_slew, cap1, pocv_enabled, d1, s1);
gate_model->gateDelay(pvt, in_slew, cap2, pocv_enabled, d2, s2);
double vth = cell->libertyLibrary()->outputThreshold(rf);
float rd = -log(vth) * abs(delayAsFloat(d1) - delayAsFloat(d2)) / (cap2 - cap1);
float rd = -std::log(vth) * std::abs(delayAsFloat(d1) - delayAsFloat(d2)) / (cap2 - cap1);
return rd;
}

8
dcalc/FindRoot.cc
View File

@ -28,8 +28,6 @@
namespace sta {
using std::abs;
double
findRoot(FindRootFunc func,
double x1,
@ -76,7 +74,7 @@ findRoot(FindRootFunc func,
// Swap x1/x2 so func(x1) < 0.
std::swap(x1, x2);
double root = (x1 + x2) * 0.5;
double dx_prev = abs(x2 - x1);
double dx_prev = std::abs(x2 - x1);
double dx = dx_prev;
double y, dy;
func(root, y, dy);
@ -84,7 +82,7 @@ findRoot(FindRootFunc func,
// Newton/raphson out of range.
if ((((root - x2) * dy - y) * ((root - x1) * dy - y) > 0.0)
// Not decreasing fast enough.
|| (abs(2.0 * y) > abs(dx_prev * dy))) {
|| (std::abs(2.0 * y) > std::abs(dx_prev * dy))) {
// Bisect x1/x2 interval.
dx_prev = dx;
dx = (x2 - x1) * 0.5;
@ -95,7 +93,7 @@ findRoot(FindRootFunc func,
dx = y / dy;
root -= dx;
}
if (abs(dx) <= x_tol * abs(root)) {
if (std::abs(dx) <= x_tol * std::abs(root)) {
// Converged.
fail = false;
return root;

18
dcalc/GraphDelayCalc.cc
View File

@ -24,6 +24,8 @@
#include "GraphDelayCalc.hh"
#include <cmath>
#include <array>
#include <set>
#include "ContainerHelpers.hh"
@ -53,10 +55,6 @@
namespace sta {
using std::string;
using std::abs;
using std::array;
static const Slew default_slew = 0.0;
static bool
@ -941,7 +939,7 @@ GraphDelayCalc::findDriverDelays1(Vertex *drvr_vertex,
initSlew(drvr_vertex);
initWireDelays(drvr_vertex);
bool delay_changed = false;
array<bool, RiseFall::index_count> delay_exists = {false, false};
std::array<bool, RiseFall::index_count> delay_exists = {false, false};
VertexInEdgeIterator edge_iter(drvr_vertex, graph_);
while (edge_iter.hasNext()) {
Edge *edge = edge_iter.next();
@ -983,7 +981,7 @@ GraphDelayCalc::findLatchEdgeDelays(Edge *edge)
Instance *drvr_inst = network_->instance(drvr_pin);
debugPrint(debug_, "delay_calc", 2, "find latch D->Q %s",
sdc_network_->pathName(drvr_inst));
array<bool, RiseFall::index_count> delay_exists = {false, false};
std::array<bool, RiseFall::index_count> delay_exists = {false, false};
LoadPinIndexMap load_pin_index_map = makeLoadPinIndexMap(drvr_vertex);
bool delay_changed = findDriverEdgeDelays(drvr_vertex, nullptr, edge,
arc_delay_calc_, load_pin_index_map,
@ -999,7 +997,7 @@ GraphDelayCalc::findDriverEdgeDelays(Vertex *drvr_vertex,
ArcDelayCalc *arc_delay_calc,
LoadPinIndexMap &load_pin_index_map,
// Return value.
array<bool, RiseFall::index_count> &delay_exists)
std::array<bool, RiseFall::index_count> &delay_exists)
{
Vertex *from_vertex = edge->from(graph_);
const TimingArcSet *arc_set = edge->timingArcSet();
@ -1231,7 +1229,7 @@ GraphDelayCalc::annotateDelaySlew(Edge *edge,
float gate_delay1 = delayAsFloat(gate_delay);
float prev_gate_delay1 = delayAsFloat(prev_gate_delay);
if (prev_gate_delay1 == 0.0
|| (abs(gate_delay1 - prev_gate_delay1) / prev_gate_delay1
|| (std::abs(gate_delay1 - prev_gate_delay1) / prev_gate_delay1
> incremental_delay_tolerance_))
delay_changed = true;
graph_->setArcDelay(edge, arc, ap_index, gate_delay);
@ -1660,7 +1658,7 @@ GraphDelayCalc::checkEdgeClkSlew(const Vertex *from_vertex,
////////////////////////////////////////////////////////////////
string
std::string
GraphDelayCalc::reportDelayCalc(const Edge *edge,
const TimingArc *arc,
const Scene *scene,
@ -1673,7 +1671,7 @@ GraphDelayCalc::reportDelayCalc(const Edge *edge,
const TimingRole *role = arc->role();
const Instance *inst = network_->instance(to_pin);
const TimingArcSet *arc_set = edge->timingArcSet();
string result;
std::string result;
const RiseFall *from_rf = arc->fromEdge()->asRiseFall();
const RiseFall *to_rf = arc->toEdge()->asRiseFall();
if (from_rf && to_rf) {

7
dcalc/LumpedCapDelayCalc.cc
View File

@ -40,9 +40,6 @@
namespace sta {
using std::string;
using std::isnan;
ArcDelayCalc *
makeLumpedCapDelayCalc(StaState *sta)
{
@ -146,7 +143,7 @@ LumpedCapDelayCalc::gateDelay(const Pin *drvr_pin,
Slew drvr_slew;
float in_slew1 = delayAsFloat(in_slew);
// NaNs cause seg faults during table lookup.
if (isnan(load_cap) || isnan(delayAsFloat(in_slew)))
if (std::isnan(load_cap) || std::isnan(delayAsFloat(in_slew)))
report_->error(1350, "gate delay input variable is NaN");
model->gateDelay(pinPvt(drvr_pin, scene, min_max), in_slew1, load_cap,
variables_->pocvEnabled(),
@ -178,7 +175,7 @@ LumpedCapDelayCalc::makeResult(const LibertyLibrary *drvr_library,
return dcalc_result;
}
string
std::string
LumpedCapDelayCalc::reportGateDelay(const Pin *check_pin,
const TimingArc *arc,
const Slew &in_slew,

6
dcalc/ParallelDelayCalc.cc
View File

@ -34,8 +34,6 @@
namespace sta {
using std::vector;
ParallelDelayCalc::ParallelDelayCalc(StaState *sta):
DelayCalcBase(sta)
{
@ -71,8 +69,8 @@ ParallelDelayCalc::gateDelaysParallel(ArcDcalcArgSeq &dcalc_args,
ArcDcalcResultSeq dcalc_results(drvr_count);
Slew slew_sum = 0.0;
ArcDelay load_delay_sum = 0.0;
vector<ArcDelay> intrinsic_delays(dcalc_args.size());
vector<ArcDelay> load_delays(dcalc_args.size());
std::vector<ArcDelay> intrinsic_delays(dcalc_args.size());
std::vector<ArcDelay> load_delays(dcalc_args.size());
for (size_t drvr_idx = 0; drvr_idx < drvr_count; drvr_idx++) {
ArcDcalcArg &dcalc_arg = dcalc_args[drvr_idx];
ArcDcalcResult &dcalc_result = dcalc_results[drvr_idx];

15
dcalc/PrimaDelayCalc.cc
View File

@ -44,9 +44,6 @@
namespace sta {
using std::string;
using std::abs;
using std::make_shared;
using Eigen::SparseLU;
using Eigen::HouseholderQR;
using Eigen::ColPivHouseholderQR;
@ -726,7 +723,7 @@ PrimaDelayCalc::dcalcResults()
ThresholdTimes &drvr_times = threshold_times_[drvr_node];
float ref_time = output_waveforms_[drvr_idx]->referenceTime(dcalc_arg.inSlewFlt());
ArcDelay gate_delay = drvr_times[threshold_vth] - ref_time;
Slew drvr_slew = abs(drvr_times[threshold_vh] - drvr_times[threshold_vl]);
Slew drvr_slew = std::abs(drvr_times[threshold_vh] - drvr_times[threshold_vl]);
dcalc_result.setGateDelay(gate_delay);
dcalc_result.setDrvrSlew(drvr_slew);
debugPrint(debug_, "ccs_dcalc", 2,
@ -743,7 +740,7 @@ PrimaDelayCalc::dcalcResults()
ThresholdTimes &wire_times = threshold_times_[load_node];
ThresholdTimes &drvr_times = threshold_times_[drvr_node];
ArcDelay wire_delay = wire_times[threshold_vth] - drvr_times[threshold_vth];
Slew load_slew = abs(wire_times[threshold_vh] - wire_times[threshold_vl]);
Slew load_slew = std::abs(wire_times[threshold_vh] - wire_times[threshold_vl]);
debugPrint(debug_, "ccs_dcalc", 2,
"load %s %s delay %s slew %s",
network_->pathName(load_pin),
@ -908,7 +905,7 @@ PrimaDelayCalc::recordWaveformStep(double time)
////////////////////////////////////////////////////////////////
string
std::string
PrimaDelayCalc::reportGateDelay(const Pin *drvr_pin,
const TimingArc *arc,
const Slew &in_slew,
@ -959,8 +956,8 @@ Waveform
PrimaDelayCalc::watchWaveform(const Pin *pin)
{
FloatSeq &voltages = watch_pin_values_[pin];
TableAxisPtr time_axis = make_shared<TableAxis>(TableAxisVariable::time,
FloatSeq(times_));
TableAxisPtr time_axis = std::make_shared<TableAxis>(TableAxisVariable::time,
FloatSeq(times_));
Table waveform(new FloatSeq(voltages), time_axis);
return waveform;
}
@ -1003,7 +1000,7 @@ void
PrimaDelayCalc::reportMatrix(MatrixSd &matrix)
{
for (Eigen::Index i = 0; i < matrix.rows(); i++) {
string line = "| ";
std::string line = "| ";
for (Eigen::Index j = 0; j < matrix.cols(); j++) {
std::string entry = stdstrPrint("%10.3e", matrix.coeff(i, j));
line += entry;

8
dcalc/UnitDelayCalc.cc
View File

@ -28,8 +28,6 @@
namespace sta {
using std::string;
ArcDelayCalc *
makeUnitDelayCalc(StaState *sta)
{
@ -142,7 +140,7 @@ UnitDelayCalc::unitDelayResult(const LoadPinIndexMap &load_pin_index_map)
return dcalc_result;
}
string
std::string
UnitDelayCalc::reportGateDelay(const Pin *,
const TimingArc *,
const Slew &,
@ -153,7 +151,7 @@ UnitDelayCalc::reportGateDelay(const Pin *,
const MinMax *,
int)
{
string result("Delay = 1.0\n");
std::string result("Delay = 1.0\n");
result += "Slew = 0.0\n";
return result;
}
@ -170,7 +168,7 @@ UnitDelayCalc::checkDelay(const Pin *,
return units_->timeUnit()->scale();
}
string
std::string
UnitDelayCalc::reportCheckDelay(const Pin *,
const TimingArc *,
const Slew &,

12
graph/Graph.cc
View File

@ -39,8 +39,6 @@
namespace sta {
using std::string;
////////////////////////////////////////////////////////////////
//
// Graph
@ -985,12 +983,12 @@ Vertex::setObjectIdx(ObjectIdx idx)
object_idx_ = idx;
}
string
std::string
Vertex::to_string(const StaState *sta) const
{
const Network *network = sta->sdcNetwork();
if (network->direction(pin_)->isBidirect()) {
string str = network->pathName(pin_);
std::string str = network->pathName(pin_);
str += ' ';
str += is_bidirect_drvr_ ? "driver" : "load";
return str;
@ -1002,7 +1000,7 @@ Vertex::to_string(const StaState *sta) const
const char *
Vertex::name(const Network *network) const
{
string name = to_string(network);
std::string name = to_string(network);
return makeTmpString(name);
}
@ -1229,11 +1227,11 @@ Edge::setObjectIdx(ObjectIdx idx)
object_idx_ = idx;
}
string
std::string
Edge::to_string(const StaState *sta) const
{
const Graph *graph = sta->graph();
string str = from(graph)->to_string(sta);
std::string str = from(graph)->to_string(sta);
str += " -> ";
str += to(graph)->to_string(sta);
str += " ";

2
liberty/EquivCells.cc
View File

@ -38,8 +38,6 @@
namespace sta {
using std::max;
static unsigned
hashCell(const LibertyCell *cell);
static unsigned

14
liberty/FuncExpr.cc
View File

@ -30,8 +30,6 @@
namespace sta {
using std::string;
FuncExpr *
FuncExpr::makePort(LibertyPort *port)
{
@ -199,20 +197,20 @@ FuncExpr::portTimingSense(const LibertyPort *port) const
return TimingSense::unknown;
}
string
std::string
FuncExpr::to_string() const
{
return to_string(false);
}
string
std::string
FuncExpr::to_string(bool with_parens) const
{
switch (op_) {
case Op::port:
return port_->name();
case Op::not_: {
string result = "!";
std::string result = "!";
result += left_ ? left_->to_string(true) : "?";
return result;
}
@ -231,12 +229,12 @@ FuncExpr::to_string(bool with_parens) const
}
}
string
std::string
FuncExpr::to_string(bool with_parens,
char op) const
{
string right = right_->to_string(true);
string result;
std::string right = right_->to_string(true);
std::string result;
if (with_parens)
result += '(';
result += left_ ? left_->to_string(true) : "?";

6
liberty/Liberty.cc
View File

@ -50,8 +50,6 @@
namespace sta {
using std::string;
void
initLiberty()
{
@ -2704,13 +2702,13 @@ LibertyPort::setReceiverModel(ReceiverModelPtr receiver_model)
receiver_model_ = receiver_model;
}
string
std::string
portLibertyToSta(const char *port_name)
{
constexpr char bus_brkt_left = '[';
constexpr char bus_brkt_right = ']';
size_t name_length = strlen(port_name);
string sta_name;
std::string sta_name;
for (size_t i = 0; i < name_length; i++) {
char ch = port_name[i];
if (ch == bus_brkt_left

8
liberty/LibertyParser.cc
View File

@ -37,8 +37,6 @@
namespace sta {
using std::string;
void
parseLibertyFile(const char *filename,
LibertyGroupVisitor *library_visitor,
@ -65,7 +63,7 @@ LibertyParser::LibertyParser(const char *filename,
}
void
LibertyParser::setFilename(const string &filename)
LibertyParser::setFilename(const std::string &filename)
{
filename_ = filename;
}
@ -253,7 +251,7 @@ LibertyScanner::includeBegin()
static const std::regex include_regexp("include_file *\\( *([^)]+) *\\) *;?");
std::cmatch matches;
if (std::regex_match(yytext, matches, include_regexp)) {
string filename = matches[1].str();
std::string filename = matches[1].str();
gzstream::igzstream *stream = new gzstream::igzstream(filename.c_str());
if (stream->is_open()) {
yypush_buffer_state(yy_create_buffer(stream, 16384));
@ -348,7 +346,7 @@ LibertyGroup::deleteSubgroup(const LibertyGroup *subgroup)
void
LibertyGroup::addDefine(LibertyDefine *define)
{
const string &define_name = define->name();
const std::string &define_name = define->name();
LibertyDefine *prev_define = findKey(define_map_, define_name);
if (prev_define) {
define_map_.erase(define_name);

6
liberty/LibertyWriter.cc
View File

@ -25,7 +25,7 @@
#include "LibertyWriter.hh"
#include <cstdlib>
#include <algorithm>
#include <cmath>
#include "Units.hh"
#include "FuncExpr.hh"
@ -39,8 +39,6 @@
namespace sta {
using std::abs;
class LibertyWriter
{
public:
@ -271,7 +269,7 @@ LibertyWriter::writeBusDcls()
fprintf(stream_, " type (\"%s\") {\n", dcl->name().c_str());
fprintf(stream_, " base_type : array;\n");
fprintf(stream_, " data_type : bit;\n");
fprintf(stream_, " bit_width : %d;\n", abs(dcl->from() - dcl->to() + 1));
fprintf(stream_, " bit_width : %d;\n", std::abs(dcl->from() - dcl->to() + 1));
fprintf(stream_, " bit_from : %d;\n", dcl->from());
fprintf(stream_, " bit_to : %d;\n", dcl->to());
fprintf(stream_, " }\n");

10
liberty/LinearModel.cc
View File

@ -29,8 +29,6 @@
namespace sta {
using std::string;
GateLinearModel::GateLinearModel(LibertyCell *cell,
float intrinsic,
float resistance) :
@ -53,7 +51,7 @@ GateLinearModel::gateDelay(const Pvt *,
drvr_slew = 0.0;
}
string
std::string
GateLinearModel::reportGateDelay(const Pvt *,
float,
float load_cap,
@ -65,7 +63,7 @@ GateLinearModel::reportGateDelay(const Pvt *,
const Unit *time_unit = units->timeUnit();
const Unit *res_unit = units->resistanceUnit();
const Unit *cap_unit = units->capacitanceUnit();
string result = "Delay = ";
std::string result = "Delay = ";
result += time_unit->asString(intrinsic_, digits);
result += " + ";
result += res_unit->asString(resistance_, digits);
@ -105,7 +103,7 @@ CheckLinearModel::checkDelay(const Pvt *,
return intrinsic_;
}
string
std::string
CheckLinearModel::reportCheckDelay(const Pvt *,
float,
const char *,
@ -117,7 +115,7 @@ CheckLinearModel::reportCheckDelay(const Pvt *,
const LibertyLibrary *library = cell_->libertyLibrary();
const Units *units = library->units();
const Unit *time_unit = units->timeUnit();
string result = "Check = ";
std::string result = "Check = ";
result += time_unit->asString(intrinsic_, digits);
return result;
}

66
liberty/TableModel.cc
View File

@ -35,23 +35,17 @@
namespace sta {
using std::string;
using std::min;
using std::max;
using std::abs;
using std::make_shared;
size_t
findValueIndex(float value,
const FloatSeq *values);
static void
sigmaModelsDelete(TableModelsEarlyLate &models);
static string
static std::string
reportPvt(const LibertyCell *cell,
const Pvt *pvt,
int digits);
static void
appendSpaces(string &result,
appendSpaces(std::string &result,
int count);
TimingModel::TimingModel(LibertyCell *cell) :
@ -162,14 +156,14 @@ GateTableModel::gateDelay(const Pvt *pvt,
gateDelay(pvt, in_slew, load_cap, pocv_enabled, gate_delay, drvr_slew);
}
string
std::string
GateTableModel::reportGateDelay(const Pvt *pvt,
float in_slew,
float load_cap,
bool pocv_enabled,
int digits) const
{
string result = reportPvt(cell_, pvt, digits);
std::string result = reportPvt(cell_, pvt, digits);
result += reportTableLookup("Delay", pvt, delay_model_.get(), in_slew,
load_cap, 0.0, digits);
if (pocv_enabled && delay_sigma_models_[EarlyLate::earlyIndex()])
@ -197,7 +191,7 @@ GateTableModel::reportGateDelay(const Pvt *pvt,
return result;
}
string
std::string
GateTableModel::reportTableLookup(const char *result_name,
const Pvt *pvt,
const TableModel *model,
@ -496,7 +490,7 @@ CheckTableModel::findValue(const Pvt *pvt,
return 0.0;
}
string
std::string
CheckTableModel::reportCheckDelay(const Pvt *pvt,
float from_slew,
const char *from_slew_annotation,
@ -505,7 +499,7 @@ CheckTableModel::reportCheckDelay(const Pvt *pvt,
bool pocv_enabled,
int digits) const
{
string result = reportTableDelay("Check", pvt, model_.get(),
std::string result = reportTableDelay("Check", pvt, model_.get(),
from_slew, from_slew_annotation, to_slew,
related_out_cap, digits);
if (pocv_enabled && sigma_models_[EarlyLate::earlyIndex()])
@ -521,7 +515,7 @@ CheckTableModel::reportCheckDelay(const Pvt *pvt,
return result;
}
string
std::string
CheckTableModel::reportTableDelay(const char *result_name,
const Pvt *pvt,
const TableModel *model,
@ -535,7 +529,7 @@ CheckTableModel::reportTableDelay(const char *result_name,
float axis_value1, axis_value2, axis_value3;
findAxisValues(from_slew, to_slew, related_out_cap,
axis_value1, axis_value2, axis_value3);
string result = reportPvt(cell_, pvt, digits);
std::string result = reportPvt(cell_, pvt, digits);
result += model_->reportValue(result_name, cell_, pvt,
axis_value1, from_slew_annotation, axis_value2,
axis_value3,
@ -735,7 +729,7 @@ TableModel::scaleFactor(const LibertyCell *cell,
rf_index_, cell, pvt);
}
string
std::string
TableModel::reportValue(const char *result_name,
const LibertyCell *cell,
const Pvt *pvt,
@ -746,7 +740,7 @@ TableModel::reportValue(const char *result_name,
const Unit *table_unit,
int digits) const
{
string result = table_->reportValue("Table value", cell, pvt, value1,
std::string result = table_->reportValue("Table value", cell, pvt, value1,
comment1, value2, value3, table_unit, digits);
result += reportPvtScaleFactor(cell, pvt, digits);
@ -758,7 +752,7 @@ TableModel::reportValue(const char *result_name,
return result;
}
static string
static std::string
reportPvt(const LibertyCell *cell,
const Pvt *pvt,
int digits)
@ -767,7 +761,7 @@ reportPvt(const LibertyCell *cell,
if (pvt == nullptr)
pvt = library->defaultOperatingConditions();
if (pvt) {
string result;
std::string result;
stringPrint(result, "P = %.*f V = %.*f T = %.*f\n",
digits, pvt->process(),
digits, pvt->voltage(),
@ -777,7 +771,7 @@ reportPvt(const LibertyCell *cell,
return "";
}
string
std::string
TableModel::reportPvtScaleFactor(const LibertyCell *cell,
const Pvt *pvt,
int digits) const
@ -785,7 +779,7 @@ TableModel::reportPvtScaleFactor(const LibertyCell *cell,
if (pvt == nullptr)
pvt = cell->libertyLibrary()->defaultOperatingConditions();
if (pvt) {
string result;
std::string result;
stringPrint(result, "PVT scale factor = %.*f\n",
digits,
scaleFactor(cell, pvt));
@ -1166,7 +1160,7 @@ Table::reportValueOrder0(const char *result_name,
const Unit *table_unit,
int digits) const
{
string result = result_name;
std::string result = result_name;
result += " constant = ";
result += table_unit->asString(value_, digits);
if (comment1)
@ -1187,7 +1181,7 @@ Table::reportValueOrder1(const char *result_name,
{
const Units *units = cell->libertyLibrary()->units();
const Unit *unit1 = axis1_->unit(units);
string result = "Table is indexed by\n ";
std::string result = "Table is indexed by\n ";
result += axis1_->variableString();
result += " = ";
result += unit1->asString(value1, digits);
@ -1228,7 +1222,7 @@ Table::reportValueOrder2(const char *result_name,
const Units *units = cell->libertyLibrary()->units();
const Unit *unit1 = axis1_->unit(units);
const Unit *unit2 = axis2_->unit(units);
string result = "------- ";
std::string result = "------- ";
result += axis1_->variableString();
result += " = ";
result += unit1->asString(value1, digits);
@ -1289,7 +1283,7 @@ Table::reportValueOrder3(const char *result_name,
const Unit *unit1 = axis1_->unit(units);
const Unit *unit2 = axis2_->unit(units);
const Unit *unit3 = axis3_->unit(units);
string result = " --------- ";
std::string result = " --------- ";
result += axis1_->variableString();
result += " = ";
result += unit1->asString(value1, digits);
@ -1391,7 +1385,7 @@ Table::report(const Units *units,
const Unit *unit1 = axis1_->unit(units);
report->reportLine("%s", tableVariableString(axis1_->variable()));
report->reportLine("------------------------------");
string line;
std::string line;
for (size_t index1 = 0; index1 < axis1_->size(); index1++) {
line += unit1->asString(axis1_->axisValue(index1), digits);
line += " ";
@ -1410,7 +1404,7 @@ Table::report(const Units *units,
const Unit *unit2 = axis2_->unit(units);
report->reportLine("%s", tableVariableString(axis2_->variable()));
report->reportLine(" ------------------------------");
string line = " ";
std::string line = " ";
for (size_t index2 = 0; index2 < axis2_->size(); index2++) {
line += unit2->asString(axis2_->axisValue(index2), digits);
line += " ";
@ -1436,7 +1430,7 @@ Table::report(const Units *units,
unit1->asString(axis1_->axisValue(axis_index1), digits));
report->reportLine("%s", tableVariableString(axis3_->variable()));
report->reportLine(" ------------------------------");
string line = " ";
std::string line = " ";
for (size_t axis_index3 = 0; axis_index3 < axis3_->size(); axis_index3++) {
line += unit3->asString(axis3_->axisValue(axis_index3), digits);
line += " ";
@ -1455,7 +1449,7 @@ Table::report(const Units *units,
}
static void
appendSpaces(string &result,
appendSpaces(std::string &result,
int count)
{
while (count--)
@ -1755,7 +1749,7 @@ OutputWaveforms::findVoltages(size_t wave_index,
// Make voltage -> current table.
FloatSeq axis_volts = volts;
TableAxisPtr volt_axis =
make_shared<TableAxis>(TableAxisVariable::input_voltage, std::move(axis_volts));
std::make_shared<TableAxis>(TableAxisVariable::input_voltage, std::move(axis_volts));
FloatSeq *currents1 = new FloatSeq(*currents->values());
Table *volt_currents = new Table(currents1, volt_axis);
voltage_currents_[wave_index] = volt_currents;
@ -1774,7 +1768,7 @@ OutputWaveforms::currentWaveform(float slew,
times->push_back(time);
currents->push_back(current);
}
TableAxisPtr time_axis = make_shared<TableAxis>(TableAxisVariable::time, std::move(*times));
TableAxisPtr time_axis = std::make_shared<TableAxis>(TableAxisVariable::time, std::move(*times));
delete times;
return Table(currents, time_axis);
}
@ -1951,7 +1945,7 @@ OutputWaveforms::voltageWaveform(float slew,
times.push_back(time);
volts.push_back(volt);
}
TableAxisPtr time_axis = make_shared<TableAxis>(TableAxisVariable::time,
TableAxisPtr time_axis = std::make_shared<TableAxis>(TableAxisVariable::time,
std::move(times));
return Table(std::move(volts), time_axis);
}
@ -2076,7 +2070,7 @@ OutputWaveforms::voltageCurrentWaveform(float slew,
currents->push_back(current);
}
TableAxisPtr volt_axis =
make_shared<TableAxis>(TableAxisVariable::input_voltage, std::move(*volts));
std::make_shared<TableAxis>(TableAxisVariable::input_voltage, std::move(*volts));
delete volts;
return Table(currents, volt_axis);
}
@ -2095,12 +2089,12 @@ OutputWaveforms::finalResistance()
const FloatSeq &voltages = voltage_currents->axis1()->values();
FloatSeq *currents = voltage_currents->values();
size_t idx_last1 = voltages.size() - 2;
return (vdd_ - voltages[idx_last1]) / abs((*currents)[idx_last1]);
return (vdd_ - voltages[idx_last1]) / std::abs((*currents)[idx_last1]);
}
////////////////////////////////////////////////////////////////
DriverWaveform::DriverWaveform(const string &name,
DriverWaveform::DriverWaveform(const std::string &name,
TablePtr waveforms) :
name_(name),
waveforms_(waveforms)
@ -2118,7 +2112,7 @@ DriverWaveform::waveform(float slew)
time_values->push_back(time);
volt_values->push_back(volt);
}
TableAxisPtr time_axis = make_shared<TableAxis>(TableAxisVariable::time,
TableAxisPtr time_axis = std::make_shared<TableAxis>(TableAxisVariable::time,
std::move(*time_values));
delete time_values;
Table waveform(volt_values, time_axis);

11
liberty/TimingArc.cc
View File

@ -35,9 +35,6 @@
namespace sta {
using std::string;
using std::make_shared;
static bool
timingArcsEquiv(const TimingArcSet *set1,
const TimingArcSet *set2);
@ -511,7 +508,7 @@ TimingArcSet::wireArcIndex(const RiseFall *rf)
void
TimingArcSet::init()
{
wire_timing_arc_attrs_ = make_shared<TimingArcAttrs>(TimingSense::positive_unate);
wire_timing_arc_attrs_ = std::make_shared<TimingArcAttrs>(TimingSense::positive_unate);
wire_timing_arc_set_ = new TimingArcSet(TimingRole::wire(), wire_timing_arc_attrs_);
new TimingArc(wire_timing_arc_set_, Transition::rise(),
Transition::rise(), nullptr);
@ -549,18 +546,18 @@ TimingArc::~TimingArc()
delete scaled_models_;
}
string
std::string
TimingArc::to_string() const
{
if (set_->role()->isWire()) {
string str = "wire ";
std::string str = "wire ";
str += from_rf_->to_string();
str += " -> ";
str += to_rf_->to_string();
return str;
}
else {
string str = set_->from()->name();
std::string str = set_->from()->name();
str += " ";
str += from_rf_->to_string();
str += " -> ";

7
liberty/Units.cc
View File

@ -32,9 +32,6 @@
namespace sta {
using std::abs;
Unit::Unit(const char *suffix) :
scale_(1.0),
suffix_(suffix),
@ -175,12 +172,12 @@ Unit::asString(float value,
int digits) const
{
// Special case INF because it blows up otherwise.
if (abs(value) >= INF * .1)
if (std::abs(value) >= INF * .1)
return (value > 0.0) ? "INF" : "-INF";
else {
float scaled_value = value / scale_;
// prevent "-0.00" on slowaris
if (abs(scaled_value) < 1E-6)
if (std::abs(scaled_value) < 1E-6)
scaled_value = 0.0;
return stringPrintTmp("%.*f", digits, scaled_value);
}

30
network/ConcreteLibrary.cc
View File

@ -24,6 +24,7 @@
#include "ConcreteLibrary.hh"
#include <cmath>
#include <cstdlib>
#include <limits>
@ -35,13 +36,6 @@
namespace sta {
using std::string;
using std::map;
using std::min;
using std::max;
using std::abs;
using std::swap;
static constexpr char escape_ = '\\';
ConcreteLibrary::ConcreteLibrary(const char *name,
@ -228,7 +222,7 @@ ConcreteCell::makeBusPortBit(ConcretePort *bus_port,
const char *bus_name,
int bit_index)
{
string bit_name;
std::string bit_name;
stringPrint(bit_name, "%s%c%d%c",
bus_name,
library_->busBrktLeft(),
@ -272,14 +266,14 @@ ConcreteCell::setIsLeaf(bool is_leaf)
}
void
ConcreteCell::setAttribute(const string &key,
const string &value)
ConcreteCell::setAttribute(const std::string &key,
const std::string &value)
{
attribute_map_[key] = value;
}
string
ConcreteCell::getAttribute(const string &key) const
std::string
ConcreteCell::getAttribute(const std::string &key) const
{
const auto &itr = attribute_map_.find(key);
if (itr != attribute_map_.end())
@ -350,8 +344,8 @@ void
BusPort::addBusBit(ConcretePort *port,
int index)
{
from_ = min(from_, index);
to_ = max(to_, index);
from_ = std::min(from_, index);
to_ = std::max(to_, index);
members_.push_back(port);
}
@ -362,7 +356,7 @@ ConcreteCell::groupBusPorts(const char bus_brkt_left,
{
const char bus_brkts_left[2]{bus_brkt_left, '\0'};
const char bus_brkts_right[2]{bus_brkt_right, '\0'};
map<string, BusPort> bus_map;
std::map<std::string, BusPort> bus_map;
// Find ungrouped bus ports.
// Remove bus bit ports from the ports_ vector during the scan by
// keeping an index to the next insertion index and skipping over
@ -372,7 +366,7 @@ ConcreteCell::groupBusPorts(const char bus_brkt_left,
for (ConcretePort *port : ports) {
const char *port_name = port->name();
bool is_bus;
string bus_name;
std::string bus_name;
int index;
parseBusName(port_name, bus_brkts_left, bus_brkts_right, escape_,
is_bus, bus_name, index);
@ -402,7 +396,7 @@ ConcreteCell::groupBusPorts(const char bus_brkt_left,
(*members)[member_index] = bus_bit;
}
if (msb_first)
swap(from, to);
std::swap(from, to);
ConcretePort *port = makeBusPort(bus_name.c_str(), from, to, members);
port->setDirection(bus_port.direction());
}
@ -505,7 +499,7 @@ int
ConcretePort::size() const
{
if (is_bus_)
return abs(to_index_ - from_index_) + 1;
return std::abs(to_index_ - from_index_) + 1;
else if (is_bundle_)
return static_cast<int>(member_ports_->size());
else

26
network/ConcreteNetwork.cc
View File

@ -35,8 +35,6 @@
namespace sta {
using std::string;
static void
makeChildNetwork(Instance *proto,
Instance *parent,
@ -581,8 +579,8 @@ ConcreteNetwork::setIsLeaf(Cell *cell,
void
ConcreteNetwork::setAttribute(Cell *cell,
const string &key,
const string &value)
const std::string &key,
const std::string &value)
{
ConcreteCell *ccell = reinterpret_cast<ConcreteCell*>(cell);
ccell->setAttribute(key, value);
@ -628,9 +626,9 @@ ConcreteNetwork::filename(const Cell *cell)
return ccell->filename();
}
string
std::string
ConcreteNetwork::getAttribute(const Cell *cell,
const string &key) const
const std::string &key) const
{
const ConcreteCell *ccell = reinterpret_cast<const ConcreteCell*>(cell);
return ccell->getAttribute(key);
@ -967,9 +965,9 @@ ConcreteNetwork::id(const Instance *instance) const
return inst->id();
}
string
std::string
ConcreteNetwork::getAttribute(const Instance *inst,
const string &key) const
const std::string &key) const
{
const ConcreteInstance *cinst = reinterpret_cast<const ConcreteInstance*>(inst);
return cinst->getAttribute(key);
@ -1389,8 +1387,8 @@ ConcreteNetwork::connect(Instance *inst,
void
ConcreteNetwork::setAttribute(Instance *inst,
const string &key,
const string &value)
const std::string &key,
const std::string &value)
{
ConcreteInstance *cinst = reinterpret_cast<ConcreteInstance*>(inst);
cinst->setAttribute(key, value);
@ -1718,14 +1716,14 @@ ConcreteInstance::childIterator() const
}
void
ConcreteInstance::setAttribute(const string &key,
const string &value)
ConcreteInstance::setAttribute(const std::string &key,
const std::string &value)
{
attribute_map_[key] = value;
}
string
ConcreteInstance::getAttribute(const string &key) const
std::string
ConcreteInstance::getAttribute(const std::string &key) const
{
const auto &itr = attribute_map_.find(key);
if (itr != attribute_map_.end())

8
network/Network.cc
View File

@ -37,8 +37,6 @@
namespace sta {
using std::string;
Network::Network() :
default_liberty_(nullptr),
divider_('/'),
@ -76,7 +74,7 @@ Network::findPortsMatching(const Cell *cell,
{
PortSeq matches;
bool is_bus, is_range, subscript_wild;
string bus_name;
std::string bus_name;
int from, to;
parseBusName(pattern->pattern(), '[', ']', '\\',
is_bus, is_range, bus_name, from, to, subscript_wild);
@ -1043,12 +1041,12 @@ Network::findInstPinsHierMatching(const Instance *instance,
// Return value.
PinSeq &matches) const
{
string inst_name = name(instance);
std::string inst_name = name(instance);
InstancePinIterator *pin_iter = pinIterator(instance);
while (pin_iter->hasNext()) {
const Pin *pin = pin_iter->next();
const char *port_name = name(port(pin));
string pin_name = inst_name + divider_ + port_name;
std::string pin_name = inst_name + divider_ + port_name;
if (pattern->match(pin_name.c_str()))
matches.push_back(pin);
}

14
network/ParseBus.cc
View File

@ -32,8 +32,6 @@
namespace sta {
using std::string;
bool
isBusName(const char *name,
const char brkt_left,
@ -60,7 +58,7 @@ parseBusName(const char *name,
const char escape,
// Return values.
bool &is_bus,
string &bus_name,
std::string &bus_name,
int &index)
{
const char brkts_left[2] = {brkt_left, '\0'};
@ -76,7 +74,7 @@ parseBusName(const char *name,
char escape,
// Return values.
bool &is_bus,
string &bus_name,
std::string &bus_name,
int &index)
{
is_bus = false;
@ -110,7 +108,7 @@ parseBusName(const char *name,
// Return values.
bool &is_bus,
bool &is_range,
string &bus_name,
std::string &bus_name,
int &from,
int &to,
bool &subscript_wild)
@ -129,7 +127,7 @@ parseBusName(const char *name,
// Return values.
bool &is_bus,
bool &is_range,
string &bus_name,
std::string &bus_name,
int &from,
int &to,
bool &subscript_wild)
@ -173,13 +171,13 @@ parseBusName(const char *name,
}
}
string
std::string
escapeChars(const char *token,
const char ch1,
const char ch2,
const char escape)
{
string escaped;
std::string escaped;
for (const char *s = token; *s; s++) {
char ch = *s;
if (ch == escape) {

89
network/SdcNetwork.cc
View File

@ -30,13 +30,10 @@
namespace sta {
using std::string;
using std::to_string;
static string
static std::string
escapeDividers(const char *token,
const Network *network);
static string
static std::string
escapeBrackets(const char *token,
const Network *network);
@ -137,9 +134,9 @@ NetworkNameAdapter::id(const Cell *cell) const
return network_->id(cell);
}
string
std::string
NetworkNameAdapter::getAttribute(const Cell *cell,
const string &key) const
const std::string &key) const
{
return network_->getAttribute(cell, key);
}
@ -355,9 +352,9 @@ NetworkNameAdapter::cell(const Instance *instance) const
return network_->cell(instance);
}
string
std::string
NetworkNameAdapter::getAttribute(const Instance *inst,
const string &key) const
const std::string &key) const
{
return network_->getAttribute(inst, key);
}
@ -675,16 +672,16 @@ SdcNetwork::findPort(const Cell *cell,
if (port == nullptr) {
// Look for matches after escaping brackets.
bool is_bus;
string bus_name;
std::string bus_name;
int index;
parseBusName(name, '[', ']', pathEscape(), is_bus, bus_name, index);
if (is_bus) {
string escaped1 = escapeBrackets(name, this);
std::string escaped1 = escapeBrackets(name, this);
port = network_->findPort(cell, escaped1.c_str());
if (port == nullptr) {
// Try escaping base foo\[0\][1]
string escaped2;
string escaped_bus_name = escapeBrackets(bus_name.c_str(), this);
std::string escaped2;
std::string escaped_bus_name = escapeBrackets(bus_name.c_str(), this);
stringPrint(escaped2, "%s[%d]",
escaped_bus_name.c_str(),
index);
@ -693,7 +690,7 @@ SdcNetwork::findPort(const Cell *cell,
}
else {
// Try escaping brackets foo\[0\].bar
string escaped = escapeBrackets(name, this);
std::string escaped = escapeBrackets(name, this);
port = network_->findPort(cell, escaped.c_str());
}
}
@ -708,19 +705,19 @@ SdcNetwork::findPortsMatching(const Cell *cell,
if (matches.empty()) {
// Look for matches after escaping brackets.
bool is_bus;
string bus_name;
std::string bus_name;
int index;
parseBusName(pattern->pattern(), '[', ']', pathEscape(),
is_bus, bus_name, index);
if (is_bus) {
string escaped1 = escapeBrackets(pattern->pattern(), this);
std::string escaped1 = escapeBrackets(pattern->pattern(), this);
PatternMatch escaped_pattern1(escaped1.c_str(), pattern);
matches = network_->findPortsMatching(cell, &escaped_pattern1);
if (matches.empty()) {
// Try escaping base foo\[0\][1]
string escaped_name = escapeBrackets(bus_name.c_str(), this);
std::string escaped_name = escapeBrackets(bus_name.c_str(), this);
escaped_name += '[';
escaped_name += to_string(index);
escaped_name += std::to_string(index);
escaped_name += ']';
PatternMatch escaped_pattern2(escaped_name.c_str(), pattern);
matches = network_->findPortsMatching(cell, &escaped_pattern2);
@ -728,7 +725,7 @@ SdcNetwork::findPortsMatching(const Cell *cell,
}
else {
// Try escaping brackets foo\[0\].bar
string escaped = escapeBrackets(pattern->pattern(), this);
std::string escaped = escapeBrackets(pattern->pattern(), this);
PatternMatch escaped_pattern(escaped.c_str(), pattern);
matches = network_->findPortsMatching(cell, &escaped_pattern);
}
@ -796,7 +793,7 @@ SdcNetwork::findInstance(const char *path_name) const
parent = network_->topInstance();
Instance *child = findChild(parent, child_name);
if (child == nullptr) {
string escaped_name = escapeDividers(child_name, this);
std::string escaped_name = escapeDividers(child_name, this);
child = findChild(parent, escaped_name.c_str());
}
return child;
@ -808,10 +805,10 @@ SdcNetwork::findInstanceRelative(const Instance *inst,
{
Instance *inst1 = network_->findInstanceRelative(inst, path_name);
if (inst1 == nullptr) {
string path_name1 = escapeBrackets(path_name, this);
std::string path_name1 = escapeBrackets(path_name, this);
inst1 = network_->findInstanceRelative(inst, path_name1.c_str());
if (inst1 == nullptr) {
string path_name2 = escapeDividers(path_name1.c_str(), network_);
std::string path_name2 = escapeDividers(path_name1.c_str(), network_);
inst1 = network_->findInstanceRelative(inst, path_name2.c_str());
}
}
@ -848,7 +845,7 @@ SdcNetwork::findChild(const Instance *parent,
{
Instance *child = network_->findChild(parent, name);
if (child == nullptr) {
string escaped = escapeBrackets(name, this);
std::string escaped = escapeBrackets(name, this);
child = network_->findChild(parent, escaped.c_str());
}
return child;
@ -873,8 +870,8 @@ SdcNetwork::findNet(const Instance *instance,
{
Net *net = network_->findNet(instance, net_name);
if (net == nullptr) {
string net_name1 = escapeBrackets(net_name, this);
string net_name2 = escapeDividers(net_name1.c_str(), network_);
std::string net_name1 = escapeBrackets(net_name, this);
std::string net_name2 = escapeDividers(net_name1.c_str(), network_);
net = network_->findNet(instance, net_name2.c_str());
}
return net;
@ -886,15 +883,15 @@ SdcNetwork::findNetRelative(const Instance *inst,
{
Net *net = network_->findNetRelative(inst, path_name);
if (net == nullptr) {
string path_name1 = escapeDividers(path_name, network_);
std::string path_name1 = escapeDividers(path_name, network_);
net = network_->findNetRelative(inst, path_name1.c_str());
if (net == nullptr) {
string path_name2 = escapeBrackets(path_name, network_);
std::string path_name2 = escapeBrackets(path_name, network_);
net = network_->findNetRelative(inst, path_name2.c_str());
if (net == nullptr) {
string path_name3 = escapeDividers(path_name2.c_str(), network_);
std::string path_name3 = escapeDividers(path_name2.c_str(), network_);
net = network_->findNetRelative(inst, path_name3.c_str());
}
}
@ -926,12 +923,12 @@ SdcNetwork::findInstNetsMatching(const Instance *instance,
network_->findInstNetsMatching(instance, pattern, matches);
if (matches.empty()) {
// Look for matches after escaping path dividers.
string escaped_pattern = escapeDividers(pattern->pattern(), this);
std::string escaped_pattern = escapeDividers(pattern->pattern(), this);
const PatternMatch escaped_dividers(escaped_pattern.c_str(), pattern);
network_->findInstNetsMatching(instance, &escaped_dividers, matches);
if (matches.empty()) {
// Look for matches after escaping brackets.
string escaped_pattern2 = escapeBrackets(pattern->pattern(),this);
std::string escaped_pattern2 = escapeBrackets(pattern->pattern(),this);
const PatternMatch escaped_brkts(escaped_pattern2.c_str(), pattern);
network_->findInstNetsMatching(instance, &escaped_brkts, matches);
}
@ -959,24 +956,24 @@ SdcNetwork::findPin(const Instance *instance,
if (pin == nullptr) {
// Look for match after escaping brackets.
bool is_bus;
string bus_name;
std::string bus_name;
int index;
parseBusName(port_name, '[', ']', pathEscape(),
is_bus, bus_name, index);
if (is_bus) {
string escaped1 = escapeBrackets(port_name, this);
std::string escaped1 = escapeBrackets(port_name, this);
pin = network_->findPin(instance, escaped1.c_str());
if (pin == nullptr) {
// Try escaping base foo\[0\][1]
string escaped_bus_name = escapeBrackets(bus_name.c_str(), this);
string escaped2;
std::string escaped_bus_name = escapeBrackets(bus_name.c_str(), this);
std::string escaped2;
stringPrint(escaped2, "%s[%d]", escaped_bus_name.c_str(), index);
pin = network_->findPin(instance, escaped2.c_str());
}
}
else {
// Try escaping port brackets foo\[0\].bar
string escaped = escapeBrackets(port_name, this);
std::string escaped = escapeBrackets(port_name, this);
pin = network_->findPin(instance, escaped.c_str());
}
}
@ -1028,7 +1025,7 @@ SdcNetwork::visitPinTail(const Instance *instance,
if (network_->hasMembers(port)) {
bool bus_matches = tail->match(port_name);
if (!bus_matches) {
string escaped_name = escapeDividers(port_name, network_);
std::string escaped_name = escapeDividers(port_name, network_);
bus_matches = tail->match(escaped_name);
}
PortMemberIterator *member_iter = network_->memberIterator(port);
@ -1044,7 +1041,7 @@ SdcNetwork::visitPinTail(const Instance *instance,
const char *member_name = network_->name(member_port);
bool member_matches = tail->match(member_name);
if (!member_matches) {
string escaped_name = escapeDividers(member_name, network_);
std::string escaped_name = escapeDividers(member_name, network_);
member_matches = tail->match(escaped_name);
}
if (member_matches) {
@ -1059,7 +1056,7 @@ SdcNetwork::visitPinTail(const Instance *instance,
else {
bool port_matches = tail->match(port_name);
if (!port_matches) {
string escaped_name = escapeDividers(port_name, network_);
std::string escaped_name = escapeDividers(port_name, network_);
port_matches = tail->match(escaped_name);
}
if (port_matches) {
@ -1081,7 +1078,7 @@ SdcNetwork::makeInstance(LibertyCell *cell,
const char *name,
Instance *parent)
{
string escaped_name = escapeDividers(name, this);
std::string escaped_name = escapeDividers(name, this);
return network_edit_->makeInstance(cell, escaped_name.c_str(), parent);
}
@ -1089,7 +1086,7 @@ Net *
SdcNetwork::makeNet(const char *name,
Instance *parent)
{
string escaped_name = escapeDividers(name, this);
std::string escaped_name = escapeDividers(name, this);
return network_edit_->makeNet(escaped_name.c_str(), parent);
}
@ -1188,7 +1185,7 @@ SdcNetwork::parsePath(const char *path,
else
*p++ = ch;
if (p - inst_path + 1 > inst_path_length)
report_->critical(1500, "inst path string lenth estimate busted");
report_->critical(1500, "inst path std::string lenth estimate busted");
}
*p = '\0';
stringDelete(inst_path);
@ -1235,7 +1232,7 @@ SdcNetwork::visitMatches(const Instance *parent,
network_->findChildrenMatching(parent, &matcher, matches);
if (has_brkts && matches.empty()) {
// Look for matches after escaping brackets.
string escaped_brkts = escapeBrackets(inst_path, this);
std::string escaped_brkts = escapeBrackets(inst_path, this);
const PatternMatch escaped_pattern(escaped_brkts, pattern);
network_->findChildrenMatching(parent, &escaped_pattern, matches);
}
@ -1257,7 +1254,7 @@ SdcNetwork::visitMatches(const Instance *parent,
*p++ = ch;
}
if (p - inst_path + 1 > inst_path_length)
report_->critical(1501, "inst path string lenth estimate exceeded");
report_->critical(1501, "inst path std::string lenth estimate exceeded");
}
*p = '\0';
if (!found_match) {
@ -1265,7 +1262,7 @@ SdcNetwork::visitMatches(const Instance *parent,
found_match |= visit_tail(parent, &tail_pattern);
if (!found_match && has_brkts) {
// Look for matches after escaping brackets.
string escaped_path = escapeBrackets(inst_path, this);
std::string escaped_path = escapeBrackets(inst_path, this);
const PatternMatch escaped_tail(escaped_path, pattern);
found_match |= visit_tail(parent, &escaped_tail);
}
@ -1276,7 +1273,7 @@ SdcNetwork::visitMatches(const Instance *parent,
////////////////////////////////////////////////////////////////
static string
static std::string
escapeDividers(const char *token,
const Network *network)
{
@ -1284,7 +1281,7 @@ escapeDividers(const char *token,
network->pathEscape());
}
static string
static std::string
escapeBrackets(const char *token,
const Network *network)
{

60
network/VerilogNamespace.cc
View File

@ -31,39 +31,37 @@
namespace sta {
using std::string;
constexpr char verilog_escape = '\\';
static string
static std::string
staToVerilog(const char *sta_name);
static string
static std::string
staToVerilog2(const char *sta_name);
static string
verilogToSta(const string *verilog_name);
static std::string
verilogToSta(const std::string *verilog_name);
string
std::string
cellVerilogName(const char *sta_name)
{
return staToVerilog(sta_name);
}
string
std::string
instanceVerilogName(const char *sta_name)
{
return staToVerilog(sta_name);
}
string
std::string
netVerilogName(const char *sta_name)
{
bool is_bus;
string bus_name;
std::string bus_name;
int index;
parseBusName(sta_name, '[', ']', verilog_escape, is_bus, bus_name, index);
if (is_bus) {
string bus_vname = staToVerilog(bus_name.c_str());
string vname;
std::string bus_vname = staToVerilog(bus_name.c_str());
std::string vname;
stringPrint(vname, "%s[%d]", bus_vname.c_str(), index);
return vname;
}
@ -71,19 +69,19 @@ netVerilogName(const char *sta_name)
return staToVerilog2(sta_name);
}
string
std::string
portVerilogName(const char *sta_name)
{
return staToVerilog2(sta_name);
}
static string
static std::string
staToVerilog(const char *sta_name)
{
// Leave room for leading escape and trailing space if the name
// needs to be escaped.
// Assume the name has to be escaped and start copying while scanning.
string escaped_name = "\\";
std::string escaped_name = "\\";
bool escaped = false;
for (const char *s = sta_name; *s ; s++) {
char ch = s[0];
@ -110,17 +108,17 @@ staToVerilog(const char *sta_name)
return escaped_name;
}
else
return string(sta_name);
return std::string(sta_name);
}
static string
static std::string
staToVerilog2(const char *sta_name)
{
constexpr char bus_brkt_left = '[';
constexpr char bus_brkt_right = ']';
// Leave room for leading escape and trailing space if the name
// needs to be escaped.
string escaped_name = "\\";
std::string escaped_name = "\\";
// Assume the name has to be escaped and start copying while scanning.
bool escaped = false;
for (const char *s = sta_name; *s ; s++) {
@ -150,37 +148,37 @@ staToVerilog2(const char *sta_name)
return escaped_name;
}
else
return string(sta_name);
return std::string(sta_name);
}
////////////////////////////////////////////////////////////////
string
moduleVerilogToSta(const string *module_name)
std::string
moduleVerilogToSta(const std::string *module_name)
{
return verilogToSta(module_name);
}
string
instanceVerilogToSta(const string *inst_name)
std::string
instanceVerilogToSta(const std::string *inst_name)
{
return verilogToSta(inst_name);
}
string
netVerilogToSta(const string *net_name)
std::string
netVerilogToSta(const std::string *net_name)
{
return verilogToSta(net_name);
}
string
portVerilogToSta(const string *port_name)
std::string
portVerilogToSta(const std::string *port_name)
{
return verilogToSta(port_name);
}
static string
verilogToSta(const string *verilog_name)
static std::string
verilogToSta(const std::string *verilog_name)
{
if (verilog_name->front() == '\\') {
constexpr char divider = '/';
@ -190,7 +188,7 @@ verilogToSta(const string *verilog_name)
size_t verilog_name_length = verilog_name->size();
if (isspace(verilog_name->back()))
verilog_name_length--;
string sta_name;
std::string sta_name;
// Ignore leading '\'.
for (size_t i = 1; i < verilog_name_length; i++) {
char ch = verilog_name->at(i);
@ -205,7 +203,7 @@ verilogToSta(const string *verilog_name)
return sta_name;
}
else
return string(*verilog_name);
return std::string(*verilog_name);
}
} // namespace

4
parasitics/ConcreteParasitics.cc
View File

@ -45,8 +45,6 @@
namespace sta {
using std::max;
ConcreteParasitic::~ConcreteParasitic()
{
}
@ -620,7 +618,7 @@ ConcreteParasiticNetwork::ensureParasiticNode(const Net *net,
node = new ConcreteParasiticNode(net, id, network->highestNetAbove(net1) != net_);
sub_nodes_[net_id] = node;
if (net == net_)
max_node_id_ = max((int) max_node_id_, id);
max_node_id_ = std::max((int) max_node_id_, id);
}
else
node = id_node->second;

5
parasitics/ReduceParasitics.cc
View File

@ -24,6 +24,7 @@
#include "ReduceParasitics.hh"
#include <algorithm>
#include <map>
#include <set>
@ -38,8 +39,6 @@
namespace sta {
using std::max;
typedef std::map<ParasiticNode*, double> ParasiticNodeValueMap;
typedef std::map<ParasiticResistor*, double> ResistorCurrentMap;
typedef std::set<ParasiticResistor*> ParasiticResistorSet;
@ -174,7 +173,7 @@ ReduceToPi::reducePiDfs(const Pin *drvr_pin,
+ pinCapacitance(node);
y1 = dwn_cap;
y2 = y3 = 0.0;
max_resistance = max(max_resistance, src_resistance);
max_resistance = std::max(max_resistance, src_resistance);
visit(node);
ParasiticResistorSeq &resistors = resistor_map_[node];

4
parasitics/SpefReader.cc
View File

@ -43,8 +43,6 @@
namespace sta {
using std::string;
bool
readSpefFile(const std::string &filename,
Instance *instance,
@ -616,7 +614,7 @@ SpefTriple::value(int index) const
////////////////////////////////////////////////////////////////
SpefScanner::SpefScanner(std::istream *stream,
const string &filename,
const std::string &filename,
SpefReader *reader,
Report *report) :
yyFlexLexer(stream),

13
power/Power.cc
View File

@ -72,13 +72,6 @@
namespace sta {
using std::abs;
using std::max;
using std::min;
using std::isnormal;
using std::vector;
using std::map;
static bool
isPositiveUnate(const LibertyCell *cell,
const LibertyPort *from,
@ -734,7 +727,7 @@ percentChange(float value,
return 1.0;
}
else
return abs(value - prev) / prev;
return std::abs(value - prev) / prev;
}
// Return true if the activity changed.
@ -1837,7 +1830,7 @@ Power::clockMinPeriod(const Sdc *sdc)
if (!clks.empty()) {
float min_period = INF;
for (const Clock *clk : clks)
min_period = min(min_period, clk->period());
min_period = std::min(min_period, clk->period());
return min_period;
}
else
@ -1963,7 +1956,7 @@ PwrActivity::check()
// Densities can get very small from multiplying probabilities
// through deep chains of logic. Clip them to prevent floating
// point anomalies.
if (abs(density_) < min_density)
if (std::abs(density_) < min_density)
density_ = 0.0;
}

16
power/SaifReader.cc
View File

@ -26,6 +26,7 @@
#include <algorithm>
#include <cinttypes>
#include <string>
#include "Error.hh"
#include "Debug.hh"
@ -42,9 +43,6 @@
namespace sta {
using std::string;
using std::min;
bool
readSaif(const char *filename,
const char *scope,
@ -129,9 +127,9 @@ SaifReader::instancePush(const char *instance_name)
// Check for a match to the annotation scope.
saif_scope_.push_back(instance_name);
string saif_scope;
std::string saif_scope;
bool first = true;
for (string &inst : saif_scope_) {
for (std::string &inst : saif_scope_) {
if (!first)
saif_scope += sdc_network_->pathDivider();
saif_scope += inst;
@ -167,7 +165,7 @@ SaifReader::setNetDurations(const char *net_name,
if (in_scope_level_ > 0) {
Instance *parent = path_.empty() ? sdc_network_->topInstance() : path_.back();
if (parent) {
string unescaped_name = unescaped(net_name);
std::string unescaped_name = unescaped(net_name);
const Pin *pin = sdc_network_->findPin(parent, unescaped_name.c_str());
LibertyPort *liberty_port = pin ? sdc_network_->libertyPort(pin) : nullptr;
if (pin
@ -194,10 +192,10 @@ SaifReader::setNetDurations(const char *net_name,
stringDelete(net_name);
}
string
std::string
SaifReader::unescaped(const char *token)
{
string unescaped;
std::string unescaped;
for (const char *t = token; *t; t++) {
char ch = *t;
if (ch != escape_)
@ -211,7 +209,7 @@ SaifReader::unescaped(const char *token)
////////////////////////////////////////////////////////////////
SaifScanner::SaifScanner(std::istream *stream,
const string &filename,
const std::string &filename,
SaifReader *reader,
Report *report) :
yyFlexLexer(stream),

52
power/VcdParse.cc
View File

@ -35,10 +35,6 @@
namespace sta {
using std::vector;
using std::string;
using std::isspace;
// Very imprecise syntax definition
// https://en.wikipedia.org/wiki/Value_change_dump#Structure.2FSyntax
// Much better syntax definition
@ -125,7 +121,7 @@ VcdParse::VcdParse(Report *report,
void
VcdParse::parseTimescale()
{
vector<string> tokens = readStmtTokens();
std::vector<std::string> tokens = readStmtTokens();
if (tokens.size() == 1) {
size_t last;
double time_scale = std::stod(tokens[0], &last);
@ -140,7 +136,7 @@ VcdParse::parseTimescale()
}
void
VcdParse::setTimeUnit(const string &time_unit,
VcdParse::setTimeUnit(const std::string &time_unit,
double time_scale)
{
double time_unit_scale = 1.0;
@ -177,19 +173,19 @@ static EnumNameMap<VcdVarType> vcd_var_type_map =
void
VcdParse::parseVar()
{
vector<string> tokens = readStmtTokens();
std::vector<std::string> tokens = readStmtTokens();
if (tokens.size() == 4
|| tokens.size() == 5) {
string type_name = tokens[0];
std::string type_name = tokens[0];
VcdVarType type = vcd_var_type_map.find(type_name, VcdVarType::unknown);
if (type == VcdVarType::unknown)
report_->fileWarn(1370, filename_, file_line_,
"Unknown variable type %s.",
type_name.c_str());
else {
size_t width = stoi(tokens[1]);
string &id = tokens[2];
string name = tokens[3];
size_t width = std::stoi(tokens[1]);
std::string &id = tokens[2];
std::string name = tokens[3];
// iverilog separates bus base name from bit range.
if (tokens.size() == 5) {
// Preserve space after esacaped name.
@ -208,8 +204,8 @@ VcdParse::parseVar()
void
VcdParse::parseScope()
{
vector<string> tokens = readStmtTokens();
string &scope = tokens[1];
std::vector<std::string> tokens = readStmtTokens();
std::string &scope = tokens[1];
scope_.push_back(scope);
}
@ -223,11 +219,11 @@ VcdParse::parseUpscope()
void
VcdParse::parseVarValues()
{
string token = getToken();
std::string token = getToken();
while (!token.empty()) {
char char0 = toupper(token[0]);
if (char0 == '#' && token.size() > 1) {
VcdTime time = stoll(token.substr(1));
VcdTime time = std::stoll(token.substr(1));
prev_time_ = time_;
time_ = time;
if (time_ > prev_time_)
@ -238,15 +234,15 @@ VcdParse::parseVarValues()
|| char0 == 'X'
|| char0 == 'U'
|| char0 == 'Z') {
string id = token.substr(1);
std::string id = token.substr(1);
if (!reader_->varIdValid(id))
report_->fileError(805, filename_, file_line_,
"unknown variable %s", id.c_str());
reader_->varAppendValue(id, time_, char0);
}
else if (char0 == 'B') {
string bus_value = token.substr(1);
string id = getToken();
std::string bus_value = token.substr(1);
std::string id = getToken();
if (!reader_->varIdValid(id))
report_->fileError(807, filename_, file_line_,
"unknown variable %s", id.c_str());
@ -261,12 +257,12 @@ VcdParse::parseVarValues()
reader_->setTimeMax(time_);
}
string
std::string
VcdParse::readStmtString()
{
stmt_line_ = file_line_;
string line;
string token = getToken();
std::string line;
std::string token = getToken();
while (!token.empty() && token != "$end") {
if (!line.empty())
line += " ";
@ -276,12 +272,12 @@ VcdParse::readStmtString()
return line;
}
vector<string>
std::vector<std::string>
VcdParse::readStmtTokens()
{
stmt_line_ = file_line_;
vector<string> tokens;
string token = getToken();
std::vector<std::string> tokens;
std::string token = getToken();
while (!token.empty() && token != "$end") {
tokens.push_back(token);
token = getToken();
@ -289,18 +285,18 @@ VcdParse::readStmtTokens()
return tokens;
}
string
std::string
VcdParse::getToken()
{
string token;
std::string token;
int ch = gzgetc(stream_);
// skip whitespace
while (ch != EOF && isspace(ch)) {
while (ch != EOF && std::isspace(ch)) {
if (ch == '\n')
file_line_++;
ch = gzgetc(stream_);
}
while (ch != EOF && !isspace(ch)) {
while (ch != EOF && !std::isspace(ch)) {
token.push_back(ch);
ch = gzgetc(stream_);
}

77
power/VcdReader.cc
View File

@ -24,8 +24,10 @@
#include "VcdReader.hh"
#include <cmath>
#include <inttypes.h>
#include <unordered_map>
#include <vector>
#include "VcdParse.hh"
#include "Debug.hh"
@ -41,13 +43,6 @@
namespace sta {
using std::string;
using std::abs;
using std::min;
using std::to_string;
using std::vector;
using std::unordered_map;
// Transition count and high time for duty cycle for a group of pins
// for one bit of vcd ID.
class VcdCount
@ -117,9 +112,9 @@ VcdCount::highTime(VcdTime time_max) const
////////////////////////////////////////////////////////////////
// VcdCount[bit]
typedef vector<VcdCount> VcdCounts;
using VcdCounts = std::vector<VcdCount>;
// ID -> VcdCount[bit]
typedef unordered_map<string, VcdCounts> VcdIdCountsMap;
using VcdIdCountsMap = std::unordered_map<std::string, VcdCounts>;
class VcdCountReader : public VcdReader
{
@ -134,31 +129,31 @@ public:
double timeScale() const { return time_scale_; }
// VcdParse callbacks.
void setDate(const string &) override {}
void setComment(const string &) override {}
void setVersion(const string &) override {}
void setTimeUnit(const string &time_unit,
void setDate(const std::string &) override {}
void setComment(const std::string &) override {}
void setVersion(const std::string &) override {}
void setTimeUnit(const std::string &time_unit,
double time_unit_scale,
double time_scale) override;
void setTimeMin(VcdTime time) override;
void setTimeMax(VcdTime time) override;
void varMinDeltaTime(VcdTime) override {}
bool varIdValid(const string &id) override;
bool varIdValid(const std::string &id) override;
void makeVar(const VcdScope &scope,
const string &name,
const std::string &name,
VcdVarType type,
size_t width,
const string &id) override;
void varAppendValue(const string &id,
const std::string &id) override;
void varAppendValue(const std::string &id,
VcdTime time,
char value) override;
void varAppendBusValue(const string &id,
void varAppendBusValue(const std::string &id,
VcdTime time,
const string &bus_value) override;
const std::string &bus_value) override;
private:
void addVarPin(const string &pin_name,
const string &id,
void addVarPin(const std::string &pin_name,
const std::string &id,
size_t width,
size_t bit_idx);
@ -189,7 +184,7 @@ VcdCountReader::VcdCountReader(const std::string &scope,
}
void
VcdCountReader::setTimeUnit(const string &,
VcdCountReader::setTimeUnit(const std::string &,
double time_unit_scale,
double time_scale)
{
@ -209,23 +204,23 @@ VcdCountReader::setTimeMax(VcdTime time)
}
bool
VcdCountReader::varIdValid(const string &)
VcdCountReader::varIdValid(const std::string &)
{
return true;
}
void
VcdCountReader::makeVar(const VcdScope &scope,
const string &name,
const std::string &name,
VcdVarType type,
size_t width,
const string &id)
const std::string &id)
{
if (type == VcdVarType::wire
|| type == VcdVarType::reg) {
string path_name;
std::string path_name;
bool first = true;
for (const string &context : scope) {
for (const std::string &context : scope) {
if (!first)
path_name += '/';
path_name += context;
@ -238,25 +233,25 @@ VcdCountReader::makeVar(const VcdScope &scope,
path_name += '/';
path_name += name;
// Strip the scope from the name.
string var_scoped = path_name.substr(scope_length + 1);
std::string var_scoped = path_name.substr(scope_length + 1);
if (width == 1) {
string pin_name = netVerilogToSta(&var_scoped);
std::string pin_name = netVerilogToSta(&var_scoped);
addVarPin(pin_name, id, width, 0);
}
else {
bool is_bus, is_range, subscript_wild;
string bus_name;
std::string bus_name;
int from, to;
parseBusName(var_scoped.c_str(), '[', ']', '\\',
is_bus, is_range, bus_name, from, to, subscript_wild);
if (is_bus) {
string sta_bus_name = netVerilogToSta(&bus_name);
std::string sta_bus_name = netVerilogToSta(&bus_name);
int bit_idx = 0;
if (to < from) {
for (int bus_bit = to; bus_bit <= from; bus_bit++) {
string pin_name = sta_bus_name;
std::string pin_name = sta_bus_name;
pin_name += '[';
pin_name += to_string(bus_bit);
pin_name += std::to_string(bus_bit);
pin_name += ']';
addVarPin(pin_name, id, width, bit_idx);
bit_idx++;
@ -264,9 +259,9 @@ VcdCountReader::makeVar(const VcdScope &scope,
}
else {
for (int bus_bit = to; bus_bit >= from; bus_bit--) {
string pin_name = sta_bus_name;
std::string pin_name = sta_bus_name;
pin_name += '[';
pin_name += to_string(bus_bit);
pin_name += std::to_string(bus_bit);
pin_name += ']';
addVarPin(pin_name, id, width, bit_idx);
bit_idx++;
@ -281,8 +276,8 @@ VcdCountReader::makeVar(const VcdScope &scope,
}
void
VcdCountReader::addVarPin(const string &pin_name,
const string &id,
VcdCountReader::addVarPin(const std::string &pin_name,
const std::string &id,
size_t width,
size_t bit_idx)
{
@ -303,7 +298,7 @@ VcdCountReader::addVarPin(const string &pin_name,
}
void
VcdCountReader::varAppendValue(const string &id,
VcdCountReader::varAppendValue(const std::string &id,
VcdTime time,
char value)
{
@ -329,9 +324,9 @@ VcdCountReader::varAppendValue(const string &id,
}
void
VcdCountReader::varAppendBusValue(const string &id,
VcdCountReader::varAppendBusValue(const std::string &id,
VcdTime time,
const string &bus_value)
const std::string &bus_value)
{
const auto &itr = vcd_count_map_.find(id);
if (itr != vcd_count_map_.end()) {
@ -476,7 +471,7 @@ ReadVcdActivities::checkClkPeriod(const Pin *pin,
sdc_network_->pathName(pin));
else {
double clk_period = clk->period();
if (abs((clk_period - sim_period) / clk_period) > sim_clk_period_tolerance_)
if (std::abs((clk_period - sim_period) / clk_period) > sim_clk_period_tolerance_)
// Warn if sim clock period differs from SDC by more than 10%.
report_->warn(1452, "clock %s vcd period %s differs from SDC clock period %s",
clk->name(),

10
sdc/ExceptionPath.cc
View File

@ -38,8 +38,6 @@
namespace sta {
using std::string;
static bool
thrusIntersectPts(ExceptionThruSeq *thrus1,
ExceptionThruSeq *thrus2,
@ -326,7 +324,7 @@ ExceptionPath::intersectsPts(ExceptionPath *exception,
const char *
ExceptionPath::fromThruToString(const Network *network) const
{
string str;
std::string str;
if (min_max_ != MinMaxAll::all()) {
str += " -";
str += min_max_->to_string();
@ -1186,7 +1184,7 @@ ExceptionFromTo::deletePinBefore(const Pin *pin,
const char *
ExceptionFromTo::asString(const Network *network) const
{
string str;
std::string str;
str += " ";
str += cmdKeyword();
str += " {";
@ -1360,7 +1358,7 @@ ExceptionTo::clone(const Network *network)
const char *
ExceptionTo::asString(const Network *network) const
{
string str;
std::string str;
if (hasObjects())
str += ExceptionFromTo::asString(network);
@ -1679,7 +1677,7 @@ ExceptionThru::~ExceptionThru()
const char *
ExceptionThru::asString(const Network *network) const
{
string str;
std::string str;
bool first = true;
int obj_count = 0;
if (pins_) {

36
sdc/Sdc.cc
View File

@ -62,8 +62,6 @@
namespace sta {
using std::swap;
bool
ClockPairLess::operator()(const ClockPair &pair1,
const ClockPair &pair2) const
@ -693,10 +691,10 @@ void
Sdc::swapDeratingFactors(Sdc *sdc1,
Sdc *sdc2)
{
swap(sdc1->derating_factors_, sdc2->derating_factors_);
swap(sdc1->net_derating_factors_, sdc2->net_derating_factors_);
swap(sdc1->inst_derating_factors_, sdc2->inst_derating_factors_);
swap(sdc1->cell_derating_factors_, sdc2->cell_derating_factors_);
std::swap(sdc1->derating_factors_, sdc2->derating_factors_);
std::swap(sdc1->net_derating_factors_, sdc2->net_derating_factors_);
std::swap(sdc1->inst_derating_factors_, sdc2->inst_derating_factors_);
std::swap(sdc1->cell_derating_factors_, sdc2->cell_derating_factors_);
}
void
@ -1818,7 +1816,7 @@ void
Sdc::swapClockInsertions(Sdc *sdc1,
Sdc *sdc2)
{
swap(sdc1->clk_insertions_, sdc2->clk_insertions_);
std::swap(sdc1->clk_insertions_, sdc2->clk_insertions_);
}
void
@ -2825,17 +2823,17 @@ void
Sdc::swapPortDelays(Sdc *sdc1,
Sdc *sdc2)
{
swap(sdc1->input_delays_, sdc2->input_delays_);
swap(sdc1->input_delay_pin_map_, sdc2->input_delay_pin_map_);
swap(sdc1->input_delay_ref_pin_map_, sdc2->input_delay_ref_pin_map_);
swap(sdc1->input_delay_leaf_pin_map_, sdc2->input_delay_leaf_pin_map_);
swap(sdc1->input_delay_internal_pin_map_, sdc2->input_delay_internal_pin_map_);
swap(sdc1->input_delay_index_, sdc2->input_delay_index_);
std::swap(sdc1->input_delays_, sdc2->input_delays_);
std::swap(sdc1->input_delay_pin_map_, sdc2->input_delay_pin_map_);
std::swap(sdc1->input_delay_ref_pin_map_, sdc2->input_delay_ref_pin_map_);
std::swap(sdc1->input_delay_leaf_pin_map_, sdc2->input_delay_leaf_pin_map_);
std::swap(sdc1->input_delay_internal_pin_map_, sdc2->input_delay_internal_pin_map_);
std::swap(sdc1->input_delay_index_, sdc2->input_delay_index_);
swap(sdc1->output_delays_, sdc2->output_delays_);
swap(sdc1->output_delay_pin_map_, sdc2->output_delay_pin_map_);
swap(sdc1->output_delay_ref_pin_map_, sdc2->output_delay_ref_pin_map_);
swap(sdc1->output_delay_leaf_pin_map_, sdc2->output_delay_leaf_pin_map_);
std::swap(sdc1->output_delays_, sdc2->output_delays_);
std::swap(sdc1->output_delay_pin_map_, sdc2->output_delay_pin_map_);
std::swap(sdc1->output_delay_ref_pin_map_, sdc2->output_delay_ref_pin_map_);
std::swap(sdc1->output_delay_leaf_pin_map_, sdc2->output_delay_leaf_pin_map_);
}
////////////////////////////////////////////////////////////////
@ -3374,8 +3372,8 @@ void
Sdc::swapPortExtCaps(Sdc *sdc1,
Sdc *sdc2)
{
swap(sdc1->port_ext_cap_map_, sdc2->port_ext_cap_map_);
swap(sdc1->net_wire_cap_map_, sdc2->net_wire_cap_map_);
std::swap(sdc1->port_ext_cap_map_, sdc2->port_ext_cap_map_);
std::swap(sdc1->net_wire_cap_map_, sdc2->net_wire_cap_map_);
}
////////////////////////////////////////////////////////////////

5
sdc/WriteSdc.cc
View File

@ -29,6 +29,7 @@
#include <ctime>
#include <vector>
#include <set>
#include <string>
#include "ContainerHelpers.hh"
#include "Zlib.hh"
@ -63,8 +64,6 @@
namespace sta {
using std::string;
typedef std::set<ClockSense*> ClockSenseSet;
typedef std::vector<ClockSense*> ClockSenseSeq;
@ -1167,7 +1166,7 @@ WriteSdc::writeDisabledEdgeSense(Edge *edge) const
{
gzprintf(stream_, "set_disable_timing ");
const char *sense = to_string(edge->sense());
string filter;
std::string filter;
stringPrint(filter, "sense == %s", sense);
writeGetTimingArcs(edge, filter.c_str());
gzprintf(stream_, "\n");

100
sdf/SdfReader.cc
View File

@ -26,6 +26,7 @@
#include <cstdarg>
#include <cctype>
#include <string>
#include "ContainerHelpers.hh"
#include "Zlib.hh"
@ -45,9 +46,6 @@
namespace sta {
using std::string;
using std::to_string;
class SdfTriple
{
public:
@ -69,14 +67,14 @@ public:
const std::string *port,
const std::string *cond);
~SdfPortSpec();
const string *port() const { return port_; }
const std::string *port() const { return port_; }
const Transition *transition() const { return tr_; }
const string *cond() const { return cond_; }
const std::string *cond() const { return cond_; }
private:
const Transition *tr_;
const string *port_;
const string *cond_; // timing checks only
const std::string *port_;
const std::string *cond_; // timing checks only
};
bool
@ -162,7 +160,7 @@ SdfReader::setDivider(char divider)
void
SdfReader::setTimescale(float multiplier,
const string *units)
const std::string *units)
{
if (multiplier == 1.0
|| multiplier == 10.0
@ -182,8 +180,8 @@ SdfReader::setTimescale(float multiplier,
}
void
SdfReader::interconnect(const string *from_pin_name,
const string *to_pin_name,
SdfReader::interconnect(const std::string *from_pin_name,
const std::string *to_pin_name,
SdfTripleSeq *triples)
{
// Ignore non-incremental annotations in incremental only mode.
@ -225,7 +223,7 @@ SdfReader::interconnect(const string *from_pin_name,
}
void
SdfReader::port(const string *to_pin_name,
SdfReader::port(const std::string *to_pin_name,
SdfTripleSeq *triples)
{
// Ignore non-incremental annotations in incremental only mode.
@ -296,13 +294,13 @@ SdfReader::setEdgeDelays(Edge *edge,
}
void
SdfReader::setCell(const string *cell_name)
SdfReader::setCell(const std::string *cell_name)
{
cell_name_ = cell_name;
}
void
SdfReader::setInstance(const string *instance_name)
SdfReader::setInstance(const std::string *instance_name)
{
if (instance_name) {
if (*instance_name == "*") {
@ -344,13 +342,13 @@ SdfReader::cellFinish()
void
SdfReader::iopath(SdfPortSpec *from_edge,
const string *to_port_name,
const std::string *to_port_name,
SdfTripleSeq *triples,
const string *cond,
const std::string *cond,
bool condelse)
{
if (instance_) {
const string *from_port_name = from_edge->port();
const std::string *from_port_name = from_edge->port();
Cell *cell = network_->cell(instance_);
Port *from_port = findPort(cell, from_port_name);
Port *to_port = findPort(cell, to_port_name);
@ -420,7 +418,7 @@ SdfReader::iopath(SdfPortSpec *from_edge,
Port *
SdfReader::findPort(const Cell *cell,
const string *port_name)
const std::string *port_name)
{
Port *port = network_->findPort(cell, port_name->c_str());
if (port == nullptr)
@ -437,8 +435,8 @@ SdfReader::timingCheck(const TimingRole *role,
SdfTriple *triple)
{
if (instance_) {
const string *data_port_name = data_edge->port();
const string *clk_port_name = clk_edge->port();
const std::string *data_port_name = data_edge->port();
const std::string *clk_port_name = clk_edge->port();
Cell *cell = network_->cell(instance_);
Port *data_port = findPort(cell, data_port_name);
Port *clk_port = findPort(cell, clk_port_name);
@ -515,8 +513,8 @@ SdfReader::annotateCheckEdges(Pin *data_pin,
bool match_generic)
{
bool matched = false;
const string *cond_start = data_edge->cond();
const string *cond_end = clk_edge->cond();
const std::string *cond_start = data_edge->cond();
const std::string *cond_end = clk_edge->cond();
// Timing check graph edges from clk to data.
Vertex *to_vertex = graph_->pinLoadVertex(data_pin);
// Fanin < fanout, so search for driver from load.
@ -557,7 +555,7 @@ SdfReader::timingCheckWidth(SdfPortSpec *edge,
// Ignore non-incremental annotations in incremental only mode.
if (!(is_incremental_only_ && !in_incremental_)
&& instance_) {
const string *port_name = edge->port();
const std::string *port_name = edge->port();
Cell *cell = network_->cell(instance_);
Port *port = findPort(cell, port_name);
if (port) {
@ -604,8 +602,8 @@ SdfReader::timingCheckSetupHold1(SdfPortSpec *data_edge,
const TimingRole *setup_role,
const TimingRole *hold_role)
{
const string *data_port_name = data_edge->port();
const string *clk_port_name = clk_edge->port();
const std::string *data_port_name = data_edge->port();
const std::string *clk_port_name = clk_edge->port();
Cell *cell = network_->cell(instance_);
Port *data_port = findPort(cell, data_port_name);
Port *clk_port = findPort(cell, clk_port_name);
@ -626,7 +624,7 @@ SdfReader::timingCheckPeriod(SdfPortSpec *edge,
// Ignore non-incremental annotations in incremental only mode.
if (!(is_incremental_only_ && !in_incremental_)
&& instance_) {
const string *port_name = edge->port();
const std::string *port_name = edge->port();
Cell *cell = network_->cell(instance_);
Port *port = findPort(cell, port_name);
if (port) {
@ -683,7 +681,7 @@ SdfReader::device(SdfTripleSeq *triples)
}
void
SdfReader::device(const string *to_port_name,
SdfReader::device(const std::string *to_port_name,
SdfTripleSeq *triples)
{
// Ignore non-incremental annotations in incremental only mode.
@ -799,7 +797,7 @@ SdfReader::setEdgeArcDelaysCondUse(Edge *edge,
}
bool
SdfReader::condMatch(const string *sdf_cond,
SdfReader::condMatch(const std::string *sdf_cond,
const std::string &lib_cond)
{
// If the sdf is not conditional it matches any library condition.
@ -828,24 +826,24 @@ SdfReader::condMatch(const string *sdf_cond,
SdfPortSpec *
SdfReader::makePortSpec(const Transition *tr,
const string *port,
const string *cond)
const std::string *port,
const std::string *cond)
{
return new SdfPortSpec(tr, port, cond);
}
SdfPortSpec *
SdfReader::makeCondPortSpec(const string *cond_port)
SdfReader::makeCondPortSpec(const std::string *cond_port)
{
// Search from end to find port name because condition may contain spaces.
string cond_port1(*cond_port);
std::string cond_port1(*cond_port);
trimRight(cond_port1);
auto port_idx = cond_port1.find_last_of(" ");
if (port_idx != cond_port1.npos) {
string *port1 = new string(cond_port1.substr(port_idx + 1));
std::string *port1 = new std::string(cond_port1.substr(port_idx + 1));
auto cond_end = cond_port1.find_last_not_of(" ", port_idx);
if (cond_end != cond_port1.npos) {
string *cond1 = new string(cond_port1.substr(0, cond_end + 1));
std::string *cond1 = new std::string(cond_port1.substr(0, cond_end + 1));
SdfPortSpec *port_spec = new SdfPortSpec(Transition::riseFall(),
port1,
cond1);
@ -913,13 +911,13 @@ SdfReader::setInIncremental(bool incr)
in_incremental_ = incr;
}
string *
SdfReader::unescaped(const string *token)
std::string *
SdfReader::unescaped(const std::string *token)
{
char path_escape = network_->pathEscape();
char path_divider = network_->pathDivider();
size_t token_length = token->size();
string *unescaped = new string;
std::string *unescaped = new std::string;
for (size_t i = 0; i < token_length; i++) {
char ch = (*token)[i];
if (ch == escape_) {
@ -955,11 +953,11 @@ SdfReader::unescaped(const string *token)
return unescaped;
}
string *
SdfReader::makePath(const string *head,
const string *tail)
std::string *
SdfReader::makePath(const std::string *head,
const std::string *tail)
{
string *path = new string(*head);
std::string *path = new std::string(*head);
*path += network_->pathDivider();
*path += *tail;
delete head;
@ -967,13 +965,13 @@ SdfReader::makePath(const string *head,
return path;
}
string *
SdfReader::makeBusName(string *base_name,
std::string *
SdfReader::makeBusName(std::string *base_name,
int index)
{
string *bus_name = unescaped(base_name);
std::string *bus_name = unescaped(base_name);
*bus_name += '[';
*bus_name += to_string(index);
*bus_name += std::to_string(index);
*bus_name += ']';
delete base_name;
return bus_name;
@ -1006,10 +1004,10 @@ SdfReader::sdfError(int id,
}
Pin *
SdfReader::findPin(const string *name)
SdfReader::findPin(const std::string *name)
{
if (path_) {
string path_name(path_);
std::string path_name(path_);
path_name += divider_;
path_name += *name;
Pin *pin = network_->findPin(path_name.c_str());
@ -1020,9 +1018,9 @@ SdfReader::findPin(const string *name)
}
Instance *
SdfReader::findInstance(const string *name)
SdfReader::findInstance(const std::string *name)
{
string inst_name;
std::string inst_name;
if (path_) {
inst_name = path_;
inst_name += divider_;
@ -1039,8 +1037,8 @@ SdfReader::findInstance(const string *name)
////////////////////////////////////////////////////////////////
SdfPortSpec::SdfPortSpec(const Transition *tr,
const string *port,
const string *cond) :
const std::string *port,
const std::string *cond) :
tr_(tr),
port_(port),
cond_(cond)
@ -1084,7 +1082,7 @@ SdfTriple::hasValue() const
////////////////////////////////////////////////////////////////
SdfScanner::SdfScanner(std::istream *stream,
const string &filename,
const std::string &filename,
SdfReader *reader,
Report *report) :
yyFlexLexer(stream),

50
sdf/SdfWriter.cc
View File

@ -45,8 +45,6 @@
namespace sta {
using std::string;
class SdfWriter : public StaState
{
public:
@ -108,10 +106,10 @@ protected:
void writeSdfTriple(float min,
float max);
void writeSdfDelay(double delay);
string sdfPortName(const Pin *pin);
string sdfPathName(const Pin *pin);
string sdfPathName(const Instance *inst);
string sdfName(const Instance *inst);
std::string sdfPortName(const Pin *pin);
std::string sdfPathName(const Pin *pin);
std::string sdfPathName(const Instance *inst);
std::string sdfName(const Instance *inst);
private:
char sdf_divider_;
@ -315,8 +313,8 @@ SdfWriter::writeInterconnectFromPin(Pin *drvr_pin)
Edge *edge = edge_iter.next();
if (edge->isWire()) {
Pin *load_pin = edge->to(graph_)->pin();
string drvr_pin_name = sdfPathName(drvr_pin);
string load_pin_name = sdfPathName(load_pin);
std::string drvr_pin_name = sdfPathName(drvr_pin);
std::string load_pin_name = sdfPathName(load_pin);
gzprintf(stream_, " (INTERCONNECT %s %s ",
drvr_pin_name.c_str(),
load_pin_name.c_str());
@ -347,7 +345,7 @@ SdfWriter::writeInstHeader(const Instance *inst)
{
gzprintf(stream_, " (CELL\n");
gzprintf(stream_, " (CELLTYPE \"%s\")\n", network_->cellName(inst));
string inst_name = sdfPathName(inst);
std::string inst_name = sdfPathName(inst);
gzprintf(stream_, " (INSTANCE %s)\n", inst_name.c_str());
}
@ -392,8 +390,8 @@ SdfWriter::writeIopaths(const Instance *inst,
gzprintf(stream_, " (COND %s\n", sdf_cond.c_str());
gzprintf(stream_, " ");
}
string from_pin_name = sdfPortName(from_pin);
string to_pin_name = sdfPortName(to_pin);
std::string from_pin_name = sdfPortName(from_pin);
std::string to_pin_name = sdfPortName(to_pin);
gzprintf(stream_, " (IOPATH %s %s ",
from_pin_name.c_str(),
to_pin_name.c_str());
@ -661,7 +659,7 @@ SdfWriter::writeCheck(Edge *edge,
if (!sdf_cond_start.empty())
gzprintf(stream_, "(COND %s ", sdf_cond_start.c_str());
string to_pin_name = sdfPortName(to_pin);
std::string to_pin_name = sdfPortName(to_pin);
if (use_data_edge) {
gzprintf(stream_, "(%s %s)",
sdfEdge(arc->toEdge()),
@ -678,7 +676,7 @@ SdfWriter::writeCheck(Edge *edge,
if (!sdf_cond_end.empty())
gzprintf(stream_, "(COND %s ", sdf_cond_end.c_str());
string from_pin_name = sdfPortName(from_pin);
std::string from_pin_name = sdfPortName(from_pin);
if (use_clk_edge)
gzprintf(stream_, "(%s %s)",
sdfEdge(arc->fromEdge()),
@ -704,7 +702,7 @@ SdfWriter::writeWidthCheck(const Pin *pin,
float min_width,
float max_width)
{
string pin_name = sdfPortName(pin);
std::string pin_name = sdfPortName(pin);
gzprintf(stream_, " (WIDTH (%s %s) ",
sdfEdge(hi_low->asTransition()),
pin_name.c_str());
@ -716,7 +714,7 @@ void
SdfWriter::writePeriodCheck(const Pin *pin,
float min_period)
{
string pin_name = sdfPortName(pin);
std::string pin_name = sdfPortName(pin);
gzprintf(stream_, " (PERIOD %s ", pin_name.c_str());
writeSdfTriple(min_period, min_period);
gzprintf(stream_, ")\n");
@ -734,16 +732,16 @@ SdfWriter::sdfEdge(const Transition *tr)
////////////////////////////////////////////////////////////////
string
std::string
SdfWriter::sdfPathName(const Pin *pin)
{
Instance *inst = network_->instance(pin);
if (network_->isTopInstance(inst))
return sdfPortName(pin);
else {
string inst_path = sdfPathName(inst);
string port_name = sdfPortName(pin);
string sdf_name = inst_path;
std::string inst_path = sdfPathName(inst);
std::string port_name = sdfPortName(pin);
std::string sdf_name = inst_path;
sdf_name += sdf_divider_;
sdf_name += port_name;
return sdf_name;
@ -751,15 +749,15 @@ SdfWriter::sdfPathName(const Pin *pin)
}
// Based on Network::pathName.
string
std::string
SdfWriter::sdfPathName(const Instance *instance)
{
InstanceSeq inst_path;
network_->path(instance, inst_path);
string path_name;
std::string path_name;
while (!inst_path.empty()) {
const Instance *inst = inst_path.back();
string inst_name = sdfName(inst);
std::string inst_name = sdfName(inst);
path_name += inst_name;
inst_path.pop_back();
if (!inst_path.empty())
@ -769,11 +767,11 @@ SdfWriter::sdfPathName(const Instance *instance)
}
// Escape for non-alpha numeric characters.
string
std::string
SdfWriter::sdfName(const Instance *inst)
{
const char *name = network_->name(inst);
string sdf_name;
std::string sdf_name;
const char *p = name;
while (*p) {
char ch = *p;
@ -789,12 +787,12 @@ SdfWriter::sdfName(const Instance *inst)
return sdf_name;
}
string
std::string
SdfWriter::sdfPortName(const Pin *pin)
{
const char *name = network_->portName(pin);
size_t name_length = strlen(name);
string sdf_name;
std::string sdf_name;
constexpr char bus_brkt_left = '[';
constexpr char bus_brkt_right = ']';

10
search/CheckTiming.cc
View File

@ -46,8 +46,6 @@
namespace sta {
using std::string;
CheckTiming::CheckTiming(StaState *sta) :
StaState(sta),
mode_(nullptr),
@ -202,7 +200,7 @@ CheckTiming::checkLoops()
loop_count++;
}
if (loop_count > 0) {
string error_msg;
std::string error_msg;
errorMsgSubst("Warning: There %is %d combinational loop%s in the design.",
loop_count, error_msg);
CheckError *error = new CheckError;
@ -362,7 +360,7 @@ CheckTiming::pushPinErrors(const char *msg,
{
if (!pins.empty()) {
CheckError *error = new CheckError;
string error_msg;
std::string error_msg;
errorMsgSubst(msg, pins.size(), error_msg);
// Copy the error strings because the error deletes them when it
// is deleted.
@ -384,7 +382,7 @@ CheckTiming::pushClkErrors(const char *msg,
{
if (!clks.empty()) {
CheckError *error = new CheckError;
string error_msg;
std::string error_msg;
errorMsgSubst(msg, clks.size(), error_msg);
// Copy the error strings because the error deletes them when it
// is deleted.
@ -404,7 +402,7 @@ CheckTiming::pushClkErrors(const char *msg,
void
CheckTiming::errorMsgSubst(const char *msg,
int obj_count,
string &error_msg)
std::string &error_msg)
{
for (const char *s = msg; *s; s++) {
char ch = *s;

10
search/ClkSkew.cc
View File

@ -49,8 +49,6 @@
namespace sta {
using std::abs;
ClkSkews::ClkSkews(StaState *sta) :
StaState(sta),
include_internal_latency_(true),
@ -148,7 +146,7 @@ ClkSkews::findWorstClkSkew(const SceneSeq &scenes,
float worst_skew = 0.0;
for (const auto& [clk, clk_skews] : skews_) {
float skew = clk_skews[setup_hold->index()].skew();
if (abs(skew) > abs(worst_skew))
if (std::abs(skew) > std::abs(worst_skew))
worst_skew = skew;
}
return worst_skew;
@ -210,8 +208,8 @@ ClkSkews::findClkSkew(ConstClockSeq &clks,
ClkSkew &partial_skew_val = partial_skew[setup_hold_idx];
float partial_skew1 = partial_skew_val.skew();
float final_skew1 = final_skew.skew();
if (abs(partial_skew1) > abs(final_skew1)
|| (fuzzyEqual(abs(partial_skew1), abs(final_skew1))
if (std::abs(partial_skew1) > std::abs(final_skew1)
|| (fuzzyEqual(std::abs(partial_skew1), std::abs(final_skew1))
// Break ties based on source/target path names.
&& ClkSkew::srcTgtPathNameLess(partial_skew_val, final_skew, this)))
final_skew = partial_skew_val;
@ -325,7 +323,7 @@ ClkSkews::findClkSkew(Vertex *src_vertex,
delayAsString(probe.crpr(this), this),
time_unit->asString(probe.skew()));
if (clk_skew.srcPath() == nullptr
|| abs(probe.skew()) > abs(clk_skew.skew()))
|| std::abs(probe.skew()) > std::abs(clk_skew.skew()))
clk_skew = probe;
}
}

20
search/Crpr.cc
View File

@ -24,8 +24,8 @@
#include "Crpr.hh"
#include <algorithm>
#include <cmath> // abs
#include <stdio.h>
#include "Debug.hh"
#include "Network.hh"
@ -44,9 +44,6 @@
namespace sta {
using std::min;
using std::abs;
CheckCrpr::CheckCrpr(StaState *sta) :
StaState(sta)
{
@ -60,11 +57,10 @@ CheckCrpr::maxCrpr(const ClkInfo *clk_info)
const Path *crpr_clk_path = clk_info->crprClkPath(this);
if (crpr_clk_path) {
Arrival other_arrival = otherMinMaxArrival(crpr_clk_path);
float crpr_diff = abs(delayAsFloat(crpr_clk_path->arrival(),
EarlyLate::late(),
this)
- delayAsFloat(other_arrival, EarlyLate::early(),
this));
float crpr_diff = std::abs(delayAsFloat(crpr_clk_path->arrival(),
EarlyLate::late(), this)
- delayAsFloat(other_arrival, EarlyLate::early(),
this));
return crpr_diff;
}
return 0.0F;
@ -284,7 +280,7 @@ CheckCrpr::findCrpr1(const Path *src_clk_path,
Arrival tgt_arrival = tgt_clk_path->arrival();
float src_clk_time = src_clk_path->clkEdge(this)->time();
float tgt_clk_time = tgt_clk_path->clkEdge(this)->time();
float crpr_mean = abs(delayAsFloat(src_arrival) - src_clk_time
float crpr_mean = std::abs(delayAsFloat(src_arrival) - src_clk_time
- (delayAsFloat(tgt_arrival) - tgt_clk_time));
// Remove the sigma from both source and target path arrivals.
float crpr_sigma2 = delaySigma2(src_arrival, src_el)
@ -300,7 +296,7 @@ CheckCrpr::findCrpr1(const Path *src_clk_path,
delayAsString(src_delta, this));
debugPrint(debug_, "crpr", 2, " tgt delta %s",
delayAsString(tgt_delta, this));
float common_delay = min(src_delta, tgt_delta);
float common_delay = std::min(src_delta, tgt_delta);
debugPrint(debug_, "crpr", 2, " %s delta %s",
network_->pathName(src_clk_path->pin(this)),
delayAsString(common_delay, this));
@ -312,7 +308,7 @@ float
CheckCrpr::crprArrivalDiff(const Path *path)
{
Arrival other_arrival = otherMinMaxArrival(path);
float crpr_diff = abs(delayAsFloat(path->arrival())
float crpr_diff = std::abs(delayAsFloat(path->arrival())
- delayAsFloat(other_arrival));
return crpr_diff;
}

6
search/Genclks.cc
View File

@ -24,6 +24,8 @@
#include "Genclks.hh"
#include <cmath>
#include "ContainerHelpers.hh"
#include "Stats.hh"
#include "Debug.hh"
@ -47,8 +49,6 @@
namespace sta {
using std::max;
class GenclkInfo
{
public:
@ -151,7 +151,7 @@ Genclks::clkPinMaxLevel(const Clock *clk) const
Level max_level = 0;
for (const Pin *pin : clk->leafPins()) {
Vertex *vertex = srcPath(pin);
max_level = max(max_level, vertex->level());
max_level = std::max(max_level, vertex->level());
}
return max_level;
}

15
search/Levelize.cc
View File

@ -25,6 +25,7 @@
#include "Levelize.hh"
#include <algorithm>
#include <cmath>
#include <deque>
#include "ContainerHelpers.hh"
@ -43,8 +44,6 @@
namespace sta {
using std::max;
Levelize::Levelize(StaState *sta) :
StaState(sta),
levelized_(false),
@ -500,16 +499,16 @@ Levelize::assignLevels(VertexSeq &topo_sorted)
Edge *edge = edge_iter.next();
Vertex *to_vertex = edge->to(graph_);
if (searchThru(edge))
setLevel(to_vertex, max(to_vertex->level(),
vertex->level() + level_space_));
setLevel(to_vertex, std::max(to_vertex->level(),
vertex->level() + level_space_));
}
// Levelize bidirect driver as if it was a fanout of the bidirect load.
const Pin *pin = vertex->pin();
if (graph_delay_calc_->bidirectDrvrSlewFromLoad(pin)
&& !vertex->isBidirectDriver()) {
Vertex *to_vertex = graph_->pinDrvrVertex(pin);
setLevel(to_vertex, max(to_vertex->level(),
vertex->level() + level_space_));
setLevel(to_vertex, std::max(to_vertex->level(),
vertex->level() + level_space_));
}
}
}
@ -541,7 +540,7 @@ Levelize::setLevel(Vertex *vertex,
vertex->to_string(this).c_str(),
level);
vertex->setLevel(level);
max_level_ = max(level, max_level_);
max_level_ = std::max(level, max_level_);
if (level >= Graph::vertex_level_max)
report_->critical(616, "maximum logic level exceeded");
}
@ -676,7 +675,7 @@ Levelize::setLevelIncr(Vertex *vertex,
observer_->levelChangedBefore(vertex);
vertex->setLevel(level);
}
max_level_ = max(level, max_level_);
max_level_ = std::max(level, max_level_);
if (level >= Graph::vertex_level_max)
criticalError(618, "maximum logic level exceeded");
}

22
search/MakeTimingModel.cc
View File

@ -26,6 +26,7 @@
#include "MakeTimingModelPvt.hh"
#include <algorithm>
#include <cmath>
#include <map>
#include "Debug.hh"
@ -51,11 +52,6 @@
namespace sta {
using std::string;
using std::min;
using std::max;
using std::make_shared;
LibertyLibrary *
makeTimingModel(const char *lib_name,
const char *cell_name,
@ -305,7 +301,7 @@ MakeEndTimingArcs::visit(PathEnd *path_end)
margins.value(input_rf_, min_max, max_margin, max_exists);
// Always max margin, even for min/hold checks.
margins.setValue(input_rf_, min_max,
max_exists ? max(max_margin, delay1) : delay1);
max_exists ? std::max(max_margin, delay1) : delay1);
}
}
@ -606,7 +602,7 @@ MakeTimingModel::makeScalarCheckModel(float value,
ScaleFactorType scale_factor_type,
const RiseFall *rf)
{
TablePtr table = make_shared<Table>(value);
TablePtr table = std::make_shared<Table>(value);
TableTemplate *tbl_template =
library_->findTableTemplate("scalar", TableTemplateType::delay);
TableModel *table_model = new TableModel(table, tbl_template,
@ -620,8 +616,8 @@ MakeTimingModel::makeGateModelScalar(Delay delay,
Slew slew,
const RiseFall *rf)
{
TablePtr delay_table = make_shared<Table>(delayAsFloat(delay));
TablePtr slew_table = make_shared<Table>(delayAsFloat(slew));
TablePtr delay_table = std::make_shared<Table>(delayAsFloat(delay));
TablePtr slew_table = std::make_shared<Table>(delayAsFloat(slew));
TableTemplate *tbl_template =
library_->findTableTemplate("scalar", TableTemplateType::delay);
TableModel *delay_model = new TableModel(delay_table, tbl_template,
@ -636,7 +632,7 @@ TimingModel *
MakeTimingModel::makeGateModelScalar(Delay delay,
const RiseFall *rf)
{
TablePtr delay_table = make_shared<Table>(delayAsFloat(delay));
TablePtr delay_table = std::make_shared<Table>(delayAsFloat(delay));
TableTemplate *tbl_template =
library_->findTableTemplate("scalar", TableTemplateType::delay);
TableModel *delay_model = new TableModel(delay_table, tbl_template,
@ -708,8 +704,8 @@ MakeTimingModel::makeGateModelTable(const Pin *output_pin,
std::make_shared<TableAxis>(TableAxisVariable::total_output_net_capacitance,
std::move(axis_values));
TablePtr delay_table = make_shared<Table>(load_values, load_axis);
TablePtr slew_table = make_shared<Table>(slew_values, load_axis);
TablePtr delay_table = std::make_shared<Table>(load_values, load_axis);
TablePtr slew_table = std::make_shared<Table>(slew_values, load_axis);
TableTemplate *model_template = ensureTableTemplate(drvr_template,
load_axis);
@ -738,7 +734,7 @@ MakeTimingModel::ensureTableTemplate(const TableTemplate *drvr_template,
{
TableTemplate *model_template = findKey(template_map_, drvr_template);
if (model_template == nullptr) {
string template_name = "template_";
std::string template_name = "template_";
template_name += std::to_string(tbl_template_index_++);
model_template = library_->makeTableTemplate(template_name,

30
search/Property.cc
View File

@ -24,6 +24,9 @@
#include "Property.hh"
#include <algorithm>
#include <string>
#include "StringUtil.hh"
#include "MinMax.hh"
#include "Transition.hh"
@ -43,22 +46,19 @@
namespace sta {
using std::string;
using std::max;
class PropertyUnknown : public Exception
{
public:
PropertyUnknown(const char *type,
const char *property);
PropertyUnknown(const char *type,
const string property);
const std::string property);
virtual ~PropertyUnknown() {}
virtual const char *what() const noexcept;
private:
const char *type_;
const string property_;
const std::string property_;
};
PropertyUnknown::PropertyUnknown(const char *type,
@ -70,7 +70,7 @@ PropertyUnknown::PropertyUnknown(const char *type,
}
PropertyUnknown::PropertyUnknown(const char *type,
const string property) :
const std::string property) :
Exception(),
type_(type),
property_(property)
@ -556,7 +556,7 @@ PropertyValue::operator=(PropertyValue &&value) noexcept
return *this;
}
string
std::string
PropertyValue::to_string(const Network *network) const
{
switch (type_) {
@ -683,9 +683,9 @@ Properties::getProperty(const Cell *cell,
return PropertyValue(network->name(cell));
else if (property == "full_name") {
Library *lib = network->library(cell);
string lib_name = network->name(lib);
string cell_name = network->name(cell);
string full_name = lib_name + network->pathDivider() + cell_name;
std::string lib_name = network->name(lib);
std::string cell_name = network->name(cell);
std::string full_name = lib_name + network->pathDivider() + cell_name;
return PropertyValue(full_name);
}
else if (property == "library")
@ -714,9 +714,9 @@ Properties::getProperty(const LibertyCell *cell,
else if (property == "full_name") {
Network *network = sta_->cmdNetwork();
LibertyLibrary *lib = cell->libertyLibrary();
string lib_name = lib->name();
string cell_name = cell->name();
string full_name = lib_name + network->pathDivider() + cell_name;
std::string lib_name = lib->name();
std::string cell_name = cell->name();
std::string full_name = lib_name + network->pathDivider() + cell_name;
return PropertyValue(full_name);
}
else if (property == "filename")
@ -1099,7 +1099,7 @@ Properties::getProperty(Edge *edge,
const std::string &property)
{
if (property == "full_name") {
string full_name = edge->to_string(sta_);
std::string full_name = edge->to_string(sta_);
return PropertyValue(full_name);
}
if (property == "delay_min_fall")
@ -1159,7 +1159,7 @@ Properties::getProperty(TimingArcSet *arc_set,
const char *from = arc_set->from()->name();
const char *to = arc_set->to()->name();
const char *cell_name = arc_set->libertyCell()->name();
string name;
std::string name;
stringPrint(name, "%s %s -> %s", cell_name, from, to);
return PropertyValue(name);
}

163
search/ReportPath.cc
View File

@ -23,6 +23,7 @@
// This notice may not be removed or altered from any source distribution.
#include <algorithm> // reverse
#include <string>
#include "ReportPath.hh"
@ -63,8 +64,6 @@
namespace sta {
using std::string;
static void
hierPinsAbove(const Net *net,
const Network *network,
@ -373,7 +372,7 @@ ReportPath::reportPathEndHeader() const
void
ReportPath::reportPathEndFooter() const
{
string header;
std::string header;
switch (format_) {
case ReportPathFormat::full:
case ReportPathFormat::full_clock:
@ -474,7 +473,7 @@ ReportPath::reportFull(const PathEndCheck *end) const
reportSlack(end);
}
string
std::string
ReportPath::checkRoleString(const PathEnd *end) const
{
return stdstrPrint("library %s time",
@ -486,7 +485,7 @@ ReportPath::reportEndpoint(const PathEndCheck *end) const
{
Instance *inst = network_->instance(end->vertex(this)->pin());
const char *inst_name = cmd_network_->pathName(inst);
string clk_name = tgtClkName(end);
std::string clk_name = tgtClkName(end);
const char *rise_fall = asRisingFalling(end->targetClkEndTrans(this));
const TimingRole *check_role = end->checkRole(this);
const TimingRole *check_generic_role = check_role->genericRole();
@ -593,7 +592,7 @@ ReportPath::reportEndpoint(const PathEndLatchCheck *end) const
{
Instance *inst = network_->instance(end->vertex(this)->pin());
const char *inst_name = cmd_network_->pathName(inst);
string clk_name = tgtClkName(end);
std::string clk_name = tgtClkName(end);
const char *reg_desc = latchDesc(end);
auto reason = stdstrPrint("%s clocked by %s", reg_desc, clk_name.c_str());
reportEndpoint(inst_name, reason);
@ -625,7 +624,7 @@ ReportPath::reportBorrowing(const PathEndLatchCheck *end,
if (borrow_limit_exists)
reportLineTotal("user max time borrow", max_borrow, early_late);
else {
string tgt_clk_name = tgtClkName(end);
std::string tgt_clk_name = tgtClkName(end);
Arrival tgt_clk_width = end->targetClkWidth(this);
const Path *tgt_clk_path = end->targetClkPath();
if (tgt_clk_path->clkInfo(search_)->isPropagated()) {
@ -691,7 +690,7 @@ ReportPath::reportEndpoint(const PathEndPathDelay *end) const
else {
Instance *inst = network_->instance(end->vertex(this)->pin());
const char *inst_name = cmd_network_->pathName(inst);
string clk_name = tgtClkName(end);
std::string clk_name = tgtClkName(end);
const char *reg_desc = clkRegLatchDesc(end);
auto reason = stdstrPrint("%s clocked by %s", reg_desc, clk_name.c_str());
reportEndpoint(inst_name, reason);
@ -723,7 +722,7 @@ ReportPath::reportFull(const PathEndPathDelay *end) const
if (min_max == MinMax::max())
margin = -margin;
string delay_msg = min_max->to_string() + "_delay";
std::string delay_msg = min_max->to_string() + "_delay";
float delay = path_delay->delay();
reportLine(delay_msg.c_str(), delay, delay, early_late);
if (!path_delay->ignoreClkLatency()) {
@ -821,7 +820,7 @@ ReportPath::reportEndpointOutputDelay(const PathEndClkConstrained *end) const
if (network_->isTopLevelPort(pin)) {
// Pin direction is "output" even for bidirects.
if (tgt_clk) {
string clk_name = tgtClkName(end);
std::string clk_name = tgtClkName(end);
auto reason = stdstrPrint("output port clocked by %s", clk_name.c_str());
reportEndpoint(pin_name, reason);
}
@ -830,7 +829,7 @@ ReportPath::reportEndpointOutputDelay(const PathEndClkConstrained *end) const
}
else {
if (tgt_clk) {
string clk_name = tgtClkName(end);
std::string clk_name = tgtClkName(end);
auto reason = stdstrPrint("internal path endpoint clocked by %s",
clk_name.c_str());
@ -875,7 +874,7 @@ ReportPath::reportEndpoint(const PathEndGatedClock *end) const
{
Instance *inst = network_->instance(end->vertex(this)->pin());
const char *inst_name = cmd_network_->pathName(inst);
string clk_name = tgtClkName(end);
std::string clk_name = tgtClkName(end);
const RiseFall *clk_end_rf = end->targetClkEndTrans(this);
const RiseFall *clk_rf =
(end->minMax(this) == MinMax::max()) ? clk_end_rf : clk_end_rf->opposite();
@ -955,7 +954,7 @@ ReportPath::reportEndpoint(const PathEndDataCheck *end) const
void
ReportPath::reportEndHeader() const
{
string line;
std::string line;
// Line one.
reportDescription("", line);
line += ' ';
@ -981,8 +980,8 @@ ReportPath::reportEndHeader() const
void
ReportPath::reportEndLine(const PathEnd *end) const
{
string line;
string endpoint = pathEndpoint(end);
std::string line;
std::string endpoint = pathEndpoint(end);
reportDescription(endpoint.c_str(), line);
const EarlyLate *early_late = end->pathEarlyLate(this);
reportSpaceFieldDelay(end->requiredTimeOffset(this), early_late, line);
@ -996,7 +995,7 @@ ReportPath::reportEndLine(const PathEnd *end) const
void
ReportPath::reportSummaryHeader() const
{
string line;
std::string line;
reportDescription("Startpoint", line);
line += ' ';
reportDescription("Endpoint", line);
@ -1010,7 +1009,7 @@ ReportPath::reportSummaryHeader() const
void
ReportPath::reportSummaryLine(const PathEnd *end) const
{
string line;
std::string line;
PathExpanded expanded(end->path(), this);
const EarlyLate *early_late = end->pathEarlyLate(this);
auto startpoint = pathStartpoint(end, expanded);
@ -1025,7 +1024,7 @@ ReportPath::reportSummaryLine(const PathEnd *end) const
report_->reportLineString(line);
}
string
std::string
ReportPath::pathStartpoint(const PathEnd *end,
const PathExpanded &expanded) const
{
@ -1043,7 +1042,7 @@ ReportPath::pathStartpoint(const PathEnd *end,
}
}
string
std::string
ReportPath::pathEndpoint(const PathEnd *end) const
{
Pin *pin = end->vertex(this)->pin();
@ -1078,7 +1077,7 @@ void
ReportPath::reportJson(const PathEnd *end,
bool last) const
{
string result;
std::string result;
result += "{\n";
stringAppend(result, " \"type\": \"%s\",\n", end->typeName());
stringAppend(result, " \"path_group\": \"%s\",\n",
@ -1149,7 +1148,7 @@ ReportPath::reportJson(const PathEnd *end,
void
ReportPath::reportJson(const Path *path) const
{
string result;
std::string result;
result += "{\n";
reportJson(path, "path", 0, false, result);
result += "}\n";
@ -1161,7 +1160,7 @@ ReportPath::reportJson(const Path *path,
const char *path_name,
int indent,
bool trailing_comma,
string &result) const
std::string &result) const
{
PathExpanded expanded(path, this);
reportJson(expanded, path_name, indent, trailing_comma, result);
@ -1172,7 +1171,7 @@ ReportPath::reportJson(const PathExpanded &expanded,
const char *path_name,
int indent,
bool trailing_comma,
string &result) const
std::string &result) const
{
stringAppend(result, "%*s\"%s\": [\n", indent, "", path_name);
for (size_t i = expanded.startIndex(); i < expanded.size(); i++) {
@ -1256,7 +1255,7 @@ ReportPath::reportJson(const PathExpanded &expanded,
void
ReportPath::reportSlackOnlyHeader() const
{
string line;
std::string line;
reportDescription("Group", line);
line += ' ';
reportField("Slack", field_total_, line);
@ -1268,7 +1267,7 @@ ReportPath::reportSlackOnlyHeader() const
void
ReportPath::reportSlackOnly(const PathEnd *end) const
{
string line;
std::string line;
const EarlyLate *early_late = end->pathEarlyLate(this);
reportDescription(end->pathGroup()->name(), line);
if (end->isUnconstrained())
@ -1318,7 +1317,7 @@ ReportPath::reportMpwChecks(const MinPulseWidthCheckSeq &checks,
void
ReportPath::reportMpwHeaderShort() const
{
string line;
std::string line;
reportDescription("", line);
line += ' ';
reportField("Required", field_total_, line);
@ -1342,7 +1341,7 @@ ReportPath::reportMpwHeaderShort() const
void
ReportPath::reportShort(const MinPulseWidthCheck &check) const
{
string line;
std::string line;
const char *pin_name = cmd_network_->pathName(check.pin(this));
const char *hi_low = mpwCheckHiLow(check);
auto what = stdstrPrint("%s (%s)", pin_name, hi_low);
@ -1356,7 +1355,7 @@ ReportPath::reportShort(const MinPulseWidthCheck &check) const
void
ReportPath::reportVerbose(const MinPulseWidthCheck &check) const
{
string line;
std::string line;
const char *pin_name = cmd_network_->pathName(check.pin(this));
line += "Pin: ";
line += pin_name;
@ -1462,7 +1461,7 @@ ReportPath::reportChecks(const MinPeriodCheckSeq &checks,
void
ReportPath::reportPeriodHeaderShort() const
{
string line;
std::string line;
reportDescription("", line);
line += ' ';
reportField("", field_total_, line);
@ -1488,7 +1487,7 @@ ReportPath::reportPeriodHeaderShort() const
void
ReportPath::reportShort(const MinPeriodCheck &check) const
{
string line;
std::string line;
const char *pin_name = cmd_network_->pathName(check.pin());
reportDescription(pin_name, line);
reportSpaceFieldDelay(check.period(), EarlyLate::early(), line);
@ -1500,7 +1499,7 @@ ReportPath::reportShort(const MinPeriodCheck &check) const
void
ReportPath::reportVerbose(const MinPeriodCheck &check) const
{
string line;
std::string line;
const char *pin_name = cmd_network_->pathName(check.pin());
line += "Pin: ";
line += pin_name;
@ -1536,7 +1535,7 @@ ReportPath::reportChecks(const MaxSkewCheckSeq &checks,
void
ReportPath::reportMaxSkewHeaderShort() const
{
string line;
std::string line;
reportDescription("", line);
line += ' ';
reportField("Required", field_total_, line);
@ -1562,7 +1561,7 @@ ReportPath::reportMaxSkewHeaderShort() const
void
ReportPath::reportShort(const MaxSkewCheck &check) const
{
string line;
std::string line;
Pin *clk_pin = check.clkPin(this);
const char *clk_pin_name = network_->pathName(clk_pin);
TimingArc *check_arc = check.checkArc();
@ -1581,7 +1580,7 @@ ReportPath::reportShort(const MaxSkewCheck &check) const
void
ReportPath::reportVerbose(const MaxSkewCheck &check) const
{
string line;
std::string line;
const char *clk_pin_name = cmd_network_->pathName(check.clkPin(this));
line += "Constrained Pin: ";
line += clk_pin_name;
@ -1617,7 +1616,7 @@ ReportPath::reportSkewClkPath(const char *arrival_msg,
const EarlyLate *early_late = clk_path->minMax(this);
const RiseFall *clk_rf = clk_edge->transition();
const RiseFall *clk_end_rf = clk_path->transition(this);
string clk_name = clkName(clk, clk_end_rf != clk_rf);
std::string clk_name = clkName(clk, clk_end_rf != clk_rf);
float clk_time = clk_edge->time();
const Arrival &clk_arrival = search_->clkPathArrival(clk_path);
Arrival clk_delay = clk_arrival - clk_time;
@ -1656,7 +1655,7 @@ ReportPath::reportSkewClkPath(const char *arrival_msg,
void
ReportPath::reportLimitShortHeader(const ReportField *field) const
{
string line;
std::string line;
reportDescription("Pin", line);
line += ' ';
reportField("Limit", field, line);
@ -1676,7 +1675,7 @@ ReportPath::reportLimitShort(const ReportField *field,
float limit,
float slack) const
{
string line;
std::string line;
const char *pin_name = cmd_network_->pathName(pin);
reportDescription(pin_name, line);
line += ' ';
@ -1701,7 +1700,7 @@ ReportPath::reportLimitVerbose(const ReportField *field,
const Scene *scene,
const MinMax *min_max) const
{
string line;
std::string line;
line += "Pin ";
line += cmd_network_->pathName(pin);
line += ' ';
@ -1781,7 +1780,7 @@ ReportPath::reportStartpoint(const PathEnd *end,
const Path *clk_path = expanded.clkPath();
bool clk_inverted = clk_path
&& clk_rf != clk_path->transition(this);
string clk_name = clkName(clk, clk_inverted);
std::string clk_name = clkName(clk, clk_inverted);
const char *reg_desc = edgeRegLatchDesc(prev_edge, prev_arc);
auto reason = stdstrPrint("%s clocked by %s", reg_desc, clk_name.c_str());
reportStartpoint(inst_name, reason);
@ -1829,7 +1828,7 @@ ReportPath::pathFromClkPin(const Path *path,
void
ReportPath::reportStartpoint(const char *start,
const string reason) const
const std::string reason) const
{
reportStartEndPoint(start, reason, "Startpoint");
}
@ -1878,17 +1877,17 @@ ReportPath::reportUnclockedEndpoint(const PathEnd *end,
void
ReportPath::reportEndpoint(const char *end,
const string reason) const
const std::string reason) const
{
reportStartEndPoint(end, reason, "Endpoint");
}
void
ReportPath::reportStartEndPoint(const char *pt,
string reason,
std::string reason,
const char *key) const
{
string line;
std::string line;
// Account for punctuation in the line.
int line_len = strlen(key) + 2 + strlen(pt) + 2 + reason.size() + 1;
if (!no_split_
@ -1921,7 +1920,7 @@ ReportPath::reportStartEndPoint(const char *pt,
void
ReportPath::reportGroup(const PathEnd *end) const
{
string line;
std::string line;
line = "Path Group: ";
PathGroup *group = end->pathGroup();
line += group ? group->name() : "(none)";
@ -1946,13 +1945,13 @@ ReportPath::reportGroup(const PathEnd *end) const
////////////////////////////////////////////////////////////////
string
std::string
ReportPath::checkRoleReason(const PathEnd *end) const
{
return stdstrPrint("%s time", end->checkRole(this)->to_string().c_str());
}
string
std::string
ReportPath::tgtClkName(const PathEnd *end) const
{
const ClockEdge *tgt_clk_edge = end->targetClkEdge(this);
@ -1962,11 +1961,11 @@ ReportPath::tgtClkName(const PathEnd *end) const
return clkName(tgt_clk, clk_end_rf != clk_rf);
}
string
std::string
ReportPath::clkName(const Clock *clk,
bool inverted) const
{
string name = clk->name();
std::string name = clk->name();
if (inverted)
name += '\'';
return name;
@ -2088,7 +2087,7 @@ ReportPath::reportSrcClkAndPath(const Path *path,
}
}
}
string clk_name = clkName(clk, clk_rf != clk_end_rf);
std::string clk_name = clkName(clk, clk_rf != clk_end_rf);
bool clk_used_as_data = pathFromClkPin(expanded);
bool is_prop = isPropagated(path);
@ -2185,7 +2184,7 @@ ReportPath::reportTgtClk(const PathEnd *end,
Clock *clk = clk_edge->clock();
const RiseFall *clk_rf = clk_edge->transition();
const RiseFall *clk_end_rf = end->targetClkEndTrans(this);
string clk_name = clkName(clk, clk_end_rf != clk_rf);
std::string clk_name = clkName(clk, clk_end_rf != clk_rf);
float clk_time = prev_time
+ end->targetClkTime(this)
+ end->targetClkMcpAdjustment(this)
@ -2439,7 +2438,7 @@ ReportPath::reportPathLine(const Path *path,
{
Vertex *vertex = path->vertex(this);
Pin *pin = vertex->pin();
const string what = descriptionField(vertex);
const std::string what = descriptionField(vertex);
const RiseFall *rf = path->transition(this);
bool is_driver = network_->isDriver(pin);
const EarlyLate *early_late = path->minMax(this);
@ -2449,7 +2448,7 @@ ReportPath::reportPathLine(const Path *path,
Slew slew = graph_->slew(vertex, rf, slew_index);
float cap = field_blank_;
Instance *inst = network_->instance(pin);
string src_attr = "";
std::string src_attr = "";
if (inst)
src_attr = network_->getAttribute(inst, "src");
// Don't show capacitance field for input pins.
@ -2462,7 +2461,7 @@ ReportPath::reportPathLine(const Path *path,
void
ReportPath::reportRequired(const PathEnd *end,
string margin_msg) const
std::string margin_msg) const
{
Required req_time = end->requiredTimeOffset(this);
const EarlyLate *early_late = end->clkEarlyLate(this);
@ -2503,7 +2502,7 @@ ReportPath::reportSlack(Slack slack) const
void
ReportPath::reportSpaceSlack(const PathEnd *end,
string &result) const
std::string &result) const
{
Slack slack = end->slack(this);
reportSpaceSlack(slack, result);
@ -2511,7 +2510,7 @@ ReportPath::reportSpaceSlack(const PathEnd *end,
void
ReportPath::reportSpaceSlack(Slack slack,
string &result) const
std::string &result) const
{
const EarlyLate *early_late = EarlyLate::early();
reportSpaceFieldDelay(slack, early_late, result);
@ -2718,7 +2717,7 @@ ReportPath::reportPath6(const Path *path,
bool is_clk_start = path1->vertex(this) == clk_start;
bool is_clk = path1->isClock(search_);
Instance *inst = network_->instance(pin);
string src_attr = "";
std::string src_attr = "";
if (inst)
src_attr = network_->getAttribute(inst, "src");
// Always show the search start point (register clk pin).
@ -2804,13 +2803,13 @@ ReportPath::reportPath6(const Path *path,
cap = graph_delay_calc_->loadCap(pin, rf, scene, min_max);
if (field_fanout_->enabled())
fanout = drvrFanout(vertex, scene, min_max);
const string what = descriptionField(vertex);
const std::string what = descriptionField(vertex);
reportLine(what.c_str(), cap, slew, fanout,
incr, time, false, min_max, rf, src_attr,
line_case);
if (report_net_) {
const string what2 = descriptionNet(pin);
const std::string what2 = descriptionNet(pin);
reportLine(what2.c_str(), field_blank_, field_blank_, field_blank_,
field_blank_, field_blank_, false, min_max,
nullptr, src_attr, "");
@ -2823,7 +2822,7 @@ ReportPath::reportPath6(const Path *path,
|| (i == 0)
|| (i == path_last_index)
|| is_clk_start) {
const string what = descriptionField(vertex);
const std::string what = descriptionField(vertex);
reportLine(what.c_str(), field_blank_, slew, field_blank_,
incr, time, false, min_max, rf, src_attr,
line_case);
@ -2843,7 +2842,7 @@ ReportPath::reportHierPinsThru(const Path *path) const
const Edge *prev_edge = path->prevEdge(this);
if (prev_edge && prev_edge->isWire()) {
for (const Pin *hpin : hierPinsThruEdge(prev_edge, network_, graph_)) {
const string what = descriptionField(hpin);
const std::string what = descriptionField(hpin);
reportLine(what.c_str(), field_blank_, field_blank_, field_blank_,
field_blank_, field_blank_, false, path->minMax(this),
nullptr, "", "");
@ -2874,13 +2873,13 @@ ReportPath::nextArcAnnotated(const Path *next_path,
return graph_->arcDelayAnnotated(edge, arc, ap_index);
}
string
std::string
ReportPath::descriptionField(const Vertex *vertex) const
{
return descriptionField(vertex->pin());
}
string
std::string
ReportPath::descriptionField(const Pin *pin) const
{
const char *pin_name = cmd_network_->pathName(pin);
@ -2906,7 +2905,7 @@ ReportPath::descriptionField(const Pin *pin) const
return stdstrPrint("%s (%s)", pin_name, name2);
}
string
std::string
ReportPath::descriptionNet(const Pin *pin) const
{
if (network_->isTopLevelPort(pin)) {
@ -3028,7 +3027,7 @@ ReportPath::pathInputDelayRefPath(const Path *path,
void
ReportPath::reportPathHeader() const
{
string line;
std::string line;
bool first_field = true;
for (const ReportField *field : fields_) {
if (field->enabled()) {
@ -3125,10 +3124,10 @@ ReportPath::reportLine(const char *what,
bool total_with_minus,
const EarlyLate *early_late,
const RiseFall *rf,
string src_attr,
std::string src_attr,
const char *line_case) const
{
string line;
std::string line;
size_t field_index = 0;
bool first_field = true;
for (const ReportField *field : fields_) {
@ -3180,7 +3179,7 @@ ReportPath::reportLine(const char *what,
field_index++;
}
// Trim trailing spaces and report the line.
string line_stdstr = line;
std::string line_stdstr = line;
trimRight(line_stdstr);
report_->reportLineString(line_stdstr.c_str());
}
@ -3211,7 +3210,7 @@ ReportPath::reportLineTotal1(const char *what,
bool incr_with_minus,
const EarlyLate *early_late) const
{
string line;
std::string line;
reportDescription(what, line);
line += ' ';
if (incr_with_minus)
@ -3231,7 +3230,7 @@ ReportPath::reportDashLineTotal() const
void
ReportPath::reportDescription(const char *what,
string &line) const
std::string &line) const
{
reportDescription(what, false, false, line);
}
@ -3240,7 +3239,7 @@ void
ReportPath::reportDescription(const char *what,
bool first_field,
bool last_field,
string &line) const
std::string &line) const
{
line += what;
int length = strlen(what);
@ -3260,7 +3259,7 @@ ReportPath::reportDescription(const char *what,
void
ReportPath::reportFieldTime(float value,
ReportField *field,
string &line) const
std::string &line) const
{
if (delayAsFloat(value) == field_blank_)
reportFieldBlank(field, line);
@ -3275,7 +3274,7 @@ ReportPath::reportFieldTime(float value,
void
ReportPath::reportSpaceFieldTime(float value,
string &line) const
std::string &line) const
{
line += ' ';
reportFieldTime(value, field_total_, line);
@ -3284,7 +3283,7 @@ ReportPath::reportSpaceFieldTime(float value,
void
ReportPath::reportSpaceFieldDelay(Delay value,
const EarlyLate *early_late,
string &line) const
std::string &line) const
{
line += ' ';
reportTotalDelay(value, early_late, line);
@ -3293,7 +3292,7 @@ ReportPath::reportSpaceFieldDelay(Delay value,
void
ReportPath::reportTotalDelay(Delay value,
const EarlyLate *early_late,
string &line) const
std::string &line) const
{
const char *str = delayAsString(value, early_late, this, digits_);
if (stringEq(str, minus_zero_))
@ -3307,7 +3306,7 @@ void
ReportPath::reportFieldDelayMinus(Delay value,
const EarlyLate *early_late,
const ReportField *field,
string &line) const
std::string &line) const
{
if (delayAsFloat(value) == field_blank_)
reportFieldBlank(field, line);
@ -3327,7 +3326,7 @@ void
ReportPath::reportFieldDelay(Delay value,
const EarlyLate *early_late,
const ReportField *field,
string &line) const
std::string &line) const
{
if (delayAsFloat(value) == field_blank_)
reportFieldBlank(field, line);
@ -3345,7 +3344,7 @@ ReportPath::reportFieldDelay(Delay value,
void
ReportPath::reportField(float value,
const ReportField *field,
string &line) const
std::string &line) const
{
if (value == field_blank_)
reportFieldBlank(field, line);
@ -3357,7 +3356,7 @@ ReportPath::reportField(float value,
}
else {
// fanout
string value_str;
std::string value_str;
stringPrint(value_str, "%.0f", value);
reportField(value_str.c_str(), field, line);
}
@ -3367,7 +3366,7 @@ ReportPath::reportField(float value,
void
ReportPath::reportField(const char *value,
const ReportField *field,
string &line) const
std::string &line) const
{
if (field->leftJustify())
line += value;
@ -3379,7 +3378,7 @@ ReportPath::reportField(const char *value,
void
ReportPath::reportFieldBlank(const ReportField *field,
string &line) const
std::string &line) const
{
line += field->blank();
}
@ -3387,7 +3386,7 @@ ReportPath::reportFieldBlank(const ReportField *field,
void
ReportPath::reportDashLine() const
{
string line;
std::string line;
for (const ReportField *field : fields_) {
if (field->enabled()) {
for (int i = 0; i < field->width(); i++)
@ -3401,7 +3400,7 @@ ReportPath::reportDashLine() const
void
ReportPath::reportDashLine(int line_width) const
{
string line;
std::string line;
for (int i = 0; i < line_width; i++)
line += '-';
report_->reportLineString(line);

7
search/Search.cc
View File

@ -24,8 +24,7 @@
#include "Search.hh"
#include <algorithm>
#include <cmath> // abs
#include <vector>
#include "ContainerHelpers.hh"
#include "Mutex.hh"
@ -70,10 +69,6 @@
namespace sta {
using std::min;
using std::max;
using std::abs;
////////////////////////////////////////////////////////////////
EvalPred::EvalPred(const StaState *sta) :

46
search/Sta.cc
View File

@ -24,7 +24,9 @@
#include "Sta.hh"
#include <algorithm>
#include <filesystem>
#include <string>
#include "Machine.hh"
#include "ContainerHelpers.hh"
@ -88,10 +90,6 @@
namespace sta {
using std::string;
using std::min;
using std::max;
static bool
libertyPortCapsEqual(const LibertyPort *port1,
const LibertyPort *port2);
@ -576,7 +574,7 @@ Sta::cmdSdc() const
}
void
Sta::setCmdMode(const string &mode_name)
Sta::setCmdMode(const std::string &mode_name)
{
if (!mode_name.empty()) {
if (!mode_name_map_.contains(mode_name)) {
@ -3203,8 +3201,8 @@ class EndpointPathEndVisitor : public PathEndVisitor
{
public:
EndpointPathEndVisitor(const std::string &path_group_name,
const MinMax *min_max,
const StaState *sta);
const MinMax *min_max,
const StaState *sta);
PathEndVisitor *copy() const;
void visit(PathEnd *path_end);
Slack slack() const { return slack_; }
@ -3217,8 +3215,8 @@ private:
};
EndpointPathEndVisitor::EndpointPathEndVisitor(const std::string &path_group_name,
const MinMax *min_max,
const StaState *sta) :
const MinMax *min_max,
const StaState *sta) :
path_group_name_(path_group_name),
min_max_(min_max),
slack_(MinMax::min()->initValue()),
@ -3249,8 +3247,8 @@ EndpointPathEndVisitor::visit(PathEnd *path_end)
Slack
Sta::endpointSlack(const Pin *pin,
const std::string &path_group_name,
const MinMax *min_max)
const std::string &path_group_name,
const MinMax *min_max)
{
ensureGraph();
Vertex *vertex = graph_->pinLoadVertex(pin);
@ -3458,7 +3456,7 @@ MinPeriodEndVisitor::visit(PathEnd *path_end)
|| pathIsFromInputPort(path_end)))) {
Slack slack = path_end->slack(sta_);
float period = clk_->period() - delayAsFloat(slack);
min_period_ = max(min_period_, period);
min_period_ = std::max(min_period_, period);
}
}
@ -3551,12 +3549,12 @@ Sta::worstSlack(const Scene *scene,
////////////////////////////////////////////////////////////////
string
std::string
Sta::reportDelayCalc(Edge *edge,
TimingArc *arc,
TimingArc *arc,
const Scene *scene,
const MinMax *min_max,
int digits)
const MinMax *min_max,
int digits)
{
findDelays();
return graph_delay_calc_->reportDelayCalc(edge, arc, scene, min_max, digits);
@ -4097,13 +4095,13 @@ Sta::setResistance(const Net *net,
bool
Sta::readSpef(const std::string &name,
const std::string &filename,
Instance *instance,
Instance *instance,
Scene *scene, // -scene deprecated 11/20/2025
const MinMaxAll *min_max,
bool pin_cap_included,
bool keep_coupling_caps,
float coupling_cap_factor,
bool reduce)
const MinMaxAll *min_max,
bool pin_cap_included,
bool keep_coupling_caps,
float coupling_cap_factor,
bool reduce)
{
ensureLibLinked();
Parasitics *parasitics = nullptr;
@ -4137,7 +4135,7 @@ Sta::readSpef(const std::string &name,
}
bool success = readSpefFile(filename.c_str(), instance,
pin_cap_included, keep_coupling_caps,
pin_cap_included, keep_coupling_caps,
coupling_cap_factor, reduce,
scene, min_max, parasitics, this);
delaysInvalid();
@ -4151,7 +4149,7 @@ Sta::findParasitics(const std::string &name)
}
void
Sta::reportParasiticAnnotation(const string &spef_name,
Sta::reportParasiticAnnotation(const std::string &spef_name,
bool report_unannotated)
{
ensureLibLinked();

6
search/WorstSlack.cc
View File

@ -24,6 +24,8 @@
#include "WorstSlack.hh"
#include <algorithm>
#include "ContainerHelpers.hh"
#include "Debug.hh"
#include "Report.hh"
@ -34,8 +36,6 @@
namespace sta {
using std::min;
WorstSlacks::WorstSlacks(StaState *sta) :
worst_slacks_(sta->scenePathCount(), sta),
sta_(sta)
@ -195,7 +195,7 @@ WorstSlack::sortQueue(PathAPIndex path_ap_index)
sort(vertices, slack_less);
int vertex_count = vertices.size();
int threshold_index = min(min_queue_size_, vertex_count - 1);
int threshold_index = std::min(min_queue_size_, vertex_count - 1);
Vertex *threshold_vertex = vertices[threshold_index];
slack_threshold_ = search_->wnsSlack(threshold_vertex, path_ap_index);
debugPrint(debug_, "wns", 3, "threshold %s",

23
spice/WritePathSpice.cc
View File

@ -24,8 +24,8 @@
#include "WritePathSpice.hh"
#include <string>
#include <fstream>
#include <string>
#include "Debug.hh"
#include "Error.hh"
@ -50,11 +50,6 @@
namespace sta {
using std::string;
using std::ofstream;
using std::ifstream;
using std::max;
typedef int Stage;
////////////////////////////////////////////////////////////////
@ -112,7 +107,7 @@ private:
//
Stage stageFirst();
Stage stageLast();
string stageName(Stage stage);
std::string stageName(Stage stage);
int stageGateInputPathIndex(Stage stage);
int stageDrvrPathIndex(Stage stage);
int stageLoadPathIndex(Stage stage);
@ -219,7 +214,7 @@ void
WritePathSpice::writeHeader()
{
const Path *start_path = path_expanded_.startPath();
string title = stdstrPrint("Path from %s %s to %s %s",
std::string title = stdstrPrint("Path from %s %s to %s %s",
network_->pathName(start_path->pin(this)),
start_path->transition(this)->to_string().c_str(),
network_->pathName(path_->pin(this)),
@ -291,7 +286,7 @@ WritePathSpice::writeStageInstances()
streamPrint(spice_stream_, "*****************\n\n");
for (Stage stage = stageFirst(); stage <= stageLast(); stage++) {
string stage_name = stageName(stage);
std::string stage_name = stageName(stage);
const char *stage_cname = stage_name.c_str();
if (stage == stageFirst())
streamPrint(spice_stream_, "x%s %s %s %s\n",
@ -450,7 +445,7 @@ WritePathSpice::writeMeasureSlewStmt(Stage stage,
{
const Pin *pin = path->pin(this);
const RiseFall *rf = path->transition(this);
string prefix = stageName(stage);
std::string prefix = stageName(stage);
writeMeasureSlewStmt(pin, rf, prefix);
}
@ -480,7 +475,7 @@ WritePathSpice::writeInputStage(Stage stage)
// External driver not handled.
const char *drvr_pin_name = stageDrvrPinName(stage);
const char *load_pin_name = stageLoadPinName(stage);
string prefix = stageName(stage);
std::string prefix = stageName(stage);
streamPrint(spice_stream_, ".subckt %s %s %s\n",
prefix.c_str(),
drvr_pin_name,
@ -499,7 +494,7 @@ WritePathSpice::writeGateStage(Stage stage)
const char *drvr_pin_name = stageDrvrPinName(stage);
const Pin *load_pin = stageLoadPin(stage);
const char *load_pin_name = stageLoadPinName(stage);
string subckt_name = "stage" + std::to_string(stage);
std::string subckt_name = "stage" + std::to_string(stage);
const Instance *inst = stageInstance(stage);
LibertyPort *input_port = stageGateInputPort(stage);
@ -614,10 +609,10 @@ WritePathSpice::stageLast()
return (path_expanded_.size() + 1) / 2;
}
string
std::string
WritePathSpice::stageName(Stage stage)
{
string name;
std::string name;
stringPrint(name, "stage%d", stage);
return name;
}

76
spice/WriteSpice.cc
View File

@ -26,6 +26,8 @@
#include <algorithm> // swap
#include <filesystem>
#include <fstream>
#include <string>
#include "cudd.h"
@ -50,12 +52,6 @@
namespace sta {
using std::string;
using std::ifstream;
using std::ofstream;
using std::swap;
using std::set;
Net *
pinNet(const Pin *pin,
const Network *network);
@ -68,7 +64,7 @@ public:
const char *what() const noexcept;
protected:
string what_;
std::string what_;
};
SubcktEndsMissing::SubcktEndsMissing(const char *cell_name,
@ -137,7 +133,7 @@ WriteSpice::initPowerGnd()
}
void
WriteSpice::writeHeader(string &title,
WriteSpice::writeHeader(std::string &title,
float max_time,
float time_step)
{
@ -159,21 +155,21 @@ WriteSpice::writePrintStmt(StdStringSeq &node_names)
{
streamPrint(spice_stream_, ".print tran");
if (ckt_sim_ == CircuitSim::xyce) {
string csv_filename = replaceFileExt(spice_filename_, "csv");
std::string csv_filename = replaceFileExt(spice_filename_, "csv");
streamPrint(spice_stream_, " format=csv file=%s", csv_filename.c_str());
writeGnuplotFile(node_names);
}
for (string &name : node_names)
for (std::string &name : node_names)
streamPrint(spice_stream_, " v(%s)", name.c_str());
streamPrint(spice_stream_, "\n\n");
}
string
WriteSpice::replaceFileExt(string filename,
std::string
WriteSpice::replaceFileExt(std::string filename,
const char *ext)
{
size_t dot = filename.rfind('.');
string ext_filename = filename.substr(0, dot + 1);
std::string ext_filename = filename.substr(0, dot + 1);
ext_filename += ext;
return ext_filename;
}
@ -184,7 +180,7 @@ WriteSpice::writeGnuplotFile(StdStringSeq &node_nanes)
{
std::string gnuplot_filename = replaceFileExt(spice_filename_, "gnuplot");
std::string csv_filename = replaceFileExt(spice_filename_, "csv");
ofstream gnuplot_stream;
std::ofstream gnuplot_stream;
gnuplot_stream.open(gnuplot_filename);
if (gnuplot_stream.is_open()) {
streamPrint(gnuplot_stream, "set datafile separator ','\n");
@ -206,12 +202,12 @@ void
WriteSpice::writeSubckts(StdStringSet &cell_names)
{
findCellSubckts(cell_names);
ifstream lib_subckts_stream(lib_subckt_filename_);
std::ifstream lib_subckts_stream(lib_subckt_filename_);
if (lib_subckts_stream.is_open()) {
ofstream subckts_stream(subckt_filename_);
std::ofstream subckts_stream(subckt_filename_);
if (subckts_stream.is_open()) {
string line;
while (getline(lib_subckts_stream, line)) {
std::string line;
while (std::getline(lib_subckts_stream, line)) {
// .subckt <cell_name> [args..]
StdStringSeq tokens = parseTokens(line, ' ');
if (tokens.size() >= 2
@ -220,7 +216,7 @@ WriteSpice::writeSubckts(StdStringSet &cell_names)
if (cell_names.contains(cell_name)) {
subckts_stream << line << "\n";
bool found_ends = false;
while (getline(lib_subckts_stream, line)) {
while (std::getline(lib_subckts_stream, line)) {
subckts_stream << line << "\n";
if (stringBeginEqual(line.c_str(), ".ends")) {
subckts_stream << "\n";
@ -239,13 +235,13 @@ WriteSpice::writeSubckts(StdStringSet &cell_names)
lib_subckts_stream.close();
if (!cell_names.empty()) {
string missing_cells;
for (const string &cell_name : cell_names) {
missing_cells += "\n";
missing_cells += cell_name;
std::string missing_cells;
for (const std::string &cell_name : cell_names) {
missing_cells += "\n";
missing_cells += cell_name;
}
report_->error(1605, "The subkct file %s is missing definitions for %s",
lib_subckt_filename_,
report_->error(1605, "The subkct file %s is missing definitions for %s",
lib_subckt_filename_,
missing_cells.c_str());
}
}
@ -284,10 +280,10 @@ WriteSpice::recordSpicePortNames(const char *cell_name,
void
WriteSpice::findCellSubckts(StdStringSet &cell_names)
{
ifstream lib_subckts_stream(lib_subckt_filename_);
std::ifstream lib_subckts_stream(lib_subckt_filename_);
if (lib_subckts_stream.is_open()) {
string line;
while (getline(lib_subckts_stream, line)) {
std::string line;
while (std::getline(lib_subckts_stream, line)) {
// .subckt <cell_name> [args..]
StdStringSeq tokens = parseTokens(line, ' ');
if (tokens.size() >= 2
@ -295,15 +291,15 @@ WriteSpice::findCellSubckts(StdStringSet &cell_names)
const char *cell_name = tokens[1].c_str();
if (cell_names.contains(cell_name)) {
// Scan the subckt definition for subckt calls.
string stmt;
while (getline(lib_subckts_stream, line)) {
std::string stmt;
while (std::getline(lib_subckts_stream, line)) {
if (line[0] == '+')
stmt += line.substr(1);
else {
// Process previous statement.
if (tolower(stmt[0]) == 'x') {
StdStringSeq tokens = parseTokens(line, ' ');
string &subckt_cell = tokens[tokens.size() - 1];
std::string &subckt_cell = tokens[tokens.size() - 1];
cell_names.insert(subckt_cell);
}
stmt = line;
@ -329,7 +325,7 @@ WriteSpice::writeSubcktInst(const Instance *inst)
const char *cell_name = cell->name();
StdStringSeq &spice_port_names = cell_spice_port_names_[cell_name];
streamPrint(spice_stream_, "x%s", inst_name);
for (string subckt_port_name : spice_port_names) {
for (std::string subckt_port_name : spice_port_names) {
const char *subckt_port_cname = subckt_port_name.c_str();
Pin *pin = network_->findPin(inst, subckt_port_cname);
LibertyPort *pg_port = cell->findLibertyPort(subckt_port_cname);
@ -359,7 +355,7 @@ WriteSpice::writeSubcktInstVoltSrcs(const Instance *inst,
const char *inst_name = network_->pathName(inst);
debugPrint(debug_, "write_spice", 2, "subckt %s", cell->name());
for (string subckt_port_sname : spice_port_names) {
for (std::string subckt_port_sname : spice_port_names) {
const char *subckt_port_name = subckt_port_sname.c_str();
LibertyPort *port = cell->findLibertyPort(subckt_port_name);
const Pin *pin = port ? network_->findPin(inst, port) : nullptr;
@ -412,7 +408,7 @@ WriteSpice::writeVoltageSource(const char *inst_name,
const char *port_name,
float voltage)
{
string node_name = inst_name;
std::string node_name = inst_name;
node_name += '/';
node_name += port_name;
writeVoltageSource(node_name.c_str(), voltage);
@ -536,7 +532,7 @@ WriteSpice::writeParasiticNetwork(const Pin *drvr_pin,
const Parasitic *parasitic,
const NetSet &coupling_nets)
{
set<const Pin*> reachable_pins;
std::set<const Pin*> reachable_pins;
// Sort resistors for consistent regression results.
ParasiticResistorSeq resistors = parasitics_->resistors(parasitic);
sort(resistors, [this] (const ParasiticResistor *r1,
@ -614,8 +610,8 @@ WriteSpice::writeParasiticNetwork(const Pin *drvr_pin,
const Net *net1 = node1 ? parasitics_->net(node1, network_) : nullptr;
const Net *net2 = node2 ? parasitics_->net(node2, network_) : nullptr;
if (net2 == net) {
swap(net1, net2);
swap(node1, node2);
std::swap(net1, net2);
std::swap(node1, node2);
}
if (net2 && coupling_nets.contains(net2))
// Write half the capacitance because the coupled net will do the same.
@ -1036,7 +1032,7 @@ WriteSpice::writeMeasureDelayStmt(const Pin *from_pin,
const RiseFall *from_rf,
const Pin *to_pin,
const RiseFall *to_rf,
string prefix)
std::string prefix)
{
const char *from_pin_name = network_->pathName(from_pin);
float from_threshold = power_voltage_ * default_library_->inputThreshold(from_rf);
@ -1062,7 +1058,7 @@ WriteSpice::writeMeasureDelayStmt(const Pin *from_pin,
void
WriteSpice::writeMeasureSlewStmt(const Pin *pin,
const RiseFall *rf,
string prefix)
std::string prefix)
{
const char *pin_name = network_->pathName(pin);
const char *spice_rf = spiceTrans(rf);
@ -1108,7 +1104,7 @@ WriteSpice::spiceTrans(const RiseFall *rf)
// fprintf for c++ streams.
// Yes, I hate formatted output to ostream THAT much.
void
streamPrint(ofstream &stream,
streamPrint(std::ofstream &stream,
const char *fmt,
...)
{

34
spice/Xyce.cc
View File

@ -26,55 +26,49 @@
#include "Xyce.hh"
#include <fstream>
#include <sstream>
#include <memory>
#include <sstream>
#include <string>
#include "Error.hh"
namespace sta {
using std::string;
using std::ifstream;
using std::getline;
using std::stringstream;
using std::vector;
using std::make_shared;
void
readXyceCsv(const char *csv_filename,
// Return values.
StdStringSeq &titles,
WaveformSeq &waveforms)
{
ifstream file(csv_filename);
std::ifstream file(csv_filename);
if (file.is_open()) {
string line;
std::string line;
// Read the header line.
getline(file, line);
stringstream ss(line);
string field;
std::getline(file, line);
std::stringstream ss(line);
std::string field;
size_t col = 0;
while (getline(ss, field, ',')) {
while (std::getline(ss, field, ',')) {
// Skip TIME title.
if (col > 0)
titles.push_back(field);
col++;
}
vector<FloatSeq> values(titles.size() + 1);
while (getline(file, line)) {
stringstream ss(line);
std::vector<FloatSeq> values(titles.size() + 1);
while (std::getline(file, line)) {
std::stringstream ss(line);
size_t col = 0;
while (getline(ss, field, ',')) {
while (std::getline(ss, field, ',')) {
float value = std::stof(field);
values[col].push_back(value);
col++;
}
}
file.close();
TableAxisPtr time_axis = make_shared<TableAxis>(TableAxisVariable::time,
std::move(values[0]));
TableAxisPtr time_axis = std::make_shared<TableAxis>(TableAxisVariable::time,
std::move(values[0]));
for (size_t var = 1; var < values.size(); var++)
waveforms.emplace_back(new FloatSeq(values[var]), time_axis);
}

11
util/Fuzzy.cc
View File

@ -31,9 +31,6 @@
namespace sta {
using std::max;
using std::abs;
constexpr static float float_equal_tolerance = 1E-15F;
bool
@ -43,18 +40,18 @@ fuzzyEqual(float v1,
if (v1 == v2)
return true;
else if (v1 == 0.0)
return abs(v2) < float_equal_tolerance;
return std::abs(v2) < float_equal_tolerance;
else if (v2 == 0.0)
return abs(v1) < float_equal_tolerance;
return std::abs(v1) < float_equal_tolerance;
else
return abs(v1 - v2) < 1E-6F * max(abs(v1), abs(v2));
return std::abs(v1 - v2) < 1E-6F * std::max(std::abs(v1), std::abs(v2));
}
bool
fuzzyZero(float v)
{
return v == 0.0
|| abs(v) < float_equal_tolerance;
|| std::abs(v) < float_equal_tolerance;
}
bool

8
util/PatternMatch.cc
View File

@ -28,8 +28,6 @@
namespace sta {
using std::string;
PatternMatch::PatternMatch(const char *pattern,
bool is_regexp,
bool nocase,
@ -65,7 +63,7 @@ PatternMatch::PatternMatch(const char *pattern,
compileRegexp();
}
PatternMatch::PatternMatch(const string &pattern,
PatternMatch::PatternMatch(const std::string &pattern,
const PatternMatch *inherit_from) :
pattern_(pattern.c_str()),
is_regexp_(inherit_from->is_regexp_),
@ -83,7 +81,7 @@ PatternMatch::compileRegexp()
int flags = TCL_REG_ADVANCED;
if (nocase_)
flags |= TCL_REG_NOCASE;
string anchored_pattern;
std::string anchored_pattern;
anchored_pattern += '^';
anchored_pattern += pattern_;
anchored_pattern += '$';
@ -112,7 +110,7 @@ PatternMatch::hasWildcards() const
}
bool
PatternMatch::match(const string &str) const
PatternMatch::match(const std::string &str) const
{
return match(str.c_str());
}

8
util/Report.cc
View File

@ -33,8 +33,6 @@
namespace sta {
using std::min;
Report *Report::default_ = nullptr;
Report::Report() :
@ -78,11 +76,11 @@ Report::printString(const char *buffer,
redirectStringPrint(buffer, length);
else {
if (redirect_stream_)
ret = min(ret, fwrite(buffer, sizeof(char), length, redirect_stream_));
ret = std::min(ret, fwrite(buffer, sizeof(char), length, redirect_stream_));
else
ret = min(ret, printConsole(buffer, length));
ret = std::min(ret, printConsole(buffer, length));
if (log_stream_)
ret = min(ret, fwrite(buffer, sizeof(char), length, log_stream_));
ret = std::min(ret, fwrite(buffer, sizeof(char), length, log_stream_));
}
return ret;
}

28
util/StringUtil.cc
View File

@ -24,21 +24,17 @@
#include "StringUtil.hh"
#include <limits>
#include <algorithm>
#include <array>
#include <cctype>
#include <cstdio>
#include <cstdlib> // exit
#include <array>
#include <algorithm>
#include "Machine.hh"
#include "Mutex.hh"
namespace sta {
using std::max;
using std::string;
static void
stringPrintTmp(const char *fmt,
va_list args,
@ -76,7 +72,7 @@ isDigits(const char *str)
// print for c++ strings.
void
stringPrint(string &str,
stringPrint(std::string &str,
const char *fmt,
...)
{
@ -90,7 +86,7 @@ stringPrint(string &str,
}
void
stringAppend(string &str,
stringAppend(std::string &str,
const char *fmt,
...)
{
@ -103,7 +99,7 @@ stringAppend(string &str,
str += tmp;
}
string
std::string
stdstrPrint(const char *fmt,
...)
{
@ -223,7 +219,7 @@ makeTmpString(size_t length)
if (tmp_length < length) {
// String isn't long enough. Make a new one.
delete [] tmp_str;
tmp_length = max(tmp_string_initial_length, length);
tmp_length = std::max(tmp_string_initial_length, length);
tmp_str = new char[tmp_length];
tmp_strings[tmp_string_next] = tmp_str;
tmp_string_lengths[tmp_string_next] = tmp_length;
@ -233,7 +229,7 @@ makeTmpString(size_t length)
}
char *
makeTmpString(string &str)
makeTmpString(std::string &str)
{
char *tmp = makeTmpString(str.length() + 1);
strcpy(tmp, str.c_str());
@ -264,24 +260,24 @@ isTmpString(const char *str)
////////////////////////////////////////////////////////////////
void
trimRight(string &str)
trimRight(std::string &str)
{
str.erase(str.find_last_not_of(" ") + 1);
}
StdStringSeq
split(const string &text,
const string &delims)
split(const std::string &text,
const std::string &delims)
{
StdStringSeq tokens;
auto start = text.find_first_not_of(delims);
auto end = text.find_first_of(delims, start);
while (end != string::npos) {
while (end != std::string::npos) {
tokens.push_back(text.substr(start, end - start));
start = text.find_first_not_of(delims, end);
end = text.find_first_of(delims, start);
}
if (start != string::npos)
if (start != std::string::npos)
tokens.push_back(text.substr(start));
return tokens;
}

6
util/Transition.cc
View File

@ -24,12 +24,12 @@
#include "Transition.hh"
#include <algorithm>
#include "ContainerHelpers.hh"
namespace sta {
using std::max;
const RiseFall RiseFall::rise_("rise", "^", 0);
const RiseFall RiseFall::fall_("fall", "v", 1);
const std::array<const RiseFall*, 2> RiseFall::range_{&rise_, &fall_};
@ -195,7 +195,7 @@ Transition::Transition(const char *name,
{
transition_map_[name_] = this;
transition_map_[init_final_] = this;
max_index_ = max(sdf_triple_index, max_index_);
max_index_ = std::max(sdf_triple_index, max_index_);
}
bool

255
verilog/VerilogReader.cc
View File

@ -25,6 +25,7 @@
#include "VerilogReader.hh"
#include <cstdlib>
#include <string>
#include "ContainerHelpers.hh"
#include "Zlib.hh"
@ -42,12 +43,10 @@
namespace sta {
using std::string;
using VerilogConstant10 = unsigned long long;
static string
verilogBusBitName(const string &bus_name,
static std::string
verilogBusBitName(const std::string &bus_name,
int index);
static int
hierarchyLevel(Net *net,
@ -227,13 +226,13 @@ VerilogReader::module(Cell *cell)
}
void
VerilogReader::makeModule(const string *module_vname,
VerilogReader::makeModule(const std::string *module_vname,
VerilogNetSeq *ports,
VerilogStmtSeq *stmts,
VerilogAttrStmtSeq *attr_stmts,
int line)
{
const string module_name = moduleVerilogToSta(module_vname);
const std::string module_name = moduleVerilogToSta(module_vname);
Cell *cell = network_->findCell(library_, module_name.c_str());
if (cell) {
VerilogModule *module = module_map_[cell];
@ -258,7 +257,7 @@ VerilogReader::makeModule(const string *module_vname,
}
void
VerilogReader::makeModule(const string *module_name,
VerilogReader::makeModule(const std::string *module_name,
VerilogStmtSeq *port_dcls,
VerilogStmtSeq *stmts,
VerilogAttrStmtSeq *attr_stmts,
@ -288,7 +287,7 @@ VerilogReader::makeCellPorts(Cell *cell,
{
StdStringSet port_names;
for (VerilogNet *mod_port : *ports) {
const string &port_name = mod_port->name();
const std::string &port_name = mod_port->name();
if (!port_names.contains(port_name)) {
port_names.insert(port_name);
if (mod_port->isNamed()) {
@ -310,7 +309,7 @@ VerilogReader::makeCellPorts(Cell *cell,
Port *
VerilogReader::makeCellPort(Cell *cell,
VerilogModule *module,
const string &port_name)
const std::string &port_name)
{
VerilogDcl *dcl = module->declaration(port_name.c_str());
if (dcl) {
@ -341,7 +340,7 @@ VerilogReader::makeNamedPortRefCellPorts(Cell *cell,
PortSeq *member_ports = new PortSeq;
VerilogNetNameIterator *net_name_iter = mod_port->nameIterator(module,this);
while (net_name_iter->hasNext()) {
const string &net_name = net_name_iter->next();
const std::string &net_name = net_name_iter->next();
port_names.insert(net_name);
Port *port = makeCellPort(cell, module, net_name);
member_ports->push_back(port);
@ -354,7 +353,7 @@ VerilogReader::makeNamedPortRefCellPorts(Cell *cell,
// Make sure each declaration appears in the module port list.
void
VerilogReader::checkModuleDcls(VerilogModule *module,
std::set<string> &port_names)
std::set<std::string> &port_names)
{
for (auto const & [port_name, dcl] : *module->declarationMap()) {
PortDirection *dir = dcl->direction();
@ -444,10 +443,10 @@ VerilogReader::makeDclBus(PortDirection *dir,
}
VerilogDclArg *
VerilogReader::makeDclArg(const string *net_vname)
VerilogReader::makeDclArg(const std::string *net_vname)
{
dcl_arg_count_++;
const string net_name = netVerilogToSta(net_vname);
const std::string net_name = netVerilogToSta(net_vname);
VerilogDclArg *dcl =new VerilogDclArg(net_name);
delete net_vname;
return dcl;
@ -461,14 +460,14 @@ VerilogReader::makeDclArg(VerilogAssign *assign)
}
VerilogNetPartSelect *
VerilogReader::makeNetPartSelect(const string *net_vname,
VerilogReader::makeNetPartSelect(const std::string *net_vname,
int from_index,
int to_index)
{
net_part_select_count_++;
if (report_stmt_stats_)
net_bus_names_ += net_vname->size() + 1;
const string net_name = netVerilogToSta(net_vname);
const std::string net_name = netVerilogToSta(net_vname);
VerilogNetPartSelect *select = new VerilogNetPartSelect(net_name,
from_index,
to_index);
@ -477,7 +476,7 @@ VerilogReader::makeNetPartSelect(const string *net_vname,
}
VerilogNetConstant *
VerilogReader::makeNetConstant(const string *constant,
VerilogReader::makeNetConstant(const std::string *constant,
int line)
{
net_constant_count_++;
@ -485,25 +484,25 @@ VerilogReader::makeNetConstant(const string *constant,
}
VerilogNetScalar *
VerilogReader::makeNetScalar(const string *net_vname)
VerilogReader::makeNetScalar(const std::string *net_vname)
{
net_scalar_count_++;
if (report_stmt_stats_)
net_scalar_names_ += net_vname->size() + 1;
const string net_name = netVerilogToSta(net_vname);
const std::string net_name = netVerilogToSta(net_vname);
VerilogNetScalar *scalar = new VerilogNetScalar(net_name);
delete net_vname;
return scalar;
}
VerilogNetBitSelect *
VerilogReader::makeNetBitSelect(const string *net_vname,
VerilogReader::makeNetBitSelect(const std::string *net_vname,
int index)
{
net_bit_select_count_++;
if (report_stmt_stats_)
net_bus_names_ += net_vname->size() + 1;
const string net_name = netVerilogToSta(net_vname);
const std::string net_name = netVerilogToSta(net_vname);
VerilogNetBitSelect *select = new VerilogNetBitSelect(net_name, index);
delete net_vname;
return select;
@ -519,14 +518,14 @@ VerilogReader::makeAssign(VerilogNet *lhs,
}
VerilogInst *
VerilogReader::makeModuleInst(const string *module_vname,
const string *inst_vname,
VerilogReader::makeModuleInst(const std::string *module_vname,
const std::string *inst_vname,
VerilogNetSeq *pins,
VerilogAttrStmtSeq *attr_stmts,
const int line)
{
const string module_name = moduleVerilogToSta(module_vname);
const string inst_name = instanceVerilogToSta(inst_vname);
const std::string module_name = moduleVerilogToSta(module_vname);
const std::string inst_name = instanceVerilogToSta(inst_vname);
Cell *cell = network_->findAnyCell(module_name.c_str());
LibertyCell *liberty_cell = nullptr;
if (cell)
@ -541,7 +540,7 @@ VerilogReader::makeModuleInst(const string *module_vname,
VerilogNetPortRefScalarNet *vpin =
dynamic_cast<VerilogNetPortRefScalarNet*>(vnet);
const char *port_name = vpin->name().c_str();
const string &net_name = vpin->netName();
const std::string &net_name = vpin->netName();
Port *port = network_->findPort(cell, port_name);
LibertyPort *lport = network_->libertyPort(port);
if (lport->isBus()) {
@ -607,20 +606,20 @@ VerilogReader::hasScalarNamedPortRefs(LibertyCell *liberty_cell,
}
VerilogNetPortRef *
VerilogReader::makeNetNamedPortRefScalarNet(const string *port_vname)
VerilogReader::makeNetNamedPortRefScalarNet(const std::string *port_vname)
{
net_port_ref_scalar_net_count_++;
if (report_stmt_stats_)
port_names_ += port_vname->size() + 1;
const string port_name = portVerilogToSta(port_vname);
const std::string port_name = portVerilogToSta(port_vname);
VerilogNetPortRef *ref = new VerilogNetPortRefScalarNet(port_name.c_str());
delete port_vname;
return ref;
}
VerilogNetPortRef *
VerilogReader::makeNetNamedPortRefScalarNet(const string *port_vname,
const string *net_vname)
VerilogReader::makeNetNamedPortRefScalarNet(const std::string *port_vname,
const std::string *net_vname)
{
net_port_ref_scalar_net_count_++;
if (report_stmt_stats_) {
@ -628,8 +627,8 @@ VerilogReader::makeNetNamedPortRefScalarNet(const string *port_vname,
net_scalar_names_ += net_vname->size() + 1;
port_names_ += port_vname->size() + 1;
}
const string port_name = portVerilogToSta(port_vname);
const string net_name = netVerilogToSta(net_vname);
const std::string port_name = portVerilogToSta(port_vname);
const std::string net_name = netVerilogToSta(net_vname);
VerilogNetPortRef *ref = new VerilogNetPortRefScalarNet(port_name.c_str(),
net_name.c_str());
delete port_vname;
@ -638,18 +637,18 @@ VerilogReader::makeNetNamedPortRefScalarNet(const string *port_vname,
}
VerilogNetPortRef *
VerilogReader::makeNetNamedPortRefBitSelect(const string *port_vname,
const string *bus_vname,
VerilogReader::makeNetNamedPortRefBitSelect(const std::string *port_vname,
const std::string *bus_vname,
int index)
{
net_port_ref_scalar_net_count_++;
const string bus_name = portVerilogToSta(bus_vname);
const string net_name = verilogBusBitName(bus_name, index);
const std::string bus_name = portVerilogToSta(bus_vname);
const std::string net_name = verilogBusBitName(bus_name, index);
if (report_stmt_stats_) {
net_scalar_names_ += net_name.length() + 1;
port_names_ += port_vname->size() + 1;
}
const string port_name = portVerilogToSta(port_vname);
const std::string port_name = portVerilogToSta(port_vname);
VerilogNetPortRef *ref = new VerilogNetPortRefScalarNet(port_name.c_str(),
net_name.c_str());
delete port_vname;
@ -658,25 +657,25 @@ VerilogReader::makeNetNamedPortRefBitSelect(const string *port_vname,
}
VerilogNetPortRef *
VerilogReader::makeNetNamedPortRefScalar(const string *port_vname,
VerilogReader::makeNetNamedPortRefScalar(const std::string *port_vname,
VerilogNet *net)
{
net_port_ref_scalar_count_++;
if (report_stmt_stats_)
port_names_ += port_vname->size() + 1;
const string port_name = portVerilogToSta(port_vname);
const std::string port_name = portVerilogToSta(port_vname);
VerilogNetPortRef *ref = new VerilogNetPortRefScalar(port_name.c_str(), net);
delete port_vname;
return ref;
}
VerilogNetPortRef *
VerilogReader::makeNetNamedPortRefBit(const string *port_vname,
VerilogReader::makeNetNamedPortRefBit(const std::string *port_vname,
int index,
VerilogNet *net)
{
net_port_ref_bit_count_++;
const string port_name = portVerilogToSta(port_vname);
const std::string port_name = portVerilogToSta(port_vname);
VerilogNetPortRef *ref = new VerilogNetPortRefBit(port_name.c_str(),
index, net);
delete port_vname;
@ -684,13 +683,13 @@ VerilogReader::makeNetNamedPortRefBit(const string *port_vname,
}
VerilogNetPortRef *
VerilogReader::makeNetNamedPortRefPart(const string *port_vname,
VerilogReader::makeNetNamedPortRefPart(const std::string *port_vname,
int from_index,
int to_index,
VerilogNet *net)
{
net_port_ref_part_count_++;
const string port_name = portVerilogToSta(port_vname);
const std::string port_name = portVerilogToSta(port_vname);
VerilogNetPortRef *ref = new VerilogNetPortRefPart(port_name,
from_index,
to_index, net);
@ -776,11 +775,11 @@ VerilogReader::warn(int id,
////////////////////////////////////////////////////////////////
VerilogModule::VerilogModule(const string &name,
VerilogModule::VerilogModule(const std::string &name,
VerilogNetSeq *ports,
VerilogStmtSeq *stmts,
VerilogAttrStmtSeq *attr_stmts,
const string &filename,
const std::string &filename,
int line,
VerilogReader *reader) :
VerilogStmt(line),
@ -822,7 +821,7 @@ VerilogModule::parseDcl(VerilogDcl *dcl,
{
for (VerilogDclArg *arg : *dcl->args()) {
if (arg->isNamed()) {
const string &net_name = arg->netName();
const std::string &net_name = arg->netName();
VerilogDcl *existing_dcl = dcl_map_[net_name.c_str()];
if (existing_dcl) {
PortDirection *existing_dir = existing_dcl->direction();
@ -845,7 +844,7 @@ VerilogModule::parseDcl(VerilogDcl *dcl,
// input/output/inout dcls.
dcl_map_[net_name.c_str()] = dcl;
else if (!dcl->direction()->isInternal()) {
string net_vname = netVerilogName(net_name.c_str());
std::string net_vname = netVerilogName(net_name.c_str());
reader->warn(1395, filename_.c_str(), dcl->line(),
"signal %s previously declared on line %d.",
net_vname.c_str(),
@ -865,14 +864,14 @@ VerilogModule::checkInstanceName(VerilogInst *inst,
StdStringSet &inst_names,
VerilogReader *reader)
{
string inst_name = inst->instanceName();
std::string inst_name = inst->instanceName();
if (inst_names.contains(inst_name)) {
int i = 1;
string replacement_name;
std::string replacement_name;
do {
replacement_name = stdstrPrint("%s_%d", inst_name.c_str(), i++);
} while (inst_names.contains(replacement_name));
string inst_vname = instanceVerilogName(inst_name.c_str());
std::string inst_vname = instanceVerilogName(inst_name.c_str());
reader->warn(1396, filename_.c_str(), inst->line(),
"instance name %s duplicated - renamed to %s.",
inst_vname.c_str(),
@ -884,7 +883,7 @@ VerilogModule::checkInstanceName(VerilogInst *inst,
}
VerilogDcl *
VerilogModule::declaration(const string &net_name)
VerilogModule::declaration(const std::string &net_name)
{
return findKey(dcl_map_, net_name.c_str());
}
@ -896,7 +895,7 @@ VerilogStmt::VerilogStmt(int line) :
{
}
VerilogInst::VerilogInst(const string &inst_name,
VerilogInst::VerilogInst(const std::string &inst_name,
VerilogAttrStmtSeq *attr_stmts,
const int line) :
VerilogStmt(line),
@ -912,13 +911,13 @@ VerilogInst::~VerilogInst()
}
void
VerilogInst::setInstanceName(const string &inst_name)
VerilogInst::setInstanceName(const std::string &inst_name)
{
inst_name_ = inst_name;
}
VerilogModuleInst::VerilogModuleInst(const string &module_name,
const string &inst_name,
VerilogModuleInst::VerilogModuleInst(const std::string &module_name,
const std::string &inst_name,
VerilogNetSeq *pins,
VerilogAttrStmtSeq *attr_stmts,
int line) :
@ -953,7 +952,7 @@ VerilogModuleInst::namedPins()
}
VerilogLibertyInst::VerilogLibertyInst(LibertyCell *cell,
const string &inst_name,
const std::string &inst_name,
const StdStringSeq &net_names,
VerilogAttrStmtSeq *attr_stmts,
const int line) :
@ -1000,7 +999,7 @@ VerilogDcl::appendArg(VerilogDclArg *arg)
args_->push_back(arg);
}
const string &
const std::string &
VerilogDcl::portName()
{
return (*args_)[0]->netName();
@ -1036,7 +1035,7 @@ VerilogDclBus::size() const
return abs(to_index_ - from_index_) + 1;
}
VerilogDclArg::VerilogDclArg(const string &net_name) :
VerilogDclArg::VerilogDclArg(const std::string &net_name) :
net_name_(net_name),
assign_(nullptr)
{
@ -1052,7 +1051,7 @@ VerilogDclArg::~VerilogDclArg()
delete assign_;
}
const string &
const std::string &
VerilogDclArg::netName()
{
if (assign_)
@ -1082,29 +1081,29 @@ class VerilogNullNetNameIterator : public VerilogNetNameIterator
{
public:
virtual bool hasNext() { return false; }
virtual const string &next();
virtual const std::string &next();
};
const string &
const std::string &
VerilogNullNetNameIterator::next()
{
static const string null;
static const std::string null;
return null;
}
class VerilogOneNetNameIterator : public VerilogNetNameIterator
{
public:
VerilogOneNetNameIterator(const string &name);
VerilogOneNetNameIterator(const std::string &name);
virtual bool hasNext();
virtual const string &next();
virtual const std::string &next();
protected:
string name_;
std::string name_;
bool has_next_;
};
VerilogOneNetNameIterator::VerilogOneNetNameIterator(const string &name) :
VerilogOneNetNameIterator::VerilogOneNetNameIterator(const std::string &name) :
name_(name),
has_next_(true)
{
@ -1116,7 +1115,7 @@ VerilogOneNetNameIterator::hasNext()
return has_next_;
}
const string &
const std::string &
VerilogOneNetNameIterator::next()
{
has_next_ = false;
@ -1126,21 +1125,21 @@ VerilogOneNetNameIterator::next()
class VerilogBusNetNameIterator : public VerilogNetNameIterator
{
public:
VerilogBusNetNameIterator(const string bus_name,
VerilogBusNetNameIterator(const std::string bus_name,
int from_index,
int to_index);
virtual bool hasNext();
virtual const string &next();
virtual const std::string &next();
protected:
const string bus_name_;
const std::string bus_name_;
int from_index_;
int to_index_;
int index_;
string bit_name_;
std::string bit_name_;
};
VerilogBusNetNameIterator::VerilogBusNetNameIterator(const string bus_name,
VerilogBusNetNameIterator::VerilogBusNetNameIterator(const std::string bus_name,
int from_index,
int to_index) :
bus_name_(bus_name),
@ -1159,7 +1158,7 @@ VerilogBusNetNameIterator::hasNext()
&& index_ >= to_index_);
}
const string &
const std::string &
VerilogBusNetNameIterator::next()
{
bit_name_ = verilogBusBitName(bus_name_, index_);
@ -1170,8 +1169,8 @@ VerilogBusNetNameIterator::next()
return bit_name_;
}
static string
verilogBusBitName(const string &bus_name,
static std::string
verilogBusBitName(const std::string &bus_name,
int index)
{
return stdstrPrint("%s[%d]", bus_name.c_str(), index);
@ -1181,22 +1180,22 @@ class VerilogConstantNetNameIterator : public VerilogNetNameIterator
{
public:
VerilogConstantNetNameIterator(VerilogConstantValue *value,
const string &zero,
const string &one);
const std::string &zero,
const std::string &one);
virtual bool hasNext();
virtual const string &next();
virtual const std::string &next();
private:
VerilogConstantValue *value_;
const string &zero_;
const string &one_;
const std::string &zero_;
const std::string &one_;
int bit_index_;
};
VerilogConstantNetNameIterator::
VerilogConstantNetNameIterator(VerilogConstantValue *value,
const string &zero,
const string &one) :
const std::string &zero,
const std::string &one) :
value_(value),
zero_(zero),
one_(one),
@ -1210,7 +1209,7 @@ VerilogConstantNetNameIterator::hasNext()
return bit_index_ >= 0;
}
const string &
const std::string &
VerilogConstantNetNameIterator::next()
{
return (*value_)[bit_index_--] ? one_ : zero_;
@ -1224,7 +1223,7 @@ public:
VerilogReader *reader);
virtual ~VerilogNetConcatNameIterator();
virtual bool hasNext();
virtual const string &next();
virtual const std::string &next();
private:
VerilogModule *module_;
@ -1262,7 +1261,7 @@ VerilogNetConcatNameIterator::hasNext()
|| net_iter_ != nets_->end();
}
const string &
const std::string &
VerilogNetConcatNameIterator::next()
{
if (net_name_iter_ && net_name_iter_->hasNext())
@ -1276,15 +1275,15 @@ VerilogNetConcatNameIterator::next()
return net_name_iter_->next();
}
}
static const string null;
static const std::string null;
return null;
}
////////////////////////////////////////////////////////////////
const string VerilogNetUnnamed::null_;
const std::string VerilogNetUnnamed::null_;
VerilogNetNamed::VerilogNetNamed(const string &name) :
VerilogNetNamed::VerilogNetNamed(const std::string &name) :
VerilogNet(),
name_(name)
{
@ -1294,7 +1293,7 @@ VerilogNetNamed::~VerilogNetNamed()
{
}
VerilogNetScalar::VerilogNetScalar(const string &name) :
VerilogNetScalar::VerilogNetScalar(const std::string &name) :
VerilogNetNamed(name)
{
}
@ -1318,7 +1317,7 @@ VerilogNetScalar::size(VerilogModule *module)
}
static VerilogNetNameIterator *
verilogNetScalarNameIterator(const string &name,
verilogNetScalarNameIterator(const std::string &name,
VerilogModule *module)
{
if (!name.empty()) {
@ -1339,7 +1338,7 @@ VerilogNetScalar::nameIterator(VerilogModule *module,
return verilogNetScalarNameIterator(name_.c_str(), module);
}
VerilogNetBitSelect::VerilogNetBitSelect(const string &name,
VerilogNetBitSelect::VerilogNetBitSelect(const std::string &name,
int index) :
VerilogNetNamed(verilogBusBitName(name, index)),
index_(index)
@ -1359,7 +1358,7 @@ VerilogNetBitSelect::nameIterator(VerilogModule *,
return new VerilogOneNetNameIterator(name_);
}
VerilogNetPartSelect::VerilogNetPartSelect(const string &name,
VerilogNetPartSelect::VerilogNetPartSelect(const std::string &name,
int from_index,
int to_index):
VerilogNetNamed(name),
@ -1384,7 +1383,7 @@ VerilogNetPartSelect::nameIterator(VerilogModule *,
return new VerilogBusNetNameIterator(name_.c_str(), from_index_, to_index_);
}
VerilogNetConstant::VerilogNetConstant(const string *constant,
VerilogNetConstant::VerilogNetConstant(const std::string *constant,
VerilogReader *reader,
int line)
{
@ -1392,13 +1391,13 @@ VerilogNetConstant::VerilogNetConstant(const string *constant,
}
void
VerilogNetConstant::parseConstant(const string *constant,
VerilogNetConstant::parseConstant(const std::string *constant,
VerilogReader *reader,
int line)
{
// Find constant size.
size_t csize_end = constant->find('\'');
string csize = constant->substr(0, csize_end);
std::string csize = constant->substr(0, csize_end);
// Read the constant size.
size_t size = std::stol(csize);
@ -1434,7 +1433,7 @@ VerilogNetConstant::parseConstant(const string *constant,
}
void
VerilogNetConstant::parseConstant(const string *constant,
VerilogNetConstant::parseConstant(const std::string *constant,
size_t base_idx,
int base,
int digit_bit_count)
@ -1463,13 +1462,13 @@ VerilogNetConstant::parseConstant(const string *constant,
}
void
VerilogNetConstant::parseConstant10(const string *constant,
VerilogNetConstant::parseConstant10(const std::string *constant,
size_t base_idx,
VerilogReader *reader,
int line)
{
// Copy the constant skipping underscores.
string tmp;
std::string tmp;
for (size_t i = base_idx + 1; i < constant->size(); i++) {
char ch = constant->at(i);
if (ch != '_')
@ -1478,7 +1477,7 @@ VerilogNetConstant::parseConstant10(const string *constant,
size_t size = value_->size();
size_t length = tmp.size();
const string &constant10_max = reader->constant10Max();
const std::string &constant10_max = reader->constant10Max();
size_t max_length = constant10_max.size();
if (length > max_length
|| (length == max_length
@ -1546,18 +1545,18 @@ VerilogNetConcat::nameIterator(VerilogModule *module,
return new VerilogNetConcatNameIterator(nets_, module, reader);
}
VerilogNetPortRef::VerilogNetPortRef(const string &name) :
VerilogNetPortRef::VerilogNetPortRef(const std::string &name) :
VerilogNetScalar(name)
{
}
VerilogNetPortRefScalarNet::VerilogNetPortRefScalarNet(const string &name) :
VerilogNetPortRefScalarNet::VerilogNetPortRefScalarNet(const std::string &name) :
VerilogNetPortRef(name)
{
}
VerilogNetPortRefScalarNet::VerilogNetPortRefScalarNet(const string &name,
const string &net_name) :
VerilogNetPortRefScalarNet::VerilogNetPortRefScalarNet(const std::string &name,
const std::string &net_name) :
VerilogNetPortRef(name),
net_name_(net_name)
{
@ -1584,7 +1583,7 @@ VerilogNetPortRefScalarNet::nameIterator(VerilogModule *module,
return verilogNetScalarNameIterator(net_name_, module);
}
VerilogNetPortRefScalar::VerilogNetPortRefScalar(const string &name,
VerilogNetPortRefScalar::VerilogNetPortRefScalar(const std::string &name,
VerilogNet *net) :
VerilogNetPortRef(name),
net_(net)
@ -1615,7 +1614,7 @@ VerilogNetPortRefScalar::nameIterator(VerilogModule *module,
return new VerilogNullNetNameIterator();
}
VerilogNetPortRefBit::VerilogNetPortRefBit(const string &name,
VerilogNetPortRefBit::VerilogNetPortRefBit(const std::string &name,
int index,
VerilogNet *net) :
VerilogNetPortRefScalar(name, net),
@ -1623,7 +1622,7 @@ VerilogNetPortRefBit::VerilogNetPortRefBit(const string &name,
{
}
VerilogNetPortRefPart::VerilogNetPortRefPart(const string &name,
VerilogNetPortRefPart::VerilogNetPortRefPart(const std::string &name,
int from_index,
int to_index,
VerilogNet *net) :
@ -1632,26 +1631,26 @@ VerilogNetPortRefPart::VerilogNetPortRefPart(const string &name,
{
}
const string &
const std::string &
VerilogNetPortRefPart::name() const
{
return name_;
}
VerilogAttrEntry::VerilogAttrEntry(const string &key,
const string &value) :
VerilogAttrEntry::VerilogAttrEntry(const std::string &key,
const std::string &value) :
key_(key),
value_(value)
{
}
string
std::string
VerilogAttrEntry::key()
{
return key_;
}
string
std::string
VerilogAttrEntry::value()
{
return value_;
@ -1687,8 +1686,8 @@ using BindingMap = std::map<const char*, Net*, CharPtrLess>;
class VerilogBindingTbl
{
public:
VerilogBindingTbl(const string &zero_net_name_,
const string &one_net_name_);
VerilogBindingTbl(const std::string &zero_net_name_,
const std::string &one_net_name_);
Net *ensureNetBinding(const char *net_name,
Instance *inst,
NetworkReader *network);
@ -1698,8 +1697,8 @@ public:
Net *net);
private:
const string &zero_net_name_;
const string &one_net_name_;
const std::string &zero_net_name_;
const std::string &one_net_name_;
BindingMap map_;
};
@ -1719,7 +1718,7 @@ VerilogReader::linkNetwork(const char *top_cell_name,
VerilogNetNameIterator *net_name_iter = mod_port->nameIterator(module,
this);
while (net_name_iter->hasNext()) {
const string &net_name = net_name_iter->next();
const std::string &net_name = net_name_iter->next();
Port *port = network_->findPort(top_cell, net_name.c_str());
Net *net = bindings.ensureNetBinding(net_name.c_str(), top_instance, network_);
// Guard against repeated port name.
@ -1795,10 +1794,10 @@ VerilogReader::makeModuleInstNetwork(VerilogModuleInst *mod_inst,
VerilogBindingTbl *parent_bindings,
bool make_black_boxes)
{
const string &module_name = mod_inst->moduleName();
const std::string &module_name = mod_inst->moduleName();
Cell *cell = network_->findAnyCell(module_name.c_str());
if (cell == nullptr) {
string inst_vname = instanceVerilogName(mod_inst->instanceName().c_str());
std::string inst_vname = instanceVerilogName(mod_inst->instanceName().c_str());
if (make_black_boxes) {
cell = makeBlackBox(mod_inst, parent_module);
linkWarn(198, parent_module->filename(), mod_inst->line(),
@ -1861,7 +1860,7 @@ VerilogReader::makeNamedInstPins(Cell *cell,
VerilogBindingTbl *parent_bindings,
bool is_leaf)
{
string inst_vname = instanceVerilogName(mod_inst->instanceName().c_str());
std::string inst_vname = instanceVerilogName(mod_inst->instanceName().c_str());
for (auto mpin : *mod_inst->pins()) {
VerilogNetPortRef *vpin = dynamic_cast<VerilogNetPortRef*>(mpin);
const char *port_name = vpin->name().c_str();
@ -1921,7 +1920,7 @@ VerilogReader::makeOrderedInstPins(Cell *cell,
VerilogNet *net = *pin_iter++;
Port *port = port_iter->next();
if (network_->size(port) != net->size(parent_module)) {
string inst_vname = instanceVerilogName(mod_inst->instanceName().c_str());
std::string inst_vname = instanceVerilogName(mod_inst->instanceName().c_str());
linkWarn(202, parent_module->filename(), mod_inst->line(),
"instance %s port %s size %d does not match net size %d.",
inst_vname.c_str(),
@ -1959,7 +1958,7 @@ VerilogReader::makeInstPin(Instance *inst,
VerilogBindingTbl *parent_bindings,
bool is_leaf)
{
string net_name;
std::string net_name;
if (net_name_iter->hasNext())
net_name = net_name_iter->next();
makeInstPin(inst, port, net_name, bindings, parent, parent_bindings,
@ -1969,7 +1968,7 @@ VerilogReader::makeInstPin(Instance *inst,
void
VerilogReader::makeInstPin(Instance *inst,
Port *port,
const string &net_name,
const std::string &net_name,
VerilogBindingTbl *bindings,
Instance *parent,
VerilogBindingTbl *parent_bindings,
@ -2013,7 +2012,7 @@ VerilogReader::makeLibertyInst(VerilogLibertyInst *lib_inst,
LibertyCellPortBitIterator port_iter(lib_cell);
while (port_iter.hasNext()) {
LibertyPort *port = port_iter.next();
const string &net_name = net_names[port->pinIndex()];
const std::string &net_name = net_names[port->pinIndex()];
// net_name may be the name of a single bit bus.
if (!net_name.empty()) {
Net *net = nullptr;
@ -2023,7 +2022,7 @@ VerilogReader::makeLibertyInst(VerilogLibertyInst *lib_inst,
if (dcl && dcl->isBus()) {
VerilogDclBus *dcl_bus = dynamic_cast<VerilogDclBus *>(dcl);
// Bus is only 1 bit wide.
string bus_name = verilogBusBitName(net_name, dcl_bus->fromIndex());
std::string bus_name = verilogBusBitName(net_name, dcl_bus->fromIndex());
net = parent_bindings->ensureNetBinding(bus_name.c_str(), parent, network_);
}
else
@ -2042,7 +2041,7 @@ Cell *
VerilogReader::makeBlackBox(VerilogModuleInst *mod_inst,
VerilogModule *parent_module)
{
const string &module_name = mod_inst->moduleName();
const std::string &module_name = mod_inst->moduleName();
Cell *cell = network_->makeCell(library_, module_name.c_str(), true,
parent_module->filename());
if (mod_inst->namedPins())
@ -2109,8 +2108,8 @@ VerilogReader::mergeAssignNet(VerilogAssign *assign,
VerilogNetNameIterator *lhs_iter = lhs->nameIterator(module, this);
VerilogNetNameIterator *rhs_iter = rhs->nameIterator(module, this);
while (lhs_iter->hasNext() && rhs_iter->hasNext()) {
const string &lhs_name = lhs_iter->next();
const string &rhs_name = rhs_iter->next();
const std::string &lhs_name = lhs_iter->next();
const std::string &rhs_name = rhs_iter->next();
Net *lhs_net = bindings->ensureNetBinding(lhs_name.c_str(), inst, network_);
Net *rhs_net = bindings->ensureNetBinding(rhs_name.c_str(), inst, network_);
// Merge lower level net into higher level net so that deleting
@ -2148,8 +2147,8 @@ hierarchyLevel(Net *net,
////////////////////////////////////////////////////////////////
VerilogBindingTbl::VerilogBindingTbl(const string &zero_net_name,
const string &one_net_name) :
VerilogBindingTbl::VerilogBindingTbl(const std::string &zero_net_name,
const std::string &one_net_name) :
zero_net_name_(zero_net_name),
one_net_name_(one_net_name)
{

27
verilog/VerilogWriter.cc
View File

@ -24,9 +24,10 @@
#include "VerilogWriter.hh"
#include <cstdlib>
#include <algorithm>
#include <cstdlib>
#include <map>
#include <string>
#include "Error.hh"
#include "Liberty.hh"
@ -38,10 +39,6 @@
namespace sta {
using std::min;
using std::max;
using std::string;
class VerilogWriter
{
public:
@ -284,8 +281,8 @@ VerilogWriter::writeWireDcls(const Instance *inst)
int index;
parseBusName(net_name, '[', ']', escape, is_bus, bus_name, index);
BusIndexRange &range = bus_ranges[bus_name];
range.first = max(range.first, index);
range.second = min(range.second, index);
range.first = std::max(range.first, index);
range.second = std::min(range.second, index);
}
else {
std::string net_vname = netVerilogName(net_name);
@ -337,8 +334,8 @@ VerilogWriter::writeChild(const Instance *child)
Cell *child_cell = network_->cell(child);
if (!remove_cells_.contains(child_cell)) {
const char *child_name = network_->name(child);
string child_vname = instanceVerilogName(child_name);
string child_cell_vname = cellVerilogName(network_->name(child_cell));
std::string child_vname = instanceVerilogName(child_name);
std::string child_cell_vname = cellVerilogName(network_->name(child_cell));
fprintf(stream_, " %s %s (",
child_cell_vname.c_str(),
child_vname.c_str());
@ -369,10 +366,10 @@ VerilogWriter::writeInstPin(const Instance *inst,
Net *net = network_->net(pin);
if (net) {
const char *net_name = network_->name(net);
string net_vname = netVerilogName(net_name);
std::string net_vname = netVerilogName(net_name);
if (!first_port)
fprintf(stream_, ",\n ");
string port_vname = portVerilogName(network_->name(port));
std::string port_vname = portVerilogName(network_->name(port));
fprintf(stream_, ".%s(%s)",
port_vname.c_str(),
net_vname.c_str());
@ -422,13 +419,13 @@ VerilogWriter::writeInstBusPinBit(const Instance *inst,
{
Pin *pin = network_->findPin(inst, port);
Net *net = pin ? network_->net(pin) : nullptr;
string net_name;
std::string net_name;
if (net)
net_name = network_->name(net);
else
// There is no verilog syntax to "skip" a bit in the concatentation.
stringPrint(net_name, "_NC%d", unconnected_net_index_++);
string net_vname = netVerilogName(net_name.c_str());
std::string net_vname = netVerilogName(net_name.c_str());
if (!first_member)
fprintf(stream_, ",\n ");
fprintf(stream_, "%s", net_vname.c_str());
@ -455,8 +452,8 @@ VerilogWriter::writeAssigns(const Instance *inst)
|| (include_pwr_gnd_ && network_->direction(port)->isPowerGround()))
&& !stringEqual(network_->name(port), network_->name(net))) {
// Port name is different from net name.
string port_vname = netVerilogName(network_->name(port));
string net_vname = netVerilogName(network_->name(net));
std::string port_vname = netVerilogName(network_->name(port));
std::string net_vname = netVerilogName(network_->name(net));
fprintf(stream_, " assign %s = %s;\n",
port_vname.c_str(),
net_vname.c_str());