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remove using std from headers 

Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry 2025-04-11 16:59:48 -07:00
parent 1d70396931
commit 1cc9df8804
99 changed files with 539 additions and 590 deletions
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1
dcalc/ArnoldiDelayCalc.cc
View File

@ -65,6 +65,7 @@ namespace sta {
// ra_get_s
using std::abs;
using std::vector;
struct delay_work;
struct delay_c;

2
dcalc/ArnoldiReduce.cc
View File

@ -38,6 +38,8 @@
namespace sta {
using std::string;
rcmodel::rcmodel() :
pinV(nullptr)
{

6
dcalc/CcsCeffDelayCalc.hh
View File

@ -29,9 +29,7 @@
namespace sta {
using std::vector;
typedef map<const Pin*, FloatSeq, PinIdLess> WatchPinValuesMap;
typedef std::map<const Pin*, FloatSeq, PinIdLess> WatchPinValuesMap;
ArcDelayCalc *
makeCcsCeffDelayCalc(StaState *sta);
@ -68,7 +66,7 @@ public:
Waveform watchWaveform(const Pin *pin) override;
protected:
typedef vector<double> Region;
typedef std::vector<double> Region;
void gateDelaySlew(const LibertyLibrary *drvr_library,
const RiseFall *rf,

1
dcalc/GraphDelayCalc.cc
View File

@ -50,6 +50,7 @@
namespace sta {
using std::abs;
using std::array;
static const Slew default_slew = 0.0;

2
dcalc/ParallelDelayCalc.cc
View File

@ -34,6 +34,8 @@
namespace sta {
using std::vector;
ParallelDelayCalc::ParallelDelayCalc(StaState *sta):
DelayCalcBase(sta)
{

88
dcalc/PrimaDelayCalc.cc
View File

@ -285,7 +285,7 @@ PrimaDelayCalc::simulate()
simulate1(Gq_, Cq_, Bq_, xq_init_, Vq_, prima_order_);
}
else {
MatrixXd x_to_v = MatrixXd::Identity(order_, order_);
Eigen::MatrixXd x_to_v = Eigen::MatrixXd::Identity(order_, order_);
simulate1(G_, C_, B_, x_init_, x_to_v, order_);
}
}
@ -293,14 +293,14 @@ PrimaDelayCalc::simulate()
void
PrimaDelayCalc::simulate1(const MatrixSd &G,
const MatrixSd &C,
const MatrixXd &B,
const VectorXd &x_init,
const MatrixXd &x_to_v,
const Eigen::MatrixXd &B,
const Eigen::VectorXd &x_init,
const Eigen::MatrixXd &x_to_v,
const size_t order)
{
VectorXd x(order);
VectorXd x_prev(order);
VectorXd x_prev2(order);
Eigen::VectorXd x(order);
Eigen::VectorXd x_prev(order);
Eigen::VectorXd x_prev2(order);
v_.resize(order);
v_prev_.resize(order);
@ -321,7 +321,7 @@ PrimaDelayCalc::simulate1(const MatrixSd &G,
// Initial time depends on ceff which impact delay, so use a sim step
// to find an initial ceff.
setPortCurrents();
VectorXd rhs(order);
Eigen::VectorXd rhs(order);
rhs = B * u_ + (1.0 / time_step_) * C * (3.0 * x_prev - x_prev2);
x = A_solver.solve(rhs);
v_ = x_to_v * x;
@ -771,12 +771,12 @@ PrimaDelayCalc::primaReduce()
SparseLU<MatrixSd> G_solver(G_);
if (G_solver.info() != Eigen::Success)
report_->error(1752, "G matrix is singular.");
MatrixXd R(order_, port_count_);
Eigen::MatrixXd R(order_, port_count_);
R = G_solver.solve(B_);
// Step 4
HouseholderQR<MatrixXd> R_solver(R);
MatrixXd Q = R_solver.householderQ();
Eigen::HouseholderQR<Eigen::MatrixXd> R_solver(R);
Eigen::MatrixXd Q = R_solver.householderQ();
// Vq is "X" in the prima paper (too many "x" variables in the paper).
Vq_.resize(order_, prima_order_);
@ -785,7 +785,7 @@ PrimaDelayCalc::primaReduce()
// Step 6 - Arnolid iteration
for (size_t k = 1; k < prima_order_; k++) {
VectorXd V = C_ * Vq_.col(k - 1);
Eigen::VectorXd V = C_ * Vq_.col(k - 1);
Vq_.col(k) = G_solver.solve(V);
// Modified Gram-Schmidt orthonormalization
@ -793,9 +793,9 @@ PrimaDelayCalc::primaReduce()
double H = Vq_.col(j).transpose() * Vq_.col(k);
Vq_.col(k) = Vq_.col(k) - H * Vq_.col(j);
}
VectorXd Vq_k = Vq_.col(k);
HouseholderQR<MatrixXd> Vq_k_solver(Vq_k);
MatrixXd VqQ = Vq_k_solver.householderQ();
Eigen::VectorXd Vq_k = Vq_.col(k);
Eigen::HouseholderQR<Eigen::MatrixXd> Vq_k_solver(Vq_k);
Eigen::MatrixXd VqQ = Vq_k_solver.householderQ();
Vq_.col(k) = VqQ.col(0);
}
@ -824,36 +824,36 @@ PrimaDelayCalc::primaReduce2()
{
G_.makeCompressed();
// Step 3: solve G*R = B for R
SparseLU<MatrixSd> G_solver(G_);
MatrixXd R(order_, port_count_);
Eigen::SparseLU<MatrixSd> G_solver(G_);
Eigen::MatrixXd R(order_, port_count_);
R = G_solver.solve(B_);
// Step 4
HouseholderQR<MatrixXd> R_solver(R);
MatrixXd Q = R_solver.householderQ();
Eigen::HouseholderQR<Eigen::MatrixXd> R_solver(R);
Eigen::MatrixXd Q = R_solver.householderQ();
// Vq is "X" in the prima paper (too many "x" variables in the paper).
size_t n = ceil(prima_order_ / static_cast<double>(port_count_));
MatrixXd Vq(order_, n * port_count_);
Eigen::MatrixXd Vq(order_, n * port_count_);
// // Vq = first port_count columns of Q.
Vq.block(0, 0, order_, port_count_) = Q.block(0, 0, order_, port_count_);
// Step 6 - Arnolid iteration
for (size_t k = 1; k < n; k++) {
MatrixXd V = C_ * Vq.block(0, (k - 1) * port_count_, order_, port_count_);
MatrixXd GV = G_solver.solve(V);
Eigen::MatrixXd V = C_ * Vq.block(0, (k - 1) * port_count_, order_, port_count_);
Eigen::MatrixXd GV = G_solver.solve(V);
Vq.block(0, k * port_count_, order_, port_count_) = GV;
// Modified Gram-Schmidt orthonormalization
for (size_t j = 0; j < k; j++) {
MatrixXd H = Vq.block(0, j * port_count_, order_, port_count_).transpose()
Eigen::MatrixXd H = Vq.block(0, j * port_count_, order_, port_count_).transpose()
* Vq.block(0, k * port_count_, order_, port_count_);
Vq.block(0, k * port_count_, order_, port_count_) =
Vq.block(0, k * port_count_, order_, port_count_) - Vq.block(0, j * port_count_, order_, port_count_) * H;
}
MatrixXd Vq_k = Vq.block(0, k * port_count_, order_, port_count_);
HouseholderQR<MatrixXd> Vq_k_solver(Vq_k);
MatrixXd VqQ = Vq_k_solver.householderQ();
Eigen::MatrixXd Vq_k = Vq.block(0, k * port_count_, order_, port_count_);
Eigen::HouseholderQR<Eigen::MatrixXd> Vq_k_solver(Vq_k);
Eigen::MatrixXd VqQ = Vq_k_solver.householderQ();
Vq.block(0, k * port_count_, order_, port_count_) =
VqQ.block(0, 0, order_, port_count_);
}
@ -970,7 +970,7 @@ PrimaDelayCalc::reportMatrix(const char *name,
void
PrimaDelayCalc::reportMatrix(const char *name,
MatrixXd &matrix)
Eigen::MatrixXd &matrix)
{
report_->reportLine("%s", name);
reportMatrix(matrix);
@ -978,7 +978,7 @@ PrimaDelayCalc::reportMatrix(const char *name,
void
PrimaDelayCalc::reportMatrix(const char *name,
VectorXd &matrix)
Eigen::VectorXd &matrix)
{
report_->reportLine("%s", name);
reportMatrix(matrix);
@ -986,7 +986,7 @@ PrimaDelayCalc::reportMatrix(const char *name,
void
PrimaDelayCalc::reportVector(const char *name,
vector<double> &matrix)
std::vector<double> &matrix)
{
report_->reportLine("%s", name);
reportVector(matrix);
@ -995,10 +995,10 @@ PrimaDelayCalc::reportVector(const char *name,
void
PrimaDelayCalc::reportMatrix(MatrixSd &matrix)
{
for (Index i = 0; i < matrix.rows(); i++) {
for (Eigen::Index i = 0; i < matrix.rows(); i++) {
string line = "| ";
for (Index j = 0; j < matrix.cols(); j++) {
string entry = stdstrPrint("%10.3e", matrix.coeff(i, j));
for (Eigen::Index j = 0; j < matrix.cols(); j++) {
std::string entry = stdstrPrint("%10.3e", matrix.coeff(i, j));
line += entry;
line += " ";
}
@ -1008,12 +1008,12 @@ PrimaDelayCalc::reportMatrix(MatrixSd &matrix)
}
void
PrimaDelayCalc::reportMatrix(MatrixXd &matrix)
PrimaDelayCalc::reportMatrix(Eigen::MatrixXd &matrix)
{
for (Index i = 0; i < matrix.rows(); i++) {
string line = "| ";
for (Index j = 0; j < matrix.cols(); j++) {
string entry = stdstrPrint("%10.3e", matrix.coeff(i, j));
for (Eigen::Index i = 0; i < matrix.rows(); i++) {
std::string line = "| ";
for (Eigen::Index j = 0; j < matrix.cols(); j++) {
std::string entry = stdstrPrint("%10.3e", matrix.coeff(i, j));
line += entry;
line += " ";
}
@ -1023,11 +1023,11 @@ PrimaDelayCalc::reportMatrix(MatrixXd &matrix)
}
void
PrimaDelayCalc::reportMatrix(VectorXd &matrix)
PrimaDelayCalc::reportMatrix(Eigen::VectorXd &matrix)
{
string line = "| ";
for (Index i = 0; i < matrix.rows(); i++) {
string entry = stdstrPrint("%10.3e", matrix.coeff(i));
std::string line = "| ";
for (Eigen::Index i = 0; i < matrix.rows(); i++) {
std::string entry = stdstrPrint("%10.3e", matrix.coeff(i));
line += entry;
line += " ";
}
@ -1036,11 +1036,11 @@ PrimaDelayCalc::reportMatrix(VectorXd &matrix)
}
void
PrimaDelayCalc::reportVector(vector<double> &matrix)
PrimaDelayCalc::reportVector(std::vector<double> &matrix)
{
string line = "| ";
std::string line = "| ";
for (size_t i = 0; i < matrix.size(); i++) {
string entry = stdstrPrint("%10.3e", matrix[i]);
std::string entry = stdstrPrint("%10.3e", matrix[i]);
line += entry;
line += " ";
}

79
dcalc/PrimaDelayCalc.hh
View File

@ -40,21 +40,12 @@ class ArcDelayCalc;
class StaState;
class Corner;
using std::vector;
using std::array;
using Eigen::MatrixXd;
using Eigen::MatrixXcd;
using Eigen::VectorXd;
using Eigen::SparseMatrix;
using Eigen::Index;
using std::map;
typedef Map<const Pin*, size_t, PinIdLess> PinNodeMap;
typedef map<const ParasiticNode*, size_t, ParasiticNodeLess> NodeIndexMap;
typedef std::map<const ParasiticNode*, size_t, ParasiticNodeLess> NodeIndexMap;
typedef Map<const Pin*, size_t> PortIndexMap;
typedef SparseMatrix<double> MatrixSd;
typedef Map<const Pin*, VectorXd, PinIdLess> PinLMap;
typedef map<const Pin*, FloatSeq, PinIdLess> WatchPinValuesMap;
typedef Eigen::SparseMatrix<double> MatrixSd;
typedef Map<const Pin*, Eigen::VectorXd, PinIdLess> PinLMap;
typedef std::map<const Pin*, FloatSeq, PinIdLess> WatchPinValuesMap;
typedef Table1 Waveform;
@ -96,14 +87,14 @@ public:
ArcDcalcResultSeq gateDelays(ArcDcalcArgSeq &dcalc_args,
const LoadPinIndexMap &load_pin_index_map,
const DcalcAnalysisPt *dcalc_ap) override;
string reportGateDelay(const Pin *drvr_pin,
const TimingArc *arc,
const Slew &in_slew,
float load_cap,
const Parasitic *parasitic,
const LoadPinIndexMap &load_pin_index_map,
const DcalcAnalysisPt *dcalc_ap,
int digits) override;
std::string reportGateDelay(const Pin *drvr_pin,
const TimingArc *arc,
const Slew &in_slew,
float load_cap,
const Parasitic *parasitic,
const LoadPinIndexMap &load_pin_index_map,
const DcalcAnalysisPt *dcalc_ap,
int digits) override;
// Record waveform for drvr/load pin.
void watchPin(const Pin *pin) override;
@ -116,9 +107,9 @@ protected:
void simulate();
void simulate1(const MatrixSd &G,
const MatrixSd &C,
const MatrixXd &B,
const VectorXd &x_init,
const MatrixXd &x_to_v,
const Eigen::MatrixXd &B,
const Eigen::VectorXd &x_init,
const Eigen::MatrixXd &x_to_v,
const size_t order);
double maxTime();
double timeStep();
@ -164,15 +155,15 @@ protected:
void reportMatrix(const char *name,
MatrixSd &matrix);
void reportMatrix(const char *name,
MatrixXd &matrix);
Eigen::MatrixXd &matrix);
void reportMatrix(const char *name,
VectorXd &matrix);
Eigen::VectorXd &matrix);
void reportVector(const char *name,
vector<double> &matrix);
std::vector<double> &matrix);
void reportMatrix(MatrixSd &matrix);
void reportMatrix(MatrixXd &matrix);
void reportMatrix(VectorXd &matrix);
void reportVector(vector<double> &matrix);
void reportMatrix(Eigen::MatrixXd &matrix);
void reportMatrix(Eigen::VectorXd &matrix);
void reportVector(std::vector<double> &matrix);
ArcDcalcArgSeq *dcalc_args_;
size_t drvr_count_;
@ -184,10 +175,10 @@ protected:
PinNodeMap pin_node_map_; // Parasitic pin -> array index
NodeIndexMap node_index_map_; // Parasitic node -> array index
vector<OutputWaveforms*> output_waveforms_;
std::vector<OutputWaveforms*> output_waveforms_;
double resistance_sum_;
vector<double> node_capacitances_;
std::vector<double> node_capacitances_;
bool includes_pin_caps_;
float coupling_cap_multiplier_;
@ -199,25 +190,25 @@ protected:
// G*x(t) + C*x'(t) = B*u(t)
MatrixSd G_;
MatrixSd C_;
MatrixXd B_;
VectorXd x_init_;
VectorXd u_;
Eigen::MatrixXd B_;
Eigen::VectorXd x_init_;
Eigen::VectorXd u_;
// Prima reduced MNA eqns
size_t prima_order_;
MatrixXd Vq_;
Eigen::MatrixXd Vq_;
MatrixSd Gq_;
MatrixSd Cq_;
MatrixXd Bq_;
VectorXd xq_init_;
Eigen::MatrixXd Bq_;
Eigen::VectorXd xq_init_;
// Node voltages.
VectorXd v_; // voltage[node_idx]
VectorXd v_prev_;
Eigen::VectorXd v_; // voltage[node_idx]
Eigen::VectorXd v_prev_;
// Indexed by driver index.
vector<double> ceff_;
vector<double> drvr_current_;
std::vector<double> ceff_;
std::vector<double> drvr_current_;
double time_step_;
double time_step_prev_;
@ -240,11 +231,11 @@ protected:
static constexpr size_t threshold_vth = 1;
static constexpr size_t threshold_vh = 2;
static constexpr size_t measure_threshold_count_ = 3;
typedef array<double, measure_threshold_count_> ThresholdTimes;
typedef std::array<double, measure_threshold_count_> ThresholdTimes;
// Vl Vth Vh
ThresholdTimes measure_thresholds_;
// Indexed by node number.
vector<ThresholdTimes> threshold_times_;
std::vector<ThresholdTimes> threshold_times_;
// Delay calculator to use when ccs waveforms are missing from liberty.
ArcDelayCalc *table_dcalc_;

5
graph/Graph.cc
View File

@ -38,6 +38,8 @@
namespace sta {
using std::string;
////////////////////////////////////////////////////////////////
//
// Graph
@ -1298,7 +1300,8 @@ Edge::setArcDelayAnnotated(const TimingArc *arc,
if (index > sizeof(intptr_t) * 8
&& arc_delay_annotated_is_bits_) {
arc_delay_annotated_is_bits_ = false;
arc_delay_annotated_.seq_ = new vector<bool>(ap_count * RiseFall::index_count * 2);
size_t bit_count = ap_count * RiseFall::index_count * 2;
arc_delay_annotated_.seq_ = new std::vector<bool>(bit_count);
}
if (arc_delay_annotated_is_bits_) {
if (annotated)

14
include/sta/ArcDelayCalc.hh
View File

@ -40,10 +40,6 @@
namespace sta {
using std::string;
using std::vector;
using std::map;
class Corner;
class Parasitic;
class DcalcAnalysisPt;
@ -54,7 +50,7 @@ typedef std::vector<ArcDcalcArg*> ArcDcalcArgPtrSeq;
typedef std::vector<ArcDcalcArg> ArcDcalcArgSeq;
// Driver load pin -> index in driver loads.
typedef map<const Pin *, size_t, PinIdLess> LoadPinIndexMap;
typedef std::map<const Pin *, size_t, PinIdLess> LoadPinIndexMap;
// Arguments for gate delay calculation delay/slew at one driver pin
// through one timing arc at one delay calc analysis point.
@ -138,12 +134,12 @@ protected:
ArcDelay gate_delay_;
Slew drvr_slew_;
// Load wire delay and slews indexed by load pin index.
vector<ArcDelay> wire_delays_;
vector<Slew> load_slews_;
std::vector<ArcDelay> wire_delays_;
std::vector<Slew> load_slews_;
};
typedef vector<ArcDcalcArg> ArcDcalcArgSeq;
typedef vector<ArcDcalcResult> ArcDcalcResultSeq;
typedef std::vector<ArcDcalcArg> ArcDcalcArgSeq;
typedef std::vector<ArcDcalcResult> ArcDcalcResultSeq;
// Delay calculator class hierarchy.
// ArcDelayCalc

22
include/sta/ConcreteLibrary.hh
View File

@ -45,10 +45,10 @@ class PatternMatch;
class LibertyCell;
class LibertyPort;
typedef Map<string, ConcreteCell*> ConcreteCellMap;
typedef std::map<string, string> AttributeMap;
typedef Map<std::string, ConcreteCell*> ConcreteCellMap;
typedef std::map<std::string, std::string> AttributeMap;
typedef Vector<ConcretePort*> ConcretePortSeq;
typedef Map<string, ConcretePort*> ConcretePortMap;
typedef Map<std::string, ConcretePort*> ConcretePortMap;
typedef ConcreteCellMap::ConstIterator ConcreteLibraryCellIterator;
typedef ConcretePortSeq::ConstIterator ConcreteCellPortIterator;
typedef ConcretePortSeq::ConstIterator ConcretePortMemberIterator;
@ -82,9 +82,9 @@ protected:
void renameCell(ConcreteCell *cell,
const char *cell_name);
string name_;
std::string name_;
ObjectId id_;
string filename_;
std::string filename_;
bool is_liberty_;
char bus_brkt_left_;
char bus_brkt_right_;
@ -114,9 +114,9 @@ public:
ConcreteCellPortBitIterator *portBitIterator() const;
bool isLeaf() const { return is_leaf_; }
void setIsLeaf(bool is_leaf);
void setAttribute(const string &key,
const string &value);
string getAttribute(const string &key) const;
void setAttribute(const std::string &key,
const std::string &value);
std::string getAttribute(const std::string &key) const;
// Cell acts as port factory.
ConcretePort *makePort(const char *name);
@ -156,10 +156,10 @@ protected:
const char *name,
int index);
string name_;
std::string name_;
ObjectId id_;
// Filename is optional.
string filename_;
std::string filename_;
ConcreteLibrary *library_;
LibertyCell *liberty_cell_;
// External application cell.
@ -236,7 +236,7 @@ protected:
ConcretePortSeq *member_ports,
ConcreteCell *cell);
string name_;
std::string name_;
ObjectId id_;
ConcreteCell *cell_;
PortDirection *direction_;

24
include/sta/ConcreteNetwork.hh
View File

@ -46,7 +46,7 @@ class ConcreteBindingTbl;
class ConcreteLibertyLibraryIterator;
typedef Vector<ConcreteLibrary*> ConcreteLibrarySeq;
typedef std::map<string, string> AttributeMap;
typedef std::map<std::string, std::string> AttributeMap;
typedef Map<const char*, ConcreteLibrary*, CharPtrLess> ConcreteLibraryMap;
typedef ConcreteLibrarySeq::ConstIterator ConcreteLibraryIterator;
typedef Map<const char *, ConcreteInstance*,
@ -83,8 +83,8 @@ public:
const PatternMatch *pattern) const override;
const char *name(const Cell *cell) const override;
string getAttribute(const Cell *cell,
const string &key) const override;
std::string getAttribute(const Cell *cell,
const std::string &key) const override;
ObjectId id(const Cell *cell) const override;
Library *library(const Cell *cell) const override;
LibertyCell *libertyCell(Cell *cell) const override;
@ -119,8 +119,8 @@ public:
PortMemberIterator *memberIterator(const Port *port) const override;
const char *name(const Instance *instance) const override;
string getAttribute(const Instance *inst,
const string &key) const override;
std::string getAttribute(const Instance *inst,
const std::string &key) const override;
ObjectId id(const Instance *instance) const override;
Cell *cell(const Instance *instance) const override;
Instance *parent(const Instance *instance) const override;
@ -189,8 +189,8 @@ public:
void setIsLeaf(Cell *cell,
bool is_leaf) override;
void setAttribute(Cell *cell,
const string &key,
const string &value) override;
const std::string &key,
const std::string &value) override;
Port *makePort(Cell *cell,
const char *name) override;
Port *makeBusPort(Cell *cell,
@ -223,8 +223,8 @@ public:
LibertyPort *port,
Net *net) override;
void setAttribute(Instance *inst,
const string &key,
const string &value) override;
const std::string &key,
const std::string &value) override;
void disconnectPin(Pin *pin) override;
void deletePin(Pin *pin) override;
Net *makeNet(const char *name,
@ -304,9 +304,9 @@ public:
InstanceNetIterator *netIterator() const;
Instance *findChild(const char *name) const;
InstanceChildIterator *childIterator() const;
void setAttribute(const string &key,
const string &value);
string getAttribute(const string &key) const;
void setAttribute(const std::string &key,
const std::string &value);
std::string getAttribute(const std::string &key) const;
void addChild(ConcreteInstance *child);
void deleteChild(ConcreteInstance *child);
void addPin(ConcretePin *pin);

2
include/sta/Corner.hh
View File

@ -126,7 +126,7 @@ protected:
void addPathAP(PathAnalysisPt *path_ap);
private:
string name_;
std::string name_;
int index_;
ParasiticAnalysisPtSeq parasitic_analysis_pts_;
DcalcAnalysisPtSeq dcalc_analysis_pts_;

21
include/sta/EnumNameMap.hh
View File

@ -29,32 +29,27 @@
namespace sta {
using std::string;
using std::map;
using std::initializer_list;
using std::pair;
// Helper for mapping enum values to strings and back.
template <class ENUM>
class EnumNameMap
{
public:
EnumNameMap(initializer_list<pair<const ENUM, string>> enum_names);
EnumNameMap(std::initializer_list<std::pair<const ENUM, std::string>> enum_names);
const char *find(ENUM key) const;
ENUM find(string name,
ENUM find(std::string name,
ENUM unknown_key) const;
void find(string name,
void find(std::string name,
// Return values.
ENUM &key,
bool &exists) const;
private:
map<ENUM, string> enum_map_;
map<string, ENUM> name_map_;
std::map<ENUM, std::string> enum_map_;
std::map<std::string, ENUM> name_map_;
};
template <class ENUM>
EnumNameMap<ENUM>::EnumNameMap(initializer_list<pair<const ENUM, string>> enum_names) :
EnumNameMap<ENUM>::EnumNameMap(std::initializer_list<std::pair<const ENUM,std::string>> enum_names) :
enum_map_(enum_names)
{
for (const auto& [key, name] : enum_map_)
@ -74,7 +69,7 @@ EnumNameMap<ENUM>::find(ENUM key) const
template <class ENUM>
void
EnumNameMap<ENUM>::find(string name,
EnumNameMap<ENUM>::find(std::string name,
// Return values.
ENUM &key,
bool &exists) const
@ -90,7 +85,7 @@ EnumNameMap<ENUM>::find(string name,
template <class ENUM>
ENUM
EnumNameMap<ENUM>::find(string name,
EnumNameMap<ENUM>::find(std::string name,
ENUM unknown_key) const
{
auto find_iter = name_map_.find(name);

2
include/sta/Error.hh
View File

@ -48,7 +48,7 @@ public:
virtual bool suppressed() const { return suppressed_; }
private:
string msg_;
std::string msg_;
bool suppressed_;
};

10
include/sta/FuncExpr.hh
View File

@ -32,8 +32,6 @@
namespace sta {
using std::string;
class FuncExpr
{
public:
@ -79,7 +77,7 @@ public:
TimingSense portTimingSense(const LibertyPort *port) const;
// Return true if expression has port as an input.
bool hasPort(const LibertyPort *port) const;
string to_string() const;
std::string to_string() const;
// Sub expression for a bus function (bit_offset is 0 to bus->size()-1).
FuncExpr *bitSubExpr(int bit_offset);
// Check to make sure the function and port size are compatible.
@ -88,9 +86,9 @@ public:
bool checkSize(LibertyPort *port);
private:
string to_string(bool with_parens) const;
string to_string(bool with_parens,
char op) const;
std::string to_string(bool with_parens) const;
std::string to_string(bool with_parens,
char op) const;
Operator op_;
FuncExpr *left_;

6
include/sta/Graph.hh
View File

@ -247,7 +247,7 @@ public:
~Vertex();
Pin *pin() const { return pin_; }
// Pin path with load/driver suffix for bidirects.
string to_string(const StaState *sta) const;
std::string to_string(const StaState *sta) const;
// compatibility
const char *name(const Network *network) const;
bool isBidirectDriver() const { return is_bidirect_drvr_; }
@ -366,7 +366,7 @@ class Edge
public:
Edge();
~Edge();
string to_string(const StaState *sta) const;
std::string to_string(const StaState *sta) const;
Vertex *to(const Graph *graph) const { return graph->vertex(to_); }
VertexId to() const { return to_; }
Vertex *from(const Graph *graph) const { return graph->vertex(from_); }
@ -426,7 +426,7 @@ protected:
ArcDelay *arc_delays_;
union {
uintptr_t bits_;
vector<bool> *seq_;
std::vector<bool> *seq_;
} arc_delay_annotated_;
bool arc_delay_annotated_is_bits_:1;
bool delay_annotation_is_incremental_:1;

4
include/sta/GraphClass.hh
View File

@ -35,8 +35,6 @@
namespace sta {
using std::vector;
// Class declarations for pointer references.
class Graph;
class Vertex;
@ -56,7 +54,7 @@ typedef int Level;
typedef int DcalcAPIndex;
typedef int TagGroupIndex;
typedef Vector<GraphLoop*> GraphLoopSeq;
typedef vector<Slew> SlewSeq;
typedef std::vector<Slew> SlewSeq;
static constexpr int level_max = std::numeric_limits<Level>::max();

10
include/sta/GraphDelayCalc.hh
View File

@ -38,17 +38,13 @@
namespace sta {
using std::vector;
using std::map;
using std::array;
class DelayCalcObserver;
class MultiDrvrNet;
class FindVertexDelays;
class NetCaps;
typedef Map<const Vertex*, MultiDrvrNet*> MultiDrvrNetMap;
typedef vector<SlewSeq> DrvrLoadSlews;
typedef std::vector<SlewSeq> DrvrLoadSlews;
// This class traverses the graph calling the arc delay calculator and
// annotating delays on graph edges.
@ -191,7 +187,7 @@ protected:
ArcDelayCalc *arc_delay_calc,
LoadPinIndexMap &load_pin_index_map,
// Return value.
array<bool, RiseFall::index_count> &delay_exists);
std::array<bool, RiseFall::index_count> &delay_exists);
bool findDriverArcDelays(Vertex *drvr_vertex,
const MultiDrvrNet *multi_drvr,
Edge *edge,
@ -333,7 +329,7 @@ private:
Vertex *dcalc_drvr_;
VertexSeq drvrs_;
// [drvr_rf->index][dcalc_ap->index]
vector<NetCaps> net_caps_;
std::vector<NetCaps> net_caps_;
};
} // namespace

2
include/sta/Hash.hh
View File

@ -29,8 +29,6 @@
namespace sta {
using std::size_t;
const size_t hash_init_value = 5381;
// Dan Bernstein, comp.lang.c.

10
include/sta/InternalPower.hh
View File

@ -87,11 +87,11 @@ public:
const Pvt *pvt,
float in_slew,
float load_cap) const;
string reportPower(const LibertyCell *cell,
const Pvt *pvt,
float in_slew,
float load_cap,
int digits) const;
std::string reportPower(const LibertyCell *cell,
const Pvt *pvt,
float in_slew,
float load_cap,
int digits) const;
protected:
void findAxisValues(float in_slew,

34
include/sta/Liberty.hh
View File

@ -88,9 +88,9 @@ typedef Map<const TimingArcSet*, LatchEnable*> LatchEnableMap;
typedef Vector<LatchEnable*> LatchEnableSeq;
typedef Map<const char *, OcvDerate*, CharPtrLess> OcvDerateMap;
typedef Vector<InternalPowerAttrs*> InternalPowerAttrsSeq;
typedef Map<string, float> SupplyVoltageMap;
typedef Map<string, LibertyPgPort*> LibertyPgPortMap;
typedef Map<string, DriverWaveform*> DriverWaveformMap;
typedef Map<std::string, float> SupplyVoltageMap;
typedef Map<std::string, LibertyPgPort*> LibertyPgPortMap;
typedef Map<std::string, DriverWaveform*> DriverWaveformMap;
typedef Vector<DcalcAnalysisPt*> DcalcAnalysisPtSeq;
enum class ClockGateType { none, latch_posedge, latch_negedge, other };
@ -647,8 +647,8 @@ protected:
bool has_internal_ports_;
std::atomic<bool> have_voltage_waveforms_;
std::mutex waveform_lock_;
string footprint_;
string user_function_class_;
std::string footprint_;
std::string user_function_class_;
private:
friend class LibertyLibrary;
@ -888,8 +888,8 @@ protected:
float min_pulse_width_[RiseFall::index_count];
const RiseFall *pulse_clk_trigger_;
const RiseFall *pulse_clk_sense_;
string related_ground_pin_;
string related_power_pin_;
std::string related_ground_pin_;
std::string related_power_pin_;
Vector<LibertyPort*> corner_ports_;
ReceiverModelPtr receiver_model_;
DriverWaveform *driver_waveform_[RiseFall::index_count];
@ -969,7 +969,7 @@ public:
void setWireloadTree(WireloadTree tree);
protected:
string name_;
std::string name_;
WireloadTree wire_load_tree_;
};
@ -996,7 +996,7 @@ public:
void print();
protected:
string name_;
std::string name_;
float scales_[scale_factor_type_count][scale_factor_pvt_count][RiseFall::index_count];
};
@ -1011,7 +1011,7 @@ public:
int to() const { return to_; }
protected:
string name_;
std::string name_;
int from_;
int to_;
};
@ -1032,7 +1032,7 @@ protected:
// Private to LibertyCell::makeModeDef.
ModeDef(const char *name);
string name_;
std::string name_;
ModeValueMap values_;
private:
@ -1056,9 +1056,9 @@ protected:
FuncExpr *cond,
const char *sdf_cond);
string value_;
std::string value_;
FuncExpr *cond_;
string sdf_cond_;
std::string sdf_cond_;
private:
friend class ModeDef;
@ -1085,7 +1085,7 @@ public:
void setAxis3(TableAxisPtr axis);
protected:
string name_;
std::string name_;
TableAxisPtr axis1_;
TableAxisPtr axis2_;
TableAxisPtr axis3_;
@ -1143,13 +1143,13 @@ public:
const LibertyPgPort *port2);
private:
string name_;
std::string name_;
PgType pg_type_;
string voltage_name_;
std::string voltage_name_;
LibertyCell *cell_;
};
string
std::string
portLibertyToSta(const char *port_name);
const char *
scanSignalTypeName(ScanSignalType scan_type);

4
include/sta/LibertyClass.hh
View File

@ -32,8 +32,6 @@
namespace sta {
using std::vector;
class Units;
class Unit;
class LibertyLibrary;
@ -81,7 +79,7 @@ typedef std::shared_ptr<Table> TablePtr;
typedef std::shared_ptr<TimingArcAttrs> TimingArcAttrsPtr;
typedef std::shared_ptr<TableAxis> TableAxisPtr;
typedef std::shared_ptr<ReceiverModel> ReceiverModelPtr;
typedef vector<StatetableRow> StatetableRows;
typedef std::vector<StatetableRow> StatetableRows;
enum class ScaleFactorType : unsigned {
pin_cap,

10
include/sta/MinMax.hh
View File

@ -32,8 +32,6 @@
namespace sta {
using std::string;
class MinMax;
class MinMaxAll;
@ -58,7 +56,7 @@ public:
static int earlyIndex() { return min_.index_; }
static int maxIndex() { return max_.index_; }
static int lateIndex() { return max_.index_; }
const string &to_string() const { return name_; }
const std::string &to_string() const { return name_; }
int index() const { return index_; }
float initValue() const { return init_value_; }
int initValueInt() const { return init_value_int_; }
@ -91,7 +89,7 @@ private:
bool (*compare)(float value1,
float value2));
const string name_;
const std::string name_;
int index_;
float init_value_;
int init_value_int_;
@ -114,7 +112,7 @@ public:
static const MinMaxAll *max() { return &max_; }
static const MinMaxAll *late() { return &max_; }
static const MinMaxAll *all() { return &all_; }
const string &to_string() const { return name_; }
const std::string &to_string() const { return name_; }
int index() const { return index_; }
const MinMax *asMinMax() const;
bool matches(const MinMax *min_max) const;
@ -131,7 +129,7 @@ private:
std::vector<const MinMax*> range,
std::vector<int> range_index);
const string name_;
const std::string name_;
int index_;
const std::vector<const MinMax*> range_;
const std::vector<int> range_index_;

22
include/sta/Network.hh
View File

@ -35,8 +35,6 @@
namespace sta {
using std::function;
class Report;
class PatternMatch;
class PinVisitor;
@ -44,8 +42,8 @@ class PinVisitor;
typedef Map<const char*, LibertyLibrary*, CharPtrLess> LibertyLibraryMap;
// Link network function returns top level instance.
// Return nullptr if link fails.
typedef function<Instance* (const char *top_cell_name,
bool make_black_boxes)> LinkNetworkFunc;
typedef std::function<Instance* (const char *top_cell_name,
bool make_black_boxes)> LinkNetworkFunc;
typedef Map<const Net*, PinSet*> NetDrvrPinsMap;
// The Network class defines the network API used by sta.
@ -153,8 +151,8 @@ public:
// Filename may return null.
virtual const char *filename(const Cell *cell) = 0;
// Attributes can be null
virtual string getAttribute(const Cell *cell,
const string &key) const = 0;
virtual std::string getAttribute(const Cell *cell,
const std::string &key) const = 0;
// Name can be a simple, bundle, bus, or bus bit name.
virtual Port *findPort(const Cell *cell,
const char *name) const = 0;
@ -217,8 +215,8 @@ public:
const PatternMatch *pattern) const;
virtual InstanceSeq findInstancesHierMatching(const Instance *instance,
const PatternMatch *pattern) const;
virtual string getAttribute(const Instance *inst,
const string &key) const = 0;
virtual std::string getAttribute(const Instance *inst,
const std::string &key) const = 0;
// Hierarchical path name.
virtual const char *pathName(const Instance *instance) const;
bool pathNameLess(const Instance *inst1,
@ -559,11 +557,11 @@ public:
virtual void setIsLeaf(Cell *cell,
bool is_leaf) = 0;
virtual void setAttribute(Cell *cell,
const string &key,
const string &value) = 0;
const std::string &key,
const std::string &value) = 0;
virtual void setAttribute(Instance *instance,
const string &key,
const string &value) = 0;
const std::string &key,
const std::string &value) = 0;
virtual Port *makePort(Cell *cell,
const char *name) = 0;
virtual Port *makeBusPort(Cell *cell,

2
include/sta/Parasitics.hh
View File

@ -314,7 +314,7 @@ public:
void setCouplingCapFactor(float factor);
private:
string name_;
std::string name_;
int index_;
int index_max_;
float coupling_cap_factor_;

12
include/sta/ParseBus.hh
View File

@ -28,8 +28,6 @@
namespace sta {
using std::string;
// Return true if name is a bus.
bool
isBusName(const char *name,
@ -51,7 +49,7 @@ parseBusName(const char *name,
char escape,
// Return values.
bool &is_bus,
string &bus_name,
std::string &bus_name,
int &index);
// Allow multiple different left/right bus brackets.
void
@ -61,7 +59,7 @@ parseBusName(const char *name,
char escape,
// Return values.
bool &is_bus,
string &bus_name,
std::string &bus_name,
int &index);
// Parse a bus range, such as BUS[4:0].
@ -75,7 +73,7 @@ parseBusName(const char *name,
// Return values.
bool &is_bus,
bool &is_range,
string &bus_name,
std::string &bus_name,
int &from,
int &to,
bool &subscript_wild);
@ -90,13 +88,13 @@ parseBusName(const char *name,
// Return values.
bool &is_bus,
bool &is_range,
string &bus_name,
std::string &bus_name,
int &from,
int &to,
bool &subscript_wild);
// Insert escapes before ch1 and ch2 in token.
string
std::string
escapeChars(const char *token,
const char ch1,
const char ch2,

2
include/sta/Path.hh
View File

@ -61,7 +61,7 @@ public:
bool is_enum,
const StaState *sta);
~Path();
string to_string(const StaState *sta) const;
std::string to_string(const StaState *sta) const;
bool isNull() const;
// prev_path null
void init(Vertex *vertex,

4
include/sta/PathAnalysisPt.hh
View File

@ -37,8 +37,6 @@ class MinMax;
class DcalcAnalysisPt;
class Corner;
using std::string;
class PathAnalysisPt
{
public:
@ -46,7 +44,7 @@ public:
PathAPIndex index,
const MinMax *path_min_max,
DcalcAnalysisPt *dcalc_ap);
string to_string() const;
std::string to_string() const;
Corner *corner() const { return corner_; }
PathAPIndex index() const { return index_; }
const MinMax *pathMinMax() const { return path_min_max_; }

2
include/sta/PathEnd.hh
View File

@ -40,8 +40,6 @@ class RiseFall;
class MinMax;
class ReportPath;
using std::string;
// PathEnds represent search endpoints that are either unconstrained
// or constrained by a timing check, output delay, data check,
// or path delay.

4
include/sta/PatternMatch.hh
View File

@ -53,10 +53,10 @@ public:
PatternMatch(const char *pattern);
PatternMatch(const char *pattern,
const PatternMatch *inherit_from);
PatternMatch(const string &pattern,
PatternMatch(const std::string &pattern,
const PatternMatch *inherit_from);
bool match(const char *str) const;
bool match(const string &str) const;
bool match(const std::string &str) const;
bool matchNoCase(const char *str) const;
const char *pattern() const { return pattern_; }
bool isRegexp() const { return is_regexp_; }

4
include/sta/Property.hh
View File

@ -34,8 +34,6 @@
namespace sta {
using std::string;
class Sta;
// Adding a new property type
@ -58,7 +56,7 @@ public:
type_clk, type_clks, type_paths, type_pwr_activity };
PropertyValue();
PropertyValue(const char *value);
PropertyValue(string &value);
PropertyValue(std::string &value);
PropertyValue(float value,
const Unit *unit);
explicit PropertyValue(bool value);

6
include/sta/Report.hh
View File

@ -36,8 +36,6 @@ struct Tcl_Interp;
namespace sta {
using std::string;
// Output streams used for printing.
// This is a wrapper for all printing. It supports logging output to
// a file and redirection of command output to a file.
@ -51,7 +49,7 @@ public:
virtual void reportLine(const char *fmt, ...)
__attribute__((format (printf, 2, 3)));
virtual void reportLineString(const char *line);
virtual void reportLineString(const string &line);
virtual void reportLineString(const std::string &line);
virtual void reportBlankLine();
////////////////////////////////////////////////////////////////
@ -158,7 +156,7 @@ protected:
FILE *log_stream_;
FILE *redirect_stream_;
bool redirect_to_string_;
string redirect_string_;
std::string redirect_string_;
// Buffer to support printf style arguments.
size_t buffer_size_;
char *buffer_;

8
include/sta/Sdc.hh
View File

@ -62,8 +62,6 @@ class Corner;
class ClockPinIterator;
class ClockIterator;
using std::vector;
typedef std::pair<const Pin*, const Clock*> PinClockPair;
class ClockInsertionkLess
@ -1321,12 +1319,12 @@ protected:
// set_load port
// set_fanout_load port
// Indexed by corner_index.
vector<PortExtCapMap> port_ext_cap_maps_;
std::vector<PortExtCapMap> port_ext_cap_maps_;
// set_load net
// Indexed by corner_index.
vector<NetWireCapMap> net_wire_cap_maps_;
std::vector<NetWireCapMap> net_wire_cap_maps_;
// Indexed by corner_index.
vector<PinWireCapMap> drvr_pin_wire_cap_maps_;
std::vector<PinWireCapMap> drvr_pin_wire_cap_maps_;
NetResistanceMap net_res_map_;
PinSet disabled_pins_;
PortSet disabled_ports_;

8
include/sta/SdcNetwork.hh
View File

@ -54,8 +54,8 @@ public:
const PatternMatch *pattern) const override;
const char *name(const Cell *cell) const override;
string getAttribute(const Cell *cell,
const string &key) const override;
std::string getAttribute(const Cell *cell,
const std::string &key) const override;
ObjectId id(const Cell *cell) const override;
Library *library(const Cell *cell) const override;
LibertyCell *libertyCell(Cell *cell) const override;
@ -91,8 +91,8 @@ public:
bool hasMembers(const Port *port) const override;
ObjectId id(const Instance *instance) const override;
string getAttribute(const Instance *inst,
const string &key) const override;
std::string getAttribute(const Instance *inst,
const std::string &key) const override;
Instance *topInstance() const override;
Cell *cell(const Instance *instance) const override;
Instance *parent(const Instance *instance) const override;

6
include/sta/Search.hh
View File

@ -70,7 +70,7 @@ typedef UnorderedSet<TagGroup*, TagGroupHash, TagGroupEqual> TagGroupSet;
typedef Map<Vertex*, Slack> VertexSlackMap;
typedef Vector<VertexSlackMap> VertexSlackMapSeq;
typedef Vector<WorstSlacks> WorstSlacksSeq;
typedef vector<DelayDbl> DelayDblSeq;
typedef std::vector<DelayDbl> DelayDblSeq;
class Search : public StaState
{
@ -629,14 +629,14 @@ protected:
// Entries in tags_ may be missing where previous filter tags were deleted.
TagIndex tag_capacity_;
std::atomic<Tag **> tags_;
vector<Tag **> tags_prev_;
std::vector<Tag **> tags_prev_;
TagIndex tag_next_;
// Holes in tags_ left by deleting filter tags.
std::vector<TagIndex> tag_free_indices_;
std::mutex tag_lock_;
TagGroupSet *tag_group_set_;
std::atomic<TagGroup **> tag_groups_;
vector<TagGroup **> tag_groups_prev_;
std::vector<TagGroup **> tag_groups_prev_;
TagGroupIndex tag_group_next_;
// Holes in tag_groups_ left by deleting filter tag groups.
std::vector<TagIndex> tag_group_free_indices_;

2
include/sta/SearchClass.hh
View File

@ -119,7 +119,7 @@ typedef UnorderedMap<Tag*, size_t, TagMatchHash, TagMatchEqual> PathIndexMap;
typedef Vector<Slack> SlackSeq;
typedef Delay Crpr;
typedef Vector<Path*> PathSeq;
typedef vector<const Path*> ConstPathSeq;
typedef std::vector<const Path*> ConstPathSeq;
enum class ReportPathFormat { full,
full_clock,

6
include/sta/Sequential.hh
View File

@ -55,10 +55,8 @@ enum class StateInternalValue {
class StatetableRow;
using std::vector;
typedef vector<StateInputValue> StateInputValues;
typedef vector<StateInternalValue> StateInternalValues;
typedef std::vector<StateInputValue> StateInputValues;
typedef std::vector<StateInternalValue> StateInternalValues;
// Register/Latch
class Sequential

3
include/sta/Sta.hh
View File

@ -44,9 +44,6 @@ struct Tcl_Interp;
namespace sta {
using std::string;
using ::Tcl_Interp;
// Don't include headers to minimize dependencies.
class MinMax;
class MinMaxAll;

2
include/sta/StringSet.hh
View File

@ -31,7 +31,7 @@
namespace sta {
typedef Set<const char*, CharPtrLess> StringSet;
typedef std::set<string> StdStringSet;
typedef std::set<std::string> StdStringSet;
void
deleteContents(StringSet *strings);

18
include/sta/StringUtil.hh
View File

@ -33,8 +33,6 @@
namespace sta {
using std::string;
inline bool
stringEq(const char *str1,
const char *str2)
@ -167,19 +165,19 @@ isDigits(const char *str);
char *
stringPrint(const char *fmt,
...) __attribute__((format (printf, 1, 2)));
string
std::string
stdstrPrint(const char *fmt,
...) __attribute__((format (printf, 1, 2)));
char *
stringPrintArgs(const char *fmt,
va_list args);
void
stringPrint(string &str,
stringPrint(std::string &str,
const char *fmt,
...) __attribute__((format (printf, 2, 3)));
// Formated append to std::string.
void
stringAppend(string &str,
stringAppend(std::string &str,
const char *fmt,
...) __attribute__((format (printf, 2, 3)));
@ -191,7 +189,7 @@ stringPrintTmp(const char *fmt,
char *
makeTmpString(size_t length);
char *
makeTmpString(string &str);
makeTmpString(std::string &str);
bool
isTmpString(const char *str);
@ -199,13 +197,13 @@ isTmpString(const char *str);
// Trim right spaces.
void
trimRight(string &str);
trimRight(std::string &str);
typedef Vector<string> StringVector;
typedef Vector<std::string> StringVector;
void
split(const string &text,
const string &delims,
split(const std::string &text,
const std::string &delims,
// Return values.
StringVector &tokens);

2
include/sta/TableModel.hh
View File

@ -35,8 +35,6 @@
namespace sta {
using std::string;
class Unit;
class Units;
class Report;

6
include/sta/TimingRole.hh
View File

@ -33,7 +33,7 @@ namespace sta {
class TimingRole;
typedef std::map<string, const TimingRole*> TimingRoleMap;
typedef std::map<std::string, const TimingRole*> TimingRoleMap;
class TimingRole
{
@ -68,7 +68,7 @@ public:
static const TimingRole *nonSeqHold() { return &non_seq_hold_; }
static const TimingRole *clockTreePathMin() { return &clock_tree_path_min_; }
static const TimingRole *clockTreePathMax() { return &clock_tree_path_max_; }
const string &to_string() const { return name_; }
const std::string &to_string() const { return name_; }
int index() const { return index_; }
bool isWire() const;
bool isTimingCheck() const { return is_timing_check_; }
@ -101,7 +101,7 @@ private:
const TimingRole *generic_role,
int index);
const string name_;
const std::string name_;
bool is_timing_check_;
bool is_sdf_iopath_;
bool is_non_seq_check_;

20
include/sta/Transition.hh
View File

@ -37,7 +37,7 @@ class Transition;
class RiseFall;
class RiseFallBoth;
typedef Map<const string, const Transition*> TransitionMap;
typedef Map<const std::string, const Transition*> TransitionMap;
// Rise/fall transition.
class RiseFall
@ -48,7 +48,7 @@ public:
static const RiseFall *fall() { return &fall_; }
static int riseIndex() { return rise_.sdf_triple_index_; }
static int fallIndex() { return fall_.sdf_triple_index_; }
const string &to_string() const { return short_name_; }
const std::string &to_string() const { return short_name_; }
const char *name() const { return name_.c_str(); }
const char *shortName() const { return short_name_.c_str(); }
int index() const { return sdf_triple_index_; }
@ -75,8 +75,8 @@ protected:
const char *short_name,
int sdf_triple_index);
const string name_;
const string short_name_;
const std::string name_;
const std::string short_name_;
const int sdf_triple_index_;
static const RiseFall rise_;
@ -93,7 +93,7 @@ public:
static const RiseFallBoth *rise() { return &rise_; }
static const RiseFallBoth *fall() { return &fall_; }
static const RiseFallBoth *riseFall() { return &rise_fall_; }
const string &to_string() const { return short_name_; }
const std::string &to_string() const { return short_name_; }
const char *name() const { return name_.c_str(); }
const char *shortName() const { return short_name_.c_str(); }
int index() const { return sdf_triple_index_; }
@ -119,8 +119,8 @@ protected:
std::vector<const RiseFall*> range,
std::vector<int> range_index);
const string name_;
const string short_name_;
const std::string name_;
const std::string short_name_;
const int sdf_triple_index_;
const RiseFall *as_rise_fall_;
const std::vector<const RiseFall*> range_;
@ -150,7 +150,7 @@ public:
static const Transition *trZX() { return &tr_ZX_; }
// Matches rise and fall.
static const Transition *riseFall() { return &rise_fall_; }
const string &to_string() const { return name_; }
const std::string &to_string() const { return name_; }
// As initial/final value pair.
const char *asInitFinalString() const { return init_final_.c_str(); }
int sdfTripleIndex() const { return sdf_triple_index_; }
@ -168,8 +168,8 @@ private:
const RiseFall *as_rise_fall,
int sdf_triple_index);
const string name_;
const string init_final_;
const std::string name_;
const std::string init_final_;
const RiseFall *as_rise_fall_;
const int sdf_triple_index_;

6
include/sta/Units.hh
View File

@ -28,8 +28,6 @@
namespace sta {
using std::string;
class Unit
{
public:
@ -62,8 +60,8 @@ private:
void setScaledSuffix();
float scale_; // multiplier from user units to internal units
string suffix_; // print suffix
string scaled_suffix_;
std::string suffix_; // print suffix
std::string scaled_suffix_;
int digits_; // print digits (after decimal pt)
};

26
include/sta/VerilogNamespace.hh
View File

@ -28,24 +28,22 @@
namespace sta {
using std::string;
string
std::string
cellVerilogName(const char *sta_name);
string
std::string
instanceVerilogName(const char *sta_name);
string
std::string
netVerilogName(const char *sta_name);
string
std::string
portVerilogName(const char *sta_name);
string
moduleVerilogToSta(const string *sta_name);
string
instanceVerilogToSta(const string *sta_name);
string
netVerilogToSta(const string *sta_name);
string
portVerilogToSta(const string *sta_name);
std::string
moduleVerilogToSta(const std::string *sta_name);
std::string
instanceVerilogToSta(const std::string *sta_name);
std::string
netVerilogToSta(const std::string *sta_name);
std::string
portVerilogToSta(const std::string *sta_name);
} // namespace

58
include/sta/VerilogReader.hh
View File

@ -70,10 +70,6 @@ typedef Vector<VerilogAttrStmt*> VerilogAttrStmtSeq;
typedef Vector<VerilogAttrEntry*> VerilogAttrEntrySeq;
typedef Vector<VerilogError*> VerilogErrorSeq;
using std::string;
using std::vector;
using std::set;
class VerilogReader
{
public:
@ -81,12 +77,12 @@ public:
~VerilogReader();
bool read(const char *filename);
void makeModule(const string *module_name,
void makeModule(const std::string *module_name,
VerilogNetSeq *ports,
VerilogStmtSeq *stmts,
VerilogAttrStmtSeq *attr_stmts,
int line);
void makeModule(const string *module_name,
void makeModule(const std::string *module_name,
VerilogStmtSeq *port_dcls,
VerilogStmtSeq *stmts,
VerilogAttrStmtSeq *attr_stmts,
@ -99,7 +95,7 @@ public:
VerilogDclArg *arg,
VerilogAttrStmtSeq *attr_stmts,
int line);
VerilogDclArg *makeDclArg(const string *net_name);
VerilogDclArg *makeDclArg(const std::string *net_name);
VerilogDclArg*makeDclArg(VerilogAssign *assign);
VerilogDclBus *makeDclBus(PortDirection *dir,
int from_index,
@ -113,36 +109,36 @@ public:
VerilogDclArgSeq *args,
VerilogAttrStmtSeq *attr_stmts,
int line);
VerilogInst *makeModuleInst(const string *module_name,
const string *inst_name,
VerilogInst *makeModuleInst(const std::string *module_name,
const std::string *inst_name,
VerilogNetSeq *pins,
VerilogAttrStmtSeq *attr_stmts,
const int line);
VerilogAssign *makeAssign(VerilogNet *lhs,
VerilogNet *rhs,
int line);
VerilogNetScalar *makeNetScalar(const string *name);
VerilogNetPortRef *makeNetNamedPortRefScalarNet(const string *port_vname);
VerilogNetPortRef *makeNetNamedPortRefScalarNet(const string *port_name,
const string *net_name);
VerilogNetPortRef *makeNetNamedPortRefBitSelect(const string *port_name,
const string *bus_name,
VerilogNetScalar *makeNetScalar(const std::string *name);
VerilogNetPortRef *makeNetNamedPortRefScalarNet(const std::string *port_vname);
VerilogNetPortRef *makeNetNamedPortRefScalarNet(const std::string *port_name,
const std::string *net_name);
VerilogNetPortRef *makeNetNamedPortRefBitSelect(const std::string *port_name,
const std::string *bus_name,
int index);
VerilogNetPortRef *makeNetNamedPortRefScalar(const string *port_name,
VerilogNetPortRef *makeNetNamedPortRefScalar(const std::string *port_name,
VerilogNet *net);
VerilogNetPortRef *makeNetNamedPortRefBit(const string *port_name,
VerilogNetPortRef *makeNetNamedPortRefBit(const std::string *port_name,
int index,
VerilogNet *net);
VerilogNetPortRef *makeNetNamedPortRefPart(const string *port_name,
VerilogNetPortRef *makeNetNamedPortRefPart(const std::string *port_name,
int from_index,
int to_index,
VerilogNet *net);
VerilogNetConcat *makeNetConcat(VerilogNetSeq *nets);
VerilogNetConstant *makeNetConstant(const string *constant,
VerilogNetConstant *makeNetConstant(const std::string *constant,
int line);
VerilogNetBitSelect *makeNetBitSelect(const string *name,
VerilogNetBitSelect *makeNetBitSelect(const std::string *name,
int index);
VerilogNetPartSelect *makeNetPartSelect(const string *name,
VerilogNetPartSelect *makeNetPartSelect(const std::string *name,
int from_index,
int to_index);
VerilogModule *module(Cell *cell);
@ -160,11 +156,11 @@ public:
const char *filename,
int line,
const char *fmt, ...);
const string &zeroNetName() const { return zero_net_name_; }
const string &oneNetName() const { return one_net_name_; }
const std::string &zeroNetName() const { return zero_net_name_; }
const std::string &oneNetName() const { return one_net_name_; }
void deleteModules();
void reportStmtCounts();
const string &constant10Max() const { return constant10_max_; }
const std::string &constant10Max() const { return constant10_max_; }
protected:
void init(const char *filename);
@ -173,13 +169,13 @@ protected:
VerilogNetSeq *ports);
Port *makeCellPort(Cell *cell,
VerilogModule *module,
const string &port_name);
const std::string &port_name);
void makeNamedPortRefCellPorts(Cell *cell,
VerilogModule *module,
VerilogNet *mod_port,
StdStringSet &port_names);
void checkModuleDcls(VerilogModule *module,
set<string> &port_names);
std::set<std::string> &port_names);
void makeModuleInstBody(VerilogModule *module,
Instance *inst,
VerilogBindingTbl *bindings,
@ -230,7 +226,7 @@ protected:
bool is_leaf);
void makeInstPin(Instance *inst,
Port *port,
const string &net_name,
const std::string &net_name,
VerilogBindingTbl *bindings,
Instance *parent,
VerilogBindingTbl *parent_bindings,
@ -259,7 +255,7 @@ protected:
bool hasScalarNamedPortRefs(LibertyCell *liberty_cell,
VerilogNetSeq *pins);
string filename_;
std::string filename_;
Report *report_;
Debug *debug_;
NetworkReader *network_;
@ -268,9 +264,9 @@ protected:
int black_box_index_;
VerilogModuleMap module_map_;
VerilogErrorSeq link_errors_;
const string zero_net_name_;
const string one_net_name_;
string constant10_max_;
const std::string zero_net_name_;
const std::string one_net_name_;
std::string constant10_max_;
ViewType *view_type_;
bool report_stmt_stats_;
int module_count_;

2
liberty/FuncExpr.cc
View File

@ -30,6 +30,8 @@
namespace sta {
using std::string;
FuncExpr *
FuncExpr::makePort(LibertyPort *port)
{

2
liberty/LibExprParse.yy
View File

@ -37,7 +37,7 @@
#pragma GCC diagnostic ignored "-Wunused-but-set-variable"
void
sta::LibExprParse::error(const string &msg)
sta::LibExprParse::error(const std::string &msg)
{
reader->parseError(msg.c_str());
}

2
liberty/LibExprReader.cc
View File

@ -42,7 +42,7 @@ parseFuncExpr(const char *func,
Report *report)
{
if (func != nullptr && func[0] != '\0') {
string func1(func);
std::string func1(func);
std::istringstream stream(func);
LibExprReader reader(func, cell, error_msg, report);
LibExprScanner scanner(stream);

4
liberty/LibExprScanner.hh
View File

@ -36,8 +36,6 @@
namespace sta {
using std::string;
class Report;
class LibExprParse;
@ -56,7 +54,7 @@ public:
private:
Report *report_;
string token_;
std::string token_;
};
} // namespace

2
liberty/LibertyParse.yy
View File

@ -39,7 +39,7 @@
void
sta::LibertyParse::error(const location_type &loc,
const string &msg)
const std::string &msg)
{
reader->report()->fileError(164, reader->filename().c_str(),
loc.begin.line, "%s", msg.c_str());

2
liberty/LibertyParser.cc
View File

@ -36,6 +36,8 @@
namespace sta {
using std::string;
void
parseLibertyFile(const char *filename,
LibertyGroupVisitor *library_visitor,

24
liberty/LibertyParser.hh
View File

@ -48,11 +48,11 @@ class LibertyScanner;
typedef Vector<LibertyStmt*> LibertyStmtSeq;
typedef Vector<LibertyGroup*> LibertyGroupSeq;
typedef Vector<LibertyAttr*> LibertyAttrSeq;
typedef Map<string, LibertyAttr*> LibertyAttrMap;
typedef Map<string, LibertyDefine*> LibertyDefineMap;
typedef Map<std::string, LibertyAttr*> LibertyAttrMap;
typedef Map<std::string, LibertyDefine*> LibertyDefineMap;
typedef Vector<LibertyAttrValue*> LibertyAttrValueSeq;
typedef Map<string, float> LibertyVariableMap;
typedef Map<string, LibertyGroupVisitor*>LibertyGroupVisitorMap;
typedef Map<std::string, float> LibertyVariableMap;
typedef Map<std::string, LibertyGroupVisitor*>LibertyGroupVisitorMap;
typedef LibertyAttrValueSeq::Iterator LibertyAttrValueIterator;
typedef Vector<LibertyGroup*> LibertyGroupSeq;
@ -67,8 +67,8 @@ public:
LibertyParser(const char *filename,
LibertyGroupVisitor *library_visitor,
Report *report);
const string &filename() const { return filename_; }
void setFilename(const string &filename);
const std::string &filename() const { return filename_; }
void setFilename(const std::string &filename);
Report *report() const { return report_; }
LibertyStmt *makeDefine(LibertyAttrValueSeq *values,
int line);
@ -93,7 +93,7 @@ public:
int line);
private:
string filename_;
std::string filename_;
LibertyGroupVisitor *group_visitor_;
Report *report_;
LibertyGroupSeq group_stack_;
@ -143,7 +143,7 @@ public:
protected:
void parseNames(LibertyAttrValueSeq *values);
string type_;
std::string type_;
LibertyAttrValueSeq *params_;
LibertyAttrSeq *attrs_;
LibertyAttrMap *attr_map_;
@ -177,7 +177,7 @@ public:
virtual LibertyAttrValue *firstValue() = 0;
protected:
string name_;
std::string name_;
};
// Abstract base class for simple attributes.
@ -239,7 +239,7 @@ public:
virtual const char *stringValue();
private:
string value_;
std::string value_;
};
class LibertyFloatAttrValue : public LibertyAttrValue
@ -272,7 +272,7 @@ public:
LibertyAttrType valueType() const { return value_type_; }
private:
string name_;
std::string name_;
LibertyGroupType group_type_;
LibertyAttrType value_type_;
};
@ -292,7 +292,7 @@ public:
float value() const { return value_; }
private:
string var_;
std::string var_;
float value_;
};

4
liberty/LibertyReaderPvt.hh
View File

@ -60,8 +60,6 @@ class TimingArcBuilder;
class LibertyAttr;
class OutputWaveform;
using std::vector;
typedef void (LibertyReader::*LibraryAttrVisitor)(LibertyAttr *attr);
typedef void (LibertyReader::*LibraryGroupVisitor)(LibertyGroup *group);
typedef Map<string, LibraryAttrVisitor> LibraryAttrMap;
@ -74,7 +72,7 @@ typedef Vector<InternalPowerGroup*> InternalPowerGroupSeq;
typedef Vector<LeakagePowerGroup*> LeakagePowerGroupSeq;
typedef void (LibertyPort::*LibertyPortBoolSetter)(bool value);
typedef Vector<OutputWaveform*> OutputWaveformSeq;
typedef vector<string> StdStringSeq;
typedef std::vector<std::string> StdStringSeq;
class LibertyReader : public LibertyGroupVisitor
{

6
liberty/LibertyScanner.hh
View File

@ -61,13 +61,13 @@ private:
void error(const char *msg);
std::istream *stream_;
string filename_;
std::string filename_;
LibertyParser *reader_;
Report *report_;
string token_;
std::string token_;
// Previous lex state for include files.
string filename_prev_;
std::string filename_prev_;
std::istream *stream_prev_;
};

1
network/ConcreteLibrary.cc
View File

@ -34,6 +34,7 @@
namespace sta {
using std::string;
using std::map;
using std::min;
using std::max;

2
network/ConcreteNetwork.cc
View File

@ -33,6 +33,8 @@
namespace sta {
using std::string;
static void
makeChildNetwork(Instance *proto,
Instance *parent,

2
network/Network.cc
View File

@ -34,6 +34,8 @@
namespace sta {
using std::string;
Network::Network() :
default_liberty_(nullptr),
divider_('/'),

1
network/SdcNetwork.cc
View File

@ -30,6 +30,7 @@
namespace sta {
using std::string;
using std::to_string;
static string

2
network/VerilogNamespace.cc
View File

@ -31,6 +31,8 @@
namespace sta {
using std::string;
constexpr char verilog_escape = '\\';
static string

2
parasitics/SpefParse.yy
View File

@ -39,7 +39,7 @@
void
sta::SpefParse::error(const location_type &loc,
const string &msg)
const std::string &msg)
{
reader->report()->fileError(164,reader->filename(),
loc.begin.line,"%s",msg.c_str());

4
parasitics/SpefReaderPvt.hh
View File

@ -41,9 +41,7 @@ class SpefTriple;
class Corner;
class SpefScanner;
using std::string;
typedef std::map<int, string> SpefNameMap;
typedef std::map<int, std::string> SpefNameMap;
class SpefReader : public StaState
{

6
parasitics/SpefScanner.hh
View File

@ -41,7 +41,7 @@ class SpefScanner : public SpefFlexLexer
{
public:
SpefScanner(std::istream *stream,
const string &filename,
const std::string &filename,
SpefReader *reader,
Report *report);
virtual ~SpefScanner() {}
@ -58,10 +58,10 @@ public:
using FlexLexer::yylex;
private:
string filename_;
std::string filename_;
SpefReader *reader_;
Report *report_;
string token_;
std::string token_;
};
} // namespace

2
power/Power.cc
View File

@ -74,6 +74,8 @@ using std::abs;
using std::max;
using std::min;
using std::isnormal;
using std::vector;
using std::map;
static bool
isPositiveUnate(const LibertyCell *cell,

2
power/SaifParse.yy
View File

@ -40,7 +40,7 @@
void
sta::SaifParse::error(const location_type &loc,
const string &msg)
const std::string &msg)
{
reader->report()->fileError(169,reader->filename(),loc.begin.line,"%s",msg.c_str());
}

9
power/SaifReaderPvt.hh
View File

@ -44,9 +44,6 @@ class Sta;
class Power;
class SaifScanner;
using std::vector;
using std::string;
enum class SaifState { T0, T1, TX, TZ, TB, TC, IG };
typedef std::array<uint64_t, static_cast<int>(SaifState::IG)+1> SaifStateDurations;
@ -70,7 +67,7 @@ public:
const char *filename() { return filename_; }
private:
string unescaped(const char *token);
std::string unescaped(const char *token);
const char *filename_;
const char *scope_; // Divider delimited scope to begin annotation.
@ -80,9 +77,9 @@ private:
double timescale_;
int64_t duration_;
vector<string> saif_scope_; // Scope during parsing.
std::vector<std::string> saif_scope_; // Scope during parsing.
size_t in_scope_level_;
vector<Instance*> path_; // Path within scope.
std::vector<Instance*> path_; // Path within scope.
std::set<const Pin*> annotated_pins_;
Power *power_;
};

6
power/SaifScanner.hh
View File

@ -41,7 +41,7 @@ class SaifScanner : public SaifFlexLexer
{
public:
SaifScanner(std::istream *stream,
const string &filename,
const std::string &filename,
SaifReader *reader,
Report *report);
virtual ~SaifScanner() {}
@ -57,10 +57,10 @@ public:
using FlexLexer::yylex;
private:
string filename_;
std::string filename_;
SaifReader *reader_;
Report *report_;
string token_;
std::string token_;
};
} // namespace

4
power/VcdParse.cc
View File

@ -34,6 +34,8 @@
namespace sta {
using std::vector;
using std::string;
using std::isspace;
// Very imprecise syntax definition
@ -52,7 +54,7 @@ VcdParse::read(const char *filename,
reader_ = reader;
file_line_ = 1;
stmt_line_ = 1;
string token = getToken();
std::string token = getToken();
while (!token.empty()) {
if (token == "$date")
reader_->setDate(readStmtString());

33
power/VcdParse.hh
View File

@ -33,11 +33,8 @@
namespace sta {
using std::string;
using std::vector;
typedef int64_t VcdTime;
typedef vector<string> VcdScope;
typedef std::vector<std::string> VcdScope;
enum class VcdVarType {
wire,
@ -71,19 +68,19 @@ public:
private:
void parseTimescale();
void setTimeUnit(const string &time_unit,
void setTimeUnit(const std::string &time_unit,
double time_scale);
void parseVar();
void parseScope();
void parseUpscope();
void parseVarValues();
string getToken();
string readStmtString();
vector<string> readStmtTokens();
std::string getToken();
std::string readStmtString();
std::vector<std::string> readStmtTokens();
VcdReader *reader_;
gzFile stream_;
string token_;
std::string token_;
const char *filename_;
int file_line_;
int stmt_line_;
@ -101,24 +98,24 @@ class VcdReader
{
public:
virtual ~VcdReader() {}
virtual void setDate(const string &date) = 0;
virtual void setComment(const string &comment) = 0;
virtual void setVersion(const string &version) = 0;
virtual void setTimeUnit(const string &time_unit,
virtual void setDate(const std::string &date) = 0;
virtual void setComment(const std::string &comment) = 0;
virtual void setVersion(const std::string &version) = 0;
virtual void setTimeUnit(const std::string &time_unit,
double time_unit_scale,
double time_scale) = 0;
virtual void setTimeMax(VcdTime time_max) = 0;
virtual void varMinDeltaTime(VcdTime min_delta_time) = 0;
virtual bool varIdValid(const string &id) = 0;
virtual bool varIdValid(const std::string &id) = 0;
virtual void makeVar(const VcdScope &scope,
const string &name,
const std::string &name,
VcdVarType type,
size_t width,
const string &id) = 0;
virtual void varAppendValue(const string &id,
const std::string &id) = 0;
virtual void varAppendValue(const std::string &id,
VcdTime time,
char value) = 0;
virtual void varAppendBusValue(const string &id,
virtual void varAppendBusValue(const std::string &id,
VcdTime time,
int64_t bus_value) = 0;
};

2
sdc/ExceptionPath.cc
View File

@ -37,6 +37,8 @@
namespace sta {
using std::string;
static bool
thrusIntersectPts(ExceptionThruSeq *thrus1,
ExceptionThruSeq *thrus2,

2
sdc/WriteSdc.cc
View File

@ -60,6 +60,8 @@
namespace sta {
using std::string;
typedef Set<ClockSense*> ClockSenseSet;
typedef Vector<ClockSense*> ClockSenseSeq;

2
sdf/ReportAnnotation.cc
View File

@ -290,7 +290,7 @@ ReportAnnotated::reportCheckCount(const TimingRole *role,
{
int index = role->index();
if (edge_count_[index] > 0) {
string title;
std::string title;
stringPrint(title, "cell %s arcs", role->to_string().c_str());
reportCount(title.c_str(), index, total, annotated_total);
}

12
sdf/SdfLex.ll
View File

@ -82,7 +82,7 @@ EOL \r?\n
"\"" {
BEGIN INITIAL;
yylval->string = new string(token_);
yylval->string = new std::string(token_);
return token::QSTRING;
}
@ -157,7 +157,7 @@ COND {
<COND_EXPR>"("{BLANK}*IOPATH {
BEGIN INITIAL;
yylval->string = new string(token_);
yylval->string = new std::string(token_);
return token::EXPR_OPEN_IOPATH;
}
@ -167,7 +167,7 @@ COND {
*/
if (reader_->inTimingCheck()) {
BEGIN INITIAL;
yylval->string = new string(token_);
yylval->string = new std::string(token_);
return token::EXPR_OPEN;
}
else
@ -179,9 +179,9 @@ COND {
if (reader_->inTimingCheck()) {
BEGIN INITIAL;
/* remove trailing ")" */
string cond_id(token_);
std::string cond_id(token_);
cond_id += yytext;
yylval->string = new string(cond_id.substr(0, cond_id.size() - 1));
yylval->string = new std::string(cond_id.substr(0, cond_id.size() - 1));
/* No way to pass expr and id separately, so pass them together. */
return token::EXPR_ID_CLOSE;
}
@ -194,7 +194,7 @@ COND {
<COND_EXPR>. { token_ += yytext[0]; }
{ID} {
yylval->string = new string(yytext);
yylval->string = new std::string(yytext);
return token::ID;
}

2
sdf/SdfParse.yy
View File

@ -36,7 +36,7 @@
void
sta::SdfParse::error(const location_type &loc,
const string &msg)
const std::string &msg)
{
reader->report()->fileError(164,reader->filename().c_str(),
loc.begin.line,"%s",msg.c_str());

5
sdf/SdfReader.cc
View File

@ -45,6 +45,7 @@
namespace sta {
using std::string;
using std::to_string;
class SdfTriple
@ -65,8 +66,8 @@ class SdfPortSpec
{
public:
SdfPortSpec(const Transition *tr,
const string *port,
const string *cond);
const std::string *port,
const std::string *cond);
~SdfPortSpec();
const string *port() const { return port_; }
const Transition *transition() const { return tr_; }

52
sdf/SdfReaderPvt.hh
View File

@ -59,7 +59,7 @@ public:
void setDivider(char divider);
void setTimescale(float multiplier,
const string *units);
const std::string *units);
void setPortDeviceDelay(Edge *edge,
SdfTripleSeq *triples,
bool from_trans);
@ -80,17 +80,17 @@ public:
int triple_index,
int arc_delay_index,
const MinMax *min_max);
void setInstance(const string *instance_name);
void setInstance(const std::string *instance_name);
void setInstanceWildcard();
void cellFinish();
void setCell(const string *cell_name);
void interconnect(const string *from_pin_name,
const string *to_pin_name,
void setCell(const std::string *cell_name);
void interconnect(const std::string *from_pin_name,
const std::string *to_pin_name,
SdfTripleSeq *triples);
void iopath(SdfPortSpec *from_edge,
const string *to_port_name,
const std::string *to_port_name,
SdfTripleSeq *triples,
const string *cond,
const std::string *cond,
bool condelse);
void timingCheck(const TimingRole *role,
SdfPortSpec *data_edge,
@ -118,10 +118,10 @@ public:
SdfPortSpec *clk_edge,
SdfTriple *before_triple,
SdfTriple *after_triple);
void port(const string *to_pin_name,
void port(const std::string *to_pin_name,
SdfTripleSeq *triples);
void device(SdfTripleSeq *triples);
void device(const string *to_pin_name,
void device(const std::string *to_pin_name,
SdfTripleSeq *triples);
SdfTriple *makeTriple();
@ -133,20 +133,20 @@ public:
SdfTripleSeq *makeTripleSeq();
void deleteTripleSeq(SdfTripleSeq *triples);
SdfPortSpec *makePortSpec(const Transition *tr,
const string *port,
const string *cond);
SdfPortSpec *makeCondPortSpec(const string *cond_port);
string *unescaped(const string *token);
string *makePath(const string *head,
const string *tail);
const std::string *port,
const std::string *cond);
SdfPortSpec *makeCondPortSpec(const std::string *cond_port);
std::string *unescaped(const std::string *token);
std::string *makePath(const std::string *head,
const std::string *tail);
// Parser state used to control lexer for COND handling.
bool inTimingCheck() { return in_timing_check_; }
void setInTimingCheck(bool in);
bool inIncremental() const { return in_incremental_; }
void setInIncremental(bool incr);
string *makeBusName(string *bus_name,
int index);
const string &filename() const { return filename_; }
std::string *makeBusName(std::string *bus_name,
int index);
const std::string &filename() const { return filename_; }
void sdfWarn(int id,
const char *fmt, ...);
void sdfError(int id,
@ -161,11 +161,11 @@ private:
Edge *findCheckEdge(Pin *from_pin,
Pin *to_pin,
const TimingRole *sdf_role,
const string *cond_start,
const string *cond_end);
const std::string *cond_start,
const std::string *cond_end);
Edge *findWireEdge(Pin *from_pin,
Pin *to_pin);
bool condMatch(const string *sdf_cond,
bool condMatch(const std::string *sdf_cond,
const char *lib_cond);
void timingCheck1(const TimingRole *role,
Port *data_port,
@ -180,17 +180,17 @@ private:
const TimingRole *sdf_role,
SdfTriple *triple,
bool match_generic);
Pin *findPin(const string *name);
Instance *findInstance(const string *name);
Pin *findPin(const std::string *name);
Instance *findInstance(const std::string *name);
void setEdgeDelays(Edge *edge,
SdfTripleSeq *triples,
const char *sdf_cmd);
void setDevicePinDelays(Pin *to_pin,
SdfTripleSeq *triples);
Port *findPort(const Cell *cell,
const string *port_name);
const std::string *port_name);
string filename_;
std::string filename_;
SdfScanner *scanner_;
const char *path_;
// Which values to pull out of the sdf triples.
@ -207,7 +207,7 @@ private:
char divider_;
char escape_;
Instance *instance_;
const string *cell_name_;
const std::string *cell_name_;
bool in_timing_check_;
bool in_incremental_;
float timescale_;

6
sdf/SdfScanner.hh
View File

@ -41,7 +41,7 @@ class SdfScanner : public SdfFlexLexer
{
public:
SdfScanner(std::istream *stream,
const string &filename,
const std::string &filename,
SdfReader *reader,
Report *report);
virtual ~SdfScanner() {}
@ -57,10 +57,10 @@ public:
using FlexLexer::yylex;
private:
string filename_;
std::string filename_;
SdfReader *reader_;
Report *report_;
string token_;
std::string token_;
};
} // namespace

2
search/CheckTiming.hh
View File

@ -72,7 +72,7 @@ protected:
ClockSet &clks);
void errorMsgSubst(const char *msg,
int count,
string &error_msg);
std::string &error_msg);
CheckErrorSeq errors_;
};

2
search/ClkInfo.cc
View File

@ -133,7 +133,7 @@ ClkInfo::asString(const StaState *sta) const
{
Network *network = sta->network();
Corners *corners = sta->corners();
string result;
std::string result;
PathAnalysisPt *path_ap = corners->findPathAnalysisPt(path_ap_index_);
result += path_ap->pathMinMax()->to_string();

2
search/Corner.cc
View File

@ -149,7 +149,7 @@ Corners::makeParasiticAnalysisPts(bool per_corner)
int ap_index = corner->index() * MinMax::index_count + mm_index;
int ap_index_max = corner->index() * MinMax::index_count
+ MinMax::max()->index();
string ap_name = corner->name();
std::string ap_name = corner->name();
ap_name += "_";
ap_name += min_max->to_string();
ParasiticAnalysisPt *ap = new ParasiticAnalysisPt(ap_name.c_str(),

4
search/Genclks.cc
View File

@ -895,7 +895,7 @@ Genclks::recordSrcPaths(Clock *gclk)
bool has_edges = gclk->edges() != nullptr;
for (const Pin *gclk_pin : gclk->leafPins()) {
vector<Path> &src_paths = genclk_src_paths_[ClockPinPair(gclk, gclk_pin)];
std::vector<Path> &src_paths = genclk_src_paths_[ClockPinPair(gclk, gclk_pin)];
src_paths.resize(path_count);
Vertex *gclk_vertex = srcPath(gclk_pin);
bool found_src_paths = false;
@ -1002,7 +1002,7 @@ Genclks::srcPath(const Clock *gclk,
{
auto itr = genclk_src_paths_.find(ClockPinPair(gclk, src_pin));
if (itr != genclk_src_paths_.end()) {
vector<Path> src_paths = itr->second;
std::vector<Path> src_paths = itr->second;
if (!src_paths.empty()) {
size_t path_index = srcPathIndex(rf, path_ap);
Path &src_path = src_paths[path_index];

2
search/Genclks.hh
View File

@ -50,7 +50,7 @@ public:
};
typedef Map<Clock*, GenclkInfo*> GenclkInfoMap;
typedef Map<ClockPinPair, vector<Path>, ClockPinPairLess> GenclkSrcPathMap;
typedef Map<ClockPinPair, std::vector<Path>, ClockPinPairLess> GenclkSrcPathMap;
class Genclks : public StaState
{

2
search/Path.cc
View File

@ -200,7 +200,7 @@ Path::init(Vertex *vertex,
is_enum_ = false;
}
string
std::string
Path::to_string(const StaState *sta) const
{
const PathAnalysisPt *path_ap = pathAnalysisPt(sta);

4
search/PathAnalysisPt.cc
View File

@ -42,10 +42,10 @@ PathAnalysisPt::PathAnalysisPt(Corner *corner,
{
}
string
std::string
PathAnalysisPt::to_string() const
{
string name = corner_->name();
std::string name = corner_->name();
name += '/';
name += path_min_max_->to_string();
return name;

64
search/ReportPath.hh
View File

@ -37,8 +37,6 @@ class DcalcAnalysisPt;
class PathExpanded;
class ReportField;
using std::string;
typedef Vector<ReportField*> ReportFieldSeq;
class ReportPath : public StaState
@ -102,12 +100,12 @@ public:
const char *path_name,
int indent,
bool trailing_comma,
string &result) const;
std::string &result) const;
void reportJson(const PathExpanded &expanded,
const char *path_name,
int indent,
bool trailing_comma,
string &result) const;
std::string &result) const;
void reportEndHeader() const;
void reportEndLine(const PathEnd *end) const;
@ -189,17 +187,17 @@ protected:
void reportEndpointOutputDelay(const PathEndClkConstrained *end) const;
void reportEndpoint(const PathEndPathDelay *end) const;
void reportEndpoint(const PathEndGatedClock *end) const;
string pathEndpoint(const PathEnd *end) const;
string pathStartpoint(const PathEnd *end,
const PathExpanded &expanded) const;
std::string pathEndpoint(const PathEnd *end) const;
std::string pathStartpoint(const PathEnd *end,
const PathExpanded &expanded) const;
void reportBorrowing(const PathEndLatchCheck *end,
Arrival &borrow,
Arrival &time_given_to_startpoint) const;
void reportEndpoint(const PathEndDataCheck *end) const;
const char *clkNetworkDelayIdealProp(bool is_ideal) const;
string checkRoleReason(const PathEnd *end) const;
string checkRoleString(const PathEnd *end) const;
std::string checkRoleReason(const PathEnd *end) const;
std::string checkRoleString(const PathEnd *end) const;
virtual void reportGroup(const PathEnd *end) const;
void reportStartpoint(const PathEnd *end,
const PathExpanded &expanded) const;
@ -209,13 +207,13 @@ protected:
void reportEndpoint(const PathEndLatchCheck *end) const;
const char *latchDesc(const PathEndLatchCheck *end) const;
void reportStartpoint(const char *start,
const string reason) const;
const std::string reason) const;
void reportEndpoint(const char *end,
const string reason) const;
const std::string reason) const;
void reportStartEndPoint(const char *pt,
const string reason,
const std::string reason,
const char *key) const;
string tgtClkName(const PathEnd *end) const;
std::string tgtClkName(const PathEnd *end) const;
const char *clkRegLatchDesc(const PathEnd *end) const;
void reportSrcPath(const PathEnd *end,
const PathExpanded &expanded) const;
@ -285,13 +283,13 @@ protected:
Arrival clk_time,
const MinMax *min_max) const ;
void reportRequired(const PathEnd *end,
string margin_msg) const ;
std::string margin_msg) const ;
void reportSlack(const PathEnd *end) const ;
void reportSlack(Slack slack) const ;
void reportSpaceSlack(const PathEnd *end,
string &line) const ;
std::string &line) const ;
void reportSpaceSlack(Slack slack,
string &line) const ;
std::string &line) const ;
void reportSrcPathArrival(const PathEnd *end,
const PathExpanded &expanded) const ;
void reportPath(const PathEnd *end,
@ -362,7 +360,7 @@ protected:
bool total_with_minus,
const EarlyLate *early_late,
const RiseFall *rf,
string src_attr,
std::string src_attr,
const char *line_case) const;
void reportLineTotal(const char *what,
Delay incr,
@ -376,47 +374,47 @@ protected:
const EarlyLate *early_late) const;
void reportDashLineTotal() const;
void reportDescription(const char *what,
string &result) const;
std::string &result) const;
void reportDescription(const char *what,
bool first_field,
bool last_field,
string &result) const;
std::string &result) const;
void reportFieldTime(float value,
ReportField *field,
string &result) const;
std::string &result) const;
void reportSpaceFieldTime(float value,
string &result) const;
std::string &result) const;
void reportSpaceFieldDelay(Delay value,
const EarlyLate *early_late,
string &result) const;
std::string &result) const;
void reportFieldDelayMinus(Delay value,
const EarlyLate *early_late,
const ReportField *field,
string &result) const;
std::string &result) const;
void reportTotalDelay(Delay value,
const EarlyLate *early_late,
string &result) const;
std::string &result) const;
void reportFieldDelay(Delay value,
const EarlyLate *early_late,
const ReportField *field,
string &result) const;
std::string &result) const;
void reportField(float value,
const ReportField *field,
string &result) const;
std::string &result) const;
void reportField(const char *value,
const ReportField *field,
string &result) const;
std::string &result) const;
void reportFieldBlank(const ReportField *field,
string &result) const;
std::string &result) const;
void reportDashLine() const;
void reportDashLine(int line_width) const;
void reportBlankLine() const;
string descriptionField(const Vertex *vertex) const;
string descriptionField(const Pin *pin) const;
string descriptionNet(const Pin *pin) const;
std::string descriptionField(const Vertex *vertex) const;
std::string descriptionField(const Pin *pin) const;
std::string descriptionNet(const Pin *pin) const;
bool reportClkPath() const;
string clkName(const Clock *clk,
bool inverted) const;
std::string clkName(const Clock *clk,
bool inverted) const;
bool hasExtInputDriver(const Pin *pin,
const RiseFall *rf,
const MinMax *min_max) const;

2
search/Search.cc
View File

@ -2774,7 +2774,7 @@ Search::reportArrivals(Vertex *vertex) const
const PathAnalysisPt *path_ap = tag->pathAnalysisPt(this);
const RiseFall *rf = tag->transition();
const char *req = delayAsString(path->required(), this);
string prev_str;
std::string prev_str;
Path *prev_path = path->prevPath();
if (prev_path) {
prev_str += prev_path->to_string(this);

6
search/Tag.cc
View File

@ -89,20 +89,20 @@ Tag::~Tag()
delete states_;
}
string
std::string
Tag::to_string(const StaState *sta) const
{
return to_string(true, true, sta);
}
string
std::string
Tag::to_string(bool report_index,
bool report_rf_min_max,
const StaState *sta) const
{
const Network *network = sta->network();
const Corners *corners = sta->corners();
string result;
std::string result;
if (report_index)
result += std::to_string(index_);

8
search/Tag.hh
View File

@ -62,10 +62,10 @@ public:
bool own_states,
const StaState *sta);
~Tag();
string to_string(const StaState *sta) const;
string to_string(bool report_index,
bool report_rf_min_max,
const StaState *sta) const;
std::string to_string(const StaState *sta) const;
std::string to_string(bool report_index,
bool report_rf_min_max,
const StaState *sta) const;
ClkInfo *clkInfo() const { return clk_info_; }
bool isClock() const { return is_clk_; }
const ClockEdge *clkEdge() const;

2
search/TagGroup.hh
View File

@ -144,7 +144,7 @@ protected:
Vertex *vertex_;
int default_path_count_;
PathIndexMap path_index_map_;
vector<Path> paths_;
std::vector<Path> paths_;
bool has_clk_tag_;
bool has_genclk_src_tag_;
bool has_filter_tag_;

5
spice/WriteSpice.cc
View File

@ -46,6 +46,7 @@
namespace sta {
using std::ifstream;
using std::ofstream;
using std::swap;
using std::set;
@ -183,8 +184,8 @@ WriteSpice::replaceFileExt(string filename,
void
WriteSpice::writeGnuplotFile(StdStringSeq &node_nanes)
{
string gnuplot_filename = replaceFileExt(spice_filename_, "gnuplot");
string csv_filename = replaceFileExt(spice_filename_, "csv");
std::string gnuplot_filename = replaceFileExt(spice_filename_, "gnuplot");
std::string csv_filename = replaceFileExt(spice_filename_, "csv");
ofstream gnuplot_stream;
gnuplot_stream.open(gnuplot_filename);
if (gnuplot_stream.is_open()) {

21
spice/WriteSpice.hh
View File

@ -39,13 +39,10 @@
namespace sta {
using std::string;
using std::ofstream;
typedef std::map<const ParasiticNode*, int> ParasiticNodeMap;
typedef Map<string, StringVector> CellSpicePortNames;
typedef Map<std::string, StringVector> CellSpicePortNames;
typedef Map<const LibertyPort*, LogicValue> LibertyPortLogicValues;
typedef std::vector<string> StdStringSeq;
typedef std::vector<std::string> StdStringSeq;
// Utilities for writing a spice deck.
class WriteSpice : public StaState
@ -63,7 +60,7 @@ public:
protected:
void initPowerGnd();
void writeHeader(string &title,
void writeHeader(std::string &title,
float max_time,
float time_step);
void writePrintStmt(StdStringSeq &node_names);
@ -128,10 +125,10 @@ protected:
const RiseFall *from_rf,
const Pin *to_pin,
const RiseFall *to_rf,
string prefix);
std::string prefix);
void writeMeasureSlewStmt(const Pin *pin,
const RiseFall *rf,
string prefix);
std::string prefix);
const char *spiceTrans(const RiseFall *rf);
float findSlew(Vertex *vertex,
const RiseFall *rf,
@ -164,8 +161,8 @@ protected:
InstanceSet &written_insts);
PinSeq drvrLoads(const Pin *drvr_pin);
void writeSubcktInstVoltSrcs();
string replaceFileExt(string filename,
const char *ext);
std::string replaceFileExt(std::string filename,
const char *ext);
const char *spice_filename_;
const char *subckt_filename_;
@ -176,7 +173,7 @@ protected:
CircuitSim ckt_sim_;
const DcalcAnalysisPt *dcalc_ap_;
ofstream spice_stream_;
std::ofstream spice_stream_;
LibertyLibrary *default_library_;
float power_voltage_;
float gnd_voltage_;
@ -193,7 +190,7 @@ protected:
};
void
streamPrint(ofstream &stream,
streamPrint(std::ofstream &stream,
const char *fmt,
...) __attribute__((format (printf, 2, 3)));

2
util/Report.cc
View File

@ -111,7 +111,7 @@ Report::reportLineString(const char *line)
}
void
Report::reportLineString(const string &line)
Report::reportLineString(const std::string &line)
{
printLine(line.c_str(), line.length());
}

1
util/StringUtil.cc
View File

@ -37,6 +37,7 @@
namespace sta {
using std::max;
using std::string;
static void
stringPrintTmp(const char *fmt,

12
verilog/VerilogLex.ll
View File

@ -93,22 +93,22 @@ ID_TOKEN {ID_ESCAPED_TOKEN}|{ID_ALPHA_TOKEN}
}
{SIGN}?{UNSIGNED_NUMBER}?"'"[sS]?[bB][01_xz]+ {
yylval->constant = new string(yytext);
yylval->constant = new std::string(yytext);
return token::CONSTANT;
}
{SIGN}?{UNSIGNED_NUMBER}?"'"[sS]?[oO][0-7_xz]+ {
yylval->constant = new string(yytext);
yylval->constant = new std::string(yytext);
return token::CONSTANT;
}
{SIGN}?{UNSIGNED_NUMBER}?"'"[sS]?[dD][0-9_]+ {
yylval->constant = new string(yytext);
yylval->constant = new std::string(yytext);
return token::CONSTANT;
}
{SIGN}?{UNSIGNED_NUMBER}?"'"[sS]?[hH][0-9a-fA-F_xz]+ {
yylval->constant = new string(yytext);
yylval->constant = new std::string(yytext);
return token::CONSTANT;
}
@ -140,7 +140,7 @@ wire { return token::WIRE; }
wor { return token::WOR; }
{ID_TOKEN}("."{ID_TOKEN})* {
yylval->string = new string(yytext, yyleng);
yylval->string = new std::string(yytext, yyleng);
return token::ID;
}
@ -152,7 +152,7 @@ wor { return token::WOR; }
{BLANK} { /* ignore blanks */ }
\" {
yylval->string = new string;
yylval->string = new std::string;
BEGIN(QSTRING);
}

4
verilog/VerilogParse.yy
View File

@ -42,7 +42,7 @@
void
sta::VerilogParse::error(const location_type &loc,
const string &msg)
const std::string &msg)
{
reader->report()->fileError(164,reader->filename(),loc.begin.line,
"%s",msg.c_str());
@ -521,7 +521,7 @@ attr_spec_value:
| STRING
{ $$ = $1; }
| INT
{ $$ = new string(std::to_string($1)); }
{ $$ = new std::string(std::to_string($1)); }
;
%%

8
verilog/VerilogReader.cc
View File

@ -41,6 +41,8 @@
namespace sta {
using std::string;
typedef unsigned long long VerilogConstant10;
static string
@ -351,7 +353,7 @@ VerilogReader::makeNamedPortRefCellPorts(Cell *cell,
// Make sure each declaration appears in the module port list.
void
VerilogReader::checkModuleDcls(VerilogModule *module,
set<string> &port_names)
std::set<string> &port_names)
{
for (auto const & [port_name, dcl] : *module->declarationMap()) {
PortDirection *dir = dcl->direction();
@ -1641,13 +1643,13 @@ VerilogAttrEntry::VerilogAttrEntry(const string &key,
{
}
std::string
string
VerilogAttrEntry::key()
{
return key_;
}
std::string
string
VerilogAttrEntry::value()
{
return value_;

58
verilog/VerilogReader.hh
View File

@ -70,10 +70,6 @@ typedef Vector<VerilogAttrStmt*> VerilogAttrStmtSeq;
typedef Vector<VerilogAttrEntry*> VerilogAttrEntrySeq;
typedef Vector<VerilogError*> VerilogErrorSeq;
using std::string;
using std::vector;
using std::set;
class VerilogReader
{
public:
@ -81,12 +77,12 @@ public:
~VerilogReader();
bool read(const char *filename);
void makeModule(const string *module_name,
void makeModule(const std::string *module_name,
VerilogNetSeq *ports,
VerilogStmtSeq *stmts,
VerilogAttrStmtSeq *attr_stmts,
int line);
void makeModule(const string *module_name,
void makeModule(const std::string *module_name,
VerilogStmtSeq *port_dcls,
VerilogStmtSeq *stmts,
VerilogAttrStmtSeq *attr_stmts,
@ -99,7 +95,7 @@ public:
VerilogDclArg *arg,
VerilogAttrStmtSeq *attr_stmts,
int line);
VerilogDclArg *makeDclArg(const string *net_name);
VerilogDclArg *makeDclArg(const std::string *net_name);
VerilogDclArg*makeDclArg(VerilogAssign *assign);
VerilogDclBus *makeDclBus(PortDirection *dir,
int from_index,
@ -113,36 +109,36 @@ public:
VerilogDclArgSeq *args,
VerilogAttrStmtSeq *attr_stmts,
int line);
VerilogInst *makeModuleInst(const string *module_name,
const string *inst_name,
VerilogInst *makeModuleInst(const std::string *module_name,
const std::string *inst_name,
VerilogNetSeq *pins,
VerilogAttrStmtSeq *attr_stmts,
const int line);
VerilogAssign *makeAssign(VerilogNet *lhs,
VerilogNet *rhs,
int line);
VerilogNetScalar *makeNetScalar(const string *name);
VerilogNetPortRef *makeNetNamedPortRefScalarNet(const string *port_vname);
VerilogNetPortRef *makeNetNamedPortRefScalarNet(const string *port_name,
const string *net_name);
VerilogNetPortRef *makeNetNamedPortRefBitSelect(const string *port_name,
const string *bus_name,
VerilogNetScalar *makeNetScalar(const std::string *name);
VerilogNetPortRef *makeNetNamedPortRefScalarNet(const std::string *port_vname);
VerilogNetPortRef *makeNetNamedPortRefScalarNet(const std::string *port_name,
const std::string *net_name);
VerilogNetPortRef *makeNetNamedPortRefBitSelect(const std::string *port_name,
const std::string *bus_name,
int index);
VerilogNetPortRef *makeNetNamedPortRefScalar(const string *port_name,
VerilogNetPortRef *makeNetNamedPortRefScalar(const std::string *port_name,
VerilogNet *net);
VerilogNetPortRef *makeNetNamedPortRefBit(const string *port_name,
VerilogNetPortRef *makeNetNamedPortRefBit(const std::string *port_name,
int index,
VerilogNet *net);
VerilogNetPortRef *makeNetNamedPortRefPart(const string *port_name,
VerilogNetPortRef *makeNetNamedPortRefPart(const std::string *port_name,
int from_index,
int to_index,
VerilogNet *net);
VerilogNetConcat *makeNetConcat(VerilogNetSeq *nets);
VerilogNetConstant *makeNetConstant(const string *constant,
VerilogNetConstant *makeNetConstant(const std::string *constant,
int line);
VerilogNetBitSelect *makeNetBitSelect(const string *name,
VerilogNetBitSelect *makeNetBitSelect(const std::string *name,
int index);
VerilogNetPartSelect *makeNetPartSelect(const string *name,
VerilogNetPartSelect *makeNetPartSelect(const std::string *name,
int from_index,
int to_index);
VerilogModule *module(Cell *cell);
@ -160,11 +156,11 @@ public:
const char *filename,
int line,
const char *fmt, ...);
const string &zeroNetName() const { return zero_net_name_; }
const string &oneNetName() const { return one_net_name_; }
const std::string &zeroNetName() const { return zero_net_name_; }
const std::string &oneNetName() const { return one_net_name_; }
void deleteModules();
void reportStmtCounts();
const string &constant10Max() const { return constant10_max_; }
const std::string &constant10Max() const { return constant10_max_; }
protected:
void init(const char *filename);
@ -173,13 +169,13 @@ protected:
VerilogNetSeq *ports);
Port *makeCellPort(Cell *cell,
VerilogModule *module,
const string &port_name);
const std::string &port_name);
void makeNamedPortRefCellPorts(Cell *cell,
VerilogModule *module,
VerilogNet *mod_port,
StdStringSet &port_names);
void checkModuleDcls(VerilogModule *module,
set<string> &port_names);
std::set<std::string> &port_names);
void makeModuleInstBody(VerilogModule *module,
Instance *inst,
VerilogBindingTbl *bindings,
@ -230,7 +226,7 @@ protected:
bool is_leaf);
void makeInstPin(Instance *inst,
Port *port,
const string &net_name,
const std::string &net_name,
VerilogBindingTbl *bindings,
Instance *parent,
VerilogBindingTbl *parent_bindings,
@ -259,7 +255,7 @@ protected:
bool hasScalarNamedPortRefs(LibertyCell *liberty_cell,
VerilogNetSeq *pins);
string filename_;
std::string filename_;
Report *report_;
Debug *debug_;
NetworkReader *network_;
@ -268,9 +264,9 @@ protected:
int black_box_index_;
VerilogModuleMap module_map_;
VerilogErrorSeq link_errors_;
const string zero_net_name_;
const string one_net_name_;
string constant10_max_;
const std::string zero_net_name_;
const std::string one_net_name_;
std::string constant10_max_;
ViewType *view_type_;
bool report_stmt_stats_;
int module_count_;

108
verilog/VerilogReaderPvt.hh
View File

@ -32,9 +32,9 @@
namespace sta {
typedef Map<string, VerilogDcl*> VerilogDclMap;
typedef Map<std::string, VerilogDcl*> VerilogDclMap;
typedef Vector<bool> VerilogConstantValue;
typedef vector<string> StdStringSeq;
typedef std::vector<std::string> StdStringSeq;
class VerilogStmt
{
@ -55,19 +55,19 @@ private:
class VerilogModule : public VerilogStmt
{
public:
VerilogModule(const string &name,
VerilogModule(const std::string &name,
VerilogNetSeq *ports,
VerilogStmtSeq *stmts,
VerilogAttrStmtSeq *attr_stmts,
const string &filename,
const std::string &filename,
int line,
VerilogReader *reader);
virtual ~VerilogModule();
const string &name() { return name_; }
const std::string &name() { return name_; }
const char *filename() { return filename_.c_str(); }
VerilogAttrStmtSeq *attrStmts() { return attr_stmts_; }
VerilogNetSeq *ports() { return ports_; }
VerilogDcl *declaration(const string &net_name);
VerilogDcl *declaration(const std::string &net_name);
VerilogStmtSeq *stmts() { return stmts_; }
VerilogDclMap *declarationMap() { return &dcl_map_; }
void parseDcl(VerilogDcl *dcl,
@ -79,8 +79,8 @@ private:
StdStringSet &inst_names,
VerilogReader *reader);
string name_;
string filename_;
std::string name_;
std::string filename_;
VerilogNetSeq *ports_;
VerilogStmtSeq *stmts_;
VerilogDclMap dcl_map_;
@ -99,7 +99,7 @@ public:
VerilogAttrStmtSeq *attr_stmts,
int line);
virtual ~VerilogDcl();
const string &portName();
const std::string &portName();
virtual bool isBus() const { return false; }
virtual bool isDeclaration() const { return true; }
VerilogDclArgSeq *args() const { return args_; }
@ -143,15 +143,15 @@ private:
class VerilogDclArg
{
public:
VerilogDclArg(const string &net_name);
VerilogDclArg(const std::string &net_name);
VerilogDclArg(VerilogAssign *assign);
~VerilogDclArg();
const string &netName();
const std::string &netName();
bool isNamed() const { return assign_ == nullptr; }
VerilogAssign *assign() { return assign_; }
private:
string net_name_;
std::string net_name_;
VerilogAssign *assign_;
};
@ -175,37 +175,37 @@ private:
class VerilogInst : public VerilogStmt
{
public:
VerilogInst(const string &inst_name,
VerilogInst(const std::string &inst_name,
VerilogAttrStmtSeq *attr_stmts,
const int line);
virtual ~VerilogInst();
virtual bool isInstance() const { return true; }
const string &instanceName() const { return inst_name_; }
const std::string &instanceName() const { return inst_name_; }
VerilogAttrStmtSeq *attrStmts() const { return attr_stmts_; }
void setInstanceName(const string &inst_name);
void setInstanceName(const std::string &inst_name);
private:
string inst_name_;
std::string inst_name_;
VerilogAttrStmtSeq *attr_stmts_;
};
class VerilogModuleInst : public VerilogInst
{
public:
VerilogModuleInst(const string &module_name,
const string &inst_name,
VerilogModuleInst(const std::string &module_name,
const std::string &inst_name,
VerilogNetSeq *pins,
VerilogAttrStmtSeq *attr_stmts,
const int line);
virtual ~VerilogModuleInst();
virtual bool isModuleInst() const { return true; }
const string &moduleName() const { return module_name_; }
const std::string &moduleName() const { return module_name_; }
VerilogNetSeq *pins() const { return pins_; }
bool namedPins();
bool hasPins();
private:
string module_name_;
std::string module_name_;
VerilogNetSeq *pins_;
};
@ -216,7 +216,7 @@ class VerilogLibertyInst : public VerilogInst
{
public:
VerilogLibertyInst(LibertyCell *cell,
const string &inst_name,
const std::string &inst_name,
const StdStringSeq &net_names,
VerilogAttrStmtSeq *attr_stmts,
const int line);
@ -236,7 +236,7 @@ public:
VerilogNet() {}
virtual ~VerilogNet() {}
virtual bool isNamed() const = 0;
virtual const string &name() const = 0;
virtual const std::string &name() const = 0;
virtual bool isNamedPortRef() { return false; }
virtual bool isNamedPortRefScalarNet() const { return false; }
virtual int size(VerilogModule *module) = 0;
@ -249,30 +249,30 @@ class VerilogNetUnnamed : public VerilogNet
public:
VerilogNetUnnamed() {}
bool isNamed() const override { return false; }
const string &name() const override { return null_; }
const std::string &name() const override { return null_; }
private:
static const string null_;
static const std::string null_;
};
class VerilogNetNamed : public VerilogNet
{
public:
VerilogNetNamed(const string &name);
VerilogNetNamed(const std::string &name);
virtual ~VerilogNetNamed();
bool isNamed() const override { return true; }
virtual bool isScalar() const = 0;
const string &name() const override { return name_; }
const std::string &name() const override { return name_; }
protected:
string name_;
std::string name_;
};
// Named net reference, which could be the name of a scalar or bus signal.
class VerilogNetScalar : public VerilogNetNamed
{
public:
VerilogNetScalar(const string &name);
VerilogNetScalar(const std::string &name);
virtual bool isScalar() const { return true; }
virtual int size(VerilogModule *module);
virtual VerilogNetNameIterator *nameIterator(VerilogModule *module,
@ -282,7 +282,7 @@ public:
class VerilogNetBitSelect : public VerilogNetNamed
{
public:
VerilogNetBitSelect(const string &name,
VerilogNetBitSelect(const std::string &name,
int index);
int index() { return index_; }
virtual bool isScalar() const { return false; }
@ -296,7 +296,7 @@ private:
class VerilogNetPartSelect : public VerilogNetNamed
{
public:
VerilogNetPartSelect(const string &name,
VerilogNetPartSelect(const std::string &name,
int from_index,
int to_index);
virtual bool isScalar() const { return false; }
@ -314,7 +314,7 @@ private:
class VerilogNetConstant : public VerilogNetUnnamed
{
public:
VerilogNetConstant(const string *constant,
VerilogNetConstant(const std::string *constant,
VerilogReader *reader,
int line);
virtual ~VerilogNetConstant();
@ -323,14 +323,14 @@ public:
VerilogReader *reader);
private:
void parseConstant(const string *constant,
void parseConstant(const std::string *constant,
VerilogReader *reader,
int line);
void parseConstant(const string *constant,
void parseConstant(const std::string *constant,
size_t base_idx,
int base,
int digit_bit_count);
void parseConstant10(const string *constant,
void parseConstant10(const std::string *constant,
size_t base_idx,
VerilogReader *reader,
int line);
@ -355,7 +355,7 @@ private:
class VerilogNetPortRef : public VerilogNetScalar
{
public:
VerilogNetPortRef(const string &name);
VerilogNetPortRef(const std::string &name);
virtual bool isNamedPortRef() { return true; }
virtual bool hasNet() = 0;
};
@ -367,26 +367,26 @@ public:
class VerilogNetPortRefScalarNet : public VerilogNetPortRef
{
public:
VerilogNetPortRefScalarNet(const string &name);
VerilogNetPortRefScalarNet(const string &name,
const string &net_name);
VerilogNetPortRefScalarNet(const std::string &name);
VerilogNetPortRefScalarNet(const std::string &name,
const std::string &net_name);
virtual bool isScalar() const { return true; }
virtual bool isNamedPortRefScalarNet() const { return true; }
virtual int size(VerilogModule *module);
virtual VerilogNetNameIterator *nameIterator(VerilogModule *module,
VerilogReader *reader);
virtual bool hasNet() { return !net_name_.empty(); }
const string &netName() const { return net_name_; }
void setNetName(const string &net_name) { net_name_ = net_name; }
const std::string &netName() const { return net_name_; }
void setNetName(const std::string &net_name) { net_name_ = net_name; }
private:
string net_name_;
std::string net_name_;
};
class VerilogNetPortRefScalar : public VerilogNetPortRef
{
public:
VerilogNetPortRefScalar(const string &name,
VerilogNetPortRefScalar(const std::string &name,
VerilogNet *net);
virtual ~VerilogNetPortRefScalar();
virtual bool isScalar() const { return true; }
@ -402,23 +402,23 @@ private:
class VerilogNetPortRefBit : public VerilogNetPortRefScalar
{
public:
VerilogNetPortRefBit(const string &name,
VerilogNetPortRefBit(const std::string &name,
int index,
VerilogNet *net);
const string &name() const override { return bit_name_; }
const std::string &name() const override { return bit_name_; }
private:
string bit_name_;
std::string bit_name_;
};
class VerilogNetPortRefPart : public VerilogNetPortRefBit
{
public:
VerilogNetPortRefPart(const string &name,
VerilogNetPortRefPart(const std::string &name,
int from_index,
int to_index,
VerilogNet *net);
const string &name() const override;
const std::string &name() const override;
int toIndex() const { return to_index_; }
private:
@ -426,7 +426,7 @@ private:
};
// Abstract class for iterating over the component nets of a net.
class VerilogNetNameIterator : public Iterator<const string&>
class VerilogNetNameIterator : public Iterator<const std::string&>
{
};
@ -444,15 +444,15 @@ private:
class VerilogAttrEntry
{
public:
VerilogAttrEntry(const string &key,
const string &value);
virtual string key();
virtual string value();
VerilogAttrEntry(const std::string &key,
const std::string &value);
virtual std::string key();
virtual std::string value();
virtual ~VerilogAttrEntry() = default;
private:
string key_;
string value_;
std::string key_;
std::string value_;
};
} // namespace

15
verilog/VerilogWriter.cc
View File

@ -39,6 +39,7 @@ namespace sta {
using std::min;
using std::max;
using std::string;
class VerilogWriter
{
@ -179,7 +180,7 @@ void
VerilogWriter::writeModule(const Instance *inst)
{
Cell *cell = network_->cell(inst);
string cell_vname = cellVerilogName(network_->name(cell));
std::string cell_vname = cellVerilogName(network_->name(cell));
fprintf(stream_, "module %s (", cell_vname.c_str());
writePorts(cell);
writePortDcls(cell);
@ -202,7 +203,7 @@ VerilogWriter::writePorts(const Cell *cell)
|| !network_->direction(port)->isPowerGround()) {
if (!first)
fprintf(stream_, ",\n ");
string verilog_name = portVerilogName(network_->name(port));
std::string verilog_name = portVerilogName(network_->name(port));
fprintf(stream_, "%s", verilog_name.c_str());
first = false;
}
@ -220,7 +221,7 @@ VerilogWriter::writePortDcls(const Cell *cell)
PortDirection *dir = network_->direction(port);
if (include_pwr_gnd_
|| !network_->direction(port)->isPowerGround()) {
string port_vname = portVerilogName(network_->name(port));
std::string port_vname = portVerilogName(network_->name(port));
const char *vtype = verilogPortDir(dir);
if (vtype) {
fprintf(stream_, " %s", vtype);
@ -274,7 +275,7 @@ VerilogWriter::writeWireDcls(const Instance *inst)
{
Cell *cell = network_->cell(inst);
char escape = network_->pathEscape();
Map<string, BusIndexRange, std::less<string>> bus_ranges;
Map<std::string, BusIndexRange, std::less<std::string>> bus_ranges;
NetIterator *net_iter = network_->netIterator(inst);
while (net_iter->hasNext()) {
Net *net = net_iter->next();
@ -284,7 +285,7 @@ VerilogWriter::writeWireDcls(const Instance *inst)
if (network_->findPort(cell, net_name) == nullptr) {
if (isBusName(net_name, '[', ']', escape)) {
bool is_bus;
string bus_name;
std::string bus_name;
int index;
parseBusName(net_name, '[', ']', escape, is_bus, bus_name, index);
BusIndexRange &range = bus_ranges[bus_name];
@ -292,7 +293,7 @@ VerilogWriter::writeWireDcls(const Instance *inst)
range.second = min(range.second, index);
}
else {
string net_vname = netVerilogName(net_name);
std::string net_vname = netVerilogName(net_name);
fprintf(stream_, " wire %s;\n", net_vname.c_str());;
}
}
@ -302,7 +303,7 @@ VerilogWriter::writeWireDcls(const Instance *inst)
for (const auto& [bus_name1, range] : bus_ranges) {
const char *bus_name = bus_name1.c_str();
string net_vname = netVerilogName(bus_name);
std::string net_vname = netVerilogName(bus_name);
fprintf(stream_, " wire [%d:%d] %s;\n",
range.first,
range.second,