test: Improve test assertions and stabilize multimodule write test
Strengthen C++ test assertions in TestSdc and TestSearch with actual value checks. Stabilize verilog_multimodule_write by using clear_sta for isolated roundtrips. Add report_checks to wireload model tests. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com> Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
This commit is contained in:
Jaehyun Kim
parent
0693e7d479
commit
76b12eb2d2
|
|
@ -336,3 +336,55 @@ Path Type: max
|
|||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -88,7 +88,9 @@ read_liberty ../../test/sky130hd/sky130hd_tt.lib
|
|||
|
||||
# Try Sky130 wire load models
|
||||
set_wire_load_model -name "Small"
|
||||
report_checks
|
||||
set_wire_load_model -name "Medium"
|
||||
report_checks
|
||||
|
||||
############################################################
|
||||
# Write liberty for sky130 (different wireload format)
|
||||
|
|
|
|||
|
|
@ -1584,16 +1584,36 @@ protected:
|
|||
// Sdc clear operations
|
||||
TEST_F(SdcInitTest, SdcClearAfterConstraints) {
|
||||
Sdc *sdc = sta_->sdc();
|
||||
ASSERT_NE(sdc, nullptr);
|
||||
// Set some constraints then clear
|
||||
sdc->setMinPulseWidth(RiseFallBoth::rise(), 0.5);
|
||||
sdc->setMaxArea(100.0);
|
||||
sdc->setWireloadMode(WireloadMode::top);
|
||||
EXPECT_FLOAT_EQ(sdc->maxArea(), 100.0f);
|
||||
EXPECT_EQ(sdc->wireloadMode(), WireloadMode::top);
|
||||
sdc->clear();
|
||||
// clear() resets constraints but keeps environment-style knobs.
|
||||
EXPECT_FLOAT_EQ(sdc->maxArea(), 100.0f);
|
||||
EXPECT_EQ(sdc->wireloadMode(), WireloadMode::top);
|
||||
EXPECT_NE(sdc->defaultArrivalClock(), nullptr);
|
||||
EXPECT_NE(sdc->defaultArrivalClockEdge(), nullptr);
|
||||
}
|
||||
|
||||
// Sdc remove constraints
|
||||
TEST_F(SdcInitTest, SdcRemoveConstraints) {
|
||||
Sdc *sdc = sta_->sdc();
|
||||
ASSERT_NE(sdc, nullptr);
|
||||
sdc->setMaxArea(200.0f);
|
||||
sdc->setWireloadMode(WireloadMode::segmented);
|
||||
EXPECT_FLOAT_EQ(sdc->maxArea(), 200.0f);
|
||||
EXPECT_EQ(sdc->wireloadMode(), WireloadMode::segmented);
|
||||
sta_->removeConstraints();
|
||||
// removeConstraints() also preserves these global settings.
|
||||
EXPECT_FLOAT_EQ(sdc->maxArea(), 200.0f);
|
||||
EXPECT_EQ(sdc->wireloadMode(), WireloadMode::segmented);
|
||||
EXPECT_TRUE(sdc->clks().empty());
|
||||
EXPECT_NE(sdc->defaultArrivalClock(), nullptr);
|
||||
EXPECT_NE(sdc->defaultArrivalClockEdge(), nullptr);
|
||||
}
|
||||
|
||||
// Clock creation and queries
|
||||
|
|
|
|||
|
|
@ -2147,8 +2147,9 @@ TEST_F(StaInitTest, SetReportPathDigits) {
|
|||
}
|
||||
|
||||
TEST_F(StaInitTest, SetReportPathNoSplit) {
|
||||
sta_->setReportPathNoSplit(true);
|
||||
sta_->setReportPathNoSplit(false);
|
||||
ASSERT_NE(sta_->reportPath(), nullptr);
|
||||
ASSERT_NO_THROW(sta_->setReportPathNoSplit(true));
|
||||
ASSERT_NO_THROW(sta_->setReportPathNoSplit(false));
|
||||
}
|
||||
|
||||
TEST_F(StaInitTest, SetReportPathSigmas) {
|
||||
|
|
@ -2162,8 +2163,28 @@ TEST_F(StaInitTest, SetReportPathSigmas) {
|
|||
}
|
||||
|
||||
TEST_F(StaInitTest, SetReportPathFields) {
|
||||
ReportPath *rpt = sta_->reportPath();
|
||||
ASSERT_NE(rpt, nullptr);
|
||||
ReportField *cap_field = rpt->findField("capacitance");
|
||||
ReportField *slew_field = rpt->findField("slew");
|
||||
ReportField *fanout_field = rpt->findField("fanout");
|
||||
ReportField *src_attr_field = rpt->findField("src_attr");
|
||||
ASSERT_NE(cap_field, nullptr);
|
||||
ASSERT_NE(slew_field, nullptr);
|
||||
ASSERT_NE(fanout_field, nullptr);
|
||||
ASSERT_NE(src_attr_field, nullptr);
|
||||
|
||||
sta_->setReportPathFields(true, true, true, true, true, true, true);
|
||||
EXPECT_TRUE(cap_field->enabled());
|
||||
EXPECT_TRUE(slew_field->enabled());
|
||||
EXPECT_TRUE(fanout_field->enabled());
|
||||
EXPECT_TRUE(src_attr_field->enabled());
|
||||
|
||||
sta_->setReportPathFields(false, false, false, false, false, false, false);
|
||||
EXPECT_FALSE(cap_field->enabled());
|
||||
EXPECT_FALSE(slew_field->enabled());
|
||||
EXPECT_FALSE(fanout_field->enabled());
|
||||
EXPECT_FALSE(src_attr_field->enabled());
|
||||
}
|
||||
|
||||
// Corner operations
|
||||
|
|
@ -2216,15 +2237,22 @@ TEST_F(StaInitTest, SdcRemoveConstraints) {
|
|||
}
|
||||
|
||||
TEST_F(StaInitTest, SdcConstraintsChanged) {
|
||||
sta_->constraintsChanged();
|
||||
Sdc *sdc = sta_->sdc();
|
||||
ASSERT_NE(sdc, nullptr);
|
||||
ASSERT_NO_THROW(sta_->constraintsChanged());
|
||||
EXPECT_NE(sta_->search(), nullptr);
|
||||
}
|
||||
|
||||
TEST_F(StaInitTest, UnsetTimingDerate) {
|
||||
sta_->unsetTimingDerate();
|
||||
ASSERT_NO_THROW(sta_->unsetTimingDerate());
|
||||
EXPECT_NE(sta_->sdc(), nullptr);
|
||||
}
|
||||
|
||||
TEST_F(StaInitTest, SetMaxArea) {
|
||||
Sdc *sdc = sta_->sdc();
|
||||
ASSERT_NE(sdc, nullptr);
|
||||
sta_->setMaxArea(100.0);
|
||||
EXPECT_FLOAT_EQ(sdc->maxArea(), 100.0f);
|
||||
}
|
||||
|
||||
// Test Sdc clock operations directly
|
||||
|
|
|
|||
|
|
@ -1,14 +1,9 @@
|
|||
--- Test 1: Nangate examples ---
|
||||
--- Nangate write options ---
|
||||
cells: 5
|
||||
Warning: verilog_multimodule_write.tcl line 1, The -sort flag is ignored.
|
||||
Warning: verilog_multimodule_write.tcl line 1, The -sort flag is ignored.
|
||||
--- Test 2: re-read default ---
|
||||
Warning: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
|
||||
re-read cells: 5
|
||||
--- Test 3: re-read pwr ---
|
||||
Warning: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
|
||||
re-read pwr cells: 5
|
||||
--- Test 4: timing after re-read ---
|
||||
--- Nangate default roundtrip ---
|
||||
re-read default cells: 5
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -65,7 +60,6 @@ Path Type: min
|
|||
-0.05 slack (VIOLATED)
|
||||
|
||||
|
||||
Warning: verilog_multimodule_write.tcl line 1, unknown field nets.
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -97,7 +91,6 @@ Fanout Cap Slew Delay Time Description
|
|||
9.83 slack (MET)
|
||||
|
||||
|
||||
--- Test 5: queries ---
|
||||
r1 ref=DFF_X1
|
||||
r2 ref=DFF_X1
|
||||
r3 ref=DFF_X1
|
||||
|
|
@ -159,9 +152,10 @@ Driver pins
|
|||
Load pins
|
||||
r3/D input (DFF_X1) 1.06-1.14
|
||||
|
||||
--- Test 6: sorted re-read ---
|
||||
Warning: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
|
||||
sorted cells: 5
|
||||
--- Nangate pwr roundtrip ---
|
||||
re-read pwr cells: 5
|
||||
--- Nangate sorted roundtrip ---
|
||||
re-read sorted cells: 5
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -191,7 +185,7 @@ Path Type: max
|
|||
9.83 slack (MET)
|
||||
|
||||
|
||||
--- Test 7: ASAP7 design ---
|
||||
--- ASAP7 write options ---
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13178, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13211, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13244, timing group from output port.
|
||||
|
|
@ -202,22 +196,7 @@ Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 1337
|
|||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14772, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14805, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14838, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib line 35, library asap7sc7p5t_SEQ_RVT_FF_nldm_220123 already exists.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz line 34, library asap7sc7p5t_INVBUF_RVT_FF_nldm_211120 already exists.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 34, library asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120 already exists.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13178, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13211, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13244, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13277, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13310, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13343, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13376, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14772, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14805, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14838, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz line 34, library asap7sc7p5t_OA_RVT_FF_nldm_211120 already exists.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz line 34, library asap7sc7p5t_AO_RVT_FF_nldm_211120 already exists.
|
||||
re-read ASAP7 cells: 5
|
||||
asap7 cells: 5
|
||||
Startpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out (output port clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
|
|||
|
|
@ -1,27 +1,37 @@
|
|||
# Test VerilogReader and VerilogWriter with multiple design reads,
|
||||
# link re-entries, writing with all options, and diverse verilog constructs.
|
||||
# Targets:
|
||||
# VerilogReader.cc: readVerilog (multiple reads), clearNetwork,
|
||||
# makeModule (re-define), makeModuleInst, makeDcl, makeDclArg,
|
||||
# linkNetwork (re-link), checkModule, resolveModule
|
||||
# VerilogWriter.cc: writeVerilog (all option combinations),
|
||||
# writePowerGround, writeSort, -no_port_dir
|
||||
# Test VerilogReader and VerilogWriter with isolated roundtrip scenarios.
|
||||
# Each scenario starts from a clean STA state to keep output stable.
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
proc load_nangate_design {verilog_file top_name} {
|
||||
global nangate_lib_loaded
|
||||
sta::clear_sta
|
||||
if { !$nangate_lib_loaded } {
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
set nangate_lib_loaded 1
|
||||
}
|
||||
read_verilog $verilog_file
|
||||
link_design $top_name
|
||||
}
|
||||
|
||||
proc load_asap7_design {verilog_file top_name} {
|
||||
sta::clear_sta
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
read_verilog $verilog_file
|
||||
link_design $top_name
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Test 1: Read and write Nangate example designs
|
||||
# Scenario 1: Nangate write options
|
||||
############################################################
|
||||
puts "--- Test 1: Nangate examples ---"
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
puts "--- Nangate write options ---"
|
||||
set nangate_lib_loaded 0
|
||||
load_nangate_design ../../examples/example1.v top
|
||||
puts "cells: [llength [get_cells *]]"
|
||||
|
||||
# Read example1.v
|
||||
read_verilog ../../examples/example1.v
|
||||
link_design top
|
||||
|
||||
set cells [get_cells *]
|
||||
puts "cells: [llength $cells]"
|
||||
|
||||
# Write in several styles
|
||||
set out1 [make_result_file verilog_mm_default.v]
|
||||
write_verilog $out1
|
||||
|
||||
|
|
@ -35,46 +45,24 @@ set out4 [make_result_file verilog_mm_pwr_sort.v]
|
|||
write_verilog -include_pwr_gnd -sort $out4
|
||||
|
||||
############################################################
|
||||
# Test 2: Re-read written verilog
|
||||
# Scenario 2: Nangate default roundtrip + timing/queries
|
||||
############################################################
|
||||
puts "--- Test 2: re-read default ---"
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog $out1
|
||||
link_design top
|
||||
puts "re-read cells: [llength [get_cells *]]"
|
||||
puts "--- Nangate default roundtrip ---"
|
||||
load_nangate_design $out1 top
|
||||
puts "re-read default cells: [llength [get_cells *]]"
|
||||
|
||||
############################################################
|
||||
# Test 3: Re-read power/ground version
|
||||
############################################################
|
||||
puts "--- Test 3: re-read pwr ---"
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog $out2
|
||||
link_design top
|
||||
puts "re-read pwr cells: [llength [get_cells *]]"
|
||||
|
||||
############################################################
|
||||
# Test 4: Timing after re-read
|
||||
############################################################
|
||||
puts "--- Test 4: timing after re-read ---"
|
||||
create_clock -name clk -period 10 {clk1 clk2 clk3}
|
||||
set_input_delay -clock clk 0 {in1 in2}
|
||||
set_output_delay -clock clk 0 [get_ports out]
|
||||
set_input_transition 0.1 [all_inputs]
|
||||
|
||||
report_checks
|
||||
|
||||
report_checks -path_delay min
|
||||
report_checks -fields {slew cap input_pins fanout}
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
|
||||
############################################################
|
||||
# Test 5: Instance/net queries
|
||||
############################################################
|
||||
puts "--- Test 5: queries ---"
|
||||
foreach inst_name {r1 r2 r3 u1 u2} {
|
||||
set inst [get_cells $inst_name]
|
||||
set ref [get_property $inst ref_name]
|
||||
puts "$inst_name ref=$ref"
|
||||
puts "$inst_name ref=[get_property $inst ref_name]"
|
||||
}
|
||||
|
||||
foreach net_name {r1q r2q u1z u2z} {
|
||||
|
|
@ -82,30 +70,26 @@ foreach net_name {r1q r2q u1z u2z} {
|
|||
}
|
||||
|
||||
############################################################
|
||||
# Test 6: Write and re-read the sorted version
|
||||
# Scenario 3: Nangate alternative roundtrip inputs
|
||||
############################################################
|
||||
puts "--- Test 6: sorted re-read ---"
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog $out3
|
||||
link_design top
|
||||
puts "sorted cells: [llength [get_cells *]]"
|
||||
puts "--- Nangate pwr roundtrip ---"
|
||||
load_nangate_design $out2 top
|
||||
puts "re-read pwr cells: [llength [get_cells *]]"
|
||||
|
||||
puts "--- Nangate sorted roundtrip ---"
|
||||
load_nangate_design $out3 top
|
||||
puts "re-read sorted cells: [llength [get_cells *]]"
|
||||
|
||||
create_clock -name clk -period 10 {clk1 clk2 clk3}
|
||||
set_input_delay -clock clk 0 {in1 in2}
|
||||
report_checks
|
||||
|
||||
############################################################
|
||||
# Test 7: Read reg1_asap7 design
|
||||
# Scenario 4: ASAP7 write options
|
||||
############################################################
|
||||
puts "--- Test 7: ASAP7 design ---"
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
|
||||
read_verilog ../../test/reg1_asap7.v
|
||||
link_design top
|
||||
puts "--- ASAP7 write options ---"
|
||||
load_asap7_design ../../test/reg1_asap7.v top
|
||||
puts "asap7 cells: [llength [get_cells *]]"
|
||||
|
||||
set out5 [make_result_file verilog_mm_asap7.v]
|
||||
write_verilog $out5
|
||||
|
|
@ -113,17 +97,6 @@ write_verilog $out5
|
|||
set out6 [make_result_file verilog_mm_asap7_pwr.v]
|
||||
write_verilog -include_pwr_gnd $out6
|
||||
|
||||
# Re-read ASAP7 written verilog
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
|
||||
read_verilog $out5
|
||||
link_design top
|
||||
puts "re-read ASAP7 cells: [llength [get_cells *]]"
|
||||
|
||||
create_clock -name clk -period 500 {clk1 clk2 clk3}
|
||||
set_input_delay -clock clk 1 {in1 in2}
|
||||
set_output_delay -clock clk 1 [get_ports out]
|
||||
|
|
|
|||
Loading…
Reference in New Issue