test: Initial upload
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
This commit is contained in:
Jaehyun Kim
parent
e872c55bfe
commit
d6c09372ba
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@ -21,6 +21,7 @@ examples/gcd_tb
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doc/._Sta.docx
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test/results
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*/test/results
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# ngspice turd
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test/b3v3_1check.log
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@ -615,3 +615,28 @@ add_custom_command(
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COMMAND ${STA_HOME}/etc/FindMessages.tcl > ${STA_HOME}/doc/messages.txt || true
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WORKING_DIRECTORY ${STA_HOME}
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)
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################################################################
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# Tests
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################################################################
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option(BUILD_TESTS "Build unit tests" OFF)
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if(BUILD_TESTS)
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enable_testing()
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find_package(GTest REQUIRED)
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include(GoogleTest)
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add_subdirectory(test)
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# Per-module tests
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add_subdirectory(util/test)
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add_subdirectory(liberty/test)
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add_subdirectory(graph/test)
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add_subdirectory(network/test)
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add_subdirectory(sdc/test)
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add_subdirectory(sdf/test)
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add_subdirectory(dcalc/test)
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add_subdirectory(search/test)
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add_subdirectory(parasitics/test)
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add_subdirectory(power/test)
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add_subdirectory(verilog/test)
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add_subdirectory(spice/test)
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endif()
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@ -0,0 +1,148 @@
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add_test(
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NAME tcl.dcalc.report
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_report
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.dcalc.report PROPERTIES LABELS "tcl;module_dcalc")
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add_test(
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NAME tcl.dcalc.engines
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_engines
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.dcalc.engines PROPERTIES LABELS "tcl;module_dcalc")
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add_test(
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NAME tcl.dcalc.corners
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_corners
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.dcalc.corners PROPERTIES LABELS "tcl;module_dcalc")
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add_test(
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NAME tcl.dcalc.spef
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_spef
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.dcalc.spef PROPERTIES LABELS "tcl;module_dcalc")
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add_test(
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NAME tcl.dcalc.advanced
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_advanced
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.dcalc.advanced PROPERTIES LABELS "tcl;module_dcalc")
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add_test(
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NAME tcl.dcalc.prima
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_prima
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.dcalc.prima PROPERTIES LABELS "tcl;module_dcalc")
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add_test(
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NAME tcl.dcalc.ccs_incremental
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_ccs_incremental
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.dcalc.ccs_incremental PROPERTIES LABELS "tcl;module_dcalc")
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add_test(
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NAME tcl.dcalc.ccs_parasitics
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_ccs_parasitics
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.dcalc.ccs_parasitics PROPERTIES LABELS "tcl;module_dcalc")
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add_test(
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NAME tcl.dcalc.graph_delay
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_graph_delay
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.dcalc.graph_delay PROPERTIES LABELS "tcl;module_dcalc")
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add_test(
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NAME tcl.dcalc.dmp_ceff
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_dmp_ceff
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.dcalc.dmp_ceff PROPERTIES LABELS "tcl;module_dcalc")
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add_test(
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NAME tcl.dcalc.arnoldi_prima
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_arnoldi_prima
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.dcalc.arnoldi_prima PROPERTIES LABELS "tcl;module_dcalc")
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add_test(
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NAME tcl.dcalc.annotated_incremental
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_annotated_incremental
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.dcalc.annotated_incremental PROPERTIES LABELS "tcl;module_dcalc")
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add_test(
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NAME tcl.dcalc.dmp_edge_cases
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_dmp_edge_cases
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.dcalc.dmp_edge_cases PROPERTIES LABELS "tcl;module_dcalc")
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add_test(
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NAME tcl.dcalc.incremental_tolerance
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_incremental_tolerance
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.dcalc.incremental_tolerance PROPERTIES LABELS "tcl;module_dcalc")
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add_test(
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NAME tcl.dcalc.multi_engine_spef
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_multi_engine_spef
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.dcalc.multi_engine_spef PROPERTIES LABELS "tcl;module_dcalc")
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add_test(
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NAME tcl.dcalc.annotate_slew
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_annotate_slew
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.dcalc.annotate_slew PROPERTIES LABELS "tcl;module_dcalc")
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add_test(
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NAME tcl.dcalc.arnoldi_spef
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_arnoldi_spef
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.dcalc.arnoldi_spef PROPERTIES LABELS "tcl;module_dcalc")
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add_test(
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NAME tcl.dcalc.dmp_convergence
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_dmp_convergence
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.dcalc.dmp_convergence PROPERTIES LABELS "tcl;module_dcalc")
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add_test(
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NAME tcl.dcalc.prima_arnoldi_deep
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_prima_arnoldi_deep
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.dcalc.prima_arnoldi_deep PROPERTIES LABELS "tcl;module_dcalc")
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add_test(
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NAME tcl.dcalc.dmp_pi_model_deep
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_dmp_pi_model_deep
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.dcalc.dmp_pi_model_deep PROPERTIES LABELS "tcl;module_dcalc")
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add_test(
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NAME tcl.dcalc.gcd_arnoldi_prima
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_gcd_arnoldi_prima
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.dcalc.gcd_arnoldi_prima PROPERTIES LABELS "tcl;module_dcalc")
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add_subdirectory(cpp)
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@ -0,0 +1,33 @@
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add_executable(TestFindRoot TestFindRoot.cc)
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target_link_libraries(TestFindRoot
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OpenSTA
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GTest::gtest
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GTest::gtest_main
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${TCL_LIBRARY}
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)
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target_include_directories(TestFindRoot PRIVATE
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${STA_HOME}/include/sta
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${STA_HOME}
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${CMAKE_BINARY_DIR}/include/sta
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)
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gtest_discover_tests(TestFindRoot
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WORKING_DIRECTORY ${STA_HOME}
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PROPERTIES LABELS "cpp;module_dcalc"
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)
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add_executable(TestDcalc TestDcalc.cc)
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target_link_libraries(TestDcalc
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OpenSTA
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GTest::gtest
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GTest::gtest_main
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${TCL_LIBRARY}
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)
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target_include_directories(TestDcalc PRIVATE
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${STA_HOME}/include/sta
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${STA_HOME}
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${CMAKE_BINARY_DIR}/include/sta
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)
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gtest_discover_tests(TestDcalc
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WORKING_DIRECTORY ${STA_HOME}
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PROPERTIES LABELS "cpp;module_dcalc"
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)
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,95 @@
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#include <gtest/gtest.h>
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#include <cmath>
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#include <functional>
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#include "dcalc/FindRoot.hh"
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namespace sta {
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class FindRootTest : public ::testing::Test {};
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// Test finding root of f(x) = x^2 - 4 (root at x=2)
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TEST_F(FindRootTest, QuadraticPositiveRoot) {
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FindRootFunc func = [](double x, double &y, double &dy) {
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y = x * x - 4.0;
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dy = 2.0 * x;
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};
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bool fail = false;
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double root = findRoot(func, 1.0, 3.0, 1e-10, 100, fail);
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EXPECT_FALSE(fail);
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EXPECT_NEAR(root, 2.0, 1e-8);
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}
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// Test finding root of f(x) = x^2 - 4 (root at x=-2)
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TEST_F(FindRootTest, QuadraticNegativeRoot) {
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FindRootFunc func = [](double x, double &y, double &dy) {
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y = x * x - 4.0;
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dy = 2.0 * x;
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};
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bool fail = false;
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double root = findRoot(func, -3.0, -1.0, 1e-10, 100, fail);
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EXPECT_FALSE(fail);
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EXPECT_NEAR(root, -2.0, 1e-8);
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}
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// Test finding root of f(x) = x - 1 (linear, root at x=1)
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TEST_F(FindRootTest, LinearRoot) {
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FindRootFunc func = [](double x, double &y, double &dy) {
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y = x - 1.0;
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dy = 1.0;
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};
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bool fail = false;
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double root = findRoot(func, 0.0, 2.0, 1e-10, 100, fail);
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EXPECT_FALSE(fail);
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EXPECT_NEAR(root, 1.0, 1e-8);
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}
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// Test finding root of f(x) = sin(x) near pi
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TEST_F(FindRootTest, SinRoot) {
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FindRootFunc func = [](double x, double &y, double &dy) {
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y = sin(x);
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dy = cos(x);
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};
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bool fail = false;
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double root = findRoot(func, 2.5, 3.8, 1e-10, 100, fail);
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EXPECT_FALSE(fail);
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EXPECT_NEAR(root, M_PI, 1e-6);
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}
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// Test finding root of f(x) = e^x - 2 (root at x=ln(2))
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TEST_F(FindRootTest, ExponentialRoot) {
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FindRootFunc func = [](double x, double &y, double &dy) {
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y = exp(x) - 2.0;
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dy = exp(x);
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};
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bool fail = false;
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double root = findRoot(func, 0.0, 1.0, 1e-10, 100, fail);
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EXPECT_FALSE(fail);
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EXPECT_NEAR(root, log(2.0), 1e-8);
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}
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// Test with tight tolerance
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TEST_F(FindRootTest, TightTolerance) {
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FindRootFunc func = [](double x, double &y, double &dy) {
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y = x * x - 2.0;
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dy = 2.0 * x;
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};
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bool fail = false;
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double root = findRoot(func, 1.0, 2.0, 1e-14, 200, fail);
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EXPECT_FALSE(fail);
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EXPECT_NEAR(root, sqrt(2.0), 1e-12);
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}
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// Test the 4-argument version with pre-computed y values
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TEST_F(FindRootTest, WithPrecomputedY) {
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FindRootFunc func = [](double x, double &y, double &dy) {
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y = x * x - 9.0;
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dy = 2.0 * x;
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};
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bool fail = false;
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// x1=2, y1=4-9=-5, x2=4, y2=16-9=7
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double root = findRoot(func, 2.0, -5.0, 4.0, 7.0, 1e-10, 100, fail);
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EXPECT_FALSE(fail);
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EXPECT_NEAR(root, 3.0, 1e-8);
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}
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} // namespace sta
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,184 @@
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# Test advanced delay calculation scenarios for coverage improvement
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# Targets: DmpDelayCalc.cc (dmp_ceff_two_pole paths, DmpCeff error paths)
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# ArcDelayCalc.cc (additional arc types)
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# GraphDelayCalc.cc (more paths through delay graph computation)
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# NetCaps.cc (net capacitance queries)
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# UnitDelayCalc.cc (more paths through unit delay calc)
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# PrimaDelayCalc.cc (prima delay calculator)
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# CcsCeffDelayCalc.cc (ccs_ceff calculator)
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog dcalc_test1.v
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link_design dcalc_test1
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 0 [get_ports in1]
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set_output_delay -clock clk 0 [get_ports out1]
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#---------------------------------------------------------------
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# Test with various set_load values to exercise NetCaps paths
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#---------------------------------------------------------------
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puts "--- set_load variations ---"
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set_load 0.001 [get_ports out1]
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report_checks
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puts "PASS: report_checks with 1fF load"
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set_load 0.1 [get_ports out1]
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report_checks
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puts "PASS: report_checks with 100fF load"
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set_load 1.0 [get_ports out1]
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report_checks
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puts "PASS: report_checks with 1pF load"
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# Reset load
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set_load 0 [get_ports out1]
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#---------------------------------------------------------------
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# Test set_input_transition with various values
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#---------------------------------------------------------------
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puts "--- set_input_transition ---"
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set_input_transition 0.01 [get_ports in1]
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report_checks
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puts "PASS: report_checks with 10ps input transition"
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set_input_transition 0.5 [get_ports in1]
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report_checks
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puts "PASS: report_checks with 500ps input transition"
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set_input_transition 0.1 [get_ports in1]
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#---------------------------------------------------------------
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# Test report_dcalc for all arcs in the design
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#---------------------------------------------------------------
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puts "--- report_dcalc all arcs ---"
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# BUF arcs
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catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
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puts "dcalc buf1 A->Z max: $msg"
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catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -min} msg
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puts "dcalc buf1 A->Z min: $msg"
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# INV arcs
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catch {report_dcalc -from [get_pins inv1/A] -to [get_pins inv1/ZN] -max} msg
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puts "dcalc inv1 A->ZN max: $msg"
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catch {report_dcalc -from [get_pins inv1/A] -to [get_pins inv1/ZN] -min} msg
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puts "dcalc inv1 A->ZN min: $msg"
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# DFF clock-to-Q
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catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max} msg
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puts "dcalc reg1 CK->Q max: $msg"
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catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -min} msg
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puts "dcalc reg1 CK->Q min: $msg"
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# DFF setup/hold
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catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D] -max} msg
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puts "dcalc reg1 setup max: $msg"
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catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D] -min} msg
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puts "dcalc reg1 hold min: $msg"
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# report_dcalc with digits
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catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -digits 8} msg
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puts "dcalc buf1 A->Z 8 digits: $msg"
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#---------------------------------------------------------------
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# Unit delay calculator
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#---------------------------------------------------------------
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puts "--- unit delay calculator ---"
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set_delay_calculator unit
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report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: unit report_checks"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: unit min path"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: unit max path"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
|
||||
puts "unit dcalc buf1: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins inv1/A] -to [get_pins inv1/ZN]} msg
|
||||
puts "unit dcalc inv1: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q]} msg
|
||||
puts "unit dcalc reg1 CK->Q: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D]} msg
|
||||
puts "unit dcalc reg1 setup: $msg"
|
||||
|
||||
report_checks -fields {slew cap}
|
||||
puts "PASS: unit with fields"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# lumped_cap delay calculator
|
||||
#---------------------------------------------------------------
|
||||
puts "--- lumped_cap delay calculator ---"
|
||||
set_delay_calculator lumped_cap
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: lumped_cap report_checks"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "lumped_cap dcalc buf1: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins inv1/A] -to [get_pins inv1/ZN] -max} msg
|
||||
puts "lumped_cap dcalc inv1: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max} msg
|
||||
puts "lumped_cap dcalc reg1: $msg"
|
||||
|
||||
report_checks -fields {slew cap input_pins}
|
||||
puts "PASS: lumped_cap with fields"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# dmp_ceff_elmore (default) delay calculator
|
||||
#---------------------------------------------------------------
|
||||
puts "--- dmp_ceff_elmore delay calculator ---"
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: dmp_ceff_elmore report_checks"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
|
||||
puts "dmp_ceff_elmore dcalc buf1: $msg"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# dmp_ceff_two_pole delay calculator
|
||||
#---------------------------------------------------------------
|
||||
puts "--- dmp_ceff_two_pole delay calculator ---"
|
||||
set_delay_calculator dmp_ceff_two_pole
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: dmp_ceff_two_pole report_checks"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: dmp_ceff_two_pole min path"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: dmp_ceff_two_pole max path"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "dmp_ceff_two_pole dcalc buf1 max: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -min} msg
|
||||
puts "dmp_ceff_two_pole dcalc buf1 min: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins inv1/A] -to [get_pins inv1/ZN] -max} msg
|
||||
puts "dmp_ceff_two_pole dcalc inv1: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max} msg
|
||||
puts "dmp_ceff_two_pole dcalc reg1 CK->Q: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D] -max} msg
|
||||
puts "dmp_ceff_two_pole dcalc reg1 setup: $msg"
|
||||
|
||||
report_checks -fields {slew cap input_pins}
|
||||
puts "PASS: dmp_ceff_two_pole with fields"
|
||||
|
||||
puts "ALL PASSED"
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,226 @@
|
|||
# Test delay calculation annotation, slew queries, and load capacitance
|
||||
# calculations with SDF annotation and multiple delay engines.
|
||||
# Targets:
|
||||
# GraphDelayCalc.cc: findDelays, loadCap, loadDelay, gateDelay,
|
||||
# annotateArcDelay, annotateSlew, incrementalDelaysValid,
|
||||
# setObserver, delayCalcObserver, seedRootSlews,
|
||||
# findVertexDelay, findCheckEdgeDelays, deleteVertexBefore,
|
||||
# levelChangedBefore, levelsChangedBefore, delayInvalid (pin/vertex)
|
||||
# DmpCeff.cc: dmpCeffElmore, dmpCeffTwoPole with annotated values,
|
||||
# Ceff iteration with various effective capacitance conditions,
|
||||
# dmpCeffDrvrPi, ceffPiElmore, dmpCeffIter convergence
|
||||
# Graph.cc: arcDelayAnnotated, wireDelayAnnotated, slew and delay
|
||||
# getters for all rise/fall combinations
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog ../test/dcalc_test1.v
|
||||
link_design dcalc_test1
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 0 [get_ports in1]
|
||||
set_output_delay -clock clk 0 [get_ports out1]
|
||||
set_input_transition 0.1 [get_ports {in1 clk}]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Baseline timing with default calculator
|
||||
#---------------------------------------------------------------
|
||||
puts "--- baseline timing ---"
|
||||
report_checks
|
||||
puts "PASS: baseline"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: baseline min"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: baseline max"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_dcalc for all arcs: exercises gateDelay, loadDelay paths
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_dcalc all arcs ---"
|
||||
|
||||
# BUF arc: rise and fall
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "buf1 A->Z max: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -min} msg
|
||||
puts "buf1 A->Z min: done"
|
||||
|
||||
# INV arc: rise and fall
|
||||
catch {report_dcalc -from [get_pins inv1/A] -to [get_pins inv1/ZN] -max} msg
|
||||
puts "inv1 A->ZN max: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins inv1/A] -to [get_pins inv1/ZN] -min} msg
|
||||
puts "inv1 A->ZN min: done"
|
||||
|
||||
# DFF CK->Q arc
|
||||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max} msg
|
||||
puts "reg1 CK->Q max: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -min} msg
|
||||
puts "reg1 CK->Q min: done"
|
||||
|
||||
# DFF setup and hold check arcs
|
||||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D] -max} msg
|
||||
puts "reg1 setup max: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D] -min} msg
|
||||
puts "reg1 hold min: done"
|
||||
|
||||
puts "PASS: report_dcalc all arcs"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Exercise different delay calculators and check delay values
|
||||
# Targets: all delay calculator engines, copy/reinit paths
|
||||
#---------------------------------------------------------------
|
||||
puts "--- delay calculator engines ---"
|
||||
|
||||
# Unit delay calculator
|
||||
set_delay_calculator unit
|
||||
report_checks
|
||||
puts "PASS: unit calculator"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
|
||||
puts "unit buf1: done"
|
||||
|
||||
# Lumped capacitance calculator
|
||||
set_delay_calculator lumped_cap
|
||||
report_checks
|
||||
puts "PASS: lumped_cap calculator"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
|
||||
puts "lumped_cap buf1: done"
|
||||
|
||||
# DMP Ceff Elmore
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_elmore calculator"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
|
||||
puts "dmp_elmore buf1: done"
|
||||
|
||||
# DMP Ceff Two Pole
|
||||
set_delay_calculator dmp_ceff_two_pole
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_two_pole calculator"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
|
||||
puts "dmp_two_pole buf1: done"
|
||||
|
||||
# CCS Ceff
|
||||
catch {set_delay_calculator ccs_ceff} msg
|
||||
report_checks
|
||||
puts "PASS: ccs_ceff calculator"
|
||||
|
||||
# Switch back to default
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Vary load capacitance to stress DmpCeff iteration
|
||||
# Targets: DmpCeff convergence with different Ceff/Cload ratios
|
||||
#---------------------------------------------------------------
|
||||
puts "--- load variation ---"
|
||||
|
||||
foreach load_val {0.00001 0.0001 0.001 0.005 0.01 0.05 0.1 0.5 1.0 5.0} {
|
||||
set_load $load_val [get_ports out1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "load=$load_val: done"
|
||||
}
|
||||
set_load 0 [get_ports out1]
|
||||
puts "PASS: load variation"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Vary input transition to exercise table lookup paths
|
||||
# Targets: DmpCeff table lookup, findRange, dmpCeffTableLookup
|
||||
#---------------------------------------------------------------
|
||||
puts "--- slew variation ---"
|
||||
|
||||
foreach slew_val {0.001 0.005 0.01 0.05 0.1 0.2 0.5 1.0 2.0} {
|
||||
set_input_transition $slew_val [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "slew=$slew_val: done"
|
||||
}
|
||||
set_input_transition 0.1 [get_ports in1]
|
||||
puts "PASS: slew variation"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Incremental delay recalculation
|
||||
# Targets: incrementalDelaysValid, seedInvalidDelays, delayInvalid
|
||||
#---------------------------------------------------------------
|
||||
puts "--- incremental delay calc ---"
|
||||
|
||||
# Change clock period
|
||||
create_clock -name clk -period 5 [get_ports clk]
|
||||
report_checks
|
||||
puts "PASS: incremental after clock change"
|
||||
|
||||
# Change input delay
|
||||
set_input_delay -clock clk 2.0 [get_ports in1]
|
||||
report_checks
|
||||
puts "PASS: incremental after input delay change"
|
||||
|
||||
# Change output delay
|
||||
set_output_delay -clock clk 3.0 [get_ports out1]
|
||||
report_checks
|
||||
puts "PASS: incremental after output delay change"
|
||||
|
||||
# Reset and recheck
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 0 [get_ports in1]
|
||||
set_output_delay -clock clk 0 [get_ports out1]
|
||||
report_checks
|
||||
puts "PASS: incremental after reset"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Report checks with various formatting to exercise reporting paths
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report formatting ---"
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: fields"
|
||||
|
||||
report_checks -format full_clock
|
||||
puts "PASS: full_clock"
|
||||
|
||||
report_checks -format full_clock_expanded
|
||||
puts "PASS: full_clock_expanded"
|
||||
|
||||
report_checks -endpoint_count 3
|
||||
puts "PASS: endpoint_count"
|
||||
|
||||
report_checks -unconstrained
|
||||
puts "PASS: unconstrained"
|
||||
|
||||
report_checks -sort_by_slack
|
||||
puts "PASS: sort_by_slack"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_check_types exercises check edge delay queries
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_check_types ---"
|
||||
|
||||
report_check_types -max_delay -verbose
|
||||
puts "PASS: check_types max"
|
||||
|
||||
report_check_types -min_delay -verbose
|
||||
puts "PASS: check_types min"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_slews for all pins: exercises slew getters
|
||||
# (rise/fall, min/max combinations in Graph.cc)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_slews ---"
|
||||
report_slews [get_ports in1]
|
||||
report_slews [get_ports out1]
|
||||
report_slews [get_pins buf1/A]
|
||||
report_slews [get_pins buf1/Z]
|
||||
report_slews [get_pins inv1/A]
|
||||
report_slews [get_pins inv1/ZN]
|
||||
report_slews [get_pins reg1/D]
|
||||
report_slews [get_pins reg1/CK]
|
||||
report_slews [get_pins reg1/Q]
|
||||
puts "PASS: report_slews"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
@ -0,0 +1,553 @@
|
|||
--- setIncrementalDelayTolerance ---
|
||||
PASS: incremental delay tolerance 0.01
|
||||
PASS: incremental delay tolerance 0.0
|
||||
PASS: incremental delay tolerance 0.1
|
||||
--- report_net for various nets ---
|
||||
Net n1
|
||||
Pin capacitance: 1.55-1.70
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 1.55-1.70
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
buf1/Z output (BUF_X1)
|
||||
|
||||
Load pins
|
||||
inv1/A input (INV_X1) 1.55-1.70
|
||||
|
||||
Net n2
|
||||
Pin capacitance: 1.59-1.78
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 1.59-1.78
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
inv1/ZN output (INV_X1)
|
||||
|
||||
Load pins
|
||||
buf2/A input (BUF_X2) 1.59-1.78
|
||||
|
||||
Net n3
|
||||
Pin capacitance: 0.79-0.95
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 0.79-0.95
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
buf2/Z output (BUF_X2)
|
||||
|
||||
Load pins
|
||||
or1/A1 input (OR2_X1) 0.79-0.95
|
||||
|
||||
Net n4
|
||||
Pin capacitance: 0.87-0.92
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 0.87-0.92
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
buf3/Z output (BUF_X4)
|
||||
|
||||
Load pins
|
||||
and1/A1 input (AND2_X1) 0.87-0.92
|
||||
|
||||
Net n5
|
||||
Pin capacitance: 0.90-0.94
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 0.90-0.94
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
and1/ZN output (AND2_X1)
|
||||
|
||||
Load pins
|
||||
or1/A2 input (OR2_X1) 0.90-0.94
|
||||
|
||||
Net n6
|
||||
Pin capacitance: 3.82-4.29
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 3.82-4.29
|
||||
Number of drivers: 1
|
||||
Number of loads: 3
|
||||
Number of pins: 4
|
||||
|
||||
Driver pins
|
||||
or1/ZN output (OR2_X1)
|
||||
|
||||
Load pins
|
||||
buf_out/A input (BUF_X1) 0.88-0.97
|
||||
nand1/A1 input (NAND2_X1) 1.53-1.60
|
||||
nor1/A1 input (NOR2_X1) 1.41-1.71
|
||||
|
||||
Net n7
|
||||
Pin capacitance: 1.06-1.14
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 1.06-1.14
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
nand1/ZN output (NAND2_X1)
|
||||
|
||||
Load pins
|
||||
reg1/D input (DFF_X1) 1.06-1.14
|
||||
|
||||
Net n8
|
||||
Pin capacitance: 1.06-1.14
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 1.06-1.14
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
nor1/ZN output (NOR2_X1)
|
||||
|
||||
Load pins
|
||||
reg2/D input (DFF_X1) 1.06-1.14
|
||||
|
||||
PASS: report_net all nets
|
||||
--- report_net with loads ---
|
||||
Net n6
|
||||
Pin capacitance: 3.82-4.29
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 3.82-4.29
|
||||
Number of drivers: 1
|
||||
Number of loads: 3
|
||||
Number of pins: 4
|
||||
|
||||
Driver pins
|
||||
or1/ZN output (OR2_X1)
|
||||
|
||||
Load pins
|
||||
buf_out/A input (BUF_X1) 0.88-0.97
|
||||
nand1/A1 input (NAND2_X1) 1.53-1.60
|
||||
nor1/A1 input (NOR2_X1) 1.41-1.71
|
||||
|
||||
Net n7
|
||||
Pin capacitance: 1.06-1.14
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 1.06-1.14
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
nand1/ZN output (NAND2_X1)
|
||||
|
||||
Load pins
|
||||
reg1/D input (DFF_X1) 1.06-1.14
|
||||
|
||||
Net n8
|
||||
Pin capacitance: 1.06-1.14
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 1.06-1.14
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
nor1/ZN output (NOR2_X1)
|
||||
|
||||
Load pins
|
||||
reg2/D input (DFF_X1) 1.06-1.14
|
||||
|
||||
PASS: report_net with loads
|
||||
--- report_net with digits ---
|
||||
Net n1
|
||||
Pin capacitance: 1.549360-1.700230
|
||||
Wire capacitance: 0.000000
|
||||
Total capacitance: 1.549360-1.700230
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
buf1/Z output (BUF_X1)
|
||||
|
||||
Load pins
|
||||
inv1/A input (INV_X1) 1.549360-1.700230
|
||||
|
||||
Net n6
|
||||
Pin capacitance: 3.82-4.29
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 3.82-4.29
|
||||
Number of drivers: 1
|
||||
Number of loads: 3
|
||||
Number of pins: 4
|
||||
|
||||
Driver pins
|
||||
or1/ZN output (OR2_X1)
|
||||
|
||||
Load pins
|
||||
buf_out/A input (BUF_X1) 0.88-0.97
|
||||
nand1/A1 input (NAND2_X1) 1.53-1.60
|
||||
nor1/A1 input (NOR2_X1) 1.41-1.71
|
||||
|
||||
PASS: report_net digits
|
||||
--- incremental with wire caps ---
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.81 slack (MET)
|
||||
|
||||
|
||||
PASS: wire cap n1
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.81 slack (MET)
|
||||
|
||||
|
||||
PASS: wire cap n6
|
||||
--- rapid constraint changes ---
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
PASS: rapid constraint changes
|
||||
--- input transition incremental ---
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
PASS: input transition incremental
|
||||
--- clock period incremental ---
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
5.00 5.00 clock clk (rise edge)
|
||||
0.00 5.00 clock network delay (ideal)
|
||||
0.00 5.00 clock reconvergence pessimism
|
||||
5.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 4.96 library setup time
|
||||
4.96 data required time
|
||||
---------------------------------------------------------
|
||||
4.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
4.81 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
20.00 20.00 clock clk (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
19.81 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
2.00 2.00 clock clk (rise edge)
|
||||
0.00 2.00 clock network delay (ideal)
|
||||
0.00 2.00 clock reconvergence pessimism
|
||||
2.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 1.96 library setup time
|
||||
1.96 data required time
|
||||
---------------------------------------------------------
|
||||
1.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
1.81 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.81 slack (MET)
|
||||
|
||||
|
||||
PASS: clock period incremental
|
||||
--- delay calc after constraint changes ---
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
PASS: constraint change incremental
|
||||
--- driving cell changes ---
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
PASS: driving cell changes
|
||||
--- write and read SDF ---
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.81 slack (MET)
|
||||
|
||||
|
||||
Warning: dcalc_annotated_incremental.tcl line 1, -list_annotated is deprecated. Use -report_annotated.
|
||||
Not
|
||||
Delay type Total Annotated Annotated
|
||||
----------------------------------------------------------------
|
||||
cell arcs 17 17 0
|
||||
internal net arcs 10 10 0
|
||||
net arcs from primary inputs 7 7 0
|
||||
net arcs to primary outputs 3 3 0
|
||||
----------------------------------------------------------------
|
||||
37 37 0
|
||||
|
||||
Annotated Arcs
|
||||
primary input net clk -> reg1/CK
|
||||
primary input net clk -> reg2/CK
|
||||
primary input net in1 -> buf1/A
|
||||
primary input net in2 -> buf3/A
|
||||
primary input net in3 -> and1/A2
|
||||
primary input net in4 -> nor1/A2
|
||||
primary input net sel -> nand1/A2
|
||||
delay and1/A1 -> and1/ZN
|
||||
delay and1/A2 -> and1/ZN
|
||||
internal net and1/ZN -> or1/A2
|
||||
delay buf1/A -> buf1/Z
|
||||
internal net buf1/Z -> inv1/A
|
||||
delay buf2/A -> buf2/Z
|
||||
internal net buf2/Z -> or1/A1
|
||||
delay buf3/A -> buf3/Z
|
||||
internal net buf3/Z -> and1/A1
|
||||
delay buf_out/A -> buf_out/Z
|
||||
primary output net buf_out/Z -> out3
|
||||
delay inv1/A -> inv1/ZN
|
||||
internal net inv1/ZN -> buf2/A
|
||||
delay nand1/A1 -> nand1/ZN
|
||||
delay nand1/A2 -> nand1/ZN
|
||||
internal net nand1/ZN -> reg1/D
|
||||
delay nor1/A1 -> nor1/ZN
|
||||
delay nor1/A2 -> nor1/ZN
|
||||
internal net nor1/ZN -> reg2/D
|
||||
delay or1/A1 -> or1/ZN
|
||||
delay or1/A2 -> or1/ZN
|
||||
internal net or1/ZN -> nand1/A1
|
||||
internal net or1/ZN -> nor1/A1
|
||||
internal net or1/ZN -> buf_out/A
|
||||
delay reg1/CK -> reg1/QN
|
||||
delay reg1/CK -> reg1/Q
|
||||
primary output net reg1/Q -> out1
|
||||
delay reg2/CK -> reg2/QN
|
||||
delay reg2/CK -> reg2/Q
|
||||
primary output net reg2/Q -> out2
|
||||
Warning: dcalc_annotated_incremental.tcl line 1, -list_annotated is deprecated. Use -report_annotated.
|
||||
Not
|
||||
Check type Total Annotated Annotated
|
||||
----------------------------------------------------------------
|
||||
cell setup arcs 2 2 0
|
||||
cell hold arcs 2 2 0
|
||||
----------------------------------------------------------------
|
||||
4 4 0
|
||||
|
||||
Annotated Arcs
|
||||
setup reg1/CK -> reg1/D
|
||||
hold reg1/CK -> reg1/D
|
||||
setup reg2/CK -> reg2/D
|
||||
hold reg2/CK -> reg2/D
|
||||
PASS: write/read SDF
|
||||
--- remove annotations ---
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.81 slack (MET)
|
||||
|
||||
|
||||
PASS: remove annotations
|
||||
--- calculator switch incremental ---
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
PASS: calculator switch incremental
|
||||
ALL PASSED
|
||||
|
|
@ -0,0 +1,221 @@
|
|||
# Test annotated delays/slews, incremental delay recalculation,
|
||||
# delay tolerance, capacitance queries, report_net.
|
||||
# Targets: GraphDelayCalc.cc findDelays incremental, seedInvalidDelays,
|
||||
# findCheckEdgeDelays, delayInvalid(pin/vertex),
|
||||
# setIncrementalDelayTolerance, incrementalDelayTolerance,
|
||||
# loadDelay, netCaps, findVertexDelay,
|
||||
# Sta.cc setArcDelay, arcDelay, arcDelayAnnotated,
|
||||
# setAnnotatedSlew, vertexSlew, connectedCap,
|
||||
# removeDelaySlewAnnotations, delaysInvalidFrom,
|
||||
# delaysInvalidFromFanin, findDelays,
|
||||
# DmpCeff.cc various convergence paths with edge-case loads
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog dcalc_multidriver_test.v
|
||||
link_design dcalc_multidriver_test
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 0 [get_ports {in1 in2 in3 in4 sel}]
|
||||
set_output_delay -clock clk 0 [get_ports {out1 out2 out3}]
|
||||
set_input_transition 0.1 [get_ports {in1 in2 in3 in4 sel clk}]
|
||||
|
||||
# Baseline
|
||||
report_checks -path_delay max > /dev/null
|
||||
|
||||
############################################################
|
||||
# Incremental delay tolerance
|
||||
############################################################
|
||||
puts "--- setIncrementalDelayTolerance ---"
|
||||
catch {
|
||||
sta::set_incremental_delay_tolerance 0.01
|
||||
report_checks -path_delay max
|
||||
}
|
||||
puts "PASS: incremental delay tolerance 0.01"
|
||||
|
||||
catch {
|
||||
sta::set_incremental_delay_tolerance 0.0
|
||||
report_checks -path_delay max
|
||||
}
|
||||
puts "PASS: incremental delay tolerance 0.0"
|
||||
|
||||
catch {
|
||||
sta::set_incremental_delay_tolerance 0.1
|
||||
report_checks -path_delay max
|
||||
}
|
||||
puts "PASS: incremental delay tolerance 0.1"
|
||||
|
||||
# Reset
|
||||
catch { sta::set_incremental_delay_tolerance 0.0 }
|
||||
|
||||
############################################################
|
||||
# report_net for capacitance queries
|
||||
############################################################
|
||||
puts "--- report_net for various nets ---"
|
||||
report_net n1
|
||||
report_net n2
|
||||
report_net n3
|
||||
report_net n4
|
||||
report_net n5
|
||||
report_net n6
|
||||
report_net n7
|
||||
report_net n8
|
||||
puts "PASS: report_net all nets"
|
||||
|
||||
############################################################
|
||||
# report_net with loads
|
||||
############################################################
|
||||
puts "--- report_net with loads ---"
|
||||
set_load 0.05 [get_ports out1]
|
||||
set_load 0.03 [get_ports out2]
|
||||
set_load 0.02 [get_ports out3]
|
||||
report_net n6
|
||||
report_net n7
|
||||
report_net n8
|
||||
puts "PASS: report_net with loads"
|
||||
|
||||
############################################################
|
||||
# report_net with digits
|
||||
############################################################
|
||||
puts "--- report_net with digits ---"
|
||||
report_net -digits 6 n1
|
||||
report_net -digits 2 n6
|
||||
puts "PASS: report_net digits"
|
||||
|
||||
############################################################
|
||||
# Incremental: add wire caps and recompute
|
||||
############################################################
|
||||
puts "--- incremental with wire caps ---"
|
||||
catch {
|
||||
set_load 0.005 [get_nets n1]
|
||||
report_checks -path_delay max
|
||||
}
|
||||
puts "PASS: wire cap n1"
|
||||
|
||||
catch {
|
||||
set_load 0.01 [get_nets n6]
|
||||
report_checks -path_delay max
|
||||
}
|
||||
puts "PASS: wire cap n6"
|
||||
|
||||
############################################################
|
||||
# Rapid constraint changes for incremental recalculation
|
||||
############################################################
|
||||
puts "--- rapid constraint changes ---"
|
||||
set_load 0.001 [get_ports out1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
|
||||
set_load 0.01 [get_ports out1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
|
||||
set_load 0.05 [get_ports out1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
|
||||
set_load 0.1 [get_ports out1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
|
||||
set_load 0.5 [get_ports out1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
|
||||
set_load 1.0 [get_ports out1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
|
||||
set_load 0 [get_ports out1]
|
||||
puts "PASS: rapid constraint changes"
|
||||
|
||||
############################################################
|
||||
# Input transition changes driving incremental
|
||||
############################################################
|
||||
puts "--- input transition incremental ---"
|
||||
foreach slew {0.001 0.005 0.01 0.05 0.1 0.5 1.0 2.0} {
|
||||
set_input_transition $slew [get_ports in1]
|
||||
catch { report_checks -from [get_ports in1] -to [get_ports out1] }
|
||||
}
|
||||
set_input_transition 0.1 [get_ports in1]
|
||||
puts "PASS: input transition incremental"
|
||||
|
||||
############################################################
|
||||
# Clock period changes
|
||||
############################################################
|
||||
puts "--- clock period incremental ---"
|
||||
create_clock -name clk -period 5 [get_ports clk]
|
||||
report_checks -path_delay max
|
||||
create_clock -name clk -period 20 [get_ports clk]
|
||||
report_checks -path_delay max
|
||||
create_clock -name clk -period 2 [get_ports clk]
|
||||
report_checks -path_delay max
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
report_checks -path_delay max
|
||||
puts "PASS: clock period incremental"
|
||||
|
||||
############################################################
|
||||
# Delay calc after adding/removing constraints
|
||||
############################################################
|
||||
puts "--- delay calc after constraint changes ---"
|
||||
set_input_delay -clock clk 2.0 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
set_output_delay -clock clk 3.0 [get_ports out1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
set_input_delay -clock clk 0 [get_ports in1]
|
||||
set_output_delay -clock clk 0 [get_ports out1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: constraint change incremental"
|
||||
|
||||
############################################################
|
||||
# Driving cell changes
|
||||
############################################################
|
||||
puts "--- driving cell changes ---"
|
||||
set_driving_cell -lib_cell BUF_X1 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
set_driving_cell -lib_cell BUF_X4 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
set_driving_cell -lib_cell INV_X1 -pin ZN [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: driving cell changes"
|
||||
|
||||
############################################################
|
||||
# read_sdf and annotated delay
|
||||
############################################################
|
||||
puts "--- write and read SDF ---"
|
||||
set sdf_file [file join [pwd] results dcalc_annotated.sdf]
|
||||
catch {
|
||||
file mkdir results
|
||||
write_sdf -no_timestamp -no_version $sdf_file
|
||||
read_sdf $sdf_file
|
||||
report_checks -path_delay max
|
||||
report_annotated_delay -list_annotated
|
||||
report_annotated_check -list_annotated -setup -hold
|
||||
}
|
||||
puts "PASS: write/read SDF"
|
||||
|
||||
############################################################
|
||||
# Remove annotations and recalculate
|
||||
############################################################
|
||||
puts "--- remove annotations ---"
|
||||
catch {
|
||||
sta::remove_delay_slew_annotations
|
||||
report_checks -path_delay max
|
||||
}
|
||||
puts "PASS: remove annotations"
|
||||
|
||||
############################################################
|
||||
# Multiple calculator with incremental
|
||||
############################################################
|
||||
puts "--- calculator switch incremental ---"
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
set_load 0.05 [get_ports out1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
|
||||
set_delay_calculator dmp_ceff_two_pole
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
|
||||
set_delay_calculator lumped_cap
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
|
||||
set_delay_calculator unit
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
set_load 0 [get_ports out1]
|
||||
puts "PASS: calculator switch incremental"
|
||||
|
||||
puts "ALL PASSED"
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,253 @@
|
|||
# Test Arnoldi and Prima delay calculators with SPEF parasitics and
|
||||
# different load/slew conditions for improved coverage.
|
||||
# Targets: PrimaDelayCalc.cc (prima delay paths, prima reduce RC,
|
||||
# prima2, prima3, primaResStamp, primaCapStamp, primaPostReduction)
|
||||
# ArnoldiDelayCalc.cc (arnoldi delay, arnoldi reduce RC,
|
||||
# arnoldi2, arnoldi3, arnoldiExpand)
|
||||
# ArnoldiReduce.cc (arnoldi reduce matrix, arnoldi iteration)
|
||||
# GraphDelayCalc.cc (delay calc with parasitics for multiple calculators)
|
||||
# DmpCeff.cc (ceff with Pi-model parasitics)
|
||||
# FindRoot.cc (root finding with parasitic-loaded timing)
|
||||
|
||||
# Read ASAP7 libraries
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
|
||||
read_verilog ../../test/reg1_asap7.v
|
||||
link_design top
|
||||
|
||||
create_clock -name clk -period 500 {clk1 clk2 clk3}
|
||||
set_input_delay -clock clk 1 {in1 in2}
|
||||
set_output_delay -clock clk 1 [get_ports out]
|
||||
set_propagated_clock {clk1 clk2 clk3}
|
||||
|
||||
# Read SPEF parasitics
|
||||
puts "--- Reading SPEF ---"
|
||||
read_spef ../../test/reg1_asap7.spef
|
||||
puts "PASS: read_spef completed"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Prima delay calculator with various input transition values
|
||||
# Exercises: primaDelay, primaReduceRc, prima2, prima3
|
||||
#---------------------------------------------------------------
|
||||
puts "--- prima with varying slews ---"
|
||||
catch {set_delay_calculator prima} msg
|
||||
puts "set_delay_calculator prima: $msg"
|
||||
|
||||
foreach slew_val {1 5 10 50 100} {
|
||||
set_input_transition $slew_val {in1 in2 clk1 clk2 clk3}
|
||||
report_checks
|
||||
puts "prima slew=$slew_val: done"
|
||||
}
|
||||
set_input_transition 10 {in1 in2 clk1 clk2 clk3}
|
||||
|
||||
# Prima with various load values
|
||||
puts "--- prima with varying loads ---"
|
||||
foreach load_val {0.0001 0.001 0.01 0.1} {
|
||||
set_load $load_val [get_ports out]
|
||||
report_checks
|
||||
puts "prima load=$load_val: done"
|
||||
}
|
||||
set_load 0 [get_ports out]
|
||||
|
||||
# Prima report_dcalc for all arcs
|
||||
puts "--- prima report_dcalc all arcs ---"
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max} msg
|
||||
puts "prima u1 A->Y max: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -min} msg
|
||||
puts "prima u1 A->Y min: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y] -max} msg
|
||||
puts "prima u2 A->Y max: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y] -min} msg
|
||||
puts "prima u2 A->Y min: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/B] -to [get_pins u2/Y] -max} msg
|
||||
puts "prima u2 B->Y max: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/B] -to [get_pins u2/Y] -min} msg
|
||||
puts "prima u2 B->Y min: $msg"
|
||||
|
||||
# DFF arcs with prima
|
||||
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -max} msg
|
||||
puts "prima r1 CLK->Q max: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -min} msg
|
||||
puts "prima r1 CLK->Q min: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins r2/CLK] -to [get_pins r2/Q] -max} msg
|
||||
puts "prima r2 CLK->Q max: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/Q] -max} msg
|
||||
puts "prima r3 CLK->Q max: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/Q] -min} msg
|
||||
puts "prima r3 CLK->Q min: $msg"
|
||||
|
||||
# DFF check arcs with prima
|
||||
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/D] -max} msg
|
||||
puts "prima r1 setup: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/D] -min} msg
|
||||
puts "prima r1 hold: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/D] -max} msg
|
||||
puts "prima r3 setup: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/D] -min} msg
|
||||
puts "prima r3 hold: $msg"
|
||||
|
||||
# report_dcalc with digits
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -digits 2} msg
|
||||
puts "prima u1 2 digits: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -digits 8} msg
|
||||
puts "prima u1 8 digits: $msg"
|
||||
|
||||
# Prima with fields
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: prima with all fields"
|
||||
|
||||
report_checks -format full_clock
|
||||
puts "PASS: prima full_clock"
|
||||
|
||||
# Prima specific paths
|
||||
report_checks -from [get_ports in1] -to [get_ports out]
|
||||
puts "PASS: prima in1->out"
|
||||
|
||||
report_checks -from [get_ports in2] -to [get_ports out]
|
||||
puts "PASS: prima in2->out"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: prima min path"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: prima max path"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Arnoldi delay calculator with same variations
|
||||
# Exercises: arnoldiDelay, arnoldiReduceRc, arnoldiExpand
|
||||
#---------------------------------------------------------------
|
||||
puts "--- arnoldi with varying slews ---"
|
||||
catch {set_delay_calculator arnoldi} msg
|
||||
puts "set_delay_calculator arnoldi: $msg"
|
||||
|
||||
foreach slew_val {1 5 10 50 100} {
|
||||
set_input_transition $slew_val {in1 in2 clk1 clk2 clk3}
|
||||
report_checks
|
||||
puts "arnoldi slew=$slew_val: done"
|
||||
}
|
||||
set_input_transition 10 {in1 in2 clk1 clk2 clk3}
|
||||
|
||||
# Arnoldi with varying loads
|
||||
puts "--- arnoldi with varying loads ---"
|
||||
foreach load_val {0.0001 0.001 0.01 0.1} {
|
||||
set_load $load_val [get_ports out]
|
||||
report_checks
|
||||
puts "arnoldi load=$load_val: done"
|
||||
}
|
||||
set_load 0 [get_ports out]
|
||||
|
||||
# Arnoldi report_dcalc for all arcs
|
||||
puts "--- arnoldi report_dcalc ---"
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max} msg
|
||||
puts "arnoldi u1 A->Y max: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -min} msg
|
||||
puts "arnoldi u1 A->Y min: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y] -max} msg
|
||||
puts "arnoldi u2 A->Y max: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/B] -to [get_pins u2/Y] -max} msg
|
||||
puts "arnoldi u2 B->Y max: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -max} msg
|
||||
puts "arnoldi r1 CLK->Q max: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -min} msg
|
||||
puts "arnoldi r1 CLK->Q min: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins r2/CLK] -to [get_pins r2/Q] -max} msg
|
||||
puts "arnoldi r2 CLK->Q max: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/Q] -max} msg
|
||||
puts "arnoldi r3 CLK->Q max: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/D] -max} msg
|
||||
puts "arnoldi r1 setup: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/D] -min} msg
|
||||
puts "arnoldi r1 hold: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/D] -max} msg
|
||||
puts "arnoldi r3 setup: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/D] -min} msg
|
||||
puts "arnoldi r3 hold: $msg"
|
||||
|
||||
# Arnoldi with fields
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: arnoldi with all fields"
|
||||
|
||||
report_checks -format full_clock
|
||||
puts "PASS: arnoldi full_clock"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Switching between parasitic calculators to exercise reinit paths
|
||||
#---------------------------------------------------------------
|
||||
puts "--- switching parasitic calculators ---"
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_elmore with parasitics"
|
||||
|
||||
set_delay_calculator dmp_ceff_two_pole
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_two_pole with parasitics"
|
||||
|
||||
catch {set_delay_calculator ccs_ceff} msg
|
||||
report_checks
|
||||
puts "PASS: ccs_ceff with parasitics"
|
||||
|
||||
set_delay_calculator lumped_cap
|
||||
report_checks
|
||||
puts "PASS: lumped_cap with parasitics"
|
||||
|
||||
catch {set_delay_calculator prima} msg
|
||||
report_checks
|
||||
puts "PASS: prima after switching"
|
||||
|
||||
catch {set_delay_calculator arnoldi} msg
|
||||
report_checks
|
||||
puts "PASS: arnoldi after switching"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Incremental updates with parasitics
|
||||
# Exercises: seedInvalidDelays with parasitic-loaded nets
|
||||
#---------------------------------------------------------------
|
||||
puts "--- incremental with parasitics ---"
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
|
||||
set_load 0.001 [get_ports out]
|
||||
report_checks
|
||||
puts "PASS: incremental parasitics after set_load"
|
||||
|
||||
set_input_transition 50 {in1 in2}
|
||||
report_checks
|
||||
puts "PASS: incremental parasitics after set_input_transition"
|
||||
|
||||
create_clock -name clk -period 200 {clk1 clk2 clk3}
|
||||
report_checks
|
||||
puts "PASS: incremental parasitics after clock change"
|
||||
|
||||
# Restore
|
||||
set_load 0 [get_ports out]
|
||||
set_input_transition 10 {in1 in2 clk1 clk2 clk3}
|
||||
create_clock -name clk -period 500 {clk1 clk2 clk3}
|
||||
|
||||
puts "ALL PASSED"
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,174 @@
|
|||
# Test Arnoldi delay calculator with SPEF parasitics, various slew/load conditions,
|
||||
# and report_dcalc for different pin combinations.
|
||||
# Targets:
|
||||
# ArnoldiDelayCalc.cc: arnoldiDelay, arnoldiReduceRc, arnoldi2, arnoldi3,
|
||||
# arnoldiExpand, loadDelay, gateDelay, gateSlew
|
||||
# ArnoldiReduce.cc: arnoldi reduce matrix iteration, arnoldi basis expansion
|
||||
# GraphDelayCalc.cc: findVertexDelay with arnoldi parasitic reduction
|
||||
# DmpCeff.cc: ceffPiElmore convergence edge cases with different slews
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
# Read ASAP7 libraries
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
|
||||
read_verilog ../../test/reg1_asap7.v
|
||||
link_design top
|
||||
|
||||
create_clock -name clk -period 500 {clk1 clk2 clk3}
|
||||
set_input_delay -clock clk 1 {in1 in2}
|
||||
set_output_delay -clock clk 1 [get_ports out]
|
||||
set_input_transition 10 {in1 in2 clk1 clk2 clk3}
|
||||
set_propagated_clock {clk1 clk2 clk3}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 1: Read SPEF and set arnoldi
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 1: arnoldi + SPEF ---"
|
||||
read_spef ../../test/reg1_asap7.spef
|
||||
set_delay_calculator arnoldi
|
||||
puts "PASS: set arnoldi"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report_checks"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: min path"
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out]
|
||||
puts "PASS: in1->out"
|
||||
|
||||
report_checks -from [get_ports in2] -to [get_ports out]
|
||||
puts "PASS: in2->out"
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: with fields"
|
||||
|
||||
report_checks -format full_clock
|
||||
puts "PASS: full_clock"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 2: report_dcalc for all cell arcs
|
||||
# Exercises: arnoldiDelay for each arc, loadDelay, gateDelay, gateSlew
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 2: report_dcalc ---"
|
||||
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max} msg
|
||||
puts "dcalc u1 A->Y max: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -min} msg
|
||||
puts "dcalc u1 A->Y min: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y] -max} msg
|
||||
puts "dcalc u2 A->Y: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/B] -to [get_pins u2/Y] -max} msg
|
||||
puts "dcalc u2 B->Y: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/B] -to [get_pins u2/Y] -min} msg
|
||||
puts "dcalc u2 B->Y min: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -max} msg
|
||||
puts "dcalc r1 CLK->Q max: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -min} msg
|
||||
puts "dcalc r1 CLK->Q min: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins r2/CLK] -to [get_pins r2/Q] -max} msg
|
||||
puts "dcalc r2 CLK->Q: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/Q] -max} msg
|
||||
puts "dcalc r3 CLK->Q: done"
|
||||
|
||||
# Setup/hold check arcs
|
||||
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/D] -max} msg
|
||||
puts "dcalc r1 setup: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/D] -min} msg
|
||||
puts "dcalc r1 hold: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/D] -max} msg
|
||||
puts "dcalc r3 setup: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/D] -min} msg
|
||||
puts "dcalc r3 hold: done"
|
||||
|
||||
puts "PASS: dcalc reports"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 3: Vary input slew with arnoldi
|
||||
# Exercises: arnoldi gate delay computation at different slew points
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 3: varying slew ---"
|
||||
|
||||
foreach slew_val {0.1 1 5 10 25 50 100 200 500} {
|
||||
set_input_transition $slew_val {in1 in2 clk1 clk2 clk3}
|
||||
report_checks
|
||||
puts "arnoldi slew=$slew_val: done"
|
||||
}
|
||||
set_input_transition 10 {in1 in2 clk1 clk2 clk3}
|
||||
puts "PASS: varying slew"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 4: Vary output load with arnoldi
|
||||
# Exercises: arnoldi load delay at different capacitance values
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 4: varying load ---"
|
||||
|
||||
foreach load_val {0.00001 0.0001 0.001 0.005 0.01 0.05 0.1} {
|
||||
set_load $load_val [get_ports out]
|
||||
report_checks
|
||||
puts "arnoldi load=$load_val: done"
|
||||
}
|
||||
set_load 0 [get_ports out]
|
||||
puts "PASS: varying load"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 5: Arnoldi after re-read SPEF
|
||||
# Exercises: deleteReducedParasitics, re-initialization
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 5: re-read SPEF ---"
|
||||
read_spef ../../test/reg1_asap7.spef
|
||||
report_checks
|
||||
puts "PASS: arnoldi after re-read"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 6: Switch engines while arnoldi active
|
||||
# Exercises: reinit paths in delay calculator switching
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 6: engine switch from arnoldi ---"
|
||||
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
report_checks
|
||||
puts "PASS: switch to dmp_ceff_elmore"
|
||||
|
||||
set_delay_calculator arnoldi
|
||||
report_checks
|
||||
puts "PASS: back to arnoldi"
|
||||
|
||||
set_delay_calculator lumped_cap
|
||||
report_checks
|
||||
puts "PASS: switch to lumped_cap"
|
||||
|
||||
set_delay_calculator arnoldi
|
||||
report_checks
|
||||
puts "PASS: back to arnoldi again"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 7: Arnoldi with digits and endpoint count
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 7: format options ---"
|
||||
report_checks -digits 6
|
||||
puts "PASS: 6 digits"
|
||||
|
||||
report_checks -endpoint_count 3
|
||||
puts "PASS: endpoint_count 3"
|
||||
|
||||
report_checks -group_count 2
|
||||
puts "PASS: group_count 2"
|
||||
|
||||
puts "ALL PASSED"
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,155 @@
|
|||
# Test CCS effective capacitance delay calculator and incremental updates.
|
||||
# Targets: CcsCeffDelayCalc.cc (0.0% -> all paths)
|
||||
# GraphDelayCalc.cc (87.3% -> incremental update, arrival annotation)
|
||||
# DmpDelayCalc.cc (51.8% -> ccs_ceff falls back to dmp when no CCS data)
|
||||
# DelayCalcBase.cc (65.3% -> additional base class paths)
|
||||
# ArcDelayCalc.cc (59.7% -> makeArcDcalcArg error paths)
|
||||
# DmpCeff.cc (79.1% -> more DmpCeff computation paths)
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog dcalc_test1.v
|
||||
link_design dcalc_test1
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 0 [get_ports in1]
|
||||
set_output_delay -clock clk 0 [get_ports out1]
|
||||
set_input_transition 0.1 [get_ports in1]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# CCS effective capacitance delay calculator
|
||||
# (Falls back to table-based for NLDM libraries but exercises
|
||||
# constructor, copy, name, and fallback paths)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- ccs_ceff delay calculator ---"
|
||||
catch {set_delay_calculator ccs_ceff} msg
|
||||
puts "set_delay_calculator ccs_ceff: $msg"
|
||||
|
||||
report_checks
|
||||
puts "PASS: ccs_ceff report_checks"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: ccs_ceff min path"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: ccs_ceff max path"
|
||||
|
||||
# report_dcalc with ccs_ceff
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "ccs_ceff dcalc buf1 max: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -min} msg
|
||||
puts "ccs_ceff dcalc buf1 min: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins inv1/A] -to [get_pins inv1/ZN] -max} msg
|
||||
puts "ccs_ceff dcalc inv1 max: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins inv1/A] -to [get_pins inv1/ZN] -min} msg
|
||||
puts "ccs_ceff dcalc inv1 min: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max} msg
|
||||
puts "ccs_ceff dcalc reg1 CK->Q max: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -min} msg
|
||||
puts "ccs_ceff dcalc reg1 CK->Q min: $msg"
|
||||
|
||||
# Setup/hold check arcs
|
||||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D] -max} msg
|
||||
puts "ccs_ceff dcalc reg1 setup: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D] -min} msg
|
||||
puts "ccs_ceff dcalc reg1 hold: $msg"
|
||||
|
||||
# With fields
|
||||
report_checks -fields {slew cap input_pins}
|
||||
puts "PASS: ccs_ceff with fields"
|
||||
|
||||
report_checks -format full_clock
|
||||
puts "PASS: ccs_ceff full_clock format"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Incremental delay update: change constraints and recompute
|
||||
#---------------------------------------------------------------
|
||||
puts "--- incremental delay update ---"
|
||||
|
||||
# Change load and recompute (exercises GraphDelayCalc incremental update)
|
||||
set_load 0.01 [get_ports out1]
|
||||
report_checks
|
||||
puts "PASS: incremental after set_load 0.01"
|
||||
|
||||
set_load 0.05 [get_ports out1]
|
||||
report_checks
|
||||
puts "PASS: incremental after set_load 0.05"
|
||||
|
||||
set_load 0.1 [get_ports out1]
|
||||
report_checks
|
||||
puts "PASS: incremental after set_load 0.1"
|
||||
|
||||
# Change input transition and recompute
|
||||
set_input_transition 0.01 [get_ports in1]
|
||||
report_checks
|
||||
puts "PASS: incremental after input_transition 0.01"
|
||||
|
||||
set_input_transition 0.5 [get_ports in1]
|
||||
report_checks
|
||||
puts "PASS: incremental after input_transition 0.5"
|
||||
|
||||
# Change clock period (triggers incremental update)
|
||||
create_clock -name clk -period 5 [get_ports clk]
|
||||
report_checks
|
||||
puts "PASS: incremental after clock period change"
|
||||
|
||||
# Change delays
|
||||
set_input_delay -clock clk 1.0 [get_ports in1]
|
||||
report_checks
|
||||
puts "PASS: incremental after input_delay change"
|
||||
|
||||
set_output_delay -clock clk 2.0 [get_ports out1]
|
||||
report_checks
|
||||
puts "PASS: incremental after output_delay change"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Switch between calculators to exercise copy/init paths
|
||||
#---------------------------------------------------------------
|
||||
puts "--- calculator switching ---"
|
||||
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
report_checks
|
||||
puts "PASS: switch to dmp_ceff_elmore"
|
||||
|
||||
set_delay_calculator ccs_ceff
|
||||
report_checks
|
||||
puts "PASS: switch back to ccs_ceff"
|
||||
|
||||
set_delay_calculator dmp_ceff_two_pole
|
||||
report_checks
|
||||
puts "PASS: switch to dmp_ceff_two_pole"
|
||||
|
||||
set_delay_calculator lumped_cap
|
||||
report_checks
|
||||
puts "PASS: switch to lumped_cap"
|
||||
|
||||
set_delay_calculator unit
|
||||
report_checks
|
||||
puts "PASS: switch to unit"
|
||||
|
||||
set_delay_calculator ccs_ceff
|
||||
report_checks
|
||||
puts "PASS: switch back to ccs_ceff final"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_dcalc with -digits (exercises formatting paths)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_dcalc with various digits ---"
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -digits 2} msg
|
||||
puts "dcalc 2 digits: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -digits 4} msg
|
||||
puts "dcalc 4 digits: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -digits 8} msg
|
||||
puts "dcalc 8 digits: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -digits 12} msg
|
||||
puts "dcalc 12 digits: $msg"
|
||||
|
||||
puts "ALL PASSED"
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,157 @@
|
|||
# Test CCS/DMP delay calc with SPEF parasitics and multi-corner.
|
||||
# Targets: CcsCeffDelayCalc.cc (0.0% -> parasitic paths)
|
||||
# GraphDelayCalc.cc (87.3% -> parasitic-driven delay calc)
|
||||
# DmpCeff.cc (79.1% -> ceff computation with Pi-model)
|
||||
# DmpDelayCalc.cc (51.8% -> Pi-model parasitic paths)
|
||||
# ArcDcalcWaveforms.cc (0.0% -> waveform data access)
|
||||
# NetCaps.cc (53.3% -> net cap with parasitics)
|
||||
# DelayCalcBase.cc (65.3% -> parasitic delay base)
|
||||
# FindRoot.cc (79.5% -> root finding edge cases)
|
||||
|
||||
# Read ASAP7 libraries
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
|
||||
read_verilog ../../test/reg1_asap7.v
|
||||
link_design top
|
||||
|
||||
create_clock -name clk -period 500 {clk1 clk2 clk3}
|
||||
set_input_delay -clock clk 1 {in1 in2}
|
||||
set_output_delay -clock clk 1 [get_ports out]
|
||||
set_input_transition 10 {in1 in2 clk1 clk2 clk3}
|
||||
set_propagated_clock {clk1 clk2 clk3}
|
||||
|
||||
# Read SPEF parasitics
|
||||
puts "--- Reading SPEF ---"
|
||||
read_spef ../../test/reg1_asap7.spef
|
||||
puts "PASS: read_spef completed"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# CCS delay calculator with parasitics
|
||||
#---------------------------------------------------------------
|
||||
puts "--- ccs_ceff delay calculator with parasitics ---"
|
||||
catch {set_delay_calculator ccs_ceff} msg
|
||||
puts "set_delay_calculator ccs_ceff: $msg"
|
||||
|
||||
report_checks
|
||||
puts "PASS: ccs_ceff with parasitics report_checks"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: ccs_ceff with parasitics min"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: ccs_ceff with parasitics max"
|
||||
|
||||
report_checks -fields {slew cap input_pins} -format full_clock
|
||||
puts "PASS: ccs_ceff with parasitics fields"
|
||||
|
||||
# report_dcalc exercises arc delay computation through parasitics
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y]} msg
|
||||
puts "ccs_ceff dcalc u1 A->Y: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y]} msg
|
||||
puts "ccs_ceff dcalc u2 A->Y: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/B] -to [get_pins u2/Y]} msg
|
||||
puts "ccs_ceff dcalc u2 B->Y: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -max} msg
|
||||
puts "ccs_ceff dcalc r1 CLK->Q max: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -min} msg
|
||||
puts "ccs_ceff dcalc r1 CLK->Q min: $msg"
|
||||
|
||||
# Setup/hold arcs with ccs_ceff
|
||||
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/D] -max} msg
|
||||
puts "ccs_ceff dcalc r3 setup: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/D] -min} msg
|
||||
puts "ccs_ceff dcalc r3 hold: $msg"
|
||||
|
||||
# Additional paths
|
||||
report_checks -from [get_ports in1] -to [get_ports out]
|
||||
puts "PASS: ccs_ceff in1->out"
|
||||
|
||||
report_checks -from [get_ports in2] -to [get_ports out]
|
||||
puts "PASS: ccs_ceff in2->out"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# DMP ceff two-pole with parasitics (incremental from ccs_ceff)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- dmp_ceff_two_pole with parasitics ---"
|
||||
set_delay_calculator dmp_ceff_two_pole
|
||||
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_two_pole with parasitics"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: dmp_ceff_two_pole min with parasitics"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: dmp_ceff_two_pole max with parasitics"
|
||||
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max} msg
|
||||
puts "dmp_two_pole dcalc u1: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y] -max} msg
|
||||
puts "dmp_two_pole dcalc u2: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -max} msg
|
||||
puts "dmp_two_pole dcalc r1 CLK->Q: $msg"
|
||||
|
||||
report_checks -fields {slew cap input_pins nets}
|
||||
puts "PASS: dmp_two_pole with full fields"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Incremental changes with parasitics
|
||||
#---------------------------------------------------------------
|
||||
puts "--- incremental with parasitics ---"
|
||||
|
||||
# Change load
|
||||
set_load 0.001 [get_ports out]
|
||||
report_checks
|
||||
puts "PASS: incremental parasitics after set_load"
|
||||
|
||||
# Change input transition
|
||||
set_input_transition 50 {in1 in2}
|
||||
report_checks
|
||||
puts "PASS: incremental parasitics after set_input_transition"
|
||||
|
||||
# Change clock period
|
||||
create_clock -name clk -period 200 {clk1 clk2 clk3}
|
||||
report_checks
|
||||
puts "PASS: incremental parasitics after clock change"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Switch to ccs_ceff after constraint changes (exercises reinit)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- ccs_ceff after constraint changes ---"
|
||||
set_delay_calculator ccs_ceff
|
||||
report_checks
|
||||
puts "PASS: ccs_ceff after constraint changes"
|
||||
|
||||
# Switch rapidly between calculators
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
set_delay_calculator ccs_ceff
|
||||
set_delay_calculator arnoldi
|
||||
set_delay_calculator ccs_ceff
|
||||
report_checks
|
||||
puts "PASS: rapid calculator switching"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Report checks with different endpoint counts
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_checks with endpoint_count ---"
|
||||
report_checks -endpoint_count 2
|
||||
puts "PASS: endpoint_count 2"
|
||||
|
||||
report_checks -group_count 3
|
||||
puts "PASS: group_count 3"
|
||||
|
||||
report_checks -path_delay min -endpoint_count 3
|
||||
puts "PASS: min endpoint_count 3"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
@ -0,0 +1,694 @@
|
|||
--- Fast corner timing ---
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
Corner: fast
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.05 0.05 v reg1/Q (DFF_X1)
|
||||
0.00 0.05 v out1 (out)
|
||||
0.05 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
0.00 10.00 output external delay
|
||||
10.00 data required time
|
||||
---------------------------------------------------------
|
||||
10.00 data required time
|
||||
-0.05 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.95 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks fast corner
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
Corner: fast
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ input external delay
|
||||
0.00 0.00 ^ in1 (in)
|
||||
0.01 0.01 ^ buf1/Z (BUF_X1)
|
||||
0.00 0.02 v inv1/ZN (INV_X1)
|
||||
0.00 0.02 v reg1/D (DFF_X1)
|
||||
0.02 data arrival time
|
||||
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg1/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
---------------------------------------------------------
|
||||
0.00 data required time
|
||||
-0.02 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.01 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks fast corner min path
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
Corner: fast
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.05 0.05 v reg1/Q (DFF_X1)
|
||||
0.00 0.05 v out1 (out)
|
||||
0.05 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
0.00 10.00 output external delay
|
||||
10.00 data required time
|
||||
---------------------------------------------------------
|
||||
10.00 data required time
|
||||
-0.05 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.95 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks fast corner max path
|
||||
--- Slow corner timing ---
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
Corner: slow
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.29 0.29 ^ reg1/Q (DFF_X1)
|
||||
0.00 0.29 ^ out1 (out)
|
||||
0.29 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
0.00 10.00 output external delay
|
||||
10.00 data required time
|
||||
---------------------------------------------------------
|
||||
10.00 data required time
|
||||
-0.29 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.71 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks slow corner
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
Corner: slow
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ input external delay
|
||||
0.00 0.00 ^ in1 (in)
|
||||
0.05 0.05 ^ buf1/Z (BUF_X1)
|
||||
0.02 0.07 v inv1/ZN (INV_X1)
|
||||
0.00 0.07 v reg1/D (DFF_X1)
|
||||
0.07 data arrival time
|
||||
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg1/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
---------------------------------------------------------
|
||||
0.00 data required time
|
||||
-0.07 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.07 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks slow corner min path
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
Corner: slow
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.29 0.29 ^ reg1/Q (DFF_X1)
|
||||
0.00 0.29 ^ out1 (out)
|
||||
0.29 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
0.00 10.00 output external delay
|
||||
10.00 data required time
|
||||
---------------------------------------------------------
|
||||
10.00 data required time
|
||||
-0.29 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.71 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks slow corner max path
|
||||
--- report_dcalc per corner ---
|
||||
Library: NangateOpenCellLibrary_fast
|
||||
Cell: BUF_X1
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Z ^
|
||||
P = 1.00 V = 1.25 T = 0.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.72
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.00 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.01
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.72
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.00
|
||||
0.00 | 0.00 0.00
|
||||
Table value = 0.00
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.00
|
||||
Driver waveform slew = 0.00
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Z v
|
||||
P = 1.00 V = 1.25 T = 0.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.60
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.00 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.01
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.60
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.00
|
||||
0.00 | 0.00 0.00
|
||||
Table value = 0.00
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.00
|
||||
Driver waveform slew = 0.00
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc fast corner buf1
|
||||
Library: NangateOpenCellLibrary_fast
|
||||
Cell: BUF_X1
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Z ^
|
||||
P = 1.00 V = 0.95 T = 125.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.64
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.04 0.05
|
||||
0.01 | 0.04 0.06
|
||||
Table value = 0.05
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.05
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.64
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.01 0.03
|
||||
0.01 | 0.01 0.03
|
||||
Table value = 0.02
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.02
|
||||
Driver waveform slew = 0.02
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Z v
|
||||
P = 1.00 V = 0.95 T = 125.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.48
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.07 0.08
|
||||
0.01 | 0.08 0.08
|
||||
Table value = 0.08
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.08
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.48
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.01 0.02
|
||||
0.01 | 0.01 0.02
|
||||
Table value = 0.02
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.02
|
||||
Driver waveform slew = 0.02
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc slow corner buf1
|
||||
Library: NangateOpenCellLibrary_fast
|
||||
Cell: INV_X1
|
||||
Arc sense: negative_unate
|
||||
Arc type: combinational
|
||||
A ^ -> ZN v
|
||||
P = 1.00 V = 1.25 T = 0.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.10
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.00
|
||||
0.01 | 0.00 0.01
|
||||
Table value = 0.00
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.00
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.10
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.00
|
||||
0.01 | 0.00 0.00
|
||||
Table value = 0.00
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.00
|
||||
Driver waveform slew = 0.00
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> ZN ^
|
||||
P = 1.00 V = 1.25 T = 0.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.16
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.01 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.01
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.16
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.00
|
||||
0.01 | 0.00 0.01
|
||||
Table value = 0.00
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.00
|
||||
Driver waveform slew = 0.00
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc fast corner inv1
|
||||
Library: NangateOpenCellLibrary_fast
|
||||
Cell: INV_X1
|
||||
Arc sense: negative_unate
|
||||
Arc type: combinational
|
||||
A ^ -> ZN v
|
||||
P = 1.00 V = 0.95 T = 125.00
|
||||
------- input_net_transition = 0.02
|
||||
| total_output_net_capacitance = 1.03
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.01 | 0.01 0.02
|
||||
0.04 | 0.02 0.03
|
||||
Table value = 0.02
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.02
|
||||
|
||||
------- input_net_transition = 0.02
|
||||
| total_output_net_capacitance = 1.03
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.01 | 0.00 0.01
|
||||
0.04 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> ZN ^
|
||||
P = 1.00 V = 0.95 T = 125.00
|
||||
------- input_net_transition = 0.02
|
||||
| total_output_net_capacitance = 1.11
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.01 | 0.02 0.04
|
||||
0.04 | 0.04 0.06
|
||||
Table value = 0.03
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.03
|
||||
|
||||
------- input_net_transition = 0.02
|
||||
| total_output_net_capacitance = 1.11
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.01 | 0.01 0.02
|
||||
0.04 | 0.02 0.03
|
||||
Table value = 0.02
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.02
|
||||
Driver waveform slew = 0.02
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc slow corner inv1
|
||||
Library: NangateOpenCellLibrary_fast
|
||||
Cell: DFF_X1
|
||||
Arc sense: non_unate
|
||||
Arc type: Reg Clk to Q
|
||||
CK ^ -> Q ^
|
||||
P = 1.00 V = 1.25 T = 0.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.05 0.05
|
||||
0.00 | 0.05 0.05
|
||||
Table value = 0.05
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.05
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.00 | 0.00 0.01
|
||||
Table value = 0.00
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.00
|
||||
Driver waveform slew = 0.00
|
||||
|
||||
.............................................
|
||||
|
||||
CK ^ -> Q v
|
||||
P = 1.00 V = 1.25 T = 0.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.05 0.05
|
||||
0.00 | 0.05 0.05
|
||||
Table value = 0.05
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.05
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.00
|
||||
0.00 | 0.00 0.00
|
||||
Table value = 0.00
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.00
|
||||
Driver waveform slew = 0.00
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc fast corner DFF CK->Q
|
||||
Library: NangateOpenCellLibrary_fast
|
||||
Cell: DFF_X1
|
||||
Arc sense: non_unate
|
||||
Arc type: Reg Clk to Q
|
||||
CK ^ -> Q ^
|
||||
P = 1.00 V = 0.95 T = 125.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.29 0.30
|
||||
0.01 | 0.30 0.31
|
||||
Table value = 0.29
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.29
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.02 0.03
|
||||
0.01 | 0.02 0.03
|
||||
Table value = 0.02
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.02
|
||||
Driver waveform slew = 0.02
|
||||
|
||||
.............................................
|
||||
|
||||
CK ^ -> Q v
|
||||
P = 1.00 V = 0.95 T = 125.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.23 0.24
|
||||
0.01 | 0.24 0.25
|
||||
Table value = 0.23
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.23
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.02 0.02
|
||||
0.01 | 0.02 0.02
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc slow corner DFF CK->Q
|
||||
Library: NangateOpenCellLibrary_fast
|
||||
Cell: DFF_X1
|
||||
Arc type: hold
|
||||
CK ^ -> D ^
|
||||
P = 1.00 V = 1.25 T = 0.00
|
||||
------- constrained_pin_transition = 0.00 (ideal clock)
|
||||
| related_pin_transition = 0.00
|
||||
| 0.00 0.03
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.03 | 0.01 0.01
|
||||
Table value = 0.00
|
||||
PVT scale factor = 1.00
|
||||
Check = 0.00
|
||||
|
||||
.............................................
|
||||
|
||||
CK ^ -> D v
|
||||
P = 1.00 V = 1.25 T = 0.00
|
||||
------- constrained_pin_transition = 0.00 (ideal clock)
|
||||
| related_pin_transition = 0.00
|
||||
| 0.00 0.03
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.03 | 0.01 0.01
|
||||
Table value = 0.00
|
||||
PVT scale factor = 1.00
|
||||
Check = 0.00
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc fast corner DFF hold check
|
||||
Library: NangateOpenCellLibrary_fast
|
||||
Cell: DFF_X1
|
||||
Arc type: setup
|
||||
CK ^ -> D ^
|
||||
P = 1.00 V = 0.95 T = 125.00
|
||||
------- constrained_pin_transition = 0.02 (ideal clock)
|
||||
| related_pin_transition = 0.00
|
||||
| 0.00 0.11
|
||||
v --------------------
|
||||
0.00 | 0.06 0.04
|
||||
0.11 | 0.11 0.08
|
||||
Table value = 0.07
|
||||
PVT scale factor = 1.00
|
||||
Check = 0.07
|
||||
|
||||
.............................................
|
||||
|
||||
CK ^ -> D v
|
||||
P = 1.00 V = 0.95 T = 125.00
|
||||
------- constrained_pin_transition = 0.01 (ideal clock)
|
||||
| related_pin_transition = 0.00
|
||||
| 0.00 0.11
|
||||
v --------------------
|
||||
0.00 | 0.15 0.09
|
||||
0.11 | 0.21 0.15
|
||||
Table value = 0.15
|
||||
PVT scale factor = 1.00
|
||||
Check = 0.15
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc slow corner DFF setup check
|
||||
--- report_checks with fields ---
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
Corner: fast
|
||||
|
||||
Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.00 0.00 0.05 0.05 v reg1/Q (DFF_X1)
|
||||
0.00 0.00 0.05 v out1 (out)
|
||||
0.05 data arrival time
|
||||
|
||||
0.00 10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
0.00 10.00 output external delay
|
||||
10.00 data required time
|
||||
-----------------------------------------------------------------------
|
||||
10.00 data required time
|
||||
-0.05 data arrival time
|
||||
-----------------------------------------------------------------------
|
||||
9.95 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks fast with fields
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
Corner: slow
|
||||
|
||||
Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.00 0.02 0.29 0.29 ^ reg1/Q (DFF_X1)
|
||||
0.02 0.00 0.29 ^ out1 (out)
|
||||
0.29 data arrival time
|
||||
|
||||
0.00 10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
0.00 10.00 output external delay
|
||||
10.00 data required time
|
||||
-----------------------------------------------------------------------
|
||||
10.00 data required time
|
||||
-0.29 data arrival time
|
||||
-----------------------------------------------------------------------
|
||||
9.71 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks slow with fields
|
||||
--- set_load and recheck corners ---
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
Corner: fast
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.05 0.05 v reg1/Q (DFF_X1)
|
||||
0.00 0.05 v out1 (out)
|
||||
0.05 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
0.00 10.00 output external delay
|
||||
10.00 data required time
|
||||
---------------------------------------------------------
|
||||
10.00 data required time
|
||||
-0.05 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.95 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks fast after set_load
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
Corner: slow
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.29 0.29 ^ reg1/Q (DFF_X1)
|
||||
0.00 0.29 ^ out1 (out)
|
||||
0.29 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
0.00 10.00 output external delay
|
||||
10.00 data required time
|
||||
---------------------------------------------------------
|
||||
10.00 data required time
|
||||
-0.29 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.71 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks slow after set_load
|
||||
ALL PASSED
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
# Test multi-corner delay calculation
|
||||
# Exercises: define_corners, corner-specific liberty, report_checks -corner, report_dcalc -corner
|
||||
|
||||
define_corners fast slow
|
||||
|
||||
read_liberty -corner fast ../../test/nangate45/Nangate45_fast.lib
|
||||
read_liberty -corner slow ../../test/nangate45/Nangate45_slow.lib
|
||||
|
||||
read_verilog dcalc_test1.v
|
||||
link_design dcalc_test1
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 0 [get_ports in1]
|
||||
set_output_delay -clock clk 0 [get_ports out1]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_checks per corner
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Fast corner timing ---"
|
||||
report_checks -corner fast
|
||||
puts "PASS: report_checks fast corner"
|
||||
|
||||
report_checks -corner fast -path_delay min
|
||||
puts "PASS: report_checks fast corner min path"
|
||||
|
||||
report_checks -corner fast -path_delay max
|
||||
puts "PASS: report_checks fast corner max path"
|
||||
|
||||
puts "--- Slow corner timing ---"
|
||||
report_checks -corner slow
|
||||
puts "PASS: report_checks slow corner"
|
||||
|
||||
report_checks -corner slow -path_delay min
|
||||
puts "PASS: report_checks slow corner min path"
|
||||
|
||||
report_checks -corner slow -path_delay max
|
||||
puts "PASS: report_checks slow corner max path"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_dcalc per corner
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_dcalc per corner ---"
|
||||
|
||||
catch {report_dcalc -corner fast -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc fast corner buf1"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc slow corner buf1"
|
||||
|
||||
catch {report_dcalc -corner fast -from [get_pins inv1/A] -to [get_pins inv1/ZN]} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc fast corner inv1"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins inv1/A] -to [get_pins inv1/ZN]} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc slow corner inv1"
|
||||
|
||||
# DFF arcs per corner
|
||||
catch {report_dcalc -corner fast -from [get_pins reg1/CK] -to [get_pins reg1/Q]} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc fast corner DFF CK->Q"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins reg1/CK] -to [get_pins reg1/Q]} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc slow corner DFF CK->Q"
|
||||
|
||||
# Setup/hold check arcs per corner
|
||||
catch {report_dcalc -corner fast -from [get_pins reg1/CK] -to [get_pins reg1/D] -min} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc fast corner DFF hold check"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins reg1/CK] -to [get_pins reg1/D] -max} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc slow corner DFF setup check"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_checks with -fields for more coverage
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_checks with fields ---"
|
||||
report_checks -corner fast -fields {slew cap input_pins}
|
||||
puts "PASS: report_checks fast with fields"
|
||||
|
||||
report_checks -corner slow -fields {slew cap input_pins}
|
||||
puts "PASS: report_checks slow with fields"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# set_load on output and recheck corners
|
||||
#---------------------------------------------------------------
|
||||
puts "--- set_load and recheck corners ---"
|
||||
set_load 0.1 [get_ports out1]
|
||||
report_checks -corner fast
|
||||
puts "PASS: report_checks fast after set_load"
|
||||
|
||||
report_checks -corner slow
|
||||
puts "PASS: report_checks slow after set_load"
|
||||
|
||||
puts "ALL PASSED"
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,203 @@
|
|||
# Test DmpCeff and DmpDelayCalc with various load and slew conditions.
|
||||
# Targets: DmpCeff.cc (dmpCeffElmore, dmpCeffTwoPole, dmpCeffDrvrPi,
|
||||
# ceffPiElmore, ceffPiD, dmpCeffIter, dmpCeffStep, dmpCeffD,
|
||||
# dmpCeffTableLookup, dmpCeffNear, dmpCeffBinaryCcs,
|
||||
# findRange, addStep, evalDmpGateDelay, evalDmpSlew)
|
||||
# DmpDelayCalc.cc (makeArcDcalcArg, gateDelay, gateSlew,
|
||||
# reportDcalc, reportArcDcalcArg, loadDelay, reportLoadDelay,
|
||||
# gateDelaySlew, delayCalcName, makeCopy)
|
||||
# PrimaDelayCalc.cc (primaDelay, primaReduceRc, prima2, prima3,
|
||||
# primaResStamp, primaCapStamp, primaPostReduction)
|
||||
# ArnoldiDelayCalc.cc (arnoldiDelay, arnoldiReduceRc, arnoldi2, arnoldi3)
|
||||
# ArnoldiReduce.cc (arnoldiReduce, arnoldiExpand)
|
||||
# FindRoot.cc (findRoot, secantMethod, newtonMethod, bisectionMethod)
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog dcalc_multidriver_test.v
|
||||
link_design dcalc_multidriver_test
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 0 [get_ports {in1 in2 in3 in4 sel}]
|
||||
set_output_delay -clock clk 0 [get_ports {out1 out2 out3}]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# DmpCeff Elmore with various load conditions
|
||||
# Exercises: dmpCeffElmore iteration with different effective capacitance
|
||||
#---------------------------------------------------------------
|
||||
puts "--- dmp_ceff_elmore with varying loads ---"
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
|
||||
# Very small load
|
||||
set_load 0.0001 [get_ports out1]
|
||||
set_input_transition 0.01 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: dmp_ceff_elmore tiny load"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "tiny load dcalc: $msg"
|
||||
|
||||
# Small load
|
||||
set_load 0.001 [get_ports out1]
|
||||
set_input_transition 0.05 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: dmp_ceff_elmore small load"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "small load dcalc: $msg"
|
||||
|
||||
# Medium load
|
||||
set_load 0.01 [get_ports out1]
|
||||
set_input_transition 0.1 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: dmp_ceff_elmore medium load"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "medium load dcalc: $msg"
|
||||
|
||||
# Large load
|
||||
set_load 0.1 [get_ports out1]
|
||||
set_input_transition 0.5 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: dmp_ceff_elmore large load"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "large load dcalc: $msg"
|
||||
|
||||
# Very large load (stress dmp iteration convergence)
|
||||
set_load 1.0 [get_ports out1]
|
||||
set_input_transition 1.0 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: dmp_ceff_elmore very large load"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "very large load dcalc: $msg"
|
||||
|
||||
# Reset
|
||||
set_load 0 [get_ports out1]
|
||||
set_input_transition 0.1 [get_ports in1]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# DmpCeff TwoPole with same load variations
|
||||
# Exercises: dmpCeffTwoPole path, different convergence behavior
|
||||
#---------------------------------------------------------------
|
||||
puts "--- dmp_ceff_two_pole with varying loads ---"
|
||||
set_delay_calculator dmp_ceff_two_pole
|
||||
|
||||
# Vary load and transition on multiple outputs
|
||||
foreach out_port {out1 out2 out3} {
|
||||
foreach load_val {0.001 0.01 0.05 0.1} {
|
||||
set_load $load_val [get_ports $out_port]
|
||||
catch {report_checks -to [get_ports $out_port]} msg
|
||||
puts "dmp_two_pole $out_port load=$load_val: done"
|
||||
}
|
||||
set_load 0 [get_ports $out_port]
|
||||
}
|
||||
|
||||
# report_dcalc for all gate types with dmp_two_pole
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "dmp_two_pole buf1: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins inv1/A] -to [get_pins inv1/ZN] -max} msg
|
||||
puts "dmp_two_pole inv1: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins and1/A1] -to [get_pins and1/ZN] -max} msg
|
||||
puts "dmp_two_pole and1 A1: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins or1/A1] -to [get_pins or1/ZN] -max} msg
|
||||
puts "dmp_two_pole or1 A1: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins nand1/A1] -to [get_pins nand1/ZN] -max} msg
|
||||
puts "dmp_two_pole nand1 A1: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins nor1/A1] -to [get_pins nor1/ZN] -max} msg
|
||||
puts "dmp_two_pole nor1 A1: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max} msg
|
||||
puts "dmp_two_pole reg1 CK->Q: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D] -max} msg
|
||||
puts "dmp_two_pole reg1 setup: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D] -min} msg
|
||||
puts "dmp_two_pole reg1 hold: $msg"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multiple input transition values to exercise different table lookups
|
||||
# Exercises: dmpCeffTableLookup, findRange
|
||||
#---------------------------------------------------------------
|
||||
puts "--- varying input transitions ---"
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
|
||||
foreach slew_val {0.001 0.01 0.05 0.1 0.2 0.5 1.0} {
|
||||
set_input_transition $slew_val [get_ports {in1 in2 in3 in4 sel}]
|
||||
catch {
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
} msg
|
||||
puts "slew=$slew_val: done"
|
||||
}
|
||||
set_input_transition 0.1 [get_ports {in1 in2 in3 in4 sel}]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# CCS effective capacitance calculator on large design
|
||||
# Exercises: CcsCeffDelayCalc paths
|
||||
#---------------------------------------------------------------
|
||||
puts "--- ccs_ceff on larger design ---"
|
||||
catch {set_delay_calculator ccs_ceff} msg
|
||||
puts "set_delay_calculator ccs_ceff: $msg"
|
||||
|
||||
report_checks
|
||||
puts "PASS: ccs_ceff on larger design"
|
||||
|
||||
# Various loads with ccs_ceff
|
||||
foreach load_val {0.001 0.01 0.1} {
|
||||
set_load $load_val [get_ports out1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "ccs_ceff load=$load_val: done"
|
||||
}
|
||||
set_load 0 [get_ports out1]
|
||||
|
||||
# report_dcalc with ccs_ceff
|
||||
catch {report_dcalc -from [get_pins nand1/A1] -to [get_pins nand1/ZN] -max} msg
|
||||
puts "ccs_ceff nand1 A1: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins nor1/A1] -to [get_pins nor1/ZN] -max} msg
|
||||
puts "ccs_ceff nor1 A1: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf2/A] -to [get_pins buf2/Z] -max} msg
|
||||
puts "ccs_ceff buf2 A->Z: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf3/A] -to [get_pins buf3/Z] -max} msg
|
||||
puts "ccs_ceff buf3 A->Z: $msg"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Rapid calculator switching to exercise copy/reinit paths
|
||||
#---------------------------------------------------------------
|
||||
puts "--- rapid calculator switching ---"
|
||||
set_delay_calculator unit
|
||||
report_checks -from [get_ports in1] -to [get_ports out3]
|
||||
set_delay_calculator lumped_cap
|
||||
report_checks -from [get_ports in1] -to [get_ports out3]
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
report_checks -from [get_ports in1] -to [get_ports out3]
|
||||
set_delay_calculator dmp_ceff_two_pole
|
||||
report_checks -from [get_ports in1] -to [get_ports out3]
|
||||
catch {set_delay_calculator ccs_ceff} msg
|
||||
report_checks -from [get_ports in1] -to [get_ports out3]
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
report_checks -from [get_ports in1] -to [get_ports out3]
|
||||
puts "PASS: rapid switching"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_checks with various reporting formats
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_checks formatting ---"
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: all fields"
|
||||
|
||||
report_checks -format full_clock
|
||||
puts "PASS: full_clock"
|
||||
|
||||
report_checks -format full_clock_expanded
|
||||
puts "PASS: full_clock_expanded"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
@ -0,0 +1,980 @@
|
|||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13178, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13211, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13244, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13277, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13310, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13343, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13376, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14772, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14805, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14838, timing group from output port.
|
||||
--- Test 1: manual pi + dmp_ceff_elmore ---
|
||||
PASS: pi/elmore set
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
48.40 48.40 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
11.77 60.17 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
14.88 75.04 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 75.04 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
75.04 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
0.00 500.00 clock network delay (propagated)
|
||||
0.00 500.00 clock reconvergence pessimism
|
||||
500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-5.78 494.22 library setup time
|
||||
494.22 data required time
|
||||
---------------------------------------------------------
|
||||
494.22 data required time
|
||||
-75.04 data arrival time
|
||||
---------------------------------------------------------
|
||||
419.17 slack (MET)
|
||||
|
||||
|
||||
PASS: dmp_ceff_elmore with pi
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: r1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v in1 (in)
|
||||
0.00 1.00 v r1/D (DFFHQx4_ASAP7_75t_R)
|
||||
1.00 data arrival time
|
||||
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ r1/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
8.56 8.56 library hold time
|
||||
8.56 data required time
|
||||
---------------------------------------------------------
|
||||
8.56 data required time
|
||||
-1.00 data arrival time
|
||||
---------------------------------------------------------
|
||||
-7.56 slack (VIOLATED)
|
||||
|
||||
|
||||
PASS: min with pi
|
||||
--- Test 2: dmp_ceff_two_pole ---
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
48.40 48.40 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
11.77 60.17 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
14.88 75.04 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 75.04 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
75.04 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
0.00 500.00 clock network delay (propagated)
|
||||
0.00 500.00 clock reconvergence pessimism
|
||||
500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-5.78 494.22 library setup time
|
||||
494.22 data required time
|
||||
---------------------------------------------------------
|
||||
494.22 data required time
|
||||
-75.04 data arrival time
|
||||
---------------------------------------------------------
|
||||
419.17 slack (MET)
|
||||
|
||||
|
||||
PASS: dmp_ceff_two_pole with pi
|
||||
No paths found.
|
||||
PASS: in1->out two_pole
|
||||
No paths found.
|
||||
PASS: in2->out two_pole
|
||||
--- Test 3: extreme slew ---
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
45.32 45.32 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
11.76 57.08 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
14.88 71.96 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 71.96 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
71.96 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
0.00 500.00 clock network delay (propagated)
|
||||
0.00 500.00 clock reconvergence pessimism
|
||||
500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-7.11 492.89 library setup time
|
||||
492.89 data required time
|
||||
---------------------------------------------------------
|
||||
492.89 data required time
|
||||
-71.96 data arrival time
|
||||
---------------------------------------------------------
|
||||
420.94 slack (MET)
|
||||
|
||||
|
||||
PASS: very small slew 0.01
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
45.34 45.34 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
11.76 57.11 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
14.88 71.98 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 71.98 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
71.98 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
0.00 500.00 clock network delay (propagated)
|
||||
0.00 500.00 clock reconvergence pessimism
|
||||
500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-7.09 492.91 library setup time
|
||||
492.91 data required time
|
||||
---------------------------------------------------------
|
||||
492.91 data required time
|
||||
-71.98 data arrival time
|
||||
---------------------------------------------------------
|
||||
420.92 slack (MET)
|
||||
|
||||
|
||||
PASS: small slew 0.1
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
56.39 56.39 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
11.77 68.16 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
14.88 83.03 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 83.03 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
83.03 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
0.00 500.00 clock network delay (propagated)
|
||||
0.00 500.00 clock reconvergence pessimism
|
||||
500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-3.73 496.27 library setup time
|
||||
496.27 data required time
|
||||
---------------------------------------------------------
|
||||
496.27 data required time
|
||||
-83.03 data arrival time
|
||||
---------------------------------------------------------
|
||||
413.24 slack (MET)
|
||||
|
||||
|
||||
PASS: medium slew 50
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
84.45 84.45 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
11.77 96.22 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
14.88 111.09 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 111.09 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
111.09 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
0.00 500.00 clock network delay (propagated)
|
||||
0.00 500.00 clock reconvergence pessimism
|
||||
500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
2.57 502.57 library setup time
|
||||
502.57 data required time
|
||||
---------------------------------------------------------
|
||||
502.57 data required time
|
||||
-111.09 data arrival time
|
||||
---------------------------------------------------------
|
||||
391.48 slack (MET)
|
||||
|
||||
|
||||
PASS: large slew 500
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
161.62 161.62 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
11.78 173.40 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
14.88 188.28 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 188.28 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
188.28 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
0.00 500.00 clock network delay (propagated)
|
||||
0.00 500.00 clock reconvergence pessimism
|
||||
500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
18.08 518.08 library setup time
|
||||
518.08 data required time
|
||||
---------------------------------------------------------
|
||||
518.08 data required time
|
||||
-188.28 data arrival time
|
||||
---------------------------------------------------------
|
||||
329.80 slack (MET)
|
||||
|
||||
|
||||
PASS: very large slew 2000
|
||||
--- Test 4: tiny pi model ---
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
48.40 48.40 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
11.77 60.17 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
14.88 75.04 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 75.04 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
75.04 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
0.00 500.00 clock network delay (propagated)
|
||||
0.00 500.00 clock reconvergence pessimism
|
||||
500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-5.78 494.22 library setup time
|
||||
494.22 data required time
|
||||
---------------------------------------------------------
|
||||
494.22 data required time
|
||||
-75.04 data arrival time
|
||||
---------------------------------------------------------
|
||||
419.17 slack (MET)
|
||||
|
||||
|
||||
PASS: tiny pi model
|
||||
--- Test 5: large pi model ---
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
48.40 48.40 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
11.77 60.17 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
14.88 75.04 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 75.04 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
75.04 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
0.00 500.00 clock network delay (propagated)
|
||||
0.00 500.00 clock reconvergence pessimism
|
||||
500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-5.78 494.22 library setup time
|
||||
494.22 data required time
|
||||
---------------------------------------------------------
|
||||
494.22 data required time
|
||||
-75.04 data arrival time
|
||||
---------------------------------------------------------
|
||||
419.17 slack (MET)
|
||||
|
||||
|
||||
PASS: large pi model
|
||||
--- Test 6: report_dcalc ---
|
||||
Library: asap7sc7p5t_INVBUF_RVT_FF_nldm_211120
|
||||
Cell: BUFx2_ASAP7_75t_R
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Y ^
|
||||
P = 1.000000 V = 0.770000 T = 0.000000
|
||||
------- input_net_transition = 6.099100
|
||||
| total_output_net_capacitance = 0.565282
|
||||
| 1.440000 2.880000
|
||||
v --------------------
|
||||
5.000000 | 12.833000 15.145800
|
||||
10.000000 | 14.375000 16.681900
|
||||
Table value = 11.767857
|
||||
PVT scale factor = 1.000000
|
||||
Delay = 11.767857
|
||||
|
||||
------- input_net_transition = 6.099100
|
||||
| total_output_net_capacitance = 0.565282
|
||||
| 1.440000 2.880000
|
||||
v --------------------
|
||||
5.000000 | 7.612690 11.681800
|
||||
10.000000 | 7.631100 11.699600
|
||||
Table value = 5.145066
|
||||
PVT scale factor = 1.000000
|
||||
Slew = 5.145066
|
||||
Driver waveform slew = 5.145066
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Y v
|
||||
P = 1.000000 V = 0.770000 T = 0.000000
|
||||
------- input_net_transition = 5.283920
|
||||
| total_output_net_capacitance = 0.565708
|
||||
| 1.440000 2.880000
|
||||
v --------------------
|
||||
5.000000 | 13.395100 15.605499
|
||||
10.000000 | 15.032999 17.245100
|
||||
Table value = 12.146009
|
||||
PVT scale factor = 1.000000
|
||||
Delay = 12.146009
|
||||
|
||||
------- input_net_transition = 5.283920
|
||||
| total_output_net_capacitance = 0.565708
|
||||
| 1.440000 2.880000
|
||||
v --------------------
|
||||
5.000000 | 6.998250 10.429300
|
||||
10.000000 | 7.020140 10.451000
|
||||
Table value = 4.916347
|
||||
PVT scale factor = 1.000000
|
||||
Slew = 4.916347
|
||||
Driver waveform slew = 4.916347
|
||||
|
||||
.............................................
|
||||
|
||||
dmp_elmore u1: done
|
||||
Library: asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120
|
||||
Cell: AND2x2_ASAP7_75t_R
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Y ^
|
||||
P = 1.0000 V = 0.7000 T = 25.0000
|
||||
------- input_net_transition = 6.0255
|
||||
| total_output_net_capacitance = 0.6212
|
||||
| 1.4400 2.8800
|
||||
v --------------------
|
||||
5.0000 | 16.6604 19.5485
|
||||
10.0000 | 17.8038 20.6883
|
||||
Table value = 15.2532
|
||||
PVT scale factor = 1.0000
|
||||
Delay = 15.2532
|
||||
|
||||
------- input_net_transition = 6.0255
|
||||
| total_output_net_capacitance = 0.6212
|
||||
| 1.4400 2.8800
|
||||
v --------------------
|
||||
5.0000 | 9.6841 14.4815
|
||||
10.0000 | 9.6803 14.4760
|
||||
Table value = 6.9558
|
||||
PVT scale factor = 1.0000
|
||||
Slew = 6.9558
|
||||
Driver waveform slew = 6.9558
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Y v
|
||||
P = 1.0000 V = 0.7000 T = 25.0000
|
||||
------- input_net_transition = 5.2046
|
||||
| total_output_net_capacitance = 0.6192
|
||||
| 1.4400 2.8800
|
||||
v --------------------
|
||||
5.0000 | 16.7215 19.2327
|
||||
10.0000 | 18.4070 20.9322
|
||||
Table value = 15.3587
|
||||
PVT scale factor = 1.0000
|
||||
Delay = 15.3587
|
||||
|
||||
------- input_net_transition = 5.2046
|
||||
| total_output_net_capacitance = 0.6192
|
||||
| 1.4400 2.8800
|
||||
v --------------------
|
||||
5.0000 | 8.1900 11.9873
|
||||
10.0000 | 8.1957 11.9745
|
||||
Table value = 6.0261
|
||||
PVT scale factor = 1.0000
|
||||
Slew = 6.0261
|
||||
Driver waveform slew = 6.0261
|
||||
|
||||
.............................................
|
||||
|
||||
dmp_elmore u2 A: done
|
||||
Library: asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120
|
||||
Cell: AND2x2_ASAP7_75t_R
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
B ^ -> Y ^
|
||||
P = 1.00 V = 0.70 T = 25.00
|
||||
------- input_net_transition = 5.15
|
||||
| total_output_net_capacitance = 0.62
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
5.00 | 16.47 19.36
|
||||
10.00 | 18.11 20.96
|
||||
Table value = 14.88
|
||||
PVT scale factor = 1.00
|
||||
Delay = 14.88
|
||||
|
||||
------- input_net_transition = 5.15
|
||||
| total_output_net_capacitance = 0.62
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
5.00 | 9.69 14.48
|
||||
10.00 | 9.69 14.49
|
||||
Table value = 6.96
|
||||
PVT scale factor = 1.00
|
||||
Slew = 6.96
|
||||
Driver waveform slew = 6.96
|
||||
|
||||
.............................................
|
||||
|
||||
B v -> Y v
|
||||
P = 1.00 V = 0.70 T = 25.00
|
||||
------- input_net_transition = 4.92
|
||||
| total_output_net_capacitance = 0.62
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
5.00 | 15.82 18.32
|
||||
10.00 | 17.62 20.13
|
||||
Table value = 14.36
|
||||
PVT scale factor = 1.00
|
||||
Delay = 14.36
|
||||
|
||||
------- input_net_transition = 4.92
|
||||
| total_output_net_capacitance = 0.62
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
5.00 | 8.02 11.83
|
||||
10.00 | 8.02 11.83
|
||||
Table value = 5.84
|
||||
PVT scale factor = 1.00
|
||||
Slew = 5.84
|
||||
Driver waveform slew = 5.84
|
||||
|
||||
.............................................
|
||||
|
||||
dmp_elmore u2 B: done
|
||||
Library: asap7sc7p5t_SEQ_RVT_FF_nldm_220123
|
||||
Cell: DFFHQx4_ASAP7_75t_R
|
||||
Arc sense: non_unate
|
||||
Arc type: Reg Clk to Q
|
||||
CLK ^ -> Q ^
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- input_net_transition = 10.00
|
||||
| total_output_net_capacitance = 0.52
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
10.00 | 49.30 50.80
|
||||
20.00 | 52.04 53.53
|
||||
Table value = 48.34
|
||||
PVT scale factor = 1.00
|
||||
Delay = 48.34
|
||||
|
||||
------- input_net_transition = 10.00
|
||||
| total_output_net_capacitance = 0.52
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
10.00 | 7.26 9.21
|
||||
20.00 | 7.26 9.21
|
||||
Table value = 6.03
|
||||
PVT scale factor = 1.00
|
||||
Slew = 6.03
|
||||
Driver waveform slew = 6.03
|
||||
|
||||
.............................................
|
||||
|
||||
CLK ^ -> Q v
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- input_net_transition = 10.00
|
||||
| total_output_net_capacitance = 0.51
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
10.00 | 47.74 49.14
|
||||
20.00 | 50.34 51.75
|
||||
Table value = 46.84
|
||||
PVT scale factor = 1.00
|
||||
Delay = 46.84
|
||||
|
||||
------- input_net_transition = 10.00
|
||||
| total_output_net_capacitance = 0.51
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
10.00 | 6.31 8.01
|
||||
20.00 | 6.30 8.01
|
||||
Table value = 5.20
|
||||
PVT scale factor = 1.00
|
||||
Slew = 5.20
|
||||
Driver waveform slew = 5.20
|
||||
|
||||
.............................................
|
||||
|
||||
dmp_elmore r1: done
|
||||
Library: asap7sc7p5t_SEQ_RVT_FF_nldm_220123
|
||||
Cell: DFFHQx4_ASAP7_75t_R
|
||||
Arc sense: non_unate
|
||||
Arc type: Reg Clk to Q
|
||||
CLK ^ -> Q ^
|
||||
Pi model C2=0.00 Rpi=2.00 C1=0.00, Ceff=0.00
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- input_net_transition = 10.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
10.00 | 49.30 50.80
|
||||
20.00 | 52.04 53.53
|
||||
Table value = 47.80
|
||||
PVT scale factor = 1.00
|
||||
Delay = 47.80
|
||||
|
||||
------- input_net_transition = 10.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
10.00 | 7.26 9.21
|
||||
20.00 | 7.26 9.21
|
||||
Table value = 5.32
|
||||
PVT scale factor = 1.00
|
||||
Slew = 5.32
|
||||
Driver waveform slew = 5.32
|
||||
|
||||
.............................................
|
||||
|
||||
CLK ^ -> Q v
|
||||
Pi model C2=0.00 Rpi=2.00 C1=0.00, Ceff=0.00
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- input_net_transition = 10.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
10.00 | 47.74 49.14
|
||||
20.00 | 50.34 51.75
|
||||
Table value = 46.35
|
||||
PVT scale factor = 1.00
|
||||
Delay = 46.35
|
||||
|
||||
------- input_net_transition = 10.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
10.00 | 6.31 8.01
|
||||
20.00 | 6.30 8.01
|
||||
Table value = 4.60
|
||||
PVT scale factor = 1.00
|
||||
Slew = 4.60
|
||||
Driver waveform slew = 4.60
|
||||
|
||||
.............................................
|
||||
|
||||
dmp_elmore r3 min: done
|
||||
Library: asap7sc7p5t_INVBUF_RVT_FF_nldm_211120
|
||||
Cell: BUFx2_ASAP7_75t_R
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Y ^
|
||||
P = 1.000000 V = 0.770000 T = 0.000000
|
||||
------- input_net_transition = 6.099100
|
||||
| total_output_net_capacitance = 0.565282
|
||||
| 1.440000 2.880000
|
||||
v --------------------
|
||||
5.000000 | 12.833000 15.145800
|
||||
10.000000 | 14.375000 16.681900
|
||||
Table value = 11.767857
|
||||
PVT scale factor = 1.000000
|
||||
Delay = 11.767857
|
||||
|
||||
------- input_net_transition = 6.099100
|
||||
| total_output_net_capacitance = 0.565282
|
||||
| 1.440000 2.880000
|
||||
v --------------------
|
||||
5.000000 | 7.612690 11.681800
|
||||
10.000000 | 7.631100 11.699600
|
||||
Table value = 5.145066
|
||||
PVT scale factor = 1.000000
|
||||
Slew = 5.145066
|
||||
Driver waveform slew = 5.145066
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Y v
|
||||
P = 1.000000 V = 0.770000 T = 0.000000
|
||||
------- input_net_transition = 5.283920
|
||||
| total_output_net_capacitance = 0.565708
|
||||
| 1.440000 2.880000
|
||||
v --------------------
|
||||
5.000000 | 13.395100 15.605499
|
||||
10.000000 | 15.032999 17.245100
|
||||
Table value = 12.146009
|
||||
PVT scale factor = 1.000000
|
||||
Delay = 12.146009
|
||||
|
||||
------- input_net_transition = 5.283920
|
||||
| total_output_net_capacitance = 0.565708
|
||||
| 1.440000 2.880000
|
||||
v --------------------
|
||||
5.000000 | 6.998250 10.429300
|
||||
10.000000 | 7.020140 10.451000
|
||||
Table value = 4.916347
|
||||
PVT scale factor = 1.000000
|
||||
Slew = 4.916347
|
||||
Driver waveform slew = 4.916347
|
||||
|
||||
.............................................
|
||||
|
||||
dmp_two_pole u1: done
|
||||
Library: asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120
|
||||
Cell: AND2x2_ASAP7_75t_R
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Y ^
|
||||
P = 1.00 V = 0.70 T = 25.00
|
||||
------- input_net_transition = 6.03
|
||||
| total_output_net_capacitance = 0.62
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
5.00 | 16.66 19.55
|
||||
10.00 | 17.80 20.69
|
||||
Table value = 15.25
|
||||
PVT scale factor = 1.00
|
||||
Delay = 15.25
|
||||
|
||||
------- input_net_transition = 6.03
|
||||
| total_output_net_capacitance = 0.62
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
5.00 | 9.68 14.48
|
||||
10.00 | 9.68 14.48
|
||||
Table value = 6.96
|
||||
PVT scale factor = 1.00
|
||||
Slew = 6.96
|
||||
Driver waveform slew = 6.96
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Y v
|
||||
P = 1.00 V = 0.70 T = 25.00
|
||||
------- input_net_transition = 5.20
|
||||
| total_output_net_capacitance = 0.62
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
5.00 | 16.72 19.23
|
||||
10.00 | 18.41 20.93
|
||||
Table value = 15.36
|
||||
PVT scale factor = 1.00
|
||||
Delay = 15.36
|
||||
|
||||
------- input_net_transition = 5.20
|
||||
| total_output_net_capacitance = 0.62
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
5.00 | 8.19 11.99
|
||||
10.00 | 8.20 11.97
|
||||
Table value = 6.03
|
||||
PVT scale factor = 1.00
|
||||
Slew = 6.03
|
||||
Driver waveform slew = 6.03
|
||||
|
||||
.............................................
|
||||
|
||||
dmp_two_pole u2: done
|
||||
Library: asap7sc7p5t_SEQ_RVT_FF_nldm_220123
|
||||
Cell: DFFHQx4_ASAP7_75t_R
|
||||
Arc sense: non_unate
|
||||
Arc type: Reg Clk to Q
|
||||
CLK ^ -> Q ^
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- input_net_transition = 10.00
|
||||
| total_output_net_capacitance = 0.58
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
10.00 | 49.30 50.80
|
||||
20.00 | 52.04 53.53
|
||||
Table value = 48.40
|
||||
PVT scale factor = 1.00
|
||||
Delay = 48.40
|
||||
|
||||
------- input_net_transition = 10.00
|
||||
| total_output_net_capacitance = 0.58
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
10.00 | 7.26 9.21
|
||||
20.00 | 7.26 9.21
|
||||
Table value = 6.10
|
||||
PVT scale factor = 1.00
|
||||
Slew = 6.10
|
||||
Driver waveform slew = 6.10
|
||||
|
||||
.............................................
|
||||
|
||||
CLK ^ -> Q v
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- input_net_transition = 10.00
|
||||
| total_output_net_capacitance = 0.58
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
10.00 | 47.74 49.14
|
||||
20.00 | 50.34 51.75
|
||||
Table value = 46.90
|
||||
PVT scale factor = 1.00
|
||||
Delay = 46.90
|
||||
|
||||
------- input_net_transition = 10.00
|
||||
| total_output_net_capacitance = 0.58
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
10.00 | 6.31 8.01
|
||||
20.00 | 6.30 8.01
|
||||
Table value = 5.28
|
||||
PVT scale factor = 1.00
|
||||
Slew = 5.28
|
||||
Driver waveform slew = 5.28
|
||||
|
||||
.............................................
|
||||
|
||||
dmp_two_pole r2: done
|
||||
PASS: dcalc reports
|
||||
--- Test 7: SPEF override manual ---
|
||||
PASS: SPEF override
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
12.11 12.11 clock network delay (propagated)
|
||||
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
56.18 68.29 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
11.77 80.05 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
14.88 94.93 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 94.93 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
94.93 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
11.92 511.92 clock network delay (propagated)
|
||||
0.00 511.92 clock reconvergence pessimism
|
||||
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-3.87 508.05 library setup time
|
||||
508.05 data required time
|
||||
---------------------------------------------------------
|
||||
508.05 data required time
|
||||
-94.93 data arrival time
|
||||
---------------------------------------------------------
|
||||
413.12 slack (MET)
|
||||
|
||||
|
||||
PASS: dmp_ceff_elmore with SPEF
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
48.40 48.40 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
11.77 60.17 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
14.88 75.04 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 75.04 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
75.04 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
0.00 500.00 clock network delay (propagated)
|
||||
0.00 500.00 clock reconvergence pessimism
|
||||
500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-5.78 494.22 library setup time
|
||||
494.22 data required time
|
||||
---------------------------------------------------------
|
||||
494.22 data required time
|
||||
-75.04 data arrival time
|
||||
---------------------------------------------------------
|
||||
419.17 slack (MET)
|
||||
|
||||
|
||||
PASS: dmp_ceff_two_pole with SPEF
|
||||
--- Test 8: load variation ---
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
12.11 12.11 clock network delay (propagated)
|
||||
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
56.18 68.29 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
11.77 80.05 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
14.88 94.93 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 94.93 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
94.93 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
11.92 511.92 clock network delay (propagated)
|
||||
0.00 511.92 clock reconvergence pessimism
|
||||
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-3.87 508.05 library setup time
|
||||
508.05 data required time
|
||||
---------------------------------------------------------
|
||||
508.05 data required time
|
||||
-94.93 data arrival time
|
||||
---------------------------------------------------------
|
||||
413.12 slack (MET)
|
||||
|
||||
|
||||
dmp load=0.0001: done
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
12.11 12.11 clock network delay (propagated)
|
||||
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
56.18 68.29 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
11.77 80.05 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
14.88 94.93 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 94.93 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
94.93 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
11.92 511.92 clock network delay (propagated)
|
||||
0.00 511.92 clock reconvergence pessimism
|
||||
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-3.87 508.05 library setup time
|
||||
508.05 data required time
|
||||
---------------------------------------------------------
|
||||
508.05 data required time
|
||||
-94.93 data arrival time
|
||||
---------------------------------------------------------
|
||||
413.12 slack (MET)
|
||||
|
||||
|
||||
dmp load=0.001: done
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
12.11 12.11 clock network delay (propagated)
|
||||
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
56.18 68.29 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
11.77 80.05 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
14.88 94.93 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 94.93 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
94.93 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
11.92 511.92 clock network delay (propagated)
|
||||
0.00 511.92 clock reconvergence pessimism
|
||||
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-3.87 508.05 library setup time
|
||||
508.05 data required time
|
||||
---------------------------------------------------------
|
||||
508.05 data required time
|
||||
-94.93 data arrival time
|
||||
---------------------------------------------------------
|
||||
413.12 slack (MET)
|
||||
|
||||
|
||||
dmp load=0.01: done
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
12.11 12.11 clock network delay (propagated)
|
||||
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
56.18 68.29 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
11.77 80.05 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
14.88 94.93 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 94.93 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
94.93 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
11.92 511.92 clock network delay (propagated)
|
||||
0.00 511.92 clock reconvergence pessimism
|
||||
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-3.87 508.05 library setup time
|
||||
508.05 data required time
|
||||
---------------------------------------------------------
|
||||
508.05 data required time
|
||||
-94.93 data arrival time
|
||||
---------------------------------------------------------
|
||||
413.12 slack (MET)
|
||||
|
||||
|
||||
dmp load=0.05: done
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
12.11 12.11 clock network delay (propagated)
|
||||
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
56.18 68.29 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
11.77 80.05 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
14.88 94.93 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 94.93 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
94.93 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
11.92 511.92 clock network delay (propagated)
|
||||
0.00 511.92 clock reconvergence pessimism
|
||||
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-3.87 508.05 library setup time
|
||||
508.05 data required time
|
||||
---------------------------------------------------------
|
||||
508.05 data required time
|
||||
-94.93 data arrival time
|
||||
---------------------------------------------------------
|
||||
413.12 slack (MET)
|
||||
|
||||
|
||||
dmp load=0.1: done
|
||||
PASS: load variation
|
||||
--- Test 9: find_delays ---
|
||||
PASS: find_delays
|
||||
PASS: invalidate + find_delays
|
||||
ALL PASSED
|
||||
|
|
@ -0,0 +1,205 @@
|
|||
# Test DMP effective capacitance convergence edge cases with extreme
|
||||
# slew/load conditions and manual pi model parasitics.
|
||||
# Targets:
|
||||
# DmpCeff.cc: dmpCeffIter convergence paths, ceffPiElmore edge cases,
|
||||
# ceffPiPoleResidue, iteration count boundaries,
|
||||
# very small/large slew handling, zero capacitance paths
|
||||
# GraphDelayCalc.cc: findVertexDelay with manual parasitics
|
||||
# ArnoldiDelayCalc.cc: arnoldi with manual pi model
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
# Read ASAP7 libraries
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
|
||||
read_verilog ../../test/reg1_asap7.v
|
||||
link_design top
|
||||
|
||||
create_clock -name clk -period 500 {clk1 clk2 clk3}
|
||||
set_input_delay -clock clk 1 {in1 in2}
|
||||
set_output_delay -clock clk 1 [get_ports out]
|
||||
set_input_transition 10 {in1 in2 clk1 clk2 clk3}
|
||||
set_propagated_clock {clk1 clk2 clk3}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 1: Manual pi model + dmp_ceff_elmore
|
||||
# Exercises: dmpCeffIter with manually set pi model
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 1: manual pi + dmp_ceff_elmore ---"
|
||||
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
|
||||
# Set pi models on all driver pins
|
||||
catch {sta::set_pi_model u1/Y 0.005 10.0 0.003} msg
|
||||
catch {sta::set_elmore u1/Y u2/B 0.005} msg
|
||||
catch {sta::set_pi_model u2/Y 0.008 15.0 0.005} msg
|
||||
catch {sta::set_elmore u2/Y r3/D 0.008} msg
|
||||
catch {sta::set_pi_model r1/Q 0.002 5.0 0.001} msg
|
||||
catch {sta::set_elmore r1/Q u2/A 0.003} msg
|
||||
catch {sta::set_pi_model r2/Q 0.003 6.0 0.002} msg
|
||||
catch {sta::set_elmore r2/Q u1/A 0.004} msg
|
||||
catch {sta::set_pi_model r3/Q 0.001 2.0 0.001} msg
|
||||
catch {sta::set_elmore r3/Q out 0.002} msg
|
||||
puts "PASS: pi/elmore set"
|
||||
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_elmore with pi"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: min with pi"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 2: dmp_ceff_two_pole with manual pi
|
||||
# Exercises: ceffPiPoleResidue, two-pole iteration
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 2: dmp_ceff_two_pole ---"
|
||||
set_delay_calculator dmp_ceff_two_pole
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_two_pole with pi"
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out]
|
||||
puts "PASS: in1->out two_pole"
|
||||
|
||||
report_checks -from [get_ports in2] -to [get_ports out]
|
||||
puts "PASS: in2->out two_pole"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 3: Extreme slew values with DMP
|
||||
# Exercises: dmpCeffIter convergence boundaries
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 3: extreme slew ---"
|
||||
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
|
||||
# Very small slew
|
||||
set_input_transition 0.01 {in1 in2 clk1 clk2 clk3}
|
||||
report_checks
|
||||
puts "PASS: very small slew 0.01"
|
||||
|
||||
# Small slew
|
||||
set_input_transition 0.1 {in1 in2 clk1 clk2 clk3}
|
||||
report_checks
|
||||
puts "PASS: small slew 0.1"
|
||||
|
||||
# Medium slew
|
||||
set_input_transition 50 {in1 in2 clk1 clk2 clk3}
|
||||
report_checks
|
||||
puts "PASS: medium slew 50"
|
||||
|
||||
# Large slew
|
||||
set_input_transition 500 {in1 in2 clk1 clk2 clk3}
|
||||
report_checks
|
||||
puts "PASS: large slew 500"
|
||||
|
||||
# Very large slew
|
||||
set_input_transition 2000 {in1 in2 clk1 clk2 clk3}
|
||||
report_checks
|
||||
puts "PASS: very large slew 2000"
|
||||
|
||||
set_input_transition 10 {in1 in2 clk1 clk2 clk3}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 4: Very small pi model values (near-zero)
|
||||
# Exercises: DMP edge case with tiny parasitics
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 4: tiny pi model ---"
|
||||
|
||||
catch {sta::set_pi_model u1/Y 0.00001 0.1 0.00001} msg
|
||||
catch {sta::set_elmore u1/Y u2/B 0.00001} msg
|
||||
report_checks
|
||||
puts "PASS: tiny pi model"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 5: Large pi model values
|
||||
# Exercises: DMP with heavy parasitic loading
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 5: large pi model ---"
|
||||
|
||||
catch {sta::set_pi_model u1/Y 0.1 100.0 0.05} msg
|
||||
catch {sta::set_elmore u1/Y u2/B 0.5} msg
|
||||
catch {sta::set_pi_model u2/Y 0.15 150.0 0.08} msg
|
||||
catch {sta::set_elmore u2/Y r3/D 0.8} msg
|
||||
report_checks
|
||||
puts "PASS: large pi model"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 6: report_dcalc with dmp calculators
|
||||
# Exercises: DMP ceff iteration for specific arcs
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 6: report_dcalc ---"
|
||||
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max -digits 6} msg
|
||||
puts "dmp_elmore u1: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y] -max -digits 4} msg
|
||||
puts "dmp_elmore u2 A: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/B] -to [get_pins u2/Y] -max} msg
|
||||
puts "dmp_elmore u2 B: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -max} msg
|
||||
puts "dmp_elmore r1: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/Q] -min} msg
|
||||
puts "dmp_elmore r3 min: done"
|
||||
|
||||
set_delay_calculator dmp_ceff_two_pole
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max -digits 6} msg
|
||||
puts "dmp_two_pole u1: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y] -max} msg
|
||||
puts "dmp_two_pole u2: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins r2/CLK] -to [get_pins r2/Q] -max} msg
|
||||
puts "dmp_two_pole r2: done"
|
||||
|
||||
puts "PASS: dcalc reports"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 7: SPEF overriding manual, then DMP
|
||||
# Exercises: deleteReducedParasitics from manual->SPEF transition
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 7: SPEF override manual ---"
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
read_spef ../../test/reg1_asap7.spef
|
||||
puts "PASS: SPEF override"
|
||||
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_elmore with SPEF"
|
||||
|
||||
set_delay_calculator dmp_ceff_two_pole
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_two_pole with SPEF"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 8: Load variation with DMP
|
||||
# Exercises: loadPinCapacitanceChanged -> deleteReducedParasitics
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 8: load variation ---"
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
|
||||
foreach load_val {0.0001 0.001 0.01 0.05 0.1} {
|
||||
set_load $load_val [get_ports out]
|
||||
report_checks
|
||||
puts "dmp load=$load_val: done"
|
||||
}
|
||||
set_load 0 [get_ports out]
|
||||
puts "PASS: load variation"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 9: find_delays and invalidation
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 9: find_delays ---"
|
||||
sta::find_delays
|
||||
puts "PASS: find_delays"
|
||||
|
||||
sta::delays_invalid
|
||||
sta::find_delays
|
||||
puts "PASS: invalidate + find_delays"
|
||||
|
||||
puts "ALL PASSED"
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,236 @@
|
|||
# Test DmpCeff edge cases: extreme loads, extreme slews, overflow handling,
|
||||
# different convergence paths for dmpCeffElmore/TwoPole,
|
||||
# report_dcalc with digits, unit delay calculator baseline.
|
||||
# Targets: DmpCeff.cc dmpCeffElmore convergence edge cases,
|
||||
# dmpCeffTwoPole convergence edge cases,
|
||||
# dmpCeffDrvrPi, ceffPiElmore, ceffPiD,
|
||||
# dmpCeffIter, dmpCeffStep, dmpCeffD,
|
||||
# overflow handling paths, findRange edge cases,
|
||||
# DmpDelayCalc.cc gateDelay/gateSlew with edge case inputs,
|
||||
# GraphDelayCalc.cc findVertexDelay, findCheckEdgeDelays,
|
||||
# report_dcalc, netCaps, loadDelay
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog dcalc_test1.v
|
||||
link_design dcalc_test1
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 0 [get_ports in1]
|
||||
set_output_delay -clock clk 0 [get_ports out1]
|
||||
|
||||
############################################################
|
||||
# DmpCeff Elmore: extreme load conditions
|
||||
############################################################
|
||||
puts "--- dmp_ceff_elmore extreme loads ---"
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
|
||||
# Zero load
|
||||
set_load 0 [get_ports out1]
|
||||
set_input_transition 0.1 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "elmore zero load: $msg"
|
||||
puts "PASS: elmore zero load"
|
||||
|
||||
# Tiny load
|
||||
set_load 0.00001 [get_ports out1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "elmore tiny load: $msg"
|
||||
puts "PASS: elmore tiny load"
|
||||
|
||||
# Very large load (potential overflow path)
|
||||
set_load 5.0 [get_ports out1]
|
||||
set_input_transition 0.1 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "elmore large load: $msg"
|
||||
puts "PASS: elmore large load"
|
||||
|
||||
# Huge load
|
||||
set_load 10.0 [get_ports out1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "elmore huge load: $msg"
|
||||
puts "PASS: elmore huge load"
|
||||
|
||||
set_load 0 [get_ports out1]
|
||||
|
||||
############################################################
|
||||
# DmpCeff Elmore: extreme input transitions
|
||||
############################################################
|
||||
puts "--- dmp_ceff_elmore extreme transitions ---"
|
||||
|
||||
# Very fast transition
|
||||
set_input_transition 0.0001 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "elmore fast transition: $msg"
|
||||
puts "PASS: elmore fast transition"
|
||||
|
||||
# Very slow transition
|
||||
set_input_transition 5.0 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "elmore slow transition: $msg"
|
||||
puts "PASS: elmore slow transition"
|
||||
|
||||
# Extreme slow
|
||||
set_input_transition 10.0 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "elmore extreme slow: $msg"
|
||||
puts "PASS: elmore extreme slow"
|
||||
|
||||
set_input_transition 0.1 [get_ports in1]
|
||||
|
||||
############################################################
|
||||
# DmpCeff Elmore: combined extreme load + transition
|
||||
############################################################
|
||||
puts "--- dmp_ceff_elmore combined extremes ---"
|
||||
|
||||
set_load 5.0 [get_ports out1]
|
||||
set_input_transition 0.001 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: elmore extreme: large load + fast slew"
|
||||
|
||||
set_load 0.0001 [get_ports out1]
|
||||
set_input_transition 5.0 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: elmore extreme: small load + slow slew"
|
||||
|
||||
set_load 5.0 [get_ports out1]
|
||||
set_input_transition 5.0 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: elmore extreme: large load + slow slew"
|
||||
|
||||
set_load 0 [get_ports out1]
|
||||
set_input_transition 0.1 [get_ports in1]
|
||||
|
||||
############################################################
|
||||
# DmpCeff TwoPole: same extreme tests
|
||||
############################################################
|
||||
puts "--- dmp_ceff_two_pole extreme loads ---"
|
||||
set_delay_calculator dmp_ceff_two_pole
|
||||
|
||||
set_load 0 [get_ports out1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: two_pole zero load"
|
||||
|
||||
set_load 0.00001 [get_ports out1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: two_pole tiny load"
|
||||
|
||||
set_load 5.0 [get_ports out1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: two_pole large load"
|
||||
|
||||
set_load 10.0 [get_ports out1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: two_pole huge load"
|
||||
|
||||
set_load 0 [get_ports out1]
|
||||
|
||||
puts "--- dmp_ceff_two_pole extreme transitions ---"
|
||||
|
||||
set_input_transition 0.0001 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: two_pole fast transition"
|
||||
|
||||
set_input_transition 5.0 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: two_pole slow transition"
|
||||
|
||||
set_input_transition 0.1 [get_ports in1]
|
||||
|
||||
############################################################
|
||||
# report_dcalc for all arc types in design
|
||||
############################################################
|
||||
puts "--- report_dcalc all arcs ---"
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
set_load 0.01 [get_ports out1]
|
||||
|
||||
# BUF arcs (both rise and fall)
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "dcalc buf1 max: $msg"
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -min} msg
|
||||
puts "dcalc buf1 min: $msg"
|
||||
|
||||
# INV arcs
|
||||
catch {report_dcalc -from [get_pins inv1/A] -to [get_pins inv1/ZN] -max} msg
|
||||
puts "dcalc inv1 max: $msg"
|
||||
catch {report_dcalc -from [get_pins inv1/A] -to [get_pins inv1/ZN] -min} msg
|
||||
puts "dcalc inv1 min: $msg"
|
||||
|
||||
# DFF CK->Q arcs
|
||||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max} msg
|
||||
puts "dcalc reg1 CK->Q max: $msg"
|
||||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -min} msg
|
||||
puts "dcalc reg1 CK->Q min: $msg"
|
||||
|
||||
# DFF check arcs (setup/hold)
|
||||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D] -max} msg
|
||||
puts "dcalc reg1 setup: $msg"
|
||||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D] -min} msg
|
||||
puts "dcalc reg1 hold: $msg"
|
||||
|
||||
puts "PASS: report_dcalc all arcs"
|
||||
|
||||
############################################################
|
||||
# report_dcalc with various digit counts
|
||||
############################################################
|
||||
puts "--- report_dcalc digits ---"
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -digits 1} msg
|
||||
puts "1 digit: $msg"
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -digits 3} msg
|
||||
puts "3 digits: $msg"
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -digits 6} msg
|
||||
puts "6 digits: $msg"
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -digits 10} msg
|
||||
puts "10 digits: $msg"
|
||||
puts "PASS: dcalc digits"
|
||||
|
||||
############################################################
|
||||
# Sweep load/slew matrix for convergence coverage
|
||||
############################################################
|
||||
puts "--- load/slew sweep ---"
|
||||
foreach calc {dmp_ceff_elmore dmp_ceff_two_pole} {
|
||||
set_delay_calculator $calc
|
||||
foreach load {0.001 0.005 0.01 0.05 0.1 0.5 1.0 2.0} {
|
||||
foreach slew {0.01 0.05 0.1 0.5 1.0} {
|
||||
set_load $load [get_ports out1]
|
||||
set_input_transition $slew [get_ports in1]
|
||||
catch { report_checks -from [get_ports in1] -to [get_ports out1] > /dev/null }
|
||||
}
|
||||
}
|
||||
}
|
||||
set_load 0 [get_ports out1]
|
||||
set_input_transition 0.1 [get_ports in1]
|
||||
puts "PASS: load/slew sweep"
|
||||
|
||||
############################################################
|
||||
# Unit delay calculator
|
||||
############################################################
|
||||
puts "--- unit calculator ---"
|
||||
set_delay_calculator unit
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "unit dcalc buf1: $msg"
|
||||
puts "PASS: unit calculator"
|
||||
|
||||
############################################################
|
||||
# Lumped cap calculator
|
||||
############################################################
|
||||
puts "--- lumped_cap calculator ---"
|
||||
set_delay_calculator lumped_cap
|
||||
set_load 0.01 [get_ports out1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "lumped_cap dcalc buf1: $msg"
|
||||
set_load 0 [get_ports out1]
|
||||
puts "PASS: lumped_cap calculator"
|
||||
|
||||
# Restore default
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
|
||||
puts "ALL PASSED"
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,242 @@
|
|||
# Deep DMP effective capacitance testing with pi model parasitics,
|
||||
# various cell types, extreme conditions, and incremental updates.
|
||||
# Targets:
|
||||
# DmpCeff.cc: dmpCeffIter convergence, ceffPiElmore boundary cases,
|
||||
# ceffPiPoleResidue, iteration count limits, very small/large caps,
|
||||
# loadDelay, gateDelay with pi model
|
||||
# GraphDelayCalc.cc: findVertexDelay with manual parasitics,
|
||||
# seedInvalidDelays, delayCalcIncrementalCond
|
||||
# ArnoldiDelayCalc.cc: arnoldi with pi model parasitics
|
||||
# FindRoot.cc: root finding edge cases
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
############################################################
|
||||
# Read Nangate45 and setup search_test1 design
|
||||
############################################################
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog ../../search/test/search_test1.v
|
||||
link_design search_test1
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 1.0 [get_ports {in1 in2}]
|
||||
set_output_delay -clock clk 2.0 [get_ports out1]
|
||||
set_input_transition 0.1 [all_inputs]
|
||||
puts "PASS: design setup"
|
||||
|
||||
############################################################
|
||||
# Test 1: Manual pi model with dmp_ceff_elmore on all outputs
|
||||
############################################################
|
||||
puts "--- Test 1: pi models on all driver pins ---"
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
|
||||
# Set pi models on representative driver pins
|
||||
set all_cells [get_cells *]
|
||||
foreach cell_obj $all_cells {
|
||||
set cname [get_name $cell_obj]
|
||||
catch {
|
||||
set ref [get_property $cell_obj ref_name]
|
||||
# Try to set pi model on output pins
|
||||
set pins [get_pins $cname/*]
|
||||
foreach pin $pins {
|
||||
catch {
|
||||
set dir [get_property $pin direction]
|
||||
if {$dir == "output"} {
|
||||
catch {sta::set_pi_model [get_name $pin] 0.003 8.0 0.002}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: set pi models"
|
||||
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_elmore with pi"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: min with pi"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: max with pi"
|
||||
|
||||
############################################################
|
||||
# Test 2: Extreme pi model values (very small)
|
||||
############################################################
|
||||
puts "--- Test 2: tiny pi model ---"
|
||||
|
||||
foreach cell_obj [lrange $all_cells 0 4] {
|
||||
set cname [get_name $cell_obj]
|
||||
catch {
|
||||
set pins [get_pins $cname/*]
|
||||
foreach pin $pins {
|
||||
catch {
|
||||
set dir [get_property $pin direction]
|
||||
if {$dir == "output"} {
|
||||
catch {sta::set_pi_model [get_name $pin] 0.00001 0.01 0.000005}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
report_checks
|
||||
puts "PASS: tiny pi model"
|
||||
|
||||
############################################################
|
||||
# Test 3: Large pi model values
|
||||
############################################################
|
||||
puts "--- Test 3: large pi model ---"
|
||||
|
||||
foreach cell_obj [lrange $all_cells 0 4] {
|
||||
set cname [get_name $cell_obj]
|
||||
catch {
|
||||
set pins [get_pins $cname/*]
|
||||
foreach pin $pins {
|
||||
catch {
|
||||
set dir [get_property $pin direction]
|
||||
if {$dir == "output"} {
|
||||
catch {sta::set_pi_model [get_name $pin] 0.1 200.0 0.05}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
report_checks
|
||||
puts "PASS: large pi model"
|
||||
|
||||
############################################################
|
||||
# Test 4: dmp_ceff_two_pole with manual pi models
|
||||
############################################################
|
||||
puts "--- Test 4: dmp_ceff_two_pole ---"
|
||||
set_delay_calculator dmp_ceff_two_pole
|
||||
|
||||
report_checks
|
||||
puts "PASS: two_pole with pi"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: two_pole min"
|
||||
|
||||
# Vary slew
|
||||
foreach slew_val {0.01 0.1 0.5 1.0 5.0} {
|
||||
set_input_transition $slew_val [all_inputs]
|
||||
report_checks
|
||||
puts "two_pole slew=$slew_val: done"
|
||||
}
|
||||
set_input_transition 0.1 [all_inputs]
|
||||
puts "PASS: two_pole varying slew"
|
||||
|
||||
############################################################
|
||||
# Test 5: SPEF then manual pi model override
|
||||
############################################################
|
||||
puts "--- Test 5: SPEF then pi override ---"
|
||||
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
read_spef ../../search/test/search_test1.spef
|
||||
puts "PASS: read SPEF"
|
||||
|
||||
report_checks
|
||||
puts "PASS: dmp with SPEF"
|
||||
|
||||
# Override with manual pi models
|
||||
foreach cell_obj [lrange $all_cells 0 2] {
|
||||
set cname [get_name $cell_obj]
|
||||
catch {
|
||||
set pins [get_pins $cname/*]
|
||||
foreach pin $pins {
|
||||
catch {
|
||||
set dir [get_property $pin direction]
|
||||
if {$dir == "output"} {
|
||||
catch {sta::set_pi_model [get_name $pin] 0.005 10.0 0.003}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
report_checks
|
||||
puts "PASS: pi override after SPEF"
|
||||
|
||||
############################################################
|
||||
# Test 6: report_dcalc with dmp calculators and pi models
|
||||
############################################################
|
||||
puts "--- Test 6: report_dcalc ---"
|
||||
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
foreach cell_obj [lrange $all_cells 0 5] {
|
||||
set cname [get_name $cell_obj]
|
||||
catch {
|
||||
set pins [get_pins $cname/*]
|
||||
if {[llength $pins] >= 2} {
|
||||
set in_pin [lindex $pins 0]
|
||||
set out_pin [lindex $pins end]
|
||||
catch {report_dcalc -from $in_pin -to $out_pin -max}
|
||||
catch {report_dcalc -from $in_pin -to $out_pin -min}
|
||||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: dmp_ceff_elmore dcalc"
|
||||
|
||||
set_delay_calculator dmp_ceff_two_pole
|
||||
foreach cell_obj [lrange $all_cells 0 5] {
|
||||
set cname [get_name $cell_obj]
|
||||
catch {
|
||||
set pins [get_pins $cname/*]
|
||||
if {[llength $pins] >= 2} {
|
||||
set in_pin [lindex $pins 0]
|
||||
set out_pin [lindex $pins end]
|
||||
catch {report_dcalc -from $in_pin -to $out_pin -max -digits 6}
|
||||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: dmp_ceff_two_pole dcalc"
|
||||
|
||||
############################################################
|
||||
# Test 7: Incremental updates with pi models
|
||||
############################################################
|
||||
puts "--- Test 7: incremental ---"
|
||||
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
|
||||
# Load change triggers incremental
|
||||
set_load 0.001 [get_ports out1]
|
||||
report_checks
|
||||
puts "PASS: incremental load out1"
|
||||
|
||||
set_load 0.005 [get_ports out1]
|
||||
report_checks
|
||||
puts "PASS: incremental load out1 (2)"
|
||||
|
||||
# Slew change triggers incremental
|
||||
set_input_transition 0.5 [all_inputs]
|
||||
report_checks
|
||||
puts "PASS: incremental slew 0.5"
|
||||
|
||||
set_input_transition 2.0 [all_inputs]
|
||||
report_checks
|
||||
puts "PASS: incremental slew 2.0"
|
||||
|
||||
# Clock change triggers incremental
|
||||
create_clock -name clk -period 5 [get_ports clk]
|
||||
report_checks
|
||||
puts "PASS: incremental clock 5"
|
||||
|
||||
create_clock -name clk -period 2 [get_ports clk]
|
||||
report_checks
|
||||
puts "PASS: incremental clock 2"
|
||||
|
||||
############################################################
|
||||
# Test 8: find_delays and invalidation
|
||||
############################################################
|
||||
puts "--- Test 8: find_delays ---"
|
||||
sta::find_delays
|
||||
puts "PASS: find_delays"
|
||||
|
||||
sta::delays_invalid
|
||||
sta::find_delays
|
||||
puts "PASS: invalidate + find_delays"
|
||||
|
||||
# Multiple invalidation cycles
|
||||
for {set i 0} {$i < 3} {incr i} {
|
||||
sta::delays_invalid
|
||||
sta::find_delays
|
||||
}
|
||||
puts "PASS: multiple invalidation cycles"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
@ -0,0 +1,656 @@
|
|||
--- Testing unit delay calculator ---
|
||||
|
||||
No paths found.
|
||||
PASS: unit delay calculator report_checks
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
1.00 1.00 ^ reg1/Q (DFF_X1)
|
||||
0.00 1.00 ^ out1 (out)
|
||||
1.00 data arrival time
|
||||
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 0.00 output external delay
|
||||
0.00 data required time
|
||||
---------------------------------------------------------
|
||||
0.00 data required time
|
||||
-1.00 data arrival time
|
||||
---------------------------------------------------------
|
||||
1.00 slack (MET)
|
||||
|
||||
|
||||
PASS: unit min path
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in1 (in)
|
||||
1.00 1.00 v buf1/Z (BUF_X1)
|
||||
1.00 2.00 ^ inv1/ZN (INV_X1)
|
||||
0.00 2.00 ^ reg1/D (DFF_X1)
|
||||
2.00 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg1/CK (DFF_X1)
|
||||
-1.00 9.00 library setup time
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-2.00 data arrival time
|
||||
---------------------------------------------------------
|
||||
7.00 slack (MET)
|
||||
|
||||
|
||||
PASS: unit max path
|
||||
--- Testing lumped_cap delay calculator ---
|
||||
|
||||
No paths found.
|
||||
PASS: lumped_cap delay calculator report_checks
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ input external delay
|
||||
0.00 0.00 ^ in1 (in)
|
||||
0.02 0.02 ^ buf1/Z (BUF_X1)
|
||||
0.01 0.02 v inv1/ZN (INV_X1)
|
||||
0.00 0.02 v reg1/D (DFF_X1)
|
||||
0.02 data arrival time
|
||||
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg1/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
---------------------------------------------------------
|
||||
0.00 data required time
|
||||
-0.02 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.02 slack (MET)
|
||||
|
||||
|
||||
PASS: lumped_cap min path
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg1/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
0.00 10.00 output external delay
|
||||
10.00 data required time
|
||||
---------------------------------------------------------
|
||||
10.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.92 slack (MET)
|
||||
|
||||
|
||||
PASS: lumped_cap max path
|
||||
--- Testing report_dcalc ---
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: BUF_X1
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Z ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.70
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.02 0.02
|
||||
0.00 | 0.02 0.02
|
||||
Table value = 0.02
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.02
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.70
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.00 | 0.00 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Z v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.55
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.02 0.02
|
||||
0.00 | 0.02 0.03
|
||||
Table value = 0.02
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.02
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.55
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.00 | 0.00 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc from/to
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: BUF_X1
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Z ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.70
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.02 0.02
|
||||
0.00 | 0.02 0.02
|
||||
Table value = 0.02
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.02
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.70
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.00 | 0.00 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Z v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.55
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.02 0.02
|
||||
0.00 | 0.02 0.03
|
||||
Table value = 0.02
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.02
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.55
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.00 | 0.00 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc -min
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: BUF_X1
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Z ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.70
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.02 0.02
|
||||
0.00 | 0.02 0.02
|
||||
Table value = 0.02
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.02
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.70
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.00 | 0.00 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Z v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.55
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.02 0.02
|
||||
0.00 | 0.02 0.03
|
||||
Table value = 0.02
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.02
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.55
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.00 | 0.00 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc -max
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: INV_X1
|
||||
Arc sense: negative_unate
|
||||
Arc type: combinational
|
||||
A ^ -> ZN v
|
||||
P = 1.000000 V = 1.100000 T = 25.000000
|
||||
------- input_net_transition = 0.007053
|
||||
| total_output_net_capacitance = 1.062342
|
||||
| 0.365616 1.897810
|
||||
v --------------------
|
||||
0.004724 | 0.004611 0.006782
|
||||
0.017186 | 0.005658 0.009630
|
||||
Table value = 0.005947
|
||||
PVT scale factor = 1.000000
|
||||
Delay = 0.005947
|
||||
|
||||
------- input_net_transition = 0.007053
|
||||
| total_output_net_capacitance = 1.062342
|
||||
| 0.365616 1.897810
|
||||
v --------------------
|
||||
0.004724 | 0.002081 0.003192
|
||||
0.017186 | 0.004539 0.006195
|
||||
Table value = 0.003092
|
||||
PVT scale factor = 1.000000
|
||||
Slew = 0.003092
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> ZN ^
|
||||
P = 1.000000 V = 1.100000 T = 25.000000
|
||||
------- input_net_transition = 0.005514
|
||||
| total_output_net_capacitance = 1.140290
|
||||
| 0.365616 1.897810
|
||||
v --------------------
|
||||
0.004724 | 0.007266 0.011031
|
||||
0.017186 | 0.011759 0.017202
|
||||
Table value = 0.009509
|
||||
PVT scale factor = 1.000000
|
||||
Delay = 0.009509
|
||||
|
||||
------- input_net_transition = 0.005514
|
||||
| total_output_net_capacitance = 1.140290
|
||||
| 0.365616 1.897810
|
||||
v --------------------
|
||||
0.004724 | 0.003321 0.006755
|
||||
0.017186 | 0.006463 0.009176
|
||||
Table value = 0.005233
|
||||
PVT scale factor = 1.000000
|
||||
Slew = 0.005233
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc -digits
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: BUF_X1
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Z ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.70
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.02 0.02
|
||||
0.00 | 0.02 0.02
|
||||
Table value = 0.02
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.02
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.70
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.00 | 0.00 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Z v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.55
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.02 0.02
|
||||
0.00 | 0.02 0.03
|
||||
Table value = 0.02
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.02
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.55
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.00 | 0.00 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc -from only
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: INV_X1
|
||||
Arc sense: negative_unate
|
||||
Arc type: combinational
|
||||
A ^ -> ZN v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 1.06
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.02 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.01
|
||||
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 1.06
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.00
|
||||
0.02 | 0.00 0.01
|
||||
Table value = 0.00
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.00
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> ZN ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 1.14
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.02 | 0.01 0.02
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.01
|
||||
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 1.14
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.02 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc -to only
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: DFF_X1
|
||||
Arc type: setup
|
||||
CK ^ -> D ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- constrained_pin_transition = 0.01 (ideal clock)
|
||||
| related_pin_transition = 0.00
|
||||
| 0.00 0.04
|
||||
v --------------------
|
||||
0.00 | 0.03 0.02
|
||||
0.04 | 0.04 0.03
|
||||
Table value = 0.03
|
||||
PVT scale factor = 1.00
|
||||
Check = 0.03
|
||||
|
||||
.............................................
|
||||
|
||||
CK ^ -> D v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- constrained_pin_transition = 0.00 (ideal clock)
|
||||
| related_pin_transition = 0.00
|
||||
| 0.00 0.04
|
||||
v --------------------
|
||||
0.00 | 0.04 0.02
|
||||
0.04 | 0.05 0.04
|
||||
Table value = 0.04
|
||||
PVT scale factor = 1.00
|
||||
Check = 0.04
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc DFF check arcs
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: DFF_X1
|
||||
Arc sense: non_unate
|
||||
Arc type: Reg Clk to Q
|
||||
CK ^ -> Q ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.08 0.09
|
||||
0.00 | 0.08 0.09
|
||||
Table value = 0.08
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.08
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.00 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
CK ^ -> Q v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.08 0.08
|
||||
0.00 | 0.08 0.08
|
||||
Table value = 0.08
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.08
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.00 | 0.01 0.01
|
||||
Table value = 0.00
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.00
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc DFF CK->Q arc
|
||||
--- Testing set_load ---
|
||||
|
||||
No paths found.
|
||||
PASS: report_checks after set_load
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: DFF_X1
|
||||
Arc sense: non_unate
|
||||
Arc type: Reg Clk to Q
|
||||
CK ^ -> Q ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.05
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.08 0.09
|
||||
0.00 | 0.08 0.09
|
||||
Table value = 0.08
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.08
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.05
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.00 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
CK ^ -> Q v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.05
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.08 0.08
|
||||
0.00 | 0.08 0.08
|
||||
Table value = 0.08
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.08
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.05
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.00 | 0.01 0.01
|
||||
Table value = 0.00
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.00
|
||||
Driver waveform slew = 0.00
|
||||
|
||||
.............................................
|
||||
|
||||
PASS: report_dcalc after set_load
|
||||
--- Testing set_input_transition ---
|
||||
No paths found.
|
||||
PASS: report_checks after set_input_transition
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: BUF_X1
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Z ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.20
|
||||
| total_output_net_capacitance = 1.70
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.13 | 0.03 0.04
|
||||
0.20 | 0.03 0.03
|
||||
Table value = 0.03
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.03
|
||||
|
||||
------- input_net_transition = 0.20
|
||||
| total_output_net_capacitance = 1.70
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.13 | 0.01 0.01
|
||||
0.20 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Z v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.20
|
||||
| total_output_net_capacitance = 1.55
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.13 | 0.06 0.07
|
||||
0.20 | 0.08 0.08
|
||||
Table value = 0.08
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.08
|
||||
|
||||
------- input_net_transition = 0.20
|
||||
| total_output_net_capacitance = 1.55
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.13 | 0.01 0.01
|
||||
0.20 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
PASS: report_dcalc after set_input_transition
|
||||
--- Testing dmp_ceff_two_pole delay calculator ---
|
||||
|
||||
No paths found.
|
||||
PASS: dmp_ceff_two_pole report_checks
|
||||
ALL PASSED
|
||||
|
|
@ -0,0 +1,124 @@
|
|||
# Test different delay calculator engines
|
||||
# Exercises: set_delay_calculator, report_dcalc, set_load, set_input_transition
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog dcalc_test1.v
|
||||
link_design dcalc_test1
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 0 [get_ports in1]
|
||||
set_output_delay -clock clk 0 [get_ports out1]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Unit delay calculator
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Testing unit delay calculator ---"
|
||||
catch {set_delay_calculator unit} msg
|
||||
puts $msg
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: unit delay calculator report_checks"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: unit min path"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: unit max path"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Lumped cap delay calculator
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Testing lumped_cap delay calculator ---"
|
||||
catch {set_delay_calculator lumped_cap} msg
|
||||
puts $msg
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: lumped_cap delay calculator report_checks"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: lumped_cap min path"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: lumped_cap max path"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_dcalc with various options
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Testing report_dcalc ---"
|
||||
|
||||
# report_dcalc from/to
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc from/to"
|
||||
|
||||
# report_dcalc -min
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -min} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc -min"
|
||||
|
||||
# report_dcalc -max
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc -max"
|
||||
|
||||
# report_dcalc with -digits
|
||||
catch {report_dcalc -from [get_pins inv1/A] -to [get_pins inv1/ZN] -digits 6} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc -digits"
|
||||
|
||||
# report_dcalc from only
|
||||
catch {report_dcalc -from [get_pins buf1/A]} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc -from only"
|
||||
|
||||
# report_dcalc to only
|
||||
catch {report_dcalc -to [get_pins inv1/ZN]} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc -to only"
|
||||
|
||||
# report_dcalc for DFF setup/hold arcs
|
||||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D]} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc DFF check arcs"
|
||||
|
||||
# report_dcalc for DFF clock->Q arc
|
||||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q]} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc DFF CK->Q arc"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# set_load on output ports and recompute
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Testing set_load ---"
|
||||
set_load 0.05 [get_ports out1]
|
||||
|
||||
# Switch back to dmp_ceff_elmore (default) for load testing
|
||||
catch {set_delay_calculator dmp_ceff_elmore} msg
|
||||
puts $msg
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: report_checks after set_load"
|
||||
|
||||
report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max
|
||||
puts "PASS: report_dcalc after set_load"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# set_input_transition on inputs and recompute
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Testing set_input_transition ---"
|
||||
set_input_transition 0.2 [get_ports in1]
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: report_checks after set_input_transition"
|
||||
|
||||
report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max
|
||||
puts "PASS: report_dcalc after set_input_transition"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test dmp_ceff_two_pole calculator
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Testing dmp_ceff_two_pole delay calculator ---"
|
||||
catch {set_delay_calculator dmp_ceff_two_pole} msg
|
||||
puts $msg
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: dmp_ceff_two_pole report_checks"
|
||||
|
||||
puts "ALL PASSED"
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,220 @@
|
|||
# Test Arnoldi and Prima delay calculators with a larger design (GCD sky130hd)
|
||||
# having many more parasitic nodes, exercising deeper Arnoldi/Prima reduction
|
||||
# paths, higher-order matrix operations, and multi-driver net handling.
|
||||
# Targets:
|
||||
# ArnoldiDelayCalc.cc: gateDelay, gateDelaySlew, ar1_ceff_delay,
|
||||
# ra_rdelay_1, ra_get_r, ra_get_s, ra_solve_for_s, pr_solve1, pr_solve3,
|
||||
# delay_work_set_thresholds, reportGateDelay, finishDrvrPin,
|
||||
# reduceParasitic (arnoldi reduce from larger networks)
|
||||
# PrimaDelayCalc.cc: gateDelay, inputPortDelay, reduceParasitic,
|
||||
# primaReduceRc, stampR, stampC, prima matrix solve,
|
||||
# setPrimaReduceOrder, buildNodeMap, findParasitic
|
||||
# ArnoldiReduce.cc: arnoldi reduce matrix, arnoldi basis,
|
||||
# arnoldi iteration (more iterations for larger networks)
|
||||
# ReduceParasitics.cc: reduceToPiElmore, reduceToPiPoleResidue
|
||||
# GraphDelayCalc.cc: findVertexDelay with arnoldi/prima
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
############################################################
|
||||
# Read Sky130 library and GCD design
|
||||
############################################################
|
||||
read_liberty ../../test/sky130hd/sky130hd_tt.lib
|
||||
puts "PASS: read sky130hd"
|
||||
|
||||
read_verilog ../../examples/gcd_sky130hd.v
|
||||
link_design gcd
|
||||
puts "PASS: link gcd"
|
||||
|
||||
source ../../examples/gcd_sky130hd.sdc
|
||||
puts "PASS: SDC"
|
||||
|
||||
# Read SPEF parasitics (large: ~19k lines, many parasitic nodes)
|
||||
read_spef ../../examples/gcd_sky130hd.spef
|
||||
puts "PASS: read gcd SPEF"
|
||||
|
||||
############################################################
|
||||
# Baseline with default delay calculator (dmp_ceff_elmore)
|
||||
############################################################
|
||||
puts "--- baseline dmp_ceff_elmore ---"
|
||||
report_checks -endpoint_count 3
|
||||
puts "PASS: dmp baseline"
|
||||
|
||||
report_checks -path_delay min -endpoint_count 3
|
||||
puts "PASS: dmp min"
|
||||
|
||||
############################################################
|
||||
# Arnoldi with large GCD design
|
||||
# More parasitic nodes => deeper arnoldi reduction
|
||||
############################################################
|
||||
puts "--- arnoldi with gcd ---"
|
||||
set_delay_calculator arnoldi
|
||||
report_checks -endpoint_count 3
|
||||
puts "PASS: arnoldi max"
|
||||
|
||||
report_checks -path_delay min -endpoint_count 3
|
||||
puts "PASS: arnoldi min"
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: arnoldi fields"
|
||||
|
||||
report_checks -format full_clock
|
||||
puts "PASS: arnoldi full_clock"
|
||||
|
||||
# Arnoldi report_dcalc on various cells in the design
|
||||
puts "--- arnoldi report_dcalc ---"
|
||||
set cell_count 0
|
||||
foreach cell_obj [get_cells *] {
|
||||
set cname [get_name $cell_obj]
|
||||
catch {
|
||||
set pins [get_pins $cname/*]
|
||||
set in_pins {}
|
||||
set out_pins {}
|
||||
foreach p $pins {
|
||||
set dir [get_property $p direction]
|
||||
if {$dir == "input"} {
|
||||
lappend in_pins $p
|
||||
} elseif {$dir == "output"} {
|
||||
lappend out_pins $p
|
||||
}
|
||||
}
|
||||
if {[llength $in_pins] > 0 && [llength $out_pins] > 0} {
|
||||
catch {
|
||||
report_dcalc -from [lindex $in_pins 0] -to [lindex $out_pins 0] -max
|
||||
}
|
||||
incr cell_count
|
||||
if {$cell_count >= 30} break
|
||||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: arnoldi report_dcalc on $cell_count cells"
|
||||
|
||||
# Arnoldi with varying input slews
|
||||
puts "--- arnoldi varying slew ---"
|
||||
foreach slew_val {0.01 0.05 0.1 0.5 1.0} {
|
||||
set_input_transition $slew_val [all_inputs]
|
||||
report_checks -endpoint_count 1
|
||||
puts "arnoldi slew=$slew_val done"
|
||||
}
|
||||
set_input_transition 0.1 [all_inputs]
|
||||
puts "PASS: arnoldi varying slew"
|
||||
|
||||
# Arnoldi with varying output loads
|
||||
puts "--- arnoldi varying loads ---"
|
||||
foreach load_val {0.0001 0.001 0.01 0.05} {
|
||||
set_load $load_val [get_ports resp_msg*]
|
||||
report_checks -endpoint_count 1
|
||||
puts "arnoldi load=$load_val done"
|
||||
}
|
||||
set_load 0 [get_ports resp_msg*]
|
||||
puts "PASS: arnoldi varying loads"
|
||||
|
||||
############################################################
|
||||
# Prima with GCD design and varying reduce orders
|
||||
############################################################
|
||||
puts "--- prima with gcd ---"
|
||||
catch {set_delay_calculator prima} msg
|
||||
puts "set prima: $msg"
|
||||
|
||||
report_checks -endpoint_count 3
|
||||
puts "PASS: prima max"
|
||||
|
||||
report_checks -path_delay min -endpoint_count 3
|
||||
puts "PASS: prima min"
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: prima fields"
|
||||
|
||||
# Prima with varying reduce orders
|
||||
puts "--- prima reduce orders ---"
|
||||
foreach order {1 2 3 4 5} {
|
||||
catch {sta::set_prima_reduce_order $order} msg
|
||||
report_checks -endpoint_count 1
|
||||
puts "prima order=$order done"
|
||||
}
|
||||
# Reset to default
|
||||
catch {sta::set_prima_reduce_order 3}
|
||||
puts "PASS: prima reduce orders"
|
||||
|
||||
# Prima report_dcalc
|
||||
puts "--- prima report_dcalc ---"
|
||||
set cell_count 0
|
||||
foreach cell_obj [get_cells *] {
|
||||
set cname [get_name $cell_obj]
|
||||
catch {
|
||||
set pins [get_pins $cname/*]
|
||||
set in_pins {}
|
||||
set out_pins {}
|
||||
foreach p $pins {
|
||||
set dir [get_property $p direction]
|
||||
if {$dir == "input"} {
|
||||
lappend in_pins $p
|
||||
} elseif {$dir == "output"} {
|
||||
lappend out_pins $p
|
||||
}
|
||||
}
|
||||
if {[llength $in_pins] > 0 && [llength $out_pins] > 0} {
|
||||
catch {
|
||||
report_dcalc -from [lindex $in_pins 0] -to [lindex $out_pins 0] -max
|
||||
}
|
||||
incr cell_count
|
||||
if {$cell_count >= 30} break
|
||||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: prima report_dcalc on $cell_count cells"
|
||||
|
||||
# Prima varying slew
|
||||
puts "--- prima varying slew ---"
|
||||
foreach slew_val {0.01 0.1 0.5 2.0} {
|
||||
set_input_transition $slew_val [all_inputs]
|
||||
report_checks -endpoint_count 1
|
||||
puts "prima slew=$slew_val done"
|
||||
}
|
||||
set_input_transition 0.1 [all_inputs]
|
||||
puts "PASS: prima varying slew"
|
||||
|
||||
############################################################
|
||||
# Rapid switching between calculators
|
||||
# Exercises reinit, cleanup, and cache invalidation paths
|
||||
############################################################
|
||||
puts "--- rapid switching ---"
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
report_checks -endpoint_count 1
|
||||
puts "PASS: switch to dmp_ceff_elmore"
|
||||
|
||||
set_delay_calculator dmp_ceff_two_pole
|
||||
report_checks -endpoint_count 1
|
||||
puts "PASS: switch to dmp_ceff_two_pole"
|
||||
|
||||
set_delay_calculator lumped_cap
|
||||
report_checks -endpoint_count 1
|
||||
puts "PASS: switch to lumped_cap"
|
||||
|
||||
catch {set_delay_calculator arnoldi}
|
||||
report_checks -endpoint_count 1
|
||||
puts "PASS: switch back to arnoldi"
|
||||
|
||||
catch {set_delay_calculator prima}
|
||||
report_checks -endpoint_count 1
|
||||
puts "PASS: switch back to prima"
|
||||
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
report_checks -endpoint_count 1
|
||||
puts "PASS: final dmp_ceff_elmore"
|
||||
|
||||
############################################################
|
||||
# delay_calc_names and is_delay_calc_name
|
||||
############################################################
|
||||
puts "--- delay calc name queries ---"
|
||||
set names [sta::delay_calc_names]
|
||||
puts "delay calc names: $names"
|
||||
|
||||
foreach name {dmp_ceff_elmore dmp_ceff_two_pole lumped_cap arnoldi prima} {
|
||||
set result [sta::is_delay_calc_name $name]
|
||||
puts "is_delay_calc_name $name = $result"
|
||||
}
|
||||
set result [sta::is_delay_calc_name nonexistent_calc]
|
||||
puts "is_delay_calc_name nonexistent_calc = $result"
|
||||
puts "PASS: delay calc name queries"
|
||||
|
||||
puts "ALL PASSED"
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,276 @@
|
|||
# Test GraphDelayCalc with a larger design for coverage improvement.
|
||||
# Targets: GraphDelayCalc.cc (findDelays, seedRootSlews, seedInvalidDelays,
|
||||
# findVertexDelay, findCheckEdgeDelays, findLatchEdgeDelays,
|
||||
# findMultiDrvrNet, mergeMultiDrvrNets, loadDelay, netCaps,
|
||||
# hasMultiDrvrNet, reportCheckMultiDrvrNet, deleteVertexBefore,
|
||||
# levelChangedBefore, levelsChangedBefore, delayInvalid(pin/vertex),
|
||||
# setIncrementalDelayTolerance, incrementalDelayTolerance)
|
||||
# DmpCeff.cc (dmpCeffElmore, dmpCeffTwoPole paths with various loads)
|
||||
# NetCaps.cc (net capacitance queries, pinCapacitance, wireCap)
|
||||
# ArcDelayCalc.cc (arc delay for various gate types)
|
||||
# DelayCalcBase.cc (base class paths)
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog dcalc_multidriver_test.v
|
||||
link_design dcalc_multidriver_test
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 0 [get_ports {in1 in2 in3 in4 sel}]
|
||||
set_output_delay -clock clk 0 [get_ports {out1 out2 out3}]
|
||||
set_input_transition 0.1 [get_ports {in1 in2 in3 in4 sel clk}]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Baseline timing (exercises findDelays, seedRootSlews)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- baseline timing ---"
|
||||
report_checks
|
||||
puts "PASS: baseline report_checks"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: baseline min path"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: baseline max path"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multiple from/to path queries (exercises findVertexDelay for many paths)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- multiple path queries ---"
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: in1->out1"
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out2]
|
||||
puts "PASS: in1->out2"
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out3]
|
||||
puts "PASS: in1->out3"
|
||||
|
||||
report_checks -from [get_ports in2] -to [get_ports out1]
|
||||
puts "PASS: in2->out1"
|
||||
|
||||
report_checks -from [get_ports in2] -to [get_ports out2]
|
||||
puts "PASS: in2->out2"
|
||||
|
||||
report_checks -from [get_ports in3] -to [get_ports out1]
|
||||
puts "PASS: in3->out1"
|
||||
|
||||
report_checks -from [get_ports in4] -to [get_ports out2]
|
||||
puts "PASS: in4->out2"
|
||||
|
||||
report_checks -from [get_ports sel] -to [get_ports out1]
|
||||
puts "PASS: sel->out1"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Through pin queries (exercises more graph traversal)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- through pin queries ---"
|
||||
catch {report_checks -through [get_pins or1/ZN]} msg
|
||||
puts "PASS: through or1/ZN"
|
||||
|
||||
catch {report_checks -through [get_pins nand1/ZN]} msg
|
||||
puts "PASS: through nand1/ZN"
|
||||
|
||||
catch {report_checks -through [get_pins nor1/ZN]} msg
|
||||
puts "PASS: through nor1/ZN"
|
||||
|
||||
catch {report_checks -through [get_pins and1/ZN]} msg
|
||||
puts "PASS: through and1/ZN"
|
||||
|
||||
catch {report_checks -through [get_pins inv1/ZN]} msg
|
||||
puts "PASS: through inv1/ZN"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_dcalc for all arc types in design
|
||||
# Exercises: arc delay computation for BUF, INV, AND, OR, NAND, NOR
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_dcalc various gate types ---"
|
||||
|
||||
# BUF arcs
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "dcalc buf1 max: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -min} msg
|
||||
puts "dcalc buf1 min: $msg"
|
||||
|
||||
# INV arcs
|
||||
catch {report_dcalc -from [get_pins inv1/A] -to [get_pins inv1/ZN] -max} msg
|
||||
puts "dcalc inv1 max: $msg"
|
||||
|
||||
# AND arcs (both inputs)
|
||||
catch {report_dcalc -from [get_pins and1/A1] -to [get_pins and1/ZN] -max} msg
|
||||
puts "dcalc and1 A1->ZN max: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins and1/A2] -to [get_pins and1/ZN] -max} msg
|
||||
puts "dcalc and1 A2->ZN max: $msg"
|
||||
|
||||
# OR arcs
|
||||
catch {report_dcalc -from [get_pins or1/A1] -to [get_pins or1/ZN] -max} msg
|
||||
puts "dcalc or1 A1->ZN max: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins or1/A2] -to [get_pins or1/ZN] -max} msg
|
||||
puts "dcalc or1 A2->ZN max: $msg"
|
||||
|
||||
# NAND arcs
|
||||
catch {report_dcalc -from [get_pins nand1/A1] -to [get_pins nand1/ZN] -max} msg
|
||||
puts "dcalc nand1 A1->ZN max: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins nand1/A2] -to [get_pins nand1/ZN] -max} msg
|
||||
puts "dcalc nand1 A2->ZN max: $msg"
|
||||
|
||||
# NOR arcs
|
||||
catch {report_dcalc -from [get_pins nor1/A1] -to [get_pins nor1/ZN] -max} msg
|
||||
puts "dcalc nor1 A1->ZN max: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins nor1/A2] -to [get_pins nor1/ZN] -max} msg
|
||||
puts "dcalc nor1 A2->ZN max: $msg"
|
||||
|
||||
# DFF arcs
|
||||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max} msg
|
||||
puts "dcalc reg1 CK->Q max: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -min} msg
|
||||
puts "dcalc reg1 CK->Q min: $msg"
|
||||
|
||||
# DFF check arcs
|
||||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D] -max} msg
|
||||
puts "dcalc reg1 setup max: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D] -min} msg
|
||||
puts "dcalc reg1 hold min: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins reg2/CK] -to [get_pins reg2/Q] -max} msg
|
||||
puts "dcalc reg2 CK->Q max: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins reg2/CK] -to [get_pins reg2/D] -max} msg
|
||||
puts "dcalc reg2 setup max: $msg"
|
||||
|
||||
# report_dcalc with -digits
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -digits 2} msg
|
||||
puts "dcalc buf1 2 digits: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -digits 6} msg
|
||||
puts "dcalc buf1 6 digits: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -digits 10} msg
|
||||
puts "dcalc buf1 10 digits: $msg"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Incremental delay calculation: change constraints, recompute
|
||||
# Exercises: seedInvalidDelays, delayInvalid, incremental paths
|
||||
#---------------------------------------------------------------
|
||||
puts "--- incremental delay calculation ---"
|
||||
|
||||
# Change loads
|
||||
set_load 0.001 [get_ports out1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: incremental after set_load 0.001 on out1"
|
||||
|
||||
set_load 0.01 [get_ports out1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: incremental after set_load 0.01 on out1"
|
||||
|
||||
set_load 0.1 [get_ports out1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: incremental after set_load 0.1 on out1"
|
||||
|
||||
set_load 0.05 [get_ports out2]
|
||||
report_checks -from [get_ports in4] -to [get_ports out2]
|
||||
puts "PASS: incremental after set_load 0.05 on out2"
|
||||
|
||||
# Reset loads
|
||||
set_load 0 [get_ports out1]
|
||||
set_load 0 [get_ports out2]
|
||||
|
||||
# Change input transitions
|
||||
set_input_transition 0.01 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: incremental after slew 0.01 on in1"
|
||||
|
||||
set_input_transition 1.0 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: incremental after slew 1.0 on in1"
|
||||
|
||||
set_input_transition 0.1 [get_ports in1]
|
||||
|
||||
# Change clock period
|
||||
create_clock -name clk -period 5 [get_ports clk]
|
||||
report_checks
|
||||
puts "PASS: incremental after clock period change to 5"
|
||||
|
||||
# Change input/output delays
|
||||
set_input_delay -clock clk 1.0 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: incremental after input_delay 1.0"
|
||||
|
||||
set_output_delay -clock clk 2.0 [get_ports out1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: incremental after output_delay 2.0"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test various delay calculators on larger design
|
||||
# Exercises: calculator switching, copy/init paths
|
||||
#---------------------------------------------------------------
|
||||
puts "--- calculator switching ---"
|
||||
|
||||
set_delay_calculator unit
|
||||
report_checks
|
||||
puts "PASS: unit on large design"
|
||||
|
||||
set_delay_calculator lumped_cap
|
||||
report_checks
|
||||
puts "PASS: lumped_cap on large design"
|
||||
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_elmore on large design"
|
||||
|
||||
set_delay_calculator dmp_ceff_two_pole
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_two_pole on large design"
|
||||
|
||||
catch {set_delay_calculator ccs_ceff} msg
|
||||
report_checks
|
||||
puts "PASS: ccs_ceff on large design"
|
||||
|
||||
# Switch back to default
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_checks with various formatting options
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_checks formatting ---"
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: report_checks with all fields"
|
||||
|
||||
report_checks -format full_clock
|
||||
puts "PASS: report_checks full_clock"
|
||||
|
||||
report_checks -format full_clock_expanded
|
||||
puts "PASS: report_checks full_clock_expanded"
|
||||
|
||||
report_checks -endpoint_count 3
|
||||
puts "PASS: report_checks endpoint_count 3"
|
||||
|
||||
report_checks -group_count 5
|
||||
puts "PASS: report_checks group_count 5"
|
||||
|
||||
report_checks -unconstrained
|
||||
puts "PASS: report_checks unconstrained"
|
||||
|
||||
report_checks -sort_by_slack
|
||||
puts "PASS: report_checks sort_by_slack"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_check_types
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_check_types ---"
|
||||
report_check_types -max_delay -verbose
|
||||
puts "PASS: report_check_types max"
|
||||
|
||||
report_check_types -min_delay -verbose
|
||||
puts "PASS: report_check_types min"
|
||||
|
||||
report_check_types -max_delay -min_delay -verbose
|
||||
puts "PASS: report_check_types max+min"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
@ -0,0 +1,646 @@
|
|||
--- Test 1: baseline timing ---
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.81 slack (MET)
|
||||
|
||||
|
||||
PASS: baseline
|
||||
Startpoint: in4 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ input external delay
|
||||
0.00 0.00 ^ in4 (in)
|
||||
0.01 0.01 v nor1/ZN (NOR2_X1)
|
||||
0.00 0.01 v reg2/D (DFF_X1)
|
||||
0.01 data arrival time
|
||||
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg2/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
---------------------------------------------------------
|
||||
0.00 data required time
|
||||
-0.01 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.01 slack (MET)
|
||||
|
||||
|
||||
PASS: baseline min
|
||||
--- Test 2: incremental delay tolerance ---
|
||||
PASS: set tolerance 0.5
|
||||
No paths found.
|
||||
PASS: after slew change with large tolerance
|
||||
No paths found.
|
||||
PASS: after slew revert with large tolerance
|
||||
PASS: set tolerance 0.001
|
||||
No paths found.
|
||||
PASS: after slew change with small tolerance
|
||||
No paths found.
|
||||
PASS: after slew revert with small tolerance
|
||||
PASS: set tolerance 0.0
|
||||
--- Test 3: incremental load changes ---
|
||||
No paths found.
|
||||
load=0.0001: done
|
||||
No paths found.
|
||||
load=0.001: done
|
||||
No paths found.
|
||||
load=0.005: done
|
||||
No paths found.
|
||||
load=0.01: done
|
||||
No paths found.
|
||||
load=0.05: done
|
||||
No paths found.
|
||||
load=0.1: done
|
||||
No paths found.
|
||||
load=0.5: done
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.81 slack (MET)
|
||||
|
||||
|
||||
PASS: load on all outputs
|
||||
--- Test 4: incremental slew changes ---
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.02 0.02 v buf3/Z (BUF_X4)
|
||||
0.02 0.04 v and1/ZN (AND2_X1)
|
||||
0.05 0.10 v or1/ZN (OR2_X1)
|
||||
0.02 0.12 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.12 ^ reg2/D (DFF_X1)
|
||||
0.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-0.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.85 slack (MET)
|
||||
|
||||
|
||||
PASS: very fast slew
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.81 slack (MET)
|
||||
|
||||
|
||||
PASS: medium slew
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in1 (in)
|
||||
0.44 0.44 v buf1/Z (BUF_X1)
|
||||
0.03 0.47 ^ inv1/ZN (INV_X1)
|
||||
0.02 0.49 ^ buf2/Z (BUF_X2)
|
||||
0.03 0.52 ^ or1/ZN (OR2_X1)
|
||||
0.01 0.53 v nor1/ZN (NOR2_X1)
|
||||
0.00 0.53 v reg2/D (DFF_X1)
|
||||
0.53 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.12 9.88 library setup time
|
||||
9.88 data required time
|
||||
---------------------------------------------------------
|
||||
9.88 data required time
|
||||
-0.53 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.35 slack (MET)
|
||||
|
||||
|
||||
PASS: very slow slew
|
||||
Startpoint: in4 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in4 (in)
|
||||
0.24 0.24 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.24 ^ reg2/D (DFF_X1)
|
||||
0.24 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.05 9.95 library setup time
|
||||
9.95 data required time
|
||||
---------------------------------------------------------
|
||||
9.95 data required time
|
||||
-0.24 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.71 slack (MET)
|
||||
|
||||
|
||||
PASS: mixed slews
|
||||
--- Test 5: constraint changes ---
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
5.00 5.00 clock clk (rise edge)
|
||||
0.00 5.00 clock network delay (ideal)
|
||||
0.00 5.00 clock reconvergence pessimism
|
||||
5.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 4.96 library setup time
|
||||
4.96 data required time
|
||||
---------------------------------------------------------
|
||||
4.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
4.81 slack (MET)
|
||||
|
||||
|
||||
PASS: clock period 5
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
20.00 20.00 clock clk (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
19.81 slack (MET)
|
||||
|
||||
|
||||
PASS: clock period 20
|
||||
No paths found.
|
||||
PASS: input_delay 2.0
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg1/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
PASS: output_delay 3.0
|
||||
--- Test 6: network modification invalidation ---
|
||||
PASS: make_instance
|
||||
PASS: make_net
|
||||
PASS: connect_pin
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.81 slack (MET)
|
||||
|
||||
|
||||
PASS: report after add
|
||||
PASS: disconnect_pin
|
||||
PASS: cleanup
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.81 slack (MET)
|
||||
|
||||
|
||||
PASS: report after cleanup
|
||||
--- Test 7: replace cell ---
|
||||
No paths found.
|
||||
PASS: replace buf1 -> BUF_X4
|
||||
No paths found.
|
||||
PASS: replace buf1 -> BUF_X2
|
||||
No paths found.
|
||||
PASS: replace buf1 -> BUF_X1 (restore)
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.02 0.08 v and1/ZN (AND2_X2)
|
||||
0.05 0.12 v or1/ZN (OR2_X2)
|
||||
0.02 0.14 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.14 ^ reg2/D (DFF_X1)
|
||||
0.14 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.14 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.82 slack (MET)
|
||||
|
||||
|
||||
PASS: replace multiple cells
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.81 slack (MET)
|
||||
|
||||
|
||||
PASS: restore cells
|
||||
--- Test 8: tolerance with calculator switching ---
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.81 slack (MET)
|
||||
|
||||
|
||||
PASS: lumped_cap with tolerance
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.81 slack (MET)
|
||||
|
||||
|
||||
PASS: dmp_ceff_elmore with tolerance
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.81 slack (MET)
|
||||
|
||||
|
||||
PASS: dmp_ceff_two_pole with tolerance
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ input external delay
|
||||
0.00 0.00 ^ in1 (in)
|
||||
1.00 1.00 ^ buf1/Z (BUF_X1)
|
||||
1.00 2.00 v inv1/ZN (INV_X1)
|
||||
1.00 3.00 v buf2/Z (BUF_X2)
|
||||
1.00 4.00 v or1/ZN (OR2_X1)
|
||||
1.00 5.00 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 5.00 ^ reg1/D (DFF_X1)
|
||||
5.00 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg1/CK (DFF_X1)
|
||||
-1.00 9.00 library setup time
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-5.00 data arrival time
|
||||
---------------------------------------------------------
|
||||
4.00 slack (MET)
|
||||
|
||||
|
||||
PASS: unit with tolerance
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.81 slack (MET)
|
||||
|
||||
|
||||
PASS: final report
|
||||
ALL PASSED
|
||||
|
|
@ -0,0 +1,249 @@
|
|||
# Test GraphDelayCalc incremental delay tolerance and various invalidation paths.
|
||||
# Targets:
|
||||
# GraphDelayCalc.cc: setIncrementalDelayTolerance, incrementalDelayTolerance,
|
||||
# seedInvalidDelays, delayInvalid(pin), delayInvalid(vertex),
|
||||
# findDelays incremental paths, levelChangedBefore, levelsChangedBefore,
|
||||
# deleteVertexBefore, findVertexDelay, findCheckEdgeDelays,
|
||||
# findLatchEdgeDelays, netCaps, loadDelay, seedRootSlews
|
||||
# DmpCeff.cc: incremental recalculation with tolerance changes
|
||||
# NetCaps.cc: net capacitance recomputation after changes
|
||||
# ArcDelayCalc.cc: arc delay recalculation paths
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog dcalc_multidriver_test.v
|
||||
link_design dcalc_multidriver_test
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 0 [get_ports {in1 in2 in3 in4 sel}]
|
||||
set_output_delay -clock clk 0 [get_ports {out1 out2 out3}]
|
||||
set_input_transition 0.1 [get_ports {in1 in2 in3 in4 sel clk}]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 1: Baseline timing
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 1: baseline timing ---"
|
||||
report_checks
|
||||
puts "PASS: baseline"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: baseline min"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 2: Set incremental delay tolerance
|
||||
# Exercises: setIncrementalDelayTolerance, incrementalDelayTolerance
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 2: incremental delay tolerance ---"
|
||||
|
||||
# Set large tolerance (will suppress many incremental updates)
|
||||
sta::set_delay_calc_incremental_tolerance 0.5
|
||||
puts "PASS: set tolerance 0.5"
|
||||
|
||||
# Change input transition - large tolerance means less recalc
|
||||
set_input_transition 0.2 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: after slew change with large tolerance"
|
||||
|
||||
# Change back
|
||||
set_input_transition 0.1 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: after slew revert with large tolerance"
|
||||
|
||||
# Set small tolerance (will recompute more aggressively)
|
||||
sta::set_delay_calc_incremental_tolerance 0.001
|
||||
puts "PASS: set tolerance 0.001"
|
||||
|
||||
set_input_transition 0.2 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: after slew change with small tolerance"
|
||||
|
||||
set_input_transition 0.1 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: after slew revert with small tolerance"
|
||||
|
||||
# Zero tolerance
|
||||
sta::set_delay_calc_incremental_tolerance 0.0
|
||||
puts "PASS: set tolerance 0.0"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 3: Incremental updates with load changes
|
||||
# Exercises: seedInvalidDelays, delayInvalid, net cap recomputation
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 3: incremental load changes ---"
|
||||
|
||||
# Successively larger loads on out1
|
||||
foreach load_val {0.0001 0.001 0.005 0.01 0.05 0.1 0.5} {
|
||||
set_load $load_val [get_ports out1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "load=$load_val: done"
|
||||
}
|
||||
set_load 0 [get_ports out1]
|
||||
|
||||
# Loads on multiple outputs simultaneously
|
||||
set_load 0.01 [get_ports out1]
|
||||
set_load 0.01 [get_ports out2]
|
||||
set_load 0.01 [get_ports out3]
|
||||
report_checks
|
||||
puts "PASS: load on all outputs"
|
||||
|
||||
set_load 0 [get_ports out1]
|
||||
set_load 0 [get_ports out2]
|
||||
set_load 0 [get_ports out3]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 4: Incremental updates with transition changes
|
||||
# Exercises: seedRootSlews with varying slew values
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 4: incremental slew changes ---"
|
||||
|
||||
# Very fast transitions
|
||||
set_input_transition 0.001 [get_ports {in1 in2 in3 in4 sel}]
|
||||
report_checks
|
||||
puts "PASS: very fast slew"
|
||||
|
||||
# Medium transitions
|
||||
set_input_transition 0.1 [get_ports {in1 in2 in3 in4 sel}]
|
||||
report_checks
|
||||
puts "PASS: medium slew"
|
||||
|
||||
# Very slow transitions
|
||||
set_input_transition 2.0 [get_ports {in1 in2 in3 in4 sel}]
|
||||
report_checks
|
||||
puts "PASS: very slow slew"
|
||||
|
||||
# Different slews on different inputs
|
||||
set_input_transition 0.01 [get_ports in1]
|
||||
set_input_transition 0.5 [get_ports in2]
|
||||
set_input_transition 0.001 [get_ports in3]
|
||||
set_input_transition 1.0 [get_ports in4]
|
||||
set_input_transition 0.1 [get_ports sel]
|
||||
report_checks
|
||||
puts "PASS: mixed slews"
|
||||
|
||||
# Restore
|
||||
set_input_transition 0.1 [get_ports {in1 in2 in3 in4 sel clk}]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 5: Incremental timing constraint changes
|
||||
# Exercises: findDelays with constraint invalidation
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 5: constraint changes ---"
|
||||
|
||||
# Change clock period
|
||||
create_clock -name clk -period 5 [get_ports clk]
|
||||
report_checks
|
||||
puts "PASS: clock period 5"
|
||||
|
||||
create_clock -name clk -period 20 [get_ports clk]
|
||||
report_checks
|
||||
puts "PASS: clock period 20"
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
|
||||
# Change input delays
|
||||
set_input_delay -clock clk 2.0 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: input_delay 2.0"
|
||||
|
||||
set_input_delay -clock clk 0.0 [get_ports in1]
|
||||
|
||||
# Change output delays
|
||||
set_output_delay -clock clk 3.0 [get_ports out1]
|
||||
report_checks -to [get_ports out1]
|
||||
puts "PASS: output_delay 3.0"
|
||||
|
||||
set_output_delay -clock clk 0.0 [get_ports out1]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 6: Network modification triggers delay invalidation
|
||||
# Exercises: makeInstance, connectPin, disconnectPin => delayInvalid
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 6: network modification invalidation ---"
|
||||
|
||||
# Add new instance
|
||||
set new_inst [make_instance extra_buf NangateOpenCellLibrary/BUF_X4]
|
||||
puts "PASS: make_instance"
|
||||
|
||||
set new_net [make_net extra_net]
|
||||
puts "PASS: make_net"
|
||||
|
||||
connect_pin extra_net extra_buf/A
|
||||
puts "PASS: connect_pin"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report after add"
|
||||
|
||||
# Disconnect and delete
|
||||
disconnect_pin extra_net extra_buf/A
|
||||
puts "PASS: disconnect_pin"
|
||||
|
||||
delete_instance extra_buf
|
||||
delete_net extra_net
|
||||
puts "PASS: cleanup"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report after cleanup"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 7: Replace cell triggers delay recalc
|
||||
# Exercises: replaceCell => incremental delay update
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 7: replace cell ---"
|
||||
|
||||
# Replace buf1 with larger buffer
|
||||
replace_cell buf1 NangateOpenCellLibrary/BUF_X4
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: replace buf1 -> BUF_X4"
|
||||
|
||||
replace_cell buf1 NangateOpenCellLibrary/BUF_X2
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: replace buf1 -> BUF_X2"
|
||||
|
||||
replace_cell buf1 NangateOpenCellLibrary/BUF_X1
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: replace buf1 -> BUF_X1 (restore)"
|
||||
|
||||
# Replace multiple cells
|
||||
replace_cell and1 NangateOpenCellLibrary/AND2_X2
|
||||
replace_cell or1 NangateOpenCellLibrary/OR2_X2
|
||||
report_checks
|
||||
puts "PASS: replace multiple cells"
|
||||
|
||||
replace_cell and1 NangateOpenCellLibrary/AND2_X1
|
||||
replace_cell or1 NangateOpenCellLibrary/OR2_X1
|
||||
report_checks
|
||||
puts "PASS: restore cells"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 8: Tolerance with calculator switching
|
||||
# Exercises: setIncrementalDelayTolerance persists across calc changes
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 8: tolerance with calculator switching ---"
|
||||
|
||||
sta::set_delay_calc_incremental_tolerance 0.1
|
||||
|
||||
set_delay_calculator lumped_cap
|
||||
report_checks
|
||||
puts "PASS: lumped_cap with tolerance"
|
||||
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_elmore with tolerance"
|
||||
|
||||
set_delay_calculator dmp_ceff_two_pole
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_two_pole with tolerance"
|
||||
|
||||
set_delay_calculator unit
|
||||
report_checks
|
||||
puts "PASS: unit with tolerance"
|
||||
|
||||
# Restore
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
sta::set_delay_calc_incremental_tolerance 0.0
|
||||
|
||||
report_checks
|
||||
puts "PASS: final report"
|
||||
|
||||
puts "ALL PASSED"
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,260 @@
|
|||
# Test multiple delay calc engines with SPEF parasitics and prima reduce order.
|
||||
# Targets:
|
||||
# PrimaDelayCalc.cc: setPrimaReduceOrder, primaDelay, primaReduceRc,
|
||||
# prima2, prima3, primaResStamp, primaCapStamp, primaPostReduction
|
||||
# ArnoldiDelayCalc.cc: arnoldiDelay, arnoldiReduceRc, arnoldi2, arnoldi3,
|
||||
# arnoldiExpand, loadDelay, gateDelay, gateSlew
|
||||
# ArnoldiReduce.cc: arnoldi reduce matrix, arnoldi iteration
|
||||
# GraphDelayCalc.cc: findDelays with parasitic calc engine changes,
|
||||
# findVertexDelay with different parasitic reduction
|
||||
# DmpCeff.cc: ceffPiElmore, dmpCeffIter with SPEF parasitics
|
||||
# DelayCalc.i: delay_calc_names, is_delay_calc_name, set_prima_reduce_order
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
# Read ASAP7 libraries
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
|
||||
read_verilog ../../test/reg1_asap7.v
|
||||
link_design top
|
||||
|
||||
create_clock -name clk -period 500 {clk1 clk2 clk3}
|
||||
set_input_delay -clock clk 1 {in1 in2}
|
||||
set_output_delay -clock clk 1 [get_ports out]
|
||||
set_input_transition 10 {in1 in2 clk1 clk2 clk3}
|
||||
set_propagated_clock {clk1 clk2 clk3}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 1: Enumerate delay calculator names
|
||||
# Exercises: delayCalcNames, isDelayCalcName
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 1: delay calc names ---"
|
||||
|
||||
set calc_names [sta::delay_calc_names]
|
||||
puts "delay calc names: $calc_names"
|
||||
|
||||
foreach name {lumped_cap dmp_ceff_elmore dmp_ceff_two_pole arnoldi prima unit} {
|
||||
set valid [sta::is_delay_calc_name $name]
|
||||
puts "is_delay_calc_name $name: $valid"
|
||||
}
|
||||
|
||||
# Invalid name
|
||||
set invalid [sta::is_delay_calc_name "nonexistent_calc"]
|
||||
puts "is_delay_calc_name nonexistent: $invalid"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 2: Read SPEF and run with default calculator
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 2: SPEF with default calc ---"
|
||||
read_spef ../../test/reg1_asap7.spef
|
||||
puts "PASS: read_spef"
|
||||
|
||||
report_checks
|
||||
puts "PASS: default calc with SPEF"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: default min with SPEF"
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out]
|
||||
puts "PASS: in1->out with SPEF"
|
||||
|
||||
report_checks -from [get_ports in2] -to [get_ports out]
|
||||
puts "PASS: in2->out with SPEF"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 3: Prima with varying reduce order
|
||||
# Exercises: setPrimaReduceOrder, prima reduction order paths
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 3: prima with reduce order ---"
|
||||
catch {set_delay_calculator prima} msg
|
||||
puts "set prima: $msg"
|
||||
|
||||
# Default prima
|
||||
report_checks
|
||||
puts "PASS: prima default order"
|
||||
|
||||
# Prima reduce order 1 (minimal)
|
||||
catch {sta::set_prima_reduce_order 1} msg
|
||||
puts "set_prima_reduce_order 1: $msg"
|
||||
report_checks
|
||||
puts "PASS: prima order 1"
|
||||
|
||||
# Prima reduce order 2
|
||||
catch {sta::set_prima_reduce_order 2} msg
|
||||
puts "set_prima_reduce_order 2: $msg"
|
||||
report_checks
|
||||
puts "PASS: prima order 2"
|
||||
|
||||
# Prima reduce order 3
|
||||
catch {sta::set_prima_reduce_order 3} msg
|
||||
puts "set_prima_reduce_order 3: $msg"
|
||||
report_checks
|
||||
puts "PASS: prima order 3"
|
||||
|
||||
# Prima reduce order 5 (higher order)
|
||||
catch {sta::set_prima_reduce_order 5} msg
|
||||
puts "set_prima_reduce_order 5: $msg"
|
||||
report_checks
|
||||
puts "PASS: prima order 5"
|
||||
|
||||
# report_dcalc with different orders
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max} msg
|
||||
puts "prima dcalc u1 order=5: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y] -max} msg
|
||||
puts "prima dcalc u2 order=5: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -max} msg
|
||||
puts "prima dcalc r1 order=5: done"
|
||||
|
||||
# Switch back to lower order
|
||||
catch {sta::set_prima_reduce_order 2} msg
|
||||
report_checks
|
||||
puts "PASS: prima order back to 2"
|
||||
|
||||
# report_dcalc at order 2
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max} msg
|
||||
puts "prima dcalc u1 order=2: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/Q] -max} msg
|
||||
puts "prima dcalc r3 order=2: done"
|
||||
|
||||
# Various slew values with prima
|
||||
foreach slew_val {1 10 50 100 200} {
|
||||
set_input_transition $slew_val {in1 in2 clk1 clk2 clk3}
|
||||
report_checks
|
||||
puts "prima slew=$slew_val: done"
|
||||
}
|
||||
set_input_transition 10 {in1 in2 clk1 clk2 clk3}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 4: Arnoldi with SPEF
|
||||
# Exercises: arnoldiDelay, arnoldiReduceRc, arnoldi expansion
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 4: arnoldi with SPEF ---"
|
||||
catch {set_delay_calculator arnoldi} msg
|
||||
puts "set arnoldi: $msg"
|
||||
|
||||
report_checks
|
||||
puts "PASS: arnoldi with SPEF"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: arnoldi min"
|
||||
|
||||
# Various slew values with arnoldi
|
||||
foreach slew_val {1 10 50 100} {
|
||||
set_input_transition $slew_val {in1 in2 clk1 clk2 clk3}
|
||||
report_checks
|
||||
puts "arnoldi slew=$slew_val: done"
|
||||
}
|
||||
set_input_transition 10 {in1 in2 clk1 clk2 clk3}
|
||||
|
||||
# Various load values with arnoldi
|
||||
foreach load_val {0.0001 0.001 0.01 0.05} {
|
||||
set_load $load_val [get_ports out]
|
||||
report_checks
|
||||
puts "arnoldi load=$load_val: done"
|
||||
}
|
||||
set_load 0 [get_ports out]
|
||||
|
||||
# report_dcalc with arnoldi
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max} msg
|
||||
puts "arnoldi dcalc u1: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y] -max} msg
|
||||
puts "arnoldi dcalc u2 A: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/B] -to [get_pins u2/Y] -max} msg
|
||||
puts "arnoldi dcalc u2 B: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -max} msg
|
||||
puts "arnoldi dcalc r1: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins r2/CLK] -to [get_pins r2/Q] -min} msg
|
||||
puts "arnoldi dcalc r2 min: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/Q] -max} msg
|
||||
puts "arnoldi dcalc r3: done"
|
||||
|
||||
# DFF check arcs
|
||||
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/D] -max} msg
|
||||
puts "arnoldi r1 setup: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/D] -min} msg
|
||||
puts "arnoldi r1 hold: done"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 5: Rapid engine switching with SPEF (reinit paths)
|
||||
# Exercises: calculator copy/reinit during switching
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 5: rapid engine switching ---"
|
||||
|
||||
set_delay_calculator lumped_cap
|
||||
report_checks
|
||||
puts "PASS: lumped_cap"
|
||||
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_elmore"
|
||||
|
||||
set_delay_calculator dmp_ceff_two_pole
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_two_pole"
|
||||
|
||||
catch {set_delay_calculator prima} msg
|
||||
report_checks
|
||||
puts "PASS: prima"
|
||||
|
||||
catch {set_delay_calculator arnoldi} msg
|
||||
report_checks
|
||||
puts "PASS: arnoldi"
|
||||
|
||||
set_delay_calculator unit
|
||||
report_checks
|
||||
puts "PASS: unit"
|
||||
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
report_checks
|
||||
puts "PASS: back to dmp_ceff_elmore"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 6: find_delays explicit call
|
||||
# Exercises: findDelays direct path
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 6: find_delays ---"
|
||||
|
||||
sta::find_delays
|
||||
puts "PASS: find_delays"
|
||||
|
||||
sta::delays_invalid
|
||||
sta::find_delays
|
||||
puts "PASS: delays_invalid + find_delays"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 7: Detailed report_checks with various formats after SPEF
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 7: report formats ---"
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: all fields"
|
||||
|
||||
report_checks -format full_clock
|
||||
puts "PASS: full_clock"
|
||||
|
||||
report_checks -format full_clock_expanded
|
||||
puts "PASS: full_clock_expanded"
|
||||
|
||||
report_checks -endpoint_count 3
|
||||
puts "PASS: endpoint_count"
|
||||
|
||||
report_checks -group_count 2
|
||||
puts "PASS: group_count"
|
||||
|
||||
report_checks -digits 6
|
||||
puts "PASS: 6 digits"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
// Design with multi-driver nets and various gate types
|
||||
// for testing GraphDelayCalc multi-driver net handling
|
||||
module dcalc_multidriver_test (clk, in1, in2, in3, in4, sel, out1, out2, out3);
|
||||
input clk, in1, in2, in3, in4, sel;
|
||||
output out1, out2, out3;
|
||||
wire n1, n2, n3, n4, n5, n6, n7, n8, n9;
|
||||
|
||||
// Chain path 1
|
||||
BUF_X1 buf1 (.A(in1), .Z(n1));
|
||||
INV_X1 inv1 (.A(n1), .ZN(n2));
|
||||
BUF_X2 buf2 (.A(n2), .Z(n3));
|
||||
|
||||
// Chain path 2
|
||||
BUF_X4 buf3 (.A(in2), .Z(n4));
|
||||
AND2_X1 and1 (.A1(n4), .A2(in3), .ZN(n5));
|
||||
|
||||
// Merging paths
|
||||
OR2_X1 or1 (.A1(n3), .A2(n5), .ZN(n6));
|
||||
NAND2_X1 nand1 (.A1(n6), .A2(sel), .ZN(n7));
|
||||
NOR2_X1 nor1 (.A1(n6), .A2(in4), .ZN(n8));
|
||||
|
||||
// Output stage with registers
|
||||
DFF_X1 reg1 (.D(n7), .CK(clk), .Q(out1));
|
||||
DFF_X1 reg2 (.D(n8), .CK(clk), .Q(out2));
|
||||
BUF_X1 buf_out (.A(n6), .Z(out3));
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,153 @@
|
|||
# Test prima delay calculator with SPEF parasitics
|
||||
# Targets: PrimaDelayCalc.cc (61.7% coverage, 603 lines)
|
||||
# Also exercises ArnoldiReduce.cc and ArnoldiDelayCalc.cc paths
|
||||
|
||||
# Read ASAP7 libraries
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
|
||||
read_verilog ../../test/reg1_asap7.v
|
||||
link_design top
|
||||
|
||||
create_clock -name clk -period 500 {clk1 clk2 clk3}
|
||||
set_input_delay -clock clk 1 {in1 in2}
|
||||
set_output_delay -clock clk 1 [get_ports out]
|
||||
set_input_transition 10 {in1 in2 clk1 clk2 clk3}
|
||||
set_propagated_clock {clk1 clk2 clk3}
|
||||
|
||||
# Read SPEF parasitics
|
||||
puts "--- Reading SPEF ---"
|
||||
read_spef ../../test/reg1_asap7.spef
|
||||
puts "PASS: read_spef completed"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test prima delay calculator
|
||||
#---------------------------------------------------------------
|
||||
puts "--- prima delay calculator ---"
|
||||
catch {set_delay_calculator prima} msg
|
||||
puts "set_delay_calculator prima: $msg"
|
||||
|
||||
report_checks
|
||||
puts "PASS: prima report_checks"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: prima min path"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: prima max path"
|
||||
|
||||
report_checks -fields {slew cap input_pins}
|
||||
puts "PASS: prima with fields"
|
||||
|
||||
report_checks -format full_clock
|
||||
puts "PASS: prima full_clock"
|
||||
|
||||
# report_dcalc with prima
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y]} msg
|
||||
puts "prima dcalc u1 A->Y: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y]} msg
|
||||
puts "prima dcalc u2 A->Y: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/B] -to [get_pins u2/Y]} msg
|
||||
puts "prima dcalc u2 B->Y: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q]} msg
|
||||
puts "prima dcalc r1 CLK->Q: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/Q] -max} msg
|
||||
puts "prima dcalc r3 CLK->Q max: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/D] -max} msg
|
||||
puts "prima dcalc r3 setup: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/D] -min} msg
|
||||
puts "prima dcalc r3 hold: $msg"
|
||||
|
||||
# Report from different paths
|
||||
report_checks -from [get_ports in1] -to [get_ports out]
|
||||
puts "PASS: prima in1->out"
|
||||
|
||||
report_checks -from [get_ports in2] -to [get_ports out]
|
||||
puts "PASS: prima in2->out"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Now switch to arnoldi and compare
|
||||
#---------------------------------------------------------------
|
||||
puts "--- arnoldi delay calculator with same design ---"
|
||||
catch {set_delay_calculator arnoldi} msg
|
||||
puts "set_delay_calculator arnoldi: $msg"
|
||||
|
||||
report_checks
|
||||
puts "PASS: arnoldi report_checks"
|
||||
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max} msg
|
||||
puts "arnoldi dcalc u1 A->Y max: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y] -max} msg
|
||||
puts "arnoldi dcalc u2 A->Y max: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -max} msg
|
||||
puts "arnoldi dcalc r1 CLK->Q max: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -min} msg
|
||||
puts "arnoldi dcalc r1 CLK->Q min: $msg"
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: arnoldi with full fields"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Switch to lumped_cap with parasitics
|
||||
#---------------------------------------------------------------
|
||||
puts "--- lumped_cap with parasitics ---"
|
||||
set_delay_calculator lumped_cap
|
||||
|
||||
report_checks
|
||||
puts "PASS: lumped_cap with parasitics"
|
||||
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max} msg
|
||||
puts "lumped_cap dcalc u1: $msg"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Switch to dmp_ceff_two_pole with parasitics
|
||||
#---------------------------------------------------------------
|
||||
puts "--- dmp_ceff_two_pole with parasitics ---"
|
||||
set_delay_calculator dmp_ceff_two_pole
|
||||
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_two_pole with parasitics"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: dmp_ceff_two_pole min"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: dmp_ceff_two_pole max"
|
||||
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max} msg
|
||||
puts "dmp_ceff_two_pole dcalc u1: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y] -max} msg
|
||||
puts "dmp_ceff_two_pole dcalc u2 A->Y: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/B] -to [get_pins u2/Y] -max} msg
|
||||
puts "dmp_ceff_two_pole dcalc u2 B->Y: $msg"
|
||||
|
||||
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -max} msg
|
||||
puts "dmp_ceff_two_pole dcalc r1 CLK->Q: $msg"
|
||||
|
||||
report_checks -fields {slew cap}
|
||||
puts "PASS: dmp_ceff_two_pole with fields"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Switch back to default
|
||||
#---------------------------------------------------------------
|
||||
puts "--- dmp_ceff_elmore (default) ---"
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
|
||||
report_checks
|
||||
puts "PASS: default dcalc with parasitics"
|
||||
|
||||
puts "ALL PASSED"
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,275 @@
|
|||
# Deep Prima and Arnoldi delay calculator testing with different
|
||||
# SPEF files, reduce orders, extreme conditions, and Nangate45 PDK.
|
||||
# Targets:
|
||||
# PrimaDelayCalc.cc: primaDelay, primaReduceRc, prima2, prima3,
|
||||
# primaResStamp, primaCapStamp, primaPostReduction,
|
||||
# gateDelay, gateSlew, loadDelay, reduceParasitics
|
||||
# ArnoldiDelayCalc.cc: arnoldiDelay, arnoldiReduceRc, arnoldi2,
|
||||
# arnoldi3, arnoldiExpand, loadDelay, gateDelay, gateSlew
|
||||
# ArnoldiReduce.cc: arnoldi reduce matrix, arnoldi basis, arnoldi iteration
|
||||
# GraphDelayCalc.cc: findVertexDelay with arnoldi/prima,
|
||||
# seedInvalidDelays, loadPinCapacitanceChanged
|
||||
# DmpCeff.cc: ceffPiElmore with arnoldi/prima parasitic models
|
||||
# DelayCalc.i: delay_calc_names, is_delay_calc_name, set_prima_reduce_order
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
############################################################
|
||||
# Read Nangate45 library and search_test1 design
|
||||
############################################################
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
puts "PASS: read Nangate45"
|
||||
|
||||
read_verilog ../../search/test/search_test1.v
|
||||
link_design search_test1
|
||||
puts "PASS: link search_test1"
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 1.0 [get_ports {in1 in2}]
|
||||
set_output_delay -clock clk 2.0 [get_ports out1]
|
||||
set_input_transition 0.1 [all_inputs]
|
||||
puts "PASS: SDC setup"
|
||||
|
||||
############################################################
|
||||
# Read SPEF parasitics for example1
|
||||
# This exercises SPEF parsing and parasitic model construction
|
||||
############################################################
|
||||
read_spef ../../search/test/search_test1.spef
|
||||
puts "PASS: read SPEF"
|
||||
|
||||
############################################################
|
||||
# Test Prima with Nangate45 + SPEF
|
||||
############################################################
|
||||
puts "--- prima with Nangate45 ---"
|
||||
|
||||
catch {set_delay_calculator prima} msg
|
||||
puts "set prima: $msg"
|
||||
|
||||
report_checks
|
||||
puts "PASS: prima report_checks"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: prima min path"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: prima max path"
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: prima with fields"
|
||||
|
||||
report_checks -format full_clock
|
||||
puts "PASS: prima full_clock"
|
||||
|
||||
# Multiple endpoint paths
|
||||
report_checks -endpoint_count 5
|
||||
puts "PASS: prima endpoint_count 5"
|
||||
|
||||
# From/to specific paths
|
||||
catch {
|
||||
report_checks -from [get_ports in1] -endpoint_count 3
|
||||
puts "PASS: prima from in1"
|
||||
}
|
||||
|
||||
catch {
|
||||
report_checks -to [get_ports out1] -endpoint_count 3
|
||||
puts "PASS: prima to out1"
|
||||
}
|
||||
|
||||
catch {
|
||||
report_checks -from [get_ports in2] -endpoint_count 3
|
||||
puts "PASS: prima from in2"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Prima with varying reduce orders
|
||||
############################################################
|
||||
puts "--- prima reduce order ---"
|
||||
|
||||
catch {sta::set_prima_reduce_order 1} msg
|
||||
puts "set_prima_reduce_order 1: $msg"
|
||||
report_checks
|
||||
puts "PASS: prima order 1"
|
||||
|
||||
catch {sta::set_prima_reduce_order 2} msg
|
||||
puts "set_prima_reduce_order 2: $msg"
|
||||
report_checks
|
||||
puts "PASS: prima order 2"
|
||||
|
||||
catch {sta::set_prima_reduce_order 3} msg
|
||||
puts "set_prima_reduce_order 3: $msg"
|
||||
report_checks
|
||||
puts "PASS: prima order 3"
|
||||
|
||||
catch {sta::set_prima_reduce_order 4} msg
|
||||
puts "set_prima_reduce_order 4: $msg"
|
||||
report_checks
|
||||
puts "PASS: prima order 4"
|
||||
|
||||
catch {sta::set_prima_reduce_order 5} msg
|
||||
puts "set_prima_reduce_order 5: $msg"
|
||||
report_checks
|
||||
puts "PASS: prima order 5"
|
||||
|
||||
# Reset to default
|
||||
catch {sta::set_prima_reduce_order 3} msg
|
||||
|
||||
############################################################
|
||||
# Prima with varying slew
|
||||
############################################################
|
||||
puts "--- prima varying slew ---"
|
||||
set_input_transition 0.05 [all_inputs]
|
||||
report_checks
|
||||
puts "PASS: prima slew=0.05"
|
||||
|
||||
set_input_transition 0.5 [all_inputs]
|
||||
report_checks
|
||||
puts "PASS: prima slew=0.5"
|
||||
|
||||
set_input_transition 2.0 [all_inputs]
|
||||
report_checks
|
||||
puts "PASS: prima slew=2.0"
|
||||
|
||||
set_input_transition 0.1 [all_inputs]
|
||||
|
||||
############################################################
|
||||
# Prima with varying loads
|
||||
############################################################
|
||||
puts "--- prima varying loads ---"
|
||||
foreach load_val {0.0001 0.001 0.005 0.01 0.05} {
|
||||
set_load $load_val [get_ports out1]
|
||||
set_load $load_val [get_ports out1]
|
||||
report_checks
|
||||
puts "prima load=$load_val: done"
|
||||
}
|
||||
set_load 0 [get_ports out1]
|
||||
set_load 0 [get_ports out1]
|
||||
puts "PASS: prima varying loads"
|
||||
|
||||
############################################################
|
||||
# Prima report_dcalc for specific arcs
|
||||
############################################################
|
||||
puts "--- prima report_dcalc ---"
|
||||
|
||||
# Find some pins in the design
|
||||
set all_cells [get_cells *]
|
||||
set first_cell [lindex $all_cells 0]
|
||||
set cell_name [get_name $first_cell]
|
||||
puts "first cell: $cell_name"
|
||||
|
||||
# Try dcalc on various cells
|
||||
foreach cell_obj $all_cells {
|
||||
set cname [get_name $cell_obj]
|
||||
catch {
|
||||
set ref [get_property $cell_obj ref_name]
|
||||
set pins [get_pins $cname/*]
|
||||
if {[llength $pins] >= 2} {
|
||||
set in_pin [lindex $pins 0]
|
||||
set out_pin [lindex $pins end]
|
||||
catch {
|
||||
report_dcalc -from $in_pin -to $out_pin -max
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: prima report_dcalc"
|
||||
|
||||
############################################################
|
||||
# Switch to Arnoldi
|
||||
############################################################
|
||||
puts "--- arnoldi with Nangate45 ---"
|
||||
|
||||
catch {set_delay_calculator arnoldi} msg
|
||||
puts "set arnoldi: $msg"
|
||||
|
||||
report_checks
|
||||
puts "PASS: arnoldi report_checks"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: arnoldi min"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: arnoldi max"
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: arnoldi with fields"
|
||||
|
||||
report_checks -endpoint_count 5
|
||||
puts "PASS: arnoldi endpoint_count 5"
|
||||
|
||||
# Arnoldi with varying slew
|
||||
puts "--- arnoldi varying slew ---"
|
||||
foreach slew_val {0.01 0.05 0.1 0.5 1.0 5.0} {
|
||||
set_input_transition $slew_val [all_inputs]
|
||||
report_checks
|
||||
puts "arnoldi slew=$slew_val: done"
|
||||
}
|
||||
set_input_transition 0.1 [all_inputs]
|
||||
puts "PASS: arnoldi varying slew"
|
||||
|
||||
# Arnoldi with varying loads
|
||||
puts "--- arnoldi varying loads ---"
|
||||
foreach load_val {0.0001 0.001 0.01 0.05 0.1} {
|
||||
set_load $load_val [get_ports out1]
|
||||
report_checks
|
||||
puts "arnoldi load=$load_val: done"
|
||||
}
|
||||
set_load 0 [get_ports out1]
|
||||
puts "PASS: arnoldi varying loads"
|
||||
|
||||
############################################################
|
||||
# Engine switching with SPEF
|
||||
############################################################
|
||||
puts "--- engine switching ---"
|
||||
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_elmore"
|
||||
|
||||
set_delay_calculator dmp_ceff_two_pole
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_two_pole"
|
||||
|
||||
set_delay_calculator lumped_cap
|
||||
report_checks
|
||||
puts "PASS: lumped_cap"
|
||||
|
||||
catch {set_delay_calculator prima}
|
||||
report_checks
|
||||
puts "PASS: prima after switching"
|
||||
|
||||
catch {set_delay_calculator arnoldi}
|
||||
report_checks
|
||||
puts "PASS: arnoldi after switching"
|
||||
|
||||
############################################################
|
||||
# Re-read SPEF and re-compute
|
||||
############################################################
|
||||
puts "--- re-read SPEF ---"
|
||||
read_spef ../../search/test/search_test1.spef
|
||||
puts "PASS: re-read SPEF"
|
||||
|
||||
catch {set_delay_calculator prima}
|
||||
report_checks
|
||||
puts "PASS: prima after SPEF re-read"
|
||||
|
||||
catch {set_delay_calculator arnoldi}
|
||||
report_checks
|
||||
puts "PASS: arnoldi after SPEF re-read"
|
||||
|
||||
############################################################
|
||||
# Incremental updates
|
||||
############################################################
|
||||
puts "--- incremental updates ---"
|
||||
|
||||
set_load 0.005 [get_ports out1]
|
||||
report_checks
|
||||
puts "PASS: arnoldi incremental load"
|
||||
|
||||
create_clock -name clk -period 5 [get_ports clk]
|
||||
report_checks
|
||||
puts "PASS: arnoldi incremental clock"
|
||||
|
||||
set_input_transition 1.0 [all_inputs]
|
||||
report_checks
|
||||
puts "PASS: arnoldi incremental slew"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
No paths found.
|
||||
PASS: delay calculation completed
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ input external delay
|
||||
0.00 0.00 ^ in1 (in)
|
||||
0.02 0.02 ^ buf1/Z (BUF_X1)
|
||||
0.01 0.02 v inv1/ZN (INV_X1)
|
||||
0.00 0.02 v reg1/D (DFF_X1)
|
||||
0.02 data arrival time
|
||||
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg1/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
---------------------------------------------------------
|
||||
0.00 data required time
|
||||
-0.02 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.02 slack (MET)
|
||||
|
||||
|
||||
PASS: min path delay reported
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg1/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
0.00 10.00 output external delay
|
||||
10.00 data required time
|
||||
---------------------------------------------------------
|
||||
10.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.92 slack (MET)
|
||||
|
||||
|
||||
PASS: max path delay reported
|
||||
ALL PASSED
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
# Test delay calculation
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog dcalc_test1.v
|
||||
link_design dcalc_test1
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 0 [get_ports in1]
|
||||
set_output_delay -clock clk 0 [get_ports out1]
|
||||
|
||||
# Force delay calculation
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: delay calculation completed"
|
||||
|
||||
# Report arrival/required
|
||||
report_checks -path_delay min
|
||||
puts "PASS: min path delay reported"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: max path delay reported"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
@ -0,0 +1,905 @@
|
|||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13178, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13211, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13244, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13277, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13310, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13343, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13376, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14772, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14805, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14838, timing group from output port.
|
||||
--- Reading SPEF ---
|
||||
PASS: read_spef completed
|
||||
--- report_checks with parasitics (default dcalc) ---
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
12.11 12.11 clock network delay (propagated)
|
||||
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
63.51 75.62 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
49.30 124.92 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
61.03 185.95 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
15.77 201.72 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
201.72 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
11.92 511.92 clock network delay (propagated)
|
||||
0.00 511.92 clock reconvergence pessimism
|
||||
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-8.46 503.46 library setup time
|
||||
503.46 data required time
|
||||
---------------------------------------------------------
|
||||
503.46 data required time
|
||||
-201.72 data arrival time
|
||||
---------------------------------------------------------
|
||||
301.74 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks with parasitics
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: r1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v in1 (in)
|
||||
12.16 13.16 v r1/D (DFFHQx4_ASAP7_75t_R)
|
||||
13.16 data arrival time
|
||||
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
12.11 12.11 clock network delay (propagated)
|
||||
0.00 12.11 clock reconvergence pessimism
|
||||
12.11 ^ r1/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
12.51 24.61 library hold time
|
||||
24.61 data required time
|
||||
---------------------------------------------------------
|
||||
24.61 data required time
|
||||
-13.16 data arrival time
|
||||
---------------------------------------------------------
|
||||
-11.46 slack (VIOLATED)
|
||||
|
||||
|
||||
PASS: report_checks min path with parasitics
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
12.11 12.11 clock network delay (propagated)
|
||||
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
63.51 75.62 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
49.30 124.92 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
61.03 185.95 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
15.77 201.72 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
201.72 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
11.92 511.92 clock network delay (propagated)
|
||||
0.00 511.92 clock reconvergence pessimism
|
||||
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-8.46 503.46 library setup time
|
||||
503.46 data required time
|
||||
---------------------------------------------------------
|
||||
503.46 data required time
|
||||
-201.72 data arrival time
|
||||
---------------------------------------------------------
|
||||
301.74 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks max path with parasitics
|
||||
No paths found.
|
||||
PASS: report_checks in1->out with parasitics
|
||||
No paths found.
|
||||
PASS: report_checks in2->out with parasitics
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
13.92 10.00 0.00 0.00 ^ clk2 (in)
|
||||
48.38 12.11 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
13.98 22.89 63.51 75.62 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
50.73 14.24 89.86 ^ u1/A (BUFx2_ASAP7_75t_R)
|
||||
13.97 47.36 35.06 124.92 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
66.26 15.35 140.27 ^ u2/B (AND2x2_ASAP7_75t_R)
|
||||
14.02 56.47 45.68 185.95 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
73.39 15.77 201.72 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
201.72 data arrival time
|
||||
|
||||
0.00 500.00 500.00 clock clk (rise edge)
|
||||
0.00 500.00 clock source latency
|
||||
13.81 10.00 0.00 500.00 ^ clk3 (in)
|
||||
47.79 11.92 511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
0.00 511.92 clock reconvergence pessimism
|
||||
-8.46 503.46 library setup time
|
||||
503.46 data required time
|
||||
-----------------------------------------------------------------------
|
||||
503.46 data required time
|
||||
-201.72 data arrival time
|
||||
-----------------------------------------------------------------------
|
||||
301.74 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks with fields and full_clock
|
||||
--- report_dcalc with parasitics ---
|
||||
Library: asap7sc7p5t_INVBUF_RVT_FF_nldm_211120
|
||||
Cell: BUFx2_ASAP7_75t_R
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Y ^
|
||||
Pi model C2=6.70 Rpi=2.42 C1=7.27, Ceff=10.50
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- input_net_transition = 50.73
|
||||
| total_output_net_capacitance = 10.50
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 27.29 35.12
|
||||
80.00 | 32.30 40.08
|
||||
Table value = 35.06
|
||||
PVT scale factor = 1.00
|
||||
Delay = 35.06
|
||||
|
||||
------- input_net_transition = 50.73
|
||||
| total_output_net_capacitance = 10.50
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 20.70 37.28
|
||||
80.00 | 21.40 38.13
|
||||
Table value = 34.55
|
||||
PVT scale factor = 1.00
|
||||
Slew = 34.55
|
||||
Driver waveform slew = 47.36
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Y v
|
||||
Pi model C2=6.70 Rpi=2.42 C1=7.27, Ceff=10.09
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- input_net_transition = 48.75
|
||||
| total_output_net_capacitance = 10.09
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 29.18 36.17
|
||||
80.00 | 36.09 43.28
|
||||
Table value = 35.98
|
||||
PVT scale factor = 1.00
|
||||
Delay = 35.98
|
||||
|
||||
------- input_net_transition = 48.75
|
||||
| total_output_net_capacitance = 10.09
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 18.15 31.72
|
||||
80.00 | 19.36 32.63
|
||||
Table value = 28.57
|
||||
PVT scale factor = 1.00
|
||||
Slew = 28.57
|
||||
Driver waveform slew = 40.66
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc BUF arc with parasitics
|
||||
Library: asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120
|
||||
Cell: AND2x2_ASAP7_75t_R
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Y ^
|
||||
Pi model C2=6.70 Rpi=2.42 C1=7.32, Ceff=10.90
|
||||
P = 1.00 V = 0.70 T = 25.00
|
||||
------- input_net_transition = 50.41
|
||||
| total_output_net_capacitance = 10.90
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 31.28 40.48
|
||||
80.00 | 36.30 45.47
|
||||
Table value = 40.79
|
||||
PVT scale factor = 1.00
|
||||
Delay = 40.79
|
||||
|
||||
------- input_net_transition = 50.41
|
||||
| total_output_net_capacitance = 10.90
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 24.52 43.68
|
||||
80.00 | 25.29 44.42
|
||||
Table value = 41.80
|
||||
PVT scale factor = 1.00
|
||||
Slew = 41.80
|
||||
Driver waveform slew = 55.90
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Y v
|
||||
Pi model C2=6.70 Rpi=2.42 C1=7.32, Ceff=10.35
|
||||
P = 1.00 V = 0.70 T = 25.00
|
||||
------- input_net_transition = 48.36
|
||||
| total_output_net_capacitance = 10.35
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 35.35 43.09
|
||||
80.00 | 44.73 52.65
|
||||
Table value = 43.51
|
||||
PVT scale factor = 1.00
|
||||
Delay = 43.51
|
||||
|
||||
------- input_net_transition = 48.36
|
||||
| total_output_net_capacitance = 10.35
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 20.09 35.08
|
||||
80.00 | 21.45 36.06
|
||||
Table value = 32.26
|
||||
PVT scale factor = 1.00
|
||||
Slew = 32.26
|
||||
Driver waveform slew = 45.57
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc AND2 A->Y with parasitics
|
||||
Library: asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120
|
||||
Cell: AND2x2_ASAP7_75t_R
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
B ^ -> Y ^
|
||||
Pi model C2=6.70 Rpi=2.42 C1=7.32, Ceff=10.94
|
||||
P = 1.00 V = 0.70 T = 25.00
|
||||
------- input_net_transition = 66.26
|
||||
| total_output_net_capacitance = 10.94
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 33.56 42.69
|
||||
80.00 | 39.48 48.65
|
||||
Table value = 45.68
|
||||
PVT scale factor = 1.00
|
||||
Delay = 45.68
|
||||
|
||||
------- input_net_transition = 66.26
|
||||
| total_output_net_capacitance = 10.94
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 24.73 43.75
|
||||
80.00 | 25.53 44.49
|
||||
Table value = 42.31
|
||||
PVT scale factor = 1.00
|
||||
Slew = 42.31
|
||||
Driver waveform slew = 56.47
|
||||
|
||||
.............................................
|
||||
|
||||
B v -> Y v
|
||||
Pi model C2=6.70 Rpi=2.42 C1=7.32, Ceff=10.39
|
||||
P = 1.00 V = 0.70 T = 25.00
|
||||
------- input_net_transition = 61.46
|
||||
| total_output_net_capacitance = 10.39
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 34.01 41.76
|
||||
80.00 | 42.66 50.55
|
||||
Table value = 44.94
|
||||
PVT scale factor = 1.00
|
||||
Delay = 44.94
|
||||
|
||||
------- input_net_transition = 61.46
|
||||
| total_output_net_capacitance = 10.39
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 20.11 35.08
|
||||
80.00 | 21.52 36.22
|
||||
Table value = 32.77
|
||||
PVT scale factor = 1.00
|
||||
Slew = 32.77
|
||||
Driver waveform slew = 45.94
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc AND2 B->Y with parasitics
|
||||
Library: asap7sc7p5t_SEQ_RVT_FF_nldm_220123
|
||||
Cell: DFFHQx4_ASAP7_75t_R
|
||||
Arc sense: non_unate
|
||||
Arc type: Reg Clk to Q
|
||||
CLK ^ -> Q ^
|
||||
Pi model C2=6.70 Rpi=2.42 C1=7.22, Ceff=9.22
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- input_net_transition = 48.38
|
||||
| total_output_net_capacitance = 9.22
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 59.92 64.09
|
||||
80.00 | 65.10 69.26
|
||||
Table value = 63.51
|
||||
PVT scale factor = 1.00
|
||||
Delay = 63.51
|
||||
|
||||
------- input_net_transition = 48.38
|
||||
| total_output_net_capacitance = 9.22
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 13.01 21.04
|
||||
80.00 | 13.01 21.05
|
||||
Table value = 17.83
|
||||
PVT scale factor = 1.00
|
||||
Slew = 17.83
|
||||
Driver waveform slew = 22.83
|
||||
|
||||
.............................................
|
||||
|
||||
CLK ^ -> Q v
|
||||
Pi model C2=6.70 Rpi=2.42 C1=7.21, Ceff=8.89
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- input_net_transition = 48.38
|
||||
| total_output_net_capacitance = 8.89
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 57.80 61.63
|
||||
80.00 | 62.64 66.47
|
||||
Table value = 60.90
|
||||
PVT scale factor = 1.00
|
||||
Delay = 60.90
|
||||
|
||||
------- input_net_transition = 48.38
|
||||
| total_output_net_capacitance = 8.89
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 11.30 17.99
|
||||
80.00 | 11.31 17.98
|
||||
Table value = 14.94
|
||||
PVT scale factor = 1.00
|
||||
Slew = 14.94
|
||||
Driver waveform slew = 19.18
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc DFF CLK->Q with parasitics
|
||||
Library: asap7sc7p5t_SEQ_RVT_FF_nldm_220123
|
||||
Cell: DFFHQx4_ASAP7_75t_R
|
||||
Arc sense: non_unate
|
||||
Arc type: Reg Clk to Q
|
||||
CLK ^ -> Q ^
|
||||
Pi model C2=6.70 Rpi=2.42 C1=6.70, Ceff=9.16
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- input_net_transition = 48.38
|
||||
| total_output_net_capacitance = 9.16
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 59.92 64.09
|
||||
80.00 | 65.10 69.26
|
||||
Table value = 63.46
|
||||
PVT scale factor = 1.00
|
||||
Delay = 63.46
|
||||
|
||||
------- input_net_transition = 48.38
|
||||
| total_output_net_capacitance = 9.16
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 13.01 21.04
|
||||
80.00 | 13.01 21.05
|
||||
Table value = 17.74
|
||||
PVT scale factor = 1.00
|
||||
Slew = 17.74
|
||||
Driver waveform slew = 22.31
|
||||
|
||||
.............................................
|
||||
|
||||
CLK ^ -> Q v
|
||||
Pi model C2=6.70 Rpi=2.42 C1=6.70, Ceff=8.85
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- input_net_transition = 48.38
|
||||
| total_output_net_capacitance = 8.85
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 57.80 61.63
|
||||
80.00 | 62.64 66.47
|
||||
Table value = 60.87
|
||||
PVT scale factor = 1.00
|
||||
Delay = 60.87
|
||||
|
||||
------- input_net_transition = 48.38
|
||||
| total_output_net_capacitance = 8.85
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 11.30 17.99
|
||||
80.00 | 11.31 17.98
|
||||
Table value = 14.89
|
||||
PVT scale factor = 1.00
|
||||
Slew = 14.89
|
||||
Driver waveform slew = 18.76
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc DFF r3 CLK->Q max with parasitics
|
||||
Library: asap7sc7p5t_SEQ_RVT_FF_nldm_220123
|
||||
Cell: DFFHQx4_ASAP7_75t_R
|
||||
Arc type: setup
|
||||
CLK ^ -> D ^
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- constrained_pin_transition = 73.39
|
||||
| related_pin_transition = 47.79
|
||||
| 40.00 80.00
|
||||
v --------------------
|
||||
40.00 | 6.68 5.15
|
||||
80.00 | 8.95 8.54
|
||||
Table value = 8.46
|
||||
PVT scale factor = 1.00
|
||||
Check = 8.46
|
||||
|
||||
.............................................
|
||||
|
||||
CLK ^ -> D v
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- constrained_pin_transition = 65.45
|
||||
| related_pin_transition = 47.79
|
||||
| 40.00 80.00
|
||||
v --------------------
|
||||
40.00 | -2.23 -7.76
|
||||
80.00 | 5.88 -2.55
|
||||
Table value = 1.49
|
||||
PVT scale factor = 1.00
|
||||
Check = 1.49
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc DFF setup check with parasitics
|
||||
Library: asap7sc7p5t_SEQ_RVT_FF_nldm_220123
|
||||
Cell: DFFHQx4_ASAP7_75t_R
|
||||
Arc type: hold
|
||||
CLK ^ -> D ^
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- constrained_pin_transition = 72.50
|
||||
| related_pin_transition = 48.38
|
||||
| 40.00 80.00
|
||||
v --------------------
|
||||
40.00 | -3.44 0.59
|
||||
80.00 | -1.12 0.23
|
||||
Table value = -1.17
|
||||
PVT scale factor = 1.00
|
||||
Check = -1.17
|
||||
|
||||
.............................................
|
||||
|
||||
CLK ^ -> D v
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- constrained_pin_transition = 64.66
|
||||
| related_pin_transition = 48.38
|
||||
| 40.00 80.00
|
||||
v --------------------
|
||||
40.00 | 11.76 17.37
|
||||
80.00 | 9.46 16.46
|
||||
Table value = 11.70
|
||||
PVT scale factor = 1.00
|
||||
Check = 11.70
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc DFF hold check with parasitics
|
||||
--- Testing arnoldi delay calculator ---
|
||||
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
12.11 12.11 clock network delay (propagated)
|
||||
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
62.99 75.10 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
49.15 124.25 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
62.20 186.45 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
18.51 204.96 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
204.96 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
11.92 511.92 clock network delay (propagated)
|
||||
0.00 511.92 clock reconvergence pessimism
|
||||
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-8.80 503.12 library setup time
|
||||
503.12 data required time
|
||||
---------------------------------------------------------
|
||||
503.12 data required time
|
||||
-204.96 data arrival time
|
||||
---------------------------------------------------------
|
||||
298.15 slack (MET)
|
||||
|
||||
|
||||
PASS: arnoldi report_checks
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: r1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v in1 (in)
|
||||
12.16 13.16 v r1/D (DFFHQx4_ASAP7_75t_R)
|
||||
13.16 data arrival time
|
||||
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
12.11 12.11 clock network delay (propagated)
|
||||
0.00 12.11 clock reconvergence pessimism
|
||||
12.11 ^ r1/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
12.51 24.61 library hold time
|
||||
24.61 data required time
|
||||
---------------------------------------------------------
|
||||
24.61 data required time
|
||||
-13.16 data arrival time
|
||||
---------------------------------------------------------
|
||||
-11.46 slack (VIOLATED)
|
||||
|
||||
|
||||
PASS: arnoldi min path
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
12.11 12.11 clock network delay (propagated)
|
||||
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
62.99 75.10 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
49.15 124.25 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
62.20 186.45 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
18.51 204.96 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
204.96 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
11.92 511.92 clock network delay (propagated)
|
||||
0.00 511.92 clock reconvergence pessimism
|
||||
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-8.80 503.12 library setup time
|
||||
503.12 data required time
|
||||
---------------------------------------------------------
|
||||
503.12 data required time
|
||||
-204.96 data arrival time
|
||||
---------------------------------------------------------
|
||||
298.15 slack (MET)
|
||||
|
||||
|
||||
PASS: arnoldi max path
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
13.92 10.00 0.00 0.00 ^ clk2 (in)
|
||||
48.38 12.11 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
13.98 29.94 62.99 75.10 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
54.60 15.52 90.62 ^ u1/A (BUFx2_ASAP7_75t_R)
|
||||
13.97 54.12 33.63 124.25 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
71.52 17.95 142.20 ^ u2/B (AND2x2_ASAP7_75t_R)
|
||||
14.02 63.30 44.25 186.45 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
78.93 18.51 204.96 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
204.96 data arrival time
|
||||
|
||||
0.00 500.00 500.00 clock clk (rise edge)
|
||||
0.00 500.00 clock source latency
|
||||
13.81 10.00 0.00 500.00 ^ clk3 (in)
|
||||
47.79 11.92 511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
0.00 511.92 clock reconvergence pessimism
|
||||
-8.80 503.12 library setup time
|
||||
503.12 data required time
|
||||
-----------------------------------------------------------------------
|
||||
503.12 data required time
|
||||
-204.96 data arrival time
|
||||
-----------------------------------------------------------------------
|
||||
298.15 slack (MET)
|
||||
|
||||
|
||||
PASS: arnoldi report_checks with fields
|
||||
Library: asap7sc7p5t_INVBUF_RVT_FF_nldm_211120
|
||||
Cell: BUFx2_ASAP7_75t_R
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Y ^
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- input_net_transition = 54.60
|
||||
| total_output_net_capacitance = 13.97
|
||||
| 11.52 23.04
|
||||
v --------------------
|
||||
40.00 | 35.12 50.39
|
||||
80.00 | 40.08 55.44
|
||||
Table value = 40.18
|
||||
PVT scale factor = 1.00
|
||||
Delay = 40.18
|
||||
|
||||
------- input_net_transition = 54.60
|
||||
| total_output_net_capacitance = 13.97
|
||||
| 11.52 23.04
|
||||
v --------------------
|
||||
40.00 | 37.28 71.28
|
||||
80.00 | 38.13 71.69
|
||||
Table value = 44.77
|
||||
PVT scale factor = 1.00
|
||||
Slew = 44.77
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Y v
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- input_net_transition = 52.63
|
||||
| total_output_net_capacitance = 13.97
|
||||
| 11.52 23.04
|
||||
v --------------------
|
||||
40.00 | 36.17 49.65
|
||||
80.00 | 43.28 56.72
|
||||
Table value = 41.27
|
||||
PVT scale factor = 1.00
|
||||
Delay = 41.27
|
||||
|
||||
------- input_net_transition = 52.63
|
||||
| total_output_net_capacitance = 13.97
|
||||
| 11.52 23.04
|
||||
v --------------------
|
||||
40.00 | 31.72 59.66
|
||||
80.00 | 32.63 60.23
|
||||
Table value = 37.92
|
||||
PVT scale factor = 1.00
|
||||
Slew = 37.92
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: arnoldi report_dcalc BUF
|
||||
Library: asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120
|
||||
Cell: AND2x2_ASAP7_75t_R
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Y ^
|
||||
P = 1.00 V = 0.70 T = 25.00
|
||||
------- input_net_transition = 54.25
|
||||
| total_output_net_capacitance = 14.02
|
||||
| 11.52 23.04
|
||||
v --------------------
|
||||
40.00 | 40.48 58.12
|
||||
80.00 | 45.47 63.31
|
||||
Table value = 46.10
|
||||
PVT scale factor = 1.00
|
||||
Delay = 46.10
|
||||
|
||||
------- input_net_transition = 54.25
|
||||
| total_output_net_capacitance = 14.02
|
||||
| 11.52 23.04
|
||||
v --------------------
|
||||
40.00 | 43.68 82.62
|
||||
80.00 | 44.42 82.97
|
||||
Table value = 52.37
|
||||
PVT scale factor = 1.00
|
||||
Slew = 52.37
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Y v
|
||||
P = 1.00 V = 0.70 T = 25.00
|
||||
------- input_net_transition = 52.20
|
||||
| total_output_net_capacitance = 14.02
|
||||
| 11.52 23.04
|
||||
v --------------------
|
||||
40.00 | 43.09 58.01
|
||||
80.00 | 52.65 67.66
|
||||
Table value = 49.25
|
||||
PVT scale factor = 1.00
|
||||
Delay = 49.25
|
||||
|
||||
------- input_net_transition = 52.20
|
||||
| total_output_net_capacitance = 14.02
|
||||
| 11.52 23.04
|
||||
v --------------------
|
||||
40.00 | 35.08 65.82
|
||||
80.00 | 36.06 66.39
|
||||
Table value = 42.02
|
||||
PVT scale factor = 1.00
|
||||
Slew = 42.02
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: arnoldi report_dcalc AND2
|
||||
--- Testing lumped_cap with parasitics ---
|
||||
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
59.07 59.07 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
35.39 94.45 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
47.16 141.62 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 141.62 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
141.62 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
0.00 500.00 clock network delay (propagated)
|
||||
0.00 500.00 clock reconvergence pessimism
|
||||
500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-10.20 489.80 library setup time
|
||||
489.80 data required time
|
||||
---------------------------------------------------------
|
||||
489.80 data required time
|
||||
-141.62 data arrival time
|
||||
---------------------------------------------------------
|
||||
348.18 slack (MET)
|
||||
|
||||
|
||||
PASS: lumped_cap with parasitics report_checks
|
||||
Library: asap7sc7p5t_INVBUF_RVT_FF_nldm_211120
|
||||
Cell: BUFx2_ASAP7_75t_R
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Y ^
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- input_net_transition = 24.64
|
||||
| total_output_net_capacitance = 13.97
|
||||
| 11.52 23.04
|
||||
v --------------------
|
||||
20.00 | 31.25 46.51
|
||||
40.00 | 35.12 50.39
|
||||
Table value = 35.39
|
||||
PVT scale factor = 1.00
|
||||
Delay = 35.39
|
||||
|
||||
------- input_net_transition = 24.64
|
||||
| total_output_net_capacitance = 13.97
|
||||
| 11.52 23.04
|
||||
v --------------------
|
||||
20.00 | 36.94 71.10
|
||||
40.00 | 37.28 71.28
|
||||
Table value = 44.26
|
||||
PVT scale factor = 1.00
|
||||
Slew = 44.26
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Y v
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- input_net_transition = 20.95
|
||||
| total_output_net_capacitance = 13.97
|
||||
| 11.52 23.04
|
||||
v --------------------
|
||||
20.00 | 31.07 44.53
|
||||
40.00 | 36.17 49.65
|
||||
Table value = 34.17
|
||||
PVT scale factor = 1.00
|
||||
Delay = 34.17
|
||||
|
||||
------- input_net_transition = 20.95
|
||||
| total_output_net_capacitance = 13.97
|
||||
| 11.52 23.04
|
||||
v --------------------
|
||||
20.00 | 31.25 59.40
|
||||
40.00 | 31.72 59.66
|
||||
Table value = 37.25
|
||||
PVT scale factor = 1.00
|
||||
Slew = 37.25
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: lumped_cap with parasitics report_dcalc
|
||||
--- Testing dmp_ceff_two_pole with parasitics ---
|
||||
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
55.73 55.73 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
30.36 86.09 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
42.76 128.85 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 128.85 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
128.85 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
0.00 500.00 clock network delay (propagated)
|
||||
0.00 500.00 clock reconvergence pessimism
|
||||
500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-10.53 489.47 library setup time
|
||||
489.47 data required time
|
||||
---------------------------------------------------------
|
||||
489.47 data required time
|
||||
-128.85 data arrival time
|
||||
---------------------------------------------------------
|
||||
360.62 slack (MET)
|
||||
|
||||
|
||||
PASS: dmp_ceff_two_pole with parasitics report_checks
|
||||
Library: asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120
|
||||
Cell: AND2x2_ASAP7_75t_R
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Y ^
|
||||
Pi model C2=6.70 Rpi=2.42 C1=7.32, Ceff=10.88
|
||||
P = 1.00 V = 0.70 T = 25.00
|
||||
------- input_net_transition = 22.83
|
||||
| total_output_net_capacitance = 10.88
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
20.00 | 27.85 36.94
|
||||
40.00 | 31.28 40.48
|
||||
Table value = 36.43
|
||||
PVT scale factor = 1.00
|
||||
Delay = 36.43
|
||||
|
||||
------- input_net_transition = 22.83
|
||||
| total_output_net_capacitance = 10.88
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
20.00 | 24.09 43.36
|
||||
40.00 | 24.52 43.68
|
||||
Table value = 41.27
|
||||
PVT scale factor = 1.00
|
||||
Slew = 41.27
|
||||
Driver waveform slew = 55.45
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Y v
|
||||
Pi model C2=6.70 Rpi=2.42 C1=7.32, Ceff=10.29
|
||||
P = 1.00 V = 0.70 T = 25.00
|
||||
------- input_net_transition = 19.29
|
||||
| total_output_net_capacitance = 10.29
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
10.00 | 25.20 32.93
|
||||
20.00 | 28.93 36.68
|
||||
Table value = 34.76
|
||||
PVT scale factor = 1.00
|
||||
Delay = 34.76
|
||||
|
||||
------- input_net_transition = 19.29
|
||||
| total_output_net_capacitance = 10.29
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
10.00 | 19.49 34.69
|
||||
20.00 | 19.55 34.72
|
||||
Table value = 31.48
|
||||
PVT scale factor = 1.00
|
||||
Slew = 31.48
|
||||
Driver waveform slew = 45.09
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: dmp_ceff_two_pole with parasitics report_dcalc
|
||||
ALL PASSED
|
||||
|
|
@ -0,0 +1,142 @@
|
|||
# Test delay calculation with SPEF parasitics
|
||||
# Exercises: GraphDelayCalc with parasitics, arnoldi delay calculator
|
||||
|
||||
# Read ASAP7 libraries
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
|
||||
read_verilog ../../test/reg1_asap7.v
|
||||
link_design top
|
||||
|
||||
create_clock -name clk -period 500 {clk1 clk2 clk3}
|
||||
set_input_delay -clock clk 1 {in1 in2}
|
||||
set_output_delay -clock clk 1 [get_ports out]
|
||||
set_input_transition 10 {in1 in2 clk1 clk2 clk3}
|
||||
set_propagated_clock {clk1 clk2 clk3}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Read SPEF parasitics
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Reading SPEF ---"
|
||||
read_spef ../../test/reg1_asap7.spef
|
||||
puts "PASS: read_spef completed"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Default delay calculator (dmp_ceff_elmore) with parasitics
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_checks with parasitics (default dcalc) ---"
|
||||
report_checks
|
||||
puts "PASS: report_checks with parasitics"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: report_checks min path with parasitics"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: report_checks max path with parasitics"
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out]
|
||||
puts "PASS: report_checks in1->out with parasitics"
|
||||
|
||||
report_checks -from [get_ports in2] -to [get_ports out]
|
||||
puts "PASS: report_checks in2->out with parasitics"
|
||||
|
||||
# With fields for more coverage
|
||||
report_checks -fields {slew cap input_pins} -format full_clock
|
||||
puts "PASS: report_checks with fields and full_clock"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_dcalc with parasitics
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_dcalc with parasitics ---"
|
||||
|
||||
# BUF gate arc
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y]} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc BUF arc with parasitics"
|
||||
|
||||
# AND gate arc
|
||||
catch {report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y]} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc AND2 A->Y with parasitics"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/B] -to [get_pins u2/Y]} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc AND2 B->Y with parasitics"
|
||||
|
||||
# DFF clock-to-Q arc
|
||||
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q]} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc DFF CLK->Q with parasitics"
|
||||
|
||||
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/Q] -max} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc DFF r3 CLK->Q max with parasitics"
|
||||
|
||||
# DFF setup/hold check arcs
|
||||
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/D] -max} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc DFF setup check with parasitics"
|
||||
|
||||
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/D] -min} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc DFF hold check with parasitics"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Arnoldi delay calculator with parasitics
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Testing arnoldi delay calculator ---"
|
||||
catch {set_delay_calculator arnoldi} msg
|
||||
puts $msg
|
||||
|
||||
report_checks
|
||||
puts "PASS: arnoldi report_checks"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: arnoldi min path"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: arnoldi max path"
|
||||
|
||||
report_checks -fields {slew cap input_pins} -format full_clock
|
||||
puts "PASS: arnoldi report_checks with fields"
|
||||
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y]} msg
|
||||
puts $msg
|
||||
puts "PASS: arnoldi report_dcalc BUF"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y]} msg
|
||||
puts $msg
|
||||
puts "PASS: arnoldi report_dcalc AND2"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Lumped cap delay calculator with parasitics
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Testing lumped_cap with parasitics ---"
|
||||
catch {set_delay_calculator lumped_cap} msg
|
||||
puts $msg
|
||||
|
||||
report_checks
|
||||
puts "PASS: lumped_cap with parasitics report_checks"
|
||||
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y]} msg
|
||||
puts $msg
|
||||
puts "PASS: lumped_cap with parasitics report_dcalc"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# dmp_ceff_two_pole delay calculator with parasitics
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Testing dmp_ceff_two_pole with parasitics ---"
|
||||
catch {set_delay_calculator dmp_ceff_two_pole} msg
|
||||
puts $msg
|
||||
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_two_pole with parasitics report_checks"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y]} msg
|
||||
puts $msg
|
||||
puts "PASS: dmp_ceff_two_pole with parasitics report_dcalc"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
module dcalc_test1 (clk, in1, out1);
|
||||
input clk, in1;
|
||||
output out1;
|
||||
wire n1, n2;
|
||||
|
||||
BUF_X1 buf1 (.A(in1), .Z(n1));
|
||||
INV_X1 inv1 (.A(n1), .ZN(n2));
|
||||
DFF_X1 reg1 (.D(n2), .CK(clk), .Q(out1));
|
||||
endmodule
|
||||
|
|
@ -0,0 +1 @@
|
|||
../../test/regression
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
add_test(
|
||||
NAME tcl.graph.make_verify
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_make_verify
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.graph.make_verify PROPERTIES LABELS "tcl;module_graph")
|
||||
|
||||
add_test(
|
||||
NAME tcl.graph.timing_edges
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_timing_edges
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.graph.timing_edges PROPERTIES LABELS "tcl;module_graph")
|
||||
|
||||
add_test(
|
||||
NAME tcl.graph.advanced
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_advanced
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.graph.advanced PROPERTIES LABELS "tcl;module_graph")
|
||||
|
||||
add_test(
|
||||
NAME tcl.graph.incremental
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_incremental
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.graph.incremental PROPERTIES LABELS "tcl;module_graph")
|
||||
|
||||
add_test(
|
||||
NAME tcl.graph.delay_corners
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_delay_corners
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.graph.delay_corners PROPERTIES LABELS "tcl;module_graph")
|
||||
|
||||
add_test(
|
||||
NAME tcl.graph.operations
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_operations
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.graph.operations PROPERTIES LABELS "tcl;module_graph")
|
||||
|
||||
add_test(
|
||||
NAME tcl.graph.modify
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_modify
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.graph.modify PROPERTIES LABELS "tcl;module_graph")
|
||||
|
||||
add_test(
|
||||
NAME tcl.graph.bidirect
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_bidirect
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.graph.bidirect PROPERTIES LABELS "tcl;module_graph")
|
||||
|
||||
add_test(
|
||||
NAME tcl.graph.wire_inst_edges
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_wire_inst_edges
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.graph.wire_inst_edges PROPERTIES LABELS "tcl;module_graph")
|
||||
|
||||
add_test(
|
||||
NAME tcl.graph.delete_modify
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_delete_modify
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.graph.delete_modify PROPERTIES LABELS "tcl;module_graph")
|
||||
|
||||
add_test(
|
||||
NAME tcl.graph.vertex_edge_ops
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_vertex_edge_ops
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.graph.vertex_edge_ops PROPERTIES LABELS "tcl;module_graph")
|
||||
|
||||
add_subdirectory(cpp)
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
add_executable(TestGraph TestGraph.cc)
|
||||
target_link_libraries(TestGraph
|
||||
OpenSTA
|
||||
GTest::gtest
|
||||
GTest::gtest_main
|
||||
${TCL_LIBRARY}
|
||||
)
|
||||
target_include_directories(TestGraph PRIVATE
|
||||
${STA_HOME}/include/sta
|
||||
${STA_HOME}
|
||||
${CMAKE_BINARY_DIR}/include/sta
|
||||
)
|
||||
gtest_discover_tests(TestGraph
|
||||
WORKING_DIRECTORY ${STA_HOME}
|
||||
PROPERTIES LABELS "cpp;module_graph"
|
||||
)
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,475 @@
|
|||
--- report_checks baseline ---
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ q (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks baseline
|
||||
--- report_checks -path_delay min ---
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 v reg1/Q (DFF_X1)
|
||||
0.00 0.08 v reg2/D (DFF_X1)
|
||||
0.08 data arrival time
|
||||
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg2/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
---------------------------------------------------------
|
||||
0.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.08 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks -path_delay min
|
||||
--- report_checks -path_delay max ---
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ q (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks -path_delay max
|
||||
--- report_checks -from/-to ---
|
||||
No paths found.
|
||||
PASS: report_checks -from/-to
|
||||
--- report_checks -through ---
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 v reg1/Q (DFF_X1)
|
||||
0.00 0.08 v reg2/D (DFF_X1)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks -through
|
||||
--- get_timing_edges full combinations ---
|
||||
reg1 all edges: 1
|
||||
reg2 all edges: 1
|
||||
--- report_edges for cells ---
|
||||
CK -> Q Reg Clk to Q
|
||||
^ -> ^ 0.08:0.08
|
||||
^ -> v 0.08:0.08
|
||||
PASS: report_edges reg1 CK->Q
|
||||
CK -> Q Reg Clk to Q
|
||||
^ -> ^ 0.08:0.08
|
||||
^ -> v 0.08:0.08
|
||||
PASS: report_edges reg2 CK->Q
|
||||
CK -> QN Reg Clk to Q
|
||||
^ -> ^ 0.06:0.06
|
||||
^ -> v 0.06:0.06
|
||||
CK -> Q Reg Clk to Q
|
||||
^ -> ^ 0.08:0.08
|
||||
^ -> v 0.08:0.08
|
||||
CK -> CK width
|
||||
^ -> v 0.05:0.05
|
||||
v -> ^ 0.05:0.05
|
||||
CK -> D setup
|
||||
^ -> ^ 0.05:0.05
|
||||
^ -> v 0.07:0.07
|
||||
CK -> D hold
|
||||
^ -> ^ 0.05:0.05
|
||||
^ -> v 0.05:0.05
|
||||
PASS: report_edges from reg1/CK
|
||||
CK -> D setup
|
||||
^ -> ^ 0.03:0.03
|
||||
^ -> v 0.04:0.04
|
||||
CK -> D hold
|
||||
^ -> ^ 0.01:0.01
|
||||
^ -> v 0.00:0.00
|
||||
reg1/Q -> D wire
|
||||
^ -> ^ 0.00:0.00
|
||||
v -> v 0.00:0.00
|
||||
PASS: report_edges to reg2/D
|
||||
--- disable_timing on port pin ---
|
||||
reg1 CK Q constraint
|
||||
reg2 CK Q constraint
|
||||
PASS: disabled CK->Q in lib cell
|
||||
Startpoint: d (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d (in)
|
||||
0.00 1.00 v reg1/D (DFF_X1)
|
||||
1.00 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg1/CK (DFF_X1)
|
||||
-0.07 9.93 library setup time
|
||||
9.93 data required time
|
||||
---------------------------------------------------------
|
||||
9.93 data required time
|
||||
-1.00 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.93 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks after lib cell disable
|
||||
PASS: unset lib cell disable
|
||||
--- set_disable_timing instance and back ---
|
||||
reg1 CK Q constraint
|
||||
reg1 CK QN constraint
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ q (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
PASS: instance disable
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ q (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
PASS: instance unset disable
|
||||
--- report_slews for various pins ---
|
||||
d ^ 0.10:0.10 v 0.10:0.10
|
||||
q ^ 0.01:0.01 v 0.00:0.00
|
||||
reg1/CK ^ 0.00:0.00 v 0.00:0.00
|
||||
reg1/Q ^ 0.01:0.01 v 0.01:0.01
|
||||
reg2/D ^ 0.01:0.01 v 0.01:0.01
|
||||
PASS: report_slews various pins
|
||||
--- report_check_types ---
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 v reg1/Q (DFF_X1)
|
||||
0.00 0.08 v reg2/D (DFF_X1)
|
||||
0.08 data arrival time
|
||||
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg2/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
---------------------------------------------------------
|
||||
0.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.08 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ q (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
PASS: report_check_types
|
||||
--- report_checks with -format ---
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ q (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks -format full_clock
|
||||
--- report_checks -unconstrained ---
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ q (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks unconstrained
|
||||
--- report_checks -group_count 2 ---
|
||||
Warning: graph_advanced.tcl line 1, report_checks -group_count is deprecated. Use -group_path_count instead.
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ q (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d (in)
|
||||
0.00 1.00 v reg1/D (DFF_X1)
|
||||
1.00 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg1/CK (DFF_X1)
|
||||
-0.07 9.93 library setup time
|
||||
9.93 data required time
|
||||
---------------------------------------------------------
|
||||
9.93 data required time
|
||||
-1.00 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.93 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks -group_count 2
|
||||
--- report_checks -endpoint_count 2 ---
|
||||
Warning: graph_advanced.tcl line 1, report_checks -endpoint_count is deprecated. Use -endpoint_path_count instead.
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ q (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 v reg2/Q (DFF_X1)
|
||||
0.00 0.08 v q (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks -endpoint_count 2
|
||||
ALL PASSED
|
||||
|
|
@ -0,0 +1,133 @@
|
|||
# Test advanced graph operations: multiple-instance design, edge traversal,
|
||||
# and graph info queries.
|
||||
# Targets uncovered Graph.cc functions: vertex operations, edge iterators,
|
||||
# constant propagation, level reporting, etc.
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Load a larger design for more graph coverage
|
||||
#---------------------------------------------------------------
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog graph_test1.v
|
||||
link_design graph_test1
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 1.0 [get_ports d]
|
||||
set_output_delay -clock clk 1.0 [get_ports q]
|
||||
set_input_transition 0.1 [get_ports d]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_checks exercises graph traversal
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_checks baseline ---"
|
||||
report_checks
|
||||
puts "PASS: report_checks baseline"
|
||||
|
||||
puts "--- report_checks -path_delay min ---"
|
||||
report_checks -path_delay min
|
||||
puts "PASS: report_checks -path_delay min"
|
||||
|
||||
puts "--- report_checks -path_delay max ---"
|
||||
report_checks -path_delay max
|
||||
puts "PASS: report_checks -path_delay max"
|
||||
|
||||
puts "--- report_checks -from/-to ---"
|
||||
report_checks -from [get_ports d] -to [get_ports q]
|
||||
puts "PASS: report_checks -from/-to"
|
||||
|
||||
puts "--- report_checks -through ---"
|
||||
set rc [catch { report_checks -through [get_pins reg1/Q] } msg]
|
||||
if { $rc == 0 } {
|
||||
puts "PASS: report_checks -through"
|
||||
} else {
|
||||
puts "INFO: report_checks -through: $msg"
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Edge queries (Graph.cc edge functions)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- get_timing_edges full combinations ---"
|
||||
set edges_all [get_timing_edges -of_objects [get_cells reg1]]
|
||||
puts "reg1 all edges: [llength $edges_all]"
|
||||
|
||||
set edges_all2 [get_timing_edges -of_objects [get_cells reg2]]
|
||||
puts "reg2 all edges: [llength $edges_all2]"
|
||||
|
||||
puts "--- report_edges for cells ---"
|
||||
report_edges -from [get_pins reg1/CK] -to [get_pins reg1/Q]
|
||||
puts "PASS: report_edges reg1 CK->Q"
|
||||
|
||||
report_edges -from [get_pins reg2/CK] -to [get_pins reg2/Q]
|
||||
puts "PASS: report_edges reg2 CK->Q"
|
||||
|
||||
report_edges -from [get_pins reg1/CK]
|
||||
puts "PASS: report_edges from reg1/CK"
|
||||
|
||||
report_edges -to [get_pins reg2/D]
|
||||
puts "PASS: report_edges to reg2/D"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# set_disable_timing / report_disabled_edges exercises more paths
|
||||
#---------------------------------------------------------------
|
||||
puts "--- disable_timing on port pin ---"
|
||||
set_disable_timing -from CK -to Q [get_lib_cells NangateOpenCellLibrary/DFF_X1]
|
||||
report_disabled_edges
|
||||
puts "PASS: disabled CK->Q in lib cell"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report_checks after lib cell disable"
|
||||
|
||||
unset_disable_timing -from CK -to Q [get_lib_cells NangateOpenCellLibrary/DFF_X1]
|
||||
report_disabled_edges
|
||||
puts "PASS: unset lib cell disable"
|
||||
|
||||
puts "--- set_disable_timing instance and back ---"
|
||||
set_disable_timing [get_cells reg1]
|
||||
report_disabled_edges
|
||||
report_checks
|
||||
puts "PASS: instance disable"
|
||||
|
||||
unset_disable_timing [get_cells reg1]
|
||||
report_disabled_edges
|
||||
report_checks
|
||||
puts "PASS: instance unset disable"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Slew reporting (exercises vertex slew access)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_slews for various pins ---"
|
||||
report_slews [get_ports d]
|
||||
report_slews [get_ports q]
|
||||
report_slews [get_pins reg1/CK]
|
||||
report_slews [get_pins reg1/Q]
|
||||
report_slews [get_pins reg2/D]
|
||||
puts "PASS: report_slews various pins"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Graph verification
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_check_types ---"
|
||||
report_check_types -max_delay -min_delay -verbose
|
||||
puts "PASS: report_check_types"
|
||||
|
||||
puts "--- report_checks with -format ---"
|
||||
report_checks -format full_clock
|
||||
puts "PASS: report_checks -format full_clock"
|
||||
|
||||
puts "--- report_checks -unconstrained ---"
|
||||
report_checks -unconstrained
|
||||
puts "PASS: report_checks unconstrained"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Additional graph traversals (exercises more vertex/edge paths)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_checks -group_count 2 ---"
|
||||
report_checks -group_count 2
|
||||
puts "PASS: report_checks -group_count 2"
|
||||
|
||||
puts "--- report_checks -endpoint_count 2 ---"
|
||||
report_checks -endpoint_count 2
|
||||
puts "PASS: report_checks -endpoint_count 2"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
@ -0,0 +1,960 @@
|
|||
--- Test 1: graph with reconvergent paths ---
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v d1 (in)
|
||||
0.06 0.06 v buf1/Z (BUF_X1)
|
||||
0.05 0.10 v or1/ZN (OR2_X1)
|
||||
0.03 0.13 v and2/ZN (AND2_X1)
|
||||
0.00 0.13 v reg2/D (DFF_X1)
|
||||
0.13 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.13 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.83 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks
|
||||
Startpoint: d4 (input port clocked by clk)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ input external delay
|
||||
0.00 0.00 ^ d4 (in)
|
||||
0.01 0.01 v inv2/ZN (INV_X1)
|
||||
0.02 0.03 ^ nand1/ZN (NAND2_X1)
|
||||
0.02 0.05 ^ or2/ZN (OR2_X1)
|
||||
0.00 0.05 ^ reg3/D (DFF_X1)
|
||||
0.05 data arrival time
|
||||
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg3/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
---------------------------------------------------------
|
||||
0.00 data required time
|
||||
-0.05 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.05 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks min
|
||||
--- Test 2: path queries ---
|
||||
No paths found.
|
||||
PASS: d1->q1
|
||||
No paths found.
|
||||
PASS: d1->q2 (reconvergent)
|
||||
No paths found.
|
||||
PASS: d2->q1
|
||||
No paths found.
|
||||
PASS: d3->q3
|
||||
No paths found.
|
||||
PASS: d4->q3
|
||||
No paths found.
|
||||
PASS: d1->q4 (reconvergent)
|
||||
No paths found.
|
||||
PASS: d3->q4 (reconvergent)
|
||||
--- Test 3: report with fields ---
|
||||
Warning: graph_bidirect.tcl line 1, unknown field nets.
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
1 0.88 0.10 0.00 0.00 v d1 (in)
|
||||
0.10 0.00 0.00 v buf1/A (BUF_X1)
|
||||
2 1.67 0.01 0.06 0.06 v buf1/Z (BUF_X1)
|
||||
0.01 0.00 0.06 v or1/A1 (OR2_X1)
|
||||
2 1.96 0.01 0.05 0.10 v or1/ZN (OR2_X1)
|
||||
0.01 0.00 0.10 v and2/A2 (AND2_X1)
|
||||
1 1.06 0.01 0.03 0.13 v and2/ZN (AND2_X1)
|
||||
0.01 0.00 0.13 v reg2/D (DFF_X1)
|
||||
0.13 data arrival time
|
||||
|
||||
0.00 10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.13 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
9.83 slack (MET)
|
||||
|
||||
|
||||
PASS: report with all fields
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v d1 (in)
|
||||
0.06 0.06 v buf1/Z (BUF_X1)
|
||||
0.05 0.10 v or1/ZN (OR2_X1)
|
||||
0.03 0.13 v and2/ZN (AND2_X1)
|
||||
0.00 0.13 v reg2/D (DFF_X1)
|
||||
0.13 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.13 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.83 slack (MET)
|
||||
|
||||
|
||||
PASS: report full_clock
|
||||
Startpoint: d4 (input port clocked by clk)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
|
||||
Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ input external delay
|
||||
1.70 0.10 0.00 0.00 ^ d4 (in)
|
||||
3.07 0.02 0.01 0.01 v inv2/ZN (INV_X1)
|
||||
0.95 0.01 0.02 0.03 ^ nand1/ZN (NAND2_X1)
|
||||
1.14 0.01 0.02 0.05 ^ or2/ZN (OR2_X1)
|
||||
0.01 0.00 0.05 ^ reg3/D (DFF_X1)
|
||||
0.05 data arrival time
|
||||
|
||||
0.00 0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg3/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
-----------------------------------------------------------------------
|
||||
0.00 data required time
|
||||
-0.05 data arrival time
|
||||
-----------------------------------------------------------------------
|
||||
0.05 slack (MET)
|
||||
|
||||
|
||||
PASS: min with slew/cap fields
|
||||
--- Test 4: fanin/fanout ---
|
||||
fanin to q2: 3
|
||||
fanout from d1: 13
|
||||
fanin cells to q2: 2
|
||||
fanout cells from d1: 8
|
||||
fanin to q3: 3
|
||||
fanout from d3: 14
|
||||
--- Test 5: report_dcalc ---
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: BUF_X1
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Z ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.10
|
||||
| total_output_net_capacitance = 1.86
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.08 | 0.03 0.03
|
||||
0.13 | 0.03 0.04
|
||||
Table value = 0.03
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.03
|
||||
|
||||
------- input_net_transition = 0.10
|
||||
| total_output_net_capacitance = 1.86
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.08 | 0.01 0.01
|
||||
0.13 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Z v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.10
|
||||
| total_output_net_capacitance = 1.67
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.08 | 0.05 0.05
|
||||
0.13 | 0.06 0.07
|
||||
Table value = 0.06
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.06
|
||||
|
||||
------- input_net_transition = 0.10
|
||||
| total_output_net_capacitance = 1.67
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.08 | 0.01 0.01
|
||||
0.13 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
dcalc buf1: done
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: AND2_X1
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A1 ^ -> ZN ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 2.06
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.03 0.03
|
||||
0.02 | 0.03 0.04
|
||||
Table value = 0.03
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.03
|
||||
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 2.06
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.02 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
A1 v -> ZN v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 1.94
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.03 0.03
|
||||
0.02 | 0.03 0.04
|
||||
Table value = 0.03
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.03
|
||||
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 1.94
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.02 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
dcalc and1 A1: done
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: AND2_X1
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A2 ^ -> ZN ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 2.06
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.03 0.04
|
||||
0.02 | 0.03 0.04
|
||||
Table value = 0.03
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.03
|
||||
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 2.06
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.02 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
A2 v -> ZN v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 1.94
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.03 0.03
|
||||
0.02 | 0.04 0.04
|
||||
Table value = 0.03
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.03
|
||||
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 1.94
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.02 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
dcalc and1 A2: done
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: OR2_X1
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A1 ^ -> ZN ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 2.11
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.02 0.03
|
||||
0.02 | 0.03 0.03
|
||||
Table value = 0.02
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.02
|
||||
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 2.11
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.02 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
A1 v -> ZN v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 1.96
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.04 0.05
|
||||
0.02 | 0.05 0.05
|
||||
Table value = 0.05
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.05
|
||||
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 1.96
|
||||
| 1.89 3.79
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.02 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
dcalc or1 A1: done
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: NAND2_X1
|
||||
Arc sense: negative_unate
|
||||
Arc type: combinational
|
||||
A1 ^ -> ZN v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 0.79
|
||||
| 0.37 1.85
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.02 | 0.01 0.02
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.01
|
||||
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 0.79
|
||||
| 0.37 1.85
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.02 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
A1 v -> ZN ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 0.95
|
||||
| 0.37 1.85
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.02 | 0.01 0.02
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.01
|
||||
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 0.95
|
||||
| 0.37 1.85
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.02 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
dcalc nand1: done
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: NOR2_X1
|
||||
Arc sense: negative_unate
|
||||
Arc type: combinational
|
||||
A1 ^ -> ZN v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.02
|
||||
| total_output_net_capacitance = 0.90
|
||||
| 0.83 1.67
|
||||
v --------------------
|
||||
0.02 | 0.01 0.01
|
||||
0.04 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.01
|
||||
|
||||
------- input_net_transition = 0.02
|
||||
| total_output_net_capacitance = 0.90
|
||||
| 0.83 1.67
|
||||
v --------------------
|
||||
0.02 | 0.01 0.01
|
||||
0.04 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
A1 v -> ZN ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.02
|
||||
| total_output_net_capacitance = 0.94
|
||||
| 0.83 1.67
|
||||
v --------------------
|
||||
0.02 | 0.02 0.03
|
||||
0.04 | 0.03 0.04
|
||||
Table value = 0.02
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.02
|
||||
|
||||
------- input_net_transition = 0.02
|
||||
| total_output_net_capacitance = 0.94
|
||||
| 0.83 1.67
|
||||
v --------------------
|
||||
0.02 | 0.01 0.02
|
||||
0.04 | 0.02 0.02
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
dcalc nor1: done
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: DFF_X1
|
||||
Arc sense: non_unate
|
||||
Arc type: Reg Clk to Q
|
||||
CK ^ -> Q ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.08 0.09
|
||||
0.00 | 0.08 0.09
|
||||
Table value = 0.08
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.08
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.00 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
CK ^ -> Q v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.08 0.08
|
||||
0.00 | 0.08 0.08
|
||||
Table value = 0.08
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.08
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.00 | 0.01 0.01
|
||||
Table value = 0.00
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.00
|
||||
Driver waveform slew = 0.00
|
||||
|
||||
.............................................
|
||||
|
||||
dcalc reg1: done
|
||||
--- Test 6: network queries ---
|
||||
total pins: 50
|
||||
total nets: 19
|
||||
Net n1
|
||||
Pin capacitance: 1.67-1.86
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 1.67-1.86
|
||||
Number of drivers: 1
|
||||
Number of loads: 2
|
||||
Number of pins: 3
|
||||
|
||||
Driver pins
|
||||
buf1/Z output (BUF_X1)
|
||||
|
||||
Load pins
|
||||
and1/A1 input (AND2_X1) 0.87-0.92
|
||||
or1/A1 input (OR2_X1) 0.79-0.95
|
||||
|
||||
Net n2
|
||||
Pin capacitance: 2.42-2.57
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 2.42-2.57
|
||||
Number of drivers: 1
|
||||
Number of loads: 2
|
||||
Number of pins: 3
|
||||
|
||||
Driver pins
|
||||
buf2/Z output (BUF_X1)
|
||||
|
||||
Load pins
|
||||
and1/A2 input (AND2_X1) 0.89-0.97
|
||||
nand1/A1 input (NAND2_X1) 1.53-1.60
|
||||
|
||||
Net n3
|
||||
Pin capacitance: 2.31-2.66
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 2.31-2.66
|
||||
Number of drivers: 1
|
||||
Number of loads: 2
|
||||
Number of pins: 3
|
||||
|
||||
Driver pins
|
||||
inv1/ZN output (INV_X1)
|
||||
|
||||
Load pins
|
||||
nor1/A1 input (NOR2_X1) 1.41-1.71
|
||||
or1/A2 input (OR2_X1) 0.90-0.94
|
||||
|
||||
Net n4
|
||||
Pin capacitance: 3.07-3.32
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 3.07-3.32
|
||||
Number of drivers: 1
|
||||
Number of loads: 2
|
||||
Number of pins: 3
|
||||
|
||||
Driver pins
|
||||
inv2/ZN output (INV_X1)
|
||||
|
||||
Load pins
|
||||
nand1/A2 input (NAND2_X1) 1.50-1.66
|
||||
nor1/A2 input (NOR2_X1) 1.56-1.65
|
||||
|
||||
Net n5
|
||||
Pin capacitance: 1.94-2.06
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 1.94-2.06
|
||||
Number of drivers: 1
|
||||
Number of loads: 2
|
||||
Number of pins: 3
|
||||
|
||||
Driver pins
|
||||
and1/ZN output (AND2_X1)
|
||||
|
||||
Load pins
|
||||
and2/A1 input (AND2_X1) 0.87-0.92
|
||||
reg1/D input (DFF_X1) 1.06-1.14
|
||||
|
||||
Net n6
|
||||
Pin capacitance: 1.96-2.11
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 1.96-2.11
|
||||
Number of drivers: 1
|
||||
Number of loads: 2
|
||||
Number of pins: 3
|
||||
|
||||
Driver pins
|
||||
or1/ZN output (OR2_X1)
|
||||
|
||||
Load pins
|
||||
and2/A2 input (AND2_X1) 0.89-0.97
|
||||
reg4/D input (DFF_X1) 1.06-1.14
|
||||
|
||||
Net n7
|
||||
Pin capacitance: 0.79-0.95
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 0.79-0.95
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
nand1/ZN output (NAND2_X1)
|
||||
|
||||
Load pins
|
||||
or2/A1 input (OR2_X1) 0.79-0.95
|
||||
|
||||
Net n8
|
||||
Pin capacitance: 0.90-0.94
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 0.90-0.94
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
nor1/ZN output (NOR2_X1)
|
||||
|
||||
Load pins
|
||||
or2/A2 input (OR2_X1) 0.90-0.94
|
||||
|
||||
Net n9
|
||||
Pin capacitance: 1.06-1.14
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 1.06-1.14
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
and2/ZN output (AND2_X1)
|
||||
|
||||
Load pins
|
||||
reg2/D input (DFF_X1) 1.06-1.14
|
||||
|
||||
Net n10
|
||||
Pin capacitance: 1.06-1.14
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 1.06-1.14
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
or2/ZN output (OR2_X1)
|
||||
|
||||
Load pins
|
||||
reg3/D input (DFF_X1) 1.06-1.14
|
||||
|
||||
PASS: report_net all
|
||||
Instance buf1
|
||||
Cell: BUF_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: BUF_X1
|
||||
Input pins:
|
||||
A input d1
|
||||
Output pins:
|
||||
Z output n1
|
||||
Other pins:
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance buf2
|
||||
Cell: BUF_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: BUF_X1
|
||||
Input pins:
|
||||
A input d2
|
||||
Output pins:
|
||||
Z output n2
|
||||
Other pins:
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance inv1
|
||||
Cell: INV_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: INV_X1
|
||||
Input pins:
|
||||
A input d3
|
||||
Output pins:
|
||||
ZN output n3
|
||||
Other pins:
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance inv2
|
||||
Cell: INV_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: INV_X1
|
||||
Input pins:
|
||||
A input d4
|
||||
Output pins:
|
||||
ZN output n4
|
||||
Other pins:
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance and1
|
||||
Cell: AND2_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: AND2_X1
|
||||
Input pins:
|
||||
A1 input n1
|
||||
A2 input n2
|
||||
Output pins:
|
||||
ZN output n5
|
||||
Other pins:
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance or1
|
||||
Cell: OR2_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: OR2_X1
|
||||
Input pins:
|
||||
A1 input n1
|
||||
A2 input n3
|
||||
Output pins:
|
||||
ZN output n6
|
||||
Other pins:
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance nand1
|
||||
Cell: NAND2_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: NAND2_X1
|
||||
Input pins:
|
||||
A1 input n2
|
||||
A2 input n4
|
||||
Output pins:
|
||||
ZN output n7
|
||||
Other pins:
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance nor1
|
||||
Cell: NOR2_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: NOR2_X1
|
||||
Input pins:
|
||||
A1 input n3
|
||||
A2 input n4
|
||||
Output pins:
|
||||
ZN output n8
|
||||
Other pins:
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance and2
|
||||
Cell: AND2_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: AND2_X1
|
||||
Input pins:
|
||||
A1 input n5
|
||||
A2 input n6
|
||||
Output pins:
|
||||
ZN output n9
|
||||
Other pins:
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance or2
|
||||
Cell: OR2_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: OR2_X1
|
||||
Input pins:
|
||||
A1 input n7
|
||||
A2 input n8
|
||||
Output pins:
|
||||
ZN output n10
|
||||
Other pins:
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance reg1
|
||||
Cell: DFF_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: DFF_X1
|
||||
Input pins:
|
||||
D input n5
|
||||
CK input clk
|
||||
Output pins:
|
||||
Q output q1
|
||||
QN output (unconnected)
|
||||
Other pins:
|
||||
IQ internal (unconnected)
|
||||
IQN internal (unconnected)
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance reg2
|
||||
Cell: DFF_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: DFF_X1
|
||||
Input pins:
|
||||
D input n9
|
||||
CK input clk
|
||||
Output pins:
|
||||
Q output q2
|
||||
QN output (unconnected)
|
||||
Other pins:
|
||||
IQ internal (unconnected)
|
||||
IQN internal (unconnected)
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance reg3
|
||||
Cell: DFF_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: DFF_X1
|
||||
Input pins:
|
||||
D input n10
|
||||
CK input clk
|
||||
Output pins:
|
||||
Q output q3
|
||||
QN output (unconnected)
|
||||
Other pins:
|
||||
IQ internal (unconnected)
|
||||
IQN internal (unconnected)
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
Instance reg4
|
||||
Cell: DFF_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
Path cells: DFF_X1
|
||||
Input pins:
|
||||
D input n6
|
||||
CK input clk
|
||||
Output pins:
|
||||
Q output q4
|
||||
QN output (unconnected)
|
||||
Other pins:
|
||||
IQ internal (unconnected)
|
||||
IQN internal (unconnected)
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
PASS: report_instance all
|
||||
--- Test 7: modify graph ---
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v d1 (in)
|
||||
0.06 0.06 v buf1/Z (BUF_X1)
|
||||
0.05 0.10 v or1/ZN (OR2_X1)
|
||||
0.03 0.13 v and2/ZN (AND2_X1)
|
||||
0.00 0.13 v reg2/D (DFF_X1)
|
||||
0.13 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.13 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.83 slack (MET)
|
||||
|
||||
|
||||
PASS: report after add instance
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v d1 (in)
|
||||
0.06 0.06 v buf1/Z (BUF_X1)
|
||||
0.05 0.10 v or1/ZN (OR2_X1)
|
||||
0.03 0.13 v and2/ZN (AND2_X1)
|
||||
0.00 0.13 v reg2/D (DFF_X1)
|
||||
0.13 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.13 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.83 slack (MET)
|
||||
|
||||
|
||||
PASS: report after delete instance
|
||||
ALL PASSED
|
||||
|
|
@ -0,0 +1,171 @@
|
|||
# Test graph construction with bidirectional pins, reconvergent paths,
|
||||
# and various edge/vertex operations.
|
||||
# Targets: Graph.cc uncovered paths:
|
||||
# makePinVertices for bidirect pins (lines 425-427)
|
||||
# pinVertices for bidirect direction (lines 453-455)
|
||||
# pinDrvrVertex for bidirect (lines 463-464)
|
||||
# makePortInstanceEdges: bidirect from_bidirect_drvr_vertex path (lines 223-229)
|
||||
# makeWireEdgesFromPin with multiple drivers (lines 277-301)
|
||||
# hasFaninOne (line 507-511)
|
||||
# gateEdgeArc (line 544+)
|
||||
# deleteVertex (lines 476-504) via delete operations
|
||||
# isIsolatedNet (lines 309-331)
|
||||
# vertex/edge iterators
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog graph_bidirect.v
|
||||
link_design graph_bidirect
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 1: Graph construction and basic timing
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 1: graph with reconvergent paths ---"
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 0 [get_ports {d1 d2 d3 d4}]
|
||||
set_output_delay -clock clk 0 [get_ports {q1 q2 q3 q4}]
|
||||
set_input_transition 0.1 [get_ports {d1 d2 d3 d4 clk}]
|
||||
|
||||
report_checks
|
||||
puts "PASS: report_checks"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: report_checks min"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 2: Multiple path queries (exercises graph traversal)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 2: path queries ---"
|
||||
report_checks -from [get_ports d1] -to [get_ports q1]
|
||||
puts "PASS: d1->q1"
|
||||
|
||||
report_checks -from [get_ports d1] -to [get_ports q2]
|
||||
puts "PASS: d1->q2 (reconvergent)"
|
||||
|
||||
report_checks -from [get_ports d2] -to [get_ports q1]
|
||||
puts "PASS: d2->q1"
|
||||
|
||||
report_checks -from [get_ports d3] -to [get_ports q3]
|
||||
puts "PASS: d3->q3"
|
||||
|
||||
report_checks -from [get_ports d4] -to [get_ports q3]
|
||||
puts "PASS: d4->q3"
|
||||
|
||||
report_checks -from [get_ports d1] -to [get_ports q4]
|
||||
puts "PASS: d1->q4 (reconvergent)"
|
||||
|
||||
report_checks -from [get_ports d3] -to [get_ports q4]
|
||||
puts "PASS: d3->q4 (reconvergent)"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 3: Fields that exercise graph delay/slew queries
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 3: report with fields ---"
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: report with all fields"
|
||||
|
||||
report_checks -format full_clock
|
||||
puts "PASS: report full_clock"
|
||||
|
||||
report_checks -path_delay min -fields {slew cap}
|
||||
puts "PASS: min with slew/cap fields"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 4: Fanin/fanout queries through reconvergent paths
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 4: fanin/fanout ---"
|
||||
catch {
|
||||
set fi [get_fanin -to [get_ports q2] -flat]
|
||||
puts "fanin to q2: [llength $fi]"
|
||||
} msg
|
||||
|
||||
catch {
|
||||
set fo [get_fanout -from [get_ports d1] -flat]
|
||||
puts "fanout from d1: [llength $fo]"
|
||||
} msg
|
||||
|
||||
catch {
|
||||
set fi_cells [get_fanin -to [get_ports q2] -only_cells]
|
||||
puts "fanin cells to q2: [llength $fi_cells]"
|
||||
} msg
|
||||
|
||||
catch {
|
||||
set fo_cells [get_fanout -from [get_ports d1] -only_cells]
|
||||
puts "fanout cells from d1: [llength $fo_cells]"
|
||||
} msg
|
||||
|
||||
catch {
|
||||
set fi_q3 [get_fanin -to [get_ports q3] -flat]
|
||||
puts "fanin to q3: [llength $fi_q3]"
|
||||
} msg
|
||||
|
||||
catch {
|
||||
set fo_d3 [get_fanout -from [get_ports d3] -flat]
|
||||
puts "fanout from d3: [llength $fo_d3]"
|
||||
} msg
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 5: report_dcalc exercises graph edge arc queries
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 5: report_dcalc ---"
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "dcalc buf1: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins and1/A1] -to [get_pins and1/ZN] -max} msg
|
||||
puts "dcalc and1 A1: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins and1/A2] -to [get_pins and1/ZN] -max} msg
|
||||
puts "dcalc and1 A2: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins or1/A1] -to [get_pins or1/ZN] -max} msg
|
||||
puts "dcalc or1 A1: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins nand1/A1] -to [get_pins nand1/ZN] -max} msg
|
||||
puts "dcalc nand1: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins nor1/A1] -to [get_pins nor1/ZN] -max} msg
|
||||
puts "dcalc nor1: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max} msg
|
||||
puts "dcalc reg1: done"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 6: Graph vertex/edge counts
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 6: network queries ---"
|
||||
set all_pins [get_pins */*]
|
||||
puts "total pins: [llength $all_pins]"
|
||||
|
||||
set all_nets [get_nets *]
|
||||
puts "total nets: [llength $all_nets]"
|
||||
|
||||
foreach net_name {n1 n2 n3 n4 n5 n6 n7 n8 n9 n10} {
|
||||
catch {report_net $net_name} msg
|
||||
}
|
||||
puts "PASS: report_net all"
|
||||
|
||||
foreach inst_name {buf1 buf2 inv1 inv2 and1 or1 nand1 nor1 and2 or2 reg1 reg2 reg3 reg4} {
|
||||
report_instance $inst_name
|
||||
}
|
||||
puts "PASS: report_instance all"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 7: Add and remove instances (exercises deleteVertex, graph modify)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 7: modify graph ---"
|
||||
set new_net [make_net test_net]
|
||||
set new_inst [make_instance test_buf BUF_X1]
|
||||
connect_pin test_net test_buf/A
|
||||
|
||||
report_checks
|
||||
puts "PASS: report after add instance"
|
||||
|
||||
disconnect_pin test_net test_buf/A
|
||||
delete_instance test_buf
|
||||
delete_net test_net
|
||||
|
||||
report_checks
|
||||
puts "PASS: report after delete instance"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
// Design with bidirectional ports and reconvergent paths
|
||||
// for testing graph bidirect vertex/edge handling
|
||||
module graph_bidirect (clk, d1, d2, d3, d4, q1, q2, q3, q4);
|
||||
input clk, d1, d2, d3, d4;
|
||||
output q1, q2, q3, q4;
|
||||
wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10;
|
||||
|
||||
// Fan-out from d1 and d2
|
||||
BUF_X1 buf1 (.A(d1), .Z(n1));
|
||||
BUF_X1 buf2 (.A(d2), .Z(n2));
|
||||
INV_X1 inv1 (.A(d3), .ZN(n3));
|
||||
INV_X1 inv2 (.A(d4), .ZN(n4));
|
||||
|
||||
// Reconvergent logic
|
||||
AND2_X1 and1 (.A1(n1), .A2(n2), .ZN(n5));
|
||||
OR2_X1 or1 (.A1(n1), .A2(n3), .ZN(n6));
|
||||
NAND2_X1 nand1 (.A1(n2), .A2(n4), .ZN(n7));
|
||||
NOR2_X1 nor1 (.A1(n3), .A2(n4), .ZN(n8));
|
||||
|
||||
// Second level reconvergence
|
||||
AND2_X1 and2 (.A1(n5), .A2(n6), .ZN(n9));
|
||||
OR2_X1 or2 (.A1(n7), .A2(n8), .ZN(n10));
|
||||
|
||||
// Registers
|
||||
DFF_X1 reg1 (.D(n5), .CK(clk), .Q(q1));
|
||||
DFF_X1 reg2 (.D(n9), .CK(clk), .Q(q2));
|
||||
DFF_X1 reg3 (.D(n10), .CK(clk), .Q(q3));
|
||||
DFF_X1 reg4 (.D(n6), .CK(clk), .Q(q4));
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,190 @@
|
|||
# Test graph delay value comparison and multi-corner graph operations.
|
||||
# Targets: DelayFloat.cc (87.8% -> delayLess with min_max, delayGreater,
|
||||
# delayGreaterEqual, delayLessEqual, delayRemove, delayRatio, delayZero,
|
||||
# delayInf, delayInitValue, delayIsInitValue)
|
||||
# Graph.cc (71.2% -> multi-corner vertex/edge access, clock vertices)
|
||||
# GraphCmp.cc (90.5% -> sortEdges with multiple edges)
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multi-corner setup for graph coverage
|
||||
#---------------------------------------------------------------
|
||||
define_corners fast slow
|
||||
|
||||
read_liberty -corner fast ../../test/nangate45/Nangate45_fast.lib
|
||||
read_liberty -corner slow ../../test/nangate45/Nangate45_slow.lib
|
||||
|
||||
read_verilog graph_test2.v
|
||||
link_design graph_test2
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 1.0 [get_ports {d1 d2 en}]
|
||||
set_output_delay -clock clk 1.0 [get_ports {q1 q2}]
|
||||
set_input_transition 0.1 [get_ports {d1 d2 en}]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multi-corner timing reports (exercises delay value comparison
|
||||
# across min/max analysis points in Graph)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- fast corner ---"
|
||||
report_checks -corner fast
|
||||
puts "PASS: fast corner"
|
||||
|
||||
report_checks -corner fast -path_delay min
|
||||
puts "PASS: fast corner min"
|
||||
|
||||
report_checks -corner fast -path_delay max
|
||||
puts "PASS: fast corner max"
|
||||
|
||||
puts "--- slow corner ---"
|
||||
report_checks -corner slow
|
||||
puts "PASS: slow corner"
|
||||
|
||||
report_checks -corner slow -path_delay min
|
||||
puts "PASS: slow corner min"
|
||||
|
||||
report_checks -corner slow -path_delay max
|
||||
puts "PASS: slow corner max"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multi-corner report_dcalc (exercises delay subtraction/comparison)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_dcalc per corner ---"
|
||||
catch {report_dcalc -corner fast -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
|
||||
puts "fast buf1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
|
||||
puts "slow buf1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner fast -from [get_pins inv1/A] -to [get_pins inv1/ZN]} msg
|
||||
puts "fast inv1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins inv1/A] -to [get_pins inv1/ZN]} msg
|
||||
puts "slow inv1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner fast -from [get_pins and1/A1] -to [get_pins and1/ZN]} msg
|
||||
puts "fast and1 A1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins and1/A1] -to [get_pins and1/ZN]} msg
|
||||
puts "slow and1 A1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner fast -from [get_pins or1/A1] -to [get_pins or1/ZN]} msg
|
||||
puts "fast or1 A1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins or1/A1] -to [get_pins or1/ZN]} msg
|
||||
puts "slow or1 A1 dcalc: done"
|
||||
|
||||
# DFF arcs
|
||||
catch {report_dcalc -corner fast -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max} msg
|
||||
puts "fast reg1 CK->Q: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max} msg
|
||||
puts "slow reg1 CK->Q: done"
|
||||
|
||||
catch {report_dcalc -corner fast -from [get_pins reg1/CK] -to [get_pins reg1/D] -max} msg
|
||||
puts "fast reg1 setup: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins reg1/CK] -to [get_pins reg1/D] -min} msg
|
||||
puts "slow reg1 hold: done"
|
||||
|
||||
puts "PASS: report_dcalc per corner"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_checks with fields across corners (exercises graph slew access)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_checks with fields ---"
|
||||
report_checks -corner fast -fields {slew cap input_pins}
|
||||
puts "PASS: fast fields"
|
||||
|
||||
report_checks -corner slow -fields {slew cap input_pins}
|
||||
puts "PASS: slow fields"
|
||||
|
||||
report_checks -corner fast -format full_clock
|
||||
puts "PASS: fast full_clock"
|
||||
|
||||
report_checks -corner slow -format full_clock
|
||||
puts "PASS: slow full_clock"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multi-corner paths (different paths in fast vs slow)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- multi-corner paths ---"
|
||||
report_checks -corner fast -from [get_ports d1] -to [get_ports q1]
|
||||
puts "PASS: fast d1->q1"
|
||||
|
||||
report_checks -corner slow -from [get_ports d1] -to [get_ports q1]
|
||||
puts "PASS: slow d1->q1"
|
||||
|
||||
report_checks -corner fast -from [get_ports d2] -to [get_ports q2]
|
||||
puts "PASS: fast d2->q2"
|
||||
|
||||
report_checks -corner slow -from [get_ports d2] -to [get_ports q2]
|
||||
puts "PASS: slow d2->q2"
|
||||
|
||||
report_checks -corner fast -from [get_ports en] -to [get_ports q1]
|
||||
puts "PASS: fast en->q1"
|
||||
|
||||
report_checks -corner slow -from [get_ports en] -to [get_ports q1]
|
||||
puts "PASS: slow en->q1"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Edge queries with multi-corner
|
||||
#---------------------------------------------------------------
|
||||
puts "--- timing edges multi-corner ---"
|
||||
set e1 [get_timing_edges -of_objects [get_cells and1]]
|
||||
puts "and1 edges: [llength $e1]"
|
||||
|
||||
set e2 [get_timing_edges -of_objects [get_cells or1]]
|
||||
puts "or1 edges: [llength $e2]"
|
||||
|
||||
set e3 [get_timing_edges -of_objects [get_cells reg1]]
|
||||
puts "reg1 edges: [llength $e3]"
|
||||
|
||||
report_edges -from [get_pins and1/A1] -to [get_pins and1/ZN]
|
||||
report_edges -from [get_pins and1/A2] -to [get_pins and1/ZN]
|
||||
report_edges -from [get_pins or1/A1] -to [get_pins or1/ZN]
|
||||
report_edges -from [get_pins or1/A2] -to [get_pins or1/ZN]
|
||||
puts "PASS: timing edges multi-corner"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Load changes with multi-corner (exercises delay recomputation)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- load changes multi-corner ---"
|
||||
set_load 0.01 [get_ports q1]
|
||||
set_load 0.05 [get_ports q2]
|
||||
|
||||
report_checks -corner fast
|
||||
puts "PASS: fast after load change"
|
||||
|
||||
report_checks -corner slow
|
||||
puts "PASS: slow after load change"
|
||||
|
||||
set_load 0 [get_ports q1]
|
||||
set_load 0 [get_ports q2]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_checks -unconstrained multi-corner
|
||||
#---------------------------------------------------------------
|
||||
puts "--- unconstrained multi-corner ---"
|
||||
report_checks -corner fast -unconstrained
|
||||
puts "PASS: fast unconstrained"
|
||||
|
||||
report_checks -corner slow -unconstrained
|
||||
puts "PASS: slow unconstrained"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Disable/enable with multi-corner
|
||||
#---------------------------------------------------------------
|
||||
puts "--- disable with multi-corner ---"
|
||||
set_disable_timing [get_cells buf1]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
puts "PASS: disable buf1 multi-corner"
|
||||
|
||||
unset_disable_timing [get_cells buf1]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
puts "PASS: enable buf1 multi-corner"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
@ -0,0 +1,751 @@
|
|||
--- Test 1: baseline ---
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: baseline max
|
||||
Startpoint: d3 (input port clocked by clk)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 ^ input external delay
|
||||
0.00 1.00 ^ d3 (in)
|
||||
0.01 1.01 v inv1/ZN (INV_X1)
|
||||
0.03 1.04 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 1.04 ^ reg3/D (DFF_X1)
|
||||
1.04 data arrival time
|
||||
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg3/CK (DFF_X1)
|
||||
0.01 0.01 library hold time
|
||||
0.01 data required time
|
||||
---------------------------------------------------------
|
||||
0.01 data required time
|
||||
-1.04 data arrival time
|
||||
---------------------------------------------------------
|
||||
1.03 slack (MET)
|
||||
|
||||
|
||||
PASS: baseline min
|
||||
Warning: graph_delete_modify.tcl line 1, unknown field nets.
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
1 0.88 0.10 0.00 1.00 v d2 (in)
|
||||
0.10 0.00 1.00 v buf2/A (BUF_X1)
|
||||
2 1.69 0.01 0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.01 0.00 1.06 v or1/A1 (OR2_X1)
|
||||
2 2.56 0.01 0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.01 0.00 1.11 v nand1/A2 (NAND2_X1)
|
||||
1 1.14 0.01 0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.01 0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
0.00 10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: baseline fields
|
||||
--- Test 2: add/delete multiple instances ---
|
||||
PASS: added buffer chain
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing after add chain
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing after partial disconnect
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing after reconnect
|
||||
PASS: full cleanup
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing after full cleanup
|
||||
--- Test 3: replace_cell ---
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
A -> Z combinational
|
||||
^ -> ^ 0.03:0.03
|
||||
v -> v 0.05:0.05
|
||||
PASS: buf1 -> BUF_X4
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: buf1 -> BUF_X2
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: buf1 restored
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: and1 -> AND2_X2
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: and1 restored
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: inv1 -> INV_X2
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: inv1 restored
|
||||
--- Test 4: add/delete register ---
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing with added register
|
||||
PASS: register removed
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing after register removal
|
||||
--- Test 5: rapid connect/disconnect ---
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
cycle 1 done
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
cycle 2 done
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
cycle 3 done
|
||||
PASS: rapid cycles
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing after rapid cycles
|
||||
--- Test 6: edge queries ---
|
||||
buf1 edges: 1
|
||||
buf2 edges: 1
|
||||
inv1 edges: 1
|
||||
and1 edges: 1
|
||||
or1 edges: 1
|
||||
nand1 edges: 1
|
||||
nor1 edges: 1
|
||||
reg1 edges: 1
|
||||
reg2 edges: 1
|
||||
reg3 edges: 1
|
||||
reg4 edges: 1
|
||||
PASS: edge queries
|
||||
d1 ^ 0.10:0.10 v 0.10:0.10
|
||||
d2 ^ 0.10:0.10 v 0.10:0.10
|
||||
d3 ^ 0.10:0.10 v 0.10:0.10
|
||||
buf1/Z ^ 0.01:0.01 v 0.01:0.01
|
||||
and1/ZN ^ 0.01:0.01 v 0.01:0.01
|
||||
reg1/Q ^ 0.01:0.01 v 0.00:0.00
|
||||
PASS: slew queries
|
||||
--- Test 7: through pins ---
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
through nand1: done
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.04 1.09 v and1/ZN (AND2_X1)
|
||||
0.02 1.11 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 1.11 ^ reg3/D (DFF_X1)
|
||||
1.11 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg3/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.11 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
through nor1: done
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.04 1.09 v and1/ZN (AND2_X1)
|
||||
0.02 1.11 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 1.11 ^ reg3/D (DFF_X1)
|
||||
1.11 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg3/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.11 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
through and1: done
|
||||
PASS: through pin queries
|
||||
ALL PASSED
|
||||
|
|
@ -0,0 +1,218 @@
|
|||
# Test graph modification: add/delete vertices via connect_pin/disconnect_pin,
|
||||
# delete_instance, replace_cell, and repeated graph rebuild.
|
||||
# Targets:
|
||||
# Graph.cc: deleteVertex (lines 476-504), deleteInEdge, deleteOutEdge,
|
||||
# makePinVertices, makeVertex, makeWireEdgesFromPin (multi-driver),
|
||||
# hasFaninOne, makeInstEdges after replace_cell,
|
||||
# removeWireEdge, removeInstEdge on disconnect/reconnect,
|
||||
# reg_clk_vertices_ insert/erase on add/delete reg
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog graph_delete_modify.v
|
||||
link_design graph_delete_modify
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 1.0 [get_ports {d1 d2 d3 rst}]
|
||||
set_output_delay -clock clk 1.0 [get_ports {q1 q2 q3 q4}]
|
||||
set_input_transition 0.1 [get_ports {d1 d2 d3 rst clk}]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 1: Baseline timing
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 1: baseline ---"
|
||||
report_checks
|
||||
puts "PASS: baseline max"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: baseline min"
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: baseline fields"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 2: Add multiple instances and nets, then delete
|
||||
# Exercises: makeVertex, makeWireEdgesFromPin, deleteVertex,
|
||||
# deleteInEdge, deleteOutEdge
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 2: add/delete multiple instances ---"
|
||||
|
||||
# Add a buffer chain
|
||||
set net_a [make_net test_net_a]
|
||||
set net_b [make_net test_net_b]
|
||||
set net_c [make_net test_net_c]
|
||||
set inst_a [make_instance test_buf_a NangateOpenCellLibrary/BUF_X1]
|
||||
set inst_b [make_instance test_buf_b NangateOpenCellLibrary/BUF_X2]
|
||||
|
||||
connect_pin test_net_a test_buf_a/A
|
||||
connect_pin test_net_b test_buf_a/Z
|
||||
connect_pin test_net_b test_buf_b/A
|
||||
connect_pin test_net_c test_buf_b/Z
|
||||
puts "PASS: added buffer chain"
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing after add chain"
|
||||
|
||||
# Disconnect middle and verify
|
||||
disconnect_pin test_net_b test_buf_b/A
|
||||
report_checks
|
||||
puts "PASS: timing after partial disconnect"
|
||||
|
||||
# Reconnect
|
||||
connect_pin test_net_b test_buf_b/A
|
||||
report_checks
|
||||
puts "PASS: timing after reconnect"
|
||||
|
||||
# Full cleanup
|
||||
disconnect_pin test_net_a test_buf_a/A
|
||||
disconnect_pin test_net_b test_buf_a/Z
|
||||
disconnect_pin test_net_b test_buf_b/A
|
||||
disconnect_pin test_net_c test_buf_b/Z
|
||||
delete_instance test_buf_a
|
||||
delete_instance test_buf_b
|
||||
delete_net test_net_a
|
||||
delete_net test_net_b
|
||||
delete_net test_net_c
|
||||
puts "PASS: full cleanup"
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing after full cleanup"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 3: Replace cell multiple times
|
||||
# Exercises: makeInstEdges rebuild, edge arc changes
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 3: replace_cell ---"
|
||||
|
||||
replace_cell buf1 NangateOpenCellLibrary/BUF_X4
|
||||
report_checks
|
||||
report_edges -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
puts "PASS: buf1 -> BUF_X4"
|
||||
|
||||
replace_cell buf1 NangateOpenCellLibrary/BUF_X2
|
||||
report_checks
|
||||
puts "PASS: buf1 -> BUF_X2"
|
||||
|
||||
replace_cell buf1 NangateOpenCellLibrary/BUF_X1
|
||||
report_checks
|
||||
puts "PASS: buf1 restored"
|
||||
|
||||
replace_cell and1 NangateOpenCellLibrary/AND2_X2
|
||||
report_checks
|
||||
puts "PASS: and1 -> AND2_X2"
|
||||
|
||||
replace_cell and1 NangateOpenCellLibrary/AND2_X1
|
||||
report_checks
|
||||
puts "PASS: and1 restored"
|
||||
|
||||
replace_cell inv1 NangateOpenCellLibrary/INV_X2
|
||||
report_checks
|
||||
puts "PASS: inv1 -> INV_X2"
|
||||
|
||||
replace_cell inv1 NangateOpenCellLibrary/INV_X1
|
||||
report_checks
|
||||
puts "PASS: inv1 restored"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 4: Add and delete register instances
|
||||
# Exercises: reg_clk_vertices_ insert/erase in makeVertex/deleteVertex
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 4: add/delete register ---"
|
||||
|
||||
set reg_net [make_net reg_test_net]
|
||||
set reg_qnet [make_net reg_test_qnet]
|
||||
set reg_inst [make_instance test_reg NangateOpenCellLibrary/DFF_X1]
|
||||
|
||||
connect_pin reg_test_net test_reg/D
|
||||
connect_pin reg_test_qnet test_reg/Q
|
||||
|
||||
# Connect clock to new register
|
||||
set clk_net_name "clk"
|
||||
catch {connect_pin $clk_net_name test_reg/CK} msg
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing with added register"
|
||||
|
||||
# Remove the register
|
||||
catch {disconnect_pin $clk_net_name test_reg/CK} msg
|
||||
disconnect_pin reg_test_net test_reg/D
|
||||
disconnect_pin reg_test_qnet test_reg/Q
|
||||
delete_instance test_reg
|
||||
delete_net reg_test_net
|
||||
delete_net reg_test_qnet
|
||||
puts "PASS: register removed"
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing after register removal"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 5: Rapid connect/disconnect on same pin
|
||||
# Exercises: edge create/delete cycling
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 5: rapid connect/disconnect ---"
|
||||
|
||||
set tmp_net [make_net tmp_net]
|
||||
set tmp_inst [make_instance tmp_buf NangateOpenCellLibrary/BUF_X1]
|
||||
|
||||
# Cycle 1
|
||||
connect_pin tmp_net tmp_buf/A
|
||||
report_checks
|
||||
disconnect_pin tmp_net tmp_buf/A
|
||||
puts "cycle 1 done"
|
||||
|
||||
# Cycle 2
|
||||
connect_pin tmp_net tmp_buf/A
|
||||
report_checks
|
||||
disconnect_pin tmp_net tmp_buf/A
|
||||
puts "cycle 2 done"
|
||||
|
||||
# Cycle 3
|
||||
connect_pin tmp_net tmp_buf/A
|
||||
report_checks
|
||||
disconnect_pin tmp_net tmp_buf/A
|
||||
puts "cycle 3 done"
|
||||
|
||||
delete_instance tmp_buf
|
||||
delete_net tmp_net
|
||||
puts "PASS: rapid cycles"
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing after rapid cycles"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 6: Edge queries after all modifications
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 6: edge queries ---"
|
||||
|
||||
foreach cell_name {buf1 buf2 inv1 and1 or1 nand1 nor1 reg1 reg2 reg3 reg4} {
|
||||
set edges [get_timing_edges -of_objects [get_cells $cell_name]]
|
||||
puts "$cell_name edges: [llength $edges]"
|
||||
}
|
||||
puts "PASS: edge queries"
|
||||
|
||||
# Slew queries
|
||||
report_slews [get_ports d1]
|
||||
report_slews [get_ports d2]
|
||||
report_slews [get_ports d3]
|
||||
report_slews [get_pins buf1/Z]
|
||||
report_slews [get_pins and1/ZN]
|
||||
report_slews [get_pins reg1/Q]
|
||||
puts "PASS: slew queries"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 7: Through-pin paths
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 7: through pins ---"
|
||||
catch {report_checks -through [get_pins nand1/ZN]} msg
|
||||
puts "through nand1: done"
|
||||
|
||||
catch {report_checks -through [get_pins nor1/ZN]} msg
|
||||
puts "through nor1: done"
|
||||
|
||||
catch {report_checks -through [get_pins and1/ZN]} msg
|
||||
puts "through and1: done"
|
||||
|
||||
puts "PASS: through pin queries"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
// Design for testing graph delete/modify operations:
|
||||
// makeVertex/deleteVertex through connect_pin/disconnect_pin/delete_instance,
|
||||
// replace_cell with different pin counts, multi-fanout nets,
|
||||
// and reconvergent paths that exercise edge deletion.
|
||||
module graph_delete_modify (clk, d1, d2, d3, rst, q1, q2, q3, q4);
|
||||
input clk, d1, d2, d3, rst;
|
||||
output q1, q2, q3, q4;
|
||||
wire n1, n2, n3, n4, n5, n6, n7, n8;
|
||||
|
||||
// Chain: d1 -> buf1 -> n1 -> and1 -> n5
|
||||
BUF_X1 buf1 (.A(d1), .Z(n1));
|
||||
// Chain: d2 -> buf2 -> n2 -> and1, or1 (multi-fanout)
|
||||
BUF_X1 buf2 (.A(d2), .Z(n2));
|
||||
// Chain: d3 -> inv1 -> n3 -> or1
|
||||
INV_X1 inv1 (.A(d3), .ZN(n3));
|
||||
|
||||
AND2_X1 and1 (.A1(n1), .A2(n2), .ZN(n5));
|
||||
OR2_X1 or1 (.A1(n2), .A2(n3), .ZN(n6));
|
||||
|
||||
// Second stage
|
||||
NAND2_X1 nand1 (.A1(n5), .A2(n6), .ZN(n7));
|
||||
NOR2_X1 nor1 (.A1(n5), .A2(n3), .ZN(n8));
|
||||
|
||||
// Registers with reset
|
||||
DFF_X1 reg1 (.D(n5), .CK(clk), .Q(q1));
|
||||
DFF_X1 reg2 (.D(n7), .CK(clk), .Q(q2));
|
||||
DFF_X1 reg3 (.D(n8), .CK(clk), .Q(q3));
|
||||
DFF_X1 reg4 (.D(n6), .CK(clk), .Q(q4));
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,225 @@
|
|||
# Test graph incremental changes, constant propagation, and level reporting.
|
||||
# Targets: Graph.cc (71.2% -> constant propagation, remove/add edges,
|
||||
# setSlew, pinDrvrVertex, pinLoadVertex, hasDownstreamClkPin, etc.)
|
||||
# GraphCmp.cc (90.5% -> EdgeLess, sortEdges, VertexNameLess)
|
||||
# DelayFloat.cc (87.8% -> delayLess with min_max, delayGreater, etc.)
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog graph_test2.v
|
||||
link_design graph_test2
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 1.0 [get_ports d1]
|
||||
set_input_delay -clock clk 1.0 [get_ports d2]
|
||||
set_input_delay -clock clk 0 [get_ports en]
|
||||
set_output_delay -clock clk 1.0 [get_ports q1]
|
||||
set_output_delay -clock clk 1.0 [get_ports q2]
|
||||
set_input_transition 0.1 [get_ports {d1 d2 en}]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Baseline timing
|
||||
#---------------------------------------------------------------
|
||||
puts "--- baseline report_checks ---"
|
||||
report_checks
|
||||
puts "PASS: baseline report_checks"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: baseline min"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: baseline max"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multiple paths through design
|
||||
#---------------------------------------------------------------
|
||||
puts "--- multiple paths ---"
|
||||
report_checks -from [get_ports d1] -to [get_ports q1]
|
||||
puts "PASS: d1->q1"
|
||||
|
||||
report_checks -from [get_ports d1] -to [get_ports q2]
|
||||
puts "PASS: d1->q2"
|
||||
|
||||
report_checks -from [get_ports d2] -to [get_ports q2]
|
||||
puts "PASS: d2->q2"
|
||||
|
||||
report_checks -from [get_ports en] -to [get_ports q1]
|
||||
puts "PASS: en->q1"
|
||||
|
||||
report_checks -from [get_ports en] -to [get_ports q2]
|
||||
puts "PASS: en->q2"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# -through paths (exercises graph traversal)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- through paths ---"
|
||||
catch { report_checks -through [get_pins inv1/ZN] } msg
|
||||
puts "through inv1/ZN: done"
|
||||
puts "PASS: through inv1/ZN"
|
||||
|
||||
catch { report_checks -through [get_pins and1/ZN] } msg
|
||||
puts "through and1/ZN: done"
|
||||
puts "PASS: through and1/ZN"
|
||||
|
||||
catch { report_checks -through [get_pins or1/ZN] } msg
|
||||
puts "through or1/ZN: done"
|
||||
puts "PASS: through or1/ZN"
|
||||
|
||||
catch { report_checks -through [get_pins buf3/Z] } msg
|
||||
puts "through buf3/Z: done"
|
||||
puts "PASS: through buf3/Z"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Timing edge queries for multi-input cells
|
||||
#---------------------------------------------------------------
|
||||
puts "--- timing edges for multi-input cells ---"
|
||||
set edges_and [get_timing_edges -of_objects [get_cells and1]]
|
||||
puts "and1 edges: [llength $edges_and]"
|
||||
|
||||
set edges_or [get_timing_edges -of_objects [get_cells or1]]
|
||||
puts "or1 edges: [llength $edges_or]"
|
||||
|
||||
set edges_reg1 [get_timing_edges -of_objects [get_cells reg1]]
|
||||
puts "reg1 edges: [llength $edges_reg1]"
|
||||
|
||||
set edges_reg2 [get_timing_edges -of_objects [get_cells reg2]]
|
||||
puts "reg2 edges: [llength $edges_reg2]"
|
||||
|
||||
# From/to specific pins
|
||||
set edges_ft [get_timing_edges -from [get_pins and1/A1] -to [get_pins and1/ZN]]
|
||||
puts "and1 A1->ZN edges: [llength $edges_ft]"
|
||||
|
||||
set edges_ft2 [get_timing_edges -from [get_pins and1/A2] -to [get_pins and1/ZN]]
|
||||
puts "and1 A2->ZN edges: [llength $edges_ft2]"
|
||||
|
||||
set edges_ft3 [get_timing_edges -from [get_pins or1/A1] -to [get_pins or1/ZN]]
|
||||
puts "or1 A1->ZN edges: [llength $edges_ft3]"
|
||||
|
||||
puts "PASS: timing edge queries"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_edges for various pin combinations
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_edges ---"
|
||||
report_edges -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
puts "PASS: report_edges buf1"
|
||||
|
||||
report_edges -from [get_pins inv1/A] -to [get_pins inv1/ZN]
|
||||
puts "PASS: report_edges inv1"
|
||||
|
||||
report_edges -from [get_pins and1/A1]
|
||||
puts "PASS: report_edges from and1/A1"
|
||||
|
||||
report_edges -to [get_pins and1/ZN]
|
||||
puts "PASS: report_edges to and1/ZN"
|
||||
|
||||
report_edges -from [get_ports d1]
|
||||
puts "PASS: report_edges from port d1"
|
||||
|
||||
report_edges -to [get_ports q2]
|
||||
puts "PASS: report_edges to port q2"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Constant propagation via set_case_analysis
|
||||
#---------------------------------------------------------------
|
||||
puts "--- set_case_analysis ---"
|
||||
set_case_analysis 1 [get_ports en]
|
||||
report_checks
|
||||
puts "PASS: report_checks en=1"
|
||||
|
||||
report_checks -from [get_ports d1] -to [get_ports q1]
|
||||
puts "PASS: d1->q1 with en=1"
|
||||
|
||||
# Change constant value
|
||||
set_case_analysis 0 [get_ports en]
|
||||
report_checks
|
||||
puts "PASS: report_checks en=0"
|
||||
|
||||
# Remove case analysis
|
||||
unset_case_analysis [get_ports en]
|
||||
report_checks
|
||||
puts "PASS: report_checks after unset_case_analysis"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Disable/enable timing with multiple cells
|
||||
#---------------------------------------------------------------
|
||||
puts "--- disable/enable timing multiple cells ---"
|
||||
set_disable_timing [get_cells buf1]
|
||||
report_checks
|
||||
puts "PASS: disable buf1"
|
||||
|
||||
set_disable_timing [get_cells inv1]
|
||||
report_checks
|
||||
puts "PASS: disable buf1+inv1"
|
||||
|
||||
unset_disable_timing [get_cells buf1]
|
||||
report_checks
|
||||
puts "PASS: enable buf1"
|
||||
|
||||
unset_disable_timing [get_cells inv1]
|
||||
report_checks
|
||||
puts "PASS: enable inv1"
|
||||
|
||||
# Disable specific lib cell arc
|
||||
set_disable_timing -from A -to Z [get_lib_cells NangateOpenCellLibrary/BUF_X1]
|
||||
report_disabled_edges
|
||||
report_checks
|
||||
puts "PASS: disable lib cell arc"
|
||||
|
||||
unset_disable_timing -from A -to Z [get_lib_cells NangateOpenCellLibrary/BUF_X1]
|
||||
report_disabled_edges
|
||||
report_checks
|
||||
puts "PASS: unset lib cell arc"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_check_types
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_check_types ---"
|
||||
report_check_types -max_delay -verbose
|
||||
puts "PASS: report_check_types max_delay"
|
||||
|
||||
report_check_types -min_delay -verbose
|
||||
puts "PASS: report_check_types min_delay"
|
||||
|
||||
report_check_types -max_delay -min_delay -verbose
|
||||
puts "PASS: report_check_types max+min"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Report slews for various pins
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_slews ---"
|
||||
report_slews [get_ports d1]
|
||||
report_slews [get_ports d2]
|
||||
report_slews [get_ports en]
|
||||
report_slews [get_ports q1]
|
||||
report_slews [get_ports q2]
|
||||
report_slews [get_pins buf1/Z]
|
||||
report_slews [get_pins inv1/ZN]
|
||||
report_slews [get_pins and1/ZN]
|
||||
report_slews [get_pins or1/ZN]
|
||||
report_slews [get_pins reg1/Q]
|
||||
report_slews [get_pins reg2/Q]
|
||||
puts "PASS: report_slews various pins"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_checks with -unconstrained
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_checks -unconstrained ---"
|
||||
report_checks -unconstrained
|
||||
puts "PASS: report_checks unconstrained"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_checks with group_count and endpoint_count
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_checks counts ---"
|
||||
report_checks -group_count 3
|
||||
puts "PASS: group_count 3"
|
||||
|
||||
report_checks -endpoint_count 3
|
||||
puts "PASS: endpoint_count 3"
|
||||
|
||||
report_checks -endpoint_count 5 -path_delay min
|
||||
puts "PASS: endpoint_count 5 min"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
No paths found.
|
||||
PASS: graph created and timing reported
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
# Read liberty and design, make graph, verify
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog graph_test1.v
|
||||
link_design graph_test1
|
||||
|
||||
# Creating the timing graph implicitly tests graph construction
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
|
||||
# report_checks exercises the graph
|
||||
report_checks -from [get_ports d] -to [get_ports q]
|
||||
puts "PASS: graph created and timing reported"
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,290 @@
|
|||
# Test graph changes with network modifications, multi-corner, and
|
||||
# incremental graph updates.
|
||||
# Targets: Graph.cc (deleteVertexBefore, addEdge, removeEdge,
|
||||
# makeWireEdge, removeWireEdge, pinVertex, pinDrvrVertex,
|
||||
# pinLoadVertex, setConstant, clearConstants, hasDownstreamClkPin,
|
||||
# widthCheckAnnotation, periodCheckAnnotation, regClkVertices, isRegClk)
|
||||
# GraphCmp.cc (sortEdges, VertexNameLess with added/removed vertices)
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multi-corner setup
|
||||
#---------------------------------------------------------------
|
||||
define_corners fast slow
|
||||
|
||||
read_liberty -corner fast ../../test/nangate45/Nangate45_fast.lib
|
||||
read_liberty -corner slow ../../test/nangate45/Nangate45_slow.lib
|
||||
|
||||
read_verilog graph_test3.v
|
||||
link_design graph_test3
|
||||
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 15 [get_ports clk2]
|
||||
set_input_delay -clock clk1 1.0 [get_ports {d1 d2 d3 d4}]
|
||||
set_output_delay -clock clk1 1.0 [get_ports {q1 q3}]
|
||||
set_output_delay -clock clk2 1.0 [get_ports q2]
|
||||
set_input_transition 0.1 [get_ports {d1 d2 d3 d4 rst clk1 clk2}]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multi-corner baseline timing
|
||||
#---------------------------------------------------------------
|
||||
puts "--- multi-corner baseline ---"
|
||||
report_checks -corner fast
|
||||
puts "PASS: fast baseline"
|
||||
|
||||
report_checks -corner slow
|
||||
puts "PASS: slow baseline"
|
||||
|
||||
report_checks -corner fast -path_delay min
|
||||
puts "PASS: fast min"
|
||||
|
||||
report_checks -corner slow -path_delay min
|
||||
puts "PASS: slow min"
|
||||
|
||||
report_checks -corner fast -path_delay max
|
||||
puts "PASS: fast max"
|
||||
|
||||
report_checks -corner slow -path_delay max
|
||||
puts "PASS: slow max"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multi-corner per-path (exercises delay comparison across corners)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- multi-corner per-path ---"
|
||||
report_checks -corner fast -from [get_ports d1] -to [get_ports q1]
|
||||
puts "PASS: fast d1->q1"
|
||||
|
||||
report_checks -corner slow -from [get_ports d1] -to [get_ports q1]
|
||||
puts "PASS: slow d1->q1"
|
||||
|
||||
report_checks -corner fast -from [get_ports d3] -to [get_ports q1]
|
||||
puts "PASS: fast d3->q1"
|
||||
|
||||
report_checks -corner slow -from [get_ports d3] -to [get_ports q1]
|
||||
puts "PASS: slow d3->q1"
|
||||
|
||||
# Cross-clock domain paths
|
||||
report_checks -corner fast -from [get_ports d1] -to [get_ports q2]
|
||||
puts "PASS: fast d1->q2 (cross-clock)"
|
||||
|
||||
report_checks -corner slow -from [get_ports d1] -to [get_ports q2]
|
||||
puts "PASS: slow d1->q2 (cross-clock)"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multi-corner report_dcalc
|
||||
# Exercises: delay value comparison across corners
|
||||
#---------------------------------------------------------------
|
||||
puts "--- multi-corner report_dcalc ---"
|
||||
catch {report_dcalc -corner fast -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
|
||||
puts "fast buf1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
|
||||
puts "slow buf1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner fast -from [get_pins nand1/A1] -to [get_pins nand1/ZN]} msg
|
||||
puts "fast nand1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins nand1/A1] -to [get_pins nand1/ZN]} msg
|
||||
puts "slow nand1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner fast -from [get_pins nor1/A1] -to [get_pins nor1/ZN]} msg
|
||||
puts "fast nor1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins nor1/A1] -to [get_pins nor1/ZN]} msg
|
||||
puts "slow nor1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner fast -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max} msg
|
||||
puts "fast reg1 CK->Q: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max} msg
|
||||
puts "slow reg1 CK->Q: done"
|
||||
|
||||
catch {report_dcalc -corner fast -from [get_pins reg1/CK] -to [get_pins reg1/D] -max} msg
|
||||
puts "fast reg1 setup: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins reg1/CK] -to [get_pins reg1/D] -min} msg
|
||||
puts "slow reg1 hold: done"
|
||||
|
||||
# Cross-clock domain DFF
|
||||
catch {report_dcalc -corner fast -from [get_pins reg3/CK] -to [get_pins reg3/Q] -max} msg
|
||||
puts "fast reg3 CK->Q: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins reg3/CK] -to [get_pins reg3/Q] -max} msg
|
||||
puts "slow reg3 CK->Q: done"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Network modification: add instance, recheck graph
|
||||
# Exercises: graph incremental update after network changes
|
||||
#---------------------------------------------------------------
|
||||
puts "--- network modification and graph update ---"
|
||||
set new_buf [make_instance added_buf NangateOpenCellLibrary/BUF_X1]
|
||||
puts "PASS: make_instance added_buf"
|
||||
|
||||
set new_net [make_net added_net]
|
||||
puts "PASS: make_net added_net"
|
||||
|
||||
connect_pin added_net added_buf/A
|
||||
puts "PASS: connect added_buf/A"
|
||||
|
||||
# Report checks after adding (graph updated incrementally)
|
||||
report_checks -corner fast
|
||||
puts "PASS: fast after add"
|
||||
|
||||
report_checks -corner slow
|
||||
puts "PASS: slow after add"
|
||||
|
||||
# Disconnect and delete
|
||||
disconnect_pin added_net added_buf/A
|
||||
delete_instance added_buf
|
||||
delete_net added_net
|
||||
puts "PASS: cleanup added instance"
|
||||
|
||||
# Report after deletion
|
||||
report_checks -corner fast
|
||||
puts "PASS: fast after delete"
|
||||
|
||||
report_checks -corner slow
|
||||
puts "PASS: slow after delete"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Replace cell and check timing
|
||||
# Exercises: graph update after cell replacement
|
||||
#---------------------------------------------------------------
|
||||
puts "--- replace_cell ---"
|
||||
replace_cell buf1 NangateOpenCellLibrary/BUF_X4
|
||||
report_checks -corner fast
|
||||
puts "PASS: fast after buf1->BUF_X4"
|
||||
|
||||
report_checks -corner slow
|
||||
puts "PASS: slow after buf1->BUF_X4"
|
||||
|
||||
# Replace back
|
||||
replace_cell buf1 NangateOpenCellLibrary/BUF_X1
|
||||
report_checks
|
||||
puts "PASS: replaced back"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Load changes with multi-corner
|
||||
# Exercises: incremental delay recomputation
|
||||
#---------------------------------------------------------------
|
||||
puts "--- load changes multi-corner ---"
|
||||
set_load 0.01 [get_ports q1]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
puts "PASS: q1 load 0.01"
|
||||
|
||||
set_load 0.05 [get_ports q2]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
puts "PASS: q2 load 0.05"
|
||||
|
||||
set_load 0.1 [get_ports q3]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
puts "PASS: q3 load 0.1"
|
||||
|
||||
# Reset loads
|
||||
set_load 0 [get_ports q1]
|
||||
set_load 0 [get_ports q2]
|
||||
set_load 0 [get_ports q3]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Disable/enable timing with multi-corner
|
||||
# Exercises: edge disable/re-enable with multiple analysis points
|
||||
#---------------------------------------------------------------
|
||||
puts "--- disable timing multi-corner ---"
|
||||
set_disable_timing [get_cells and1]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
puts "PASS: disable and1"
|
||||
|
||||
set_disable_timing [get_cells or1]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
puts "PASS: disable and1+or1"
|
||||
|
||||
unset_disable_timing [get_cells and1]
|
||||
unset_disable_timing [get_cells or1]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
puts "PASS: enable all"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Case analysis with multi-corner
|
||||
#---------------------------------------------------------------
|
||||
puts "--- case analysis multi-corner ---"
|
||||
set_case_analysis 1 [get_ports d1]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
puts "PASS: d1=1 multi-corner"
|
||||
|
||||
unset_case_analysis [get_ports d1]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
puts "PASS: d1 unset multi-corner"
|
||||
|
||||
set_case_analysis 0 [get_ports d4]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
puts "PASS: d4=0 multi-corner"
|
||||
|
||||
unset_case_analysis [get_ports d4]
|
||||
report_checks
|
||||
puts "PASS: d4 unset"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Report slews per corner
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_slews multi-corner ---"
|
||||
report_slews [get_ports d1]
|
||||
report_slews [get_ports q1]
|
||||
report_slews [get_ports q2]
|
||||
report_slews [get_pins nand1/ZN]
|
||||
report_slews [get_pins nor1/ZN]
|
||||
report_slews [get_pins reg3/Q]
|
||||
puts "PASS: slews multi-corner"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Report edges (exercises EdgeLess comparator)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_edges multi-corner ---"
|
||||
report_edges -from [get_pins nand1/A1] -to [get_pins nand1/ZN]
|
||||
report_edges -from [get_pins nand1/A2] -to [get_pins nand1/ZN]
|
||||
report_edges -from [get_pins nor1/A1] -to [get_pins nor1/ZN]
|
||||
report_edges -from [get_pins nor1/A2] -to [get_pins nor1/ZN]
|
||||
report_edges -from [get_pins and2/A1] -to [get_pins and2/ZN]
|
||||
report_edges -from [get_pins and2/A2] -to [get_pins and2/ZN]
|
||||
report_edges -from [get_pins or2/A1] -to [get_pins or2/ZN]
|
||||
report_edges -from [get_pins or2/A2] -to [get_pins or2/ZN]
|
||||
puts "PASS: report_edges multi-corner"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_checks with fields per corner
|
||||
#---------------------------------------------------------------
|
||||
puts "--- fields per corner ---"
|
||||
report_checks -corner fast -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: fast with fields"
|
||||
|
||||
report_checks -corner slow -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: slow with fields"
|
||||
|
||||
report_checks -corner fast -format full_clock
|
||||
puts "PASS: fast full_clock"
|
||||
|
||||
report_checks -corner slow -format full_clock
|
||||
puts "PASS: slow full_clock"
|
||||
|
||||
report_checks -corner fast -unconstrained
|
||||
puts "PASS: fast unconstrained"
|
||||
|
||||
report_checks -corner slow -unconstrained
|
||||
puts "PASS: slow unconstrained"
|
||||
|
||||
report_checks -corner fast -group_count 3
|
||||
puts "PASS: fast group_count 3"
|
||||
|
||||
report_checks -corner slow -endpoint_count 5
|
||||
puts "PASS: slow endpoint_count 5"
|
||||
|
||||
puts "ALL PASSED"
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,307 @@
|
|||
# Test graph operations with larger multi-clock design for coverage.
|
||||
# Targets: Graph.cc (makeGraph, makeVerticesAndEdges, makeWireEdges,
|
||||
# makePinVertices, makeInstanceEdges, pinVertices, pinDrvrVertex,
|
||||
# pinLoadVertex, vertexCount, edgeCount, vertexIterator, edgeIterator,
|
||||
# arcDelayCount, hasDownstreamClkPin, regClkVertices, isRegClk,
|
||||
# isLatchData, widthCheckAnnotation, periodCheckAnnotation)
|
||||
# GraphCmp.cc (EdgeLess, sortEdges, VertexNameLess, vertexLess)
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog graph_test3.v
|
||||
link_design graph_test3
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Two clock domains
|
||||
#---------------------------------------------------------------
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 15 [get_ports clk2]
|
||||
set_input_delay -clock clk1 1.0 [get_ports {d1 d2 d3 d4}]
|
||||
set_output_delay -clock clk1 1.0 [get_ports {q1 q3}]
|
||||
set_output_delay -clock clk2 1.0 [get_ports q2]
|
||||
set_input_transition 0.1 [get_ports {d1 d2 d3 d4 rst clk1 clk2}]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Baseline timing (exercises makeGraph, graph construction)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- baseline timing ---"
|
||||
report_checks
|
||||
puts "PASS: baseline report_checks"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: baseline min"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: baseline max"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# All path combinations (exercises vertex/edge traversal thoroughly)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- all path combinations ---"
|
||||
foreach from_port {d1 d2 d3 d4} {
|
||||
foreach to_port {q1 q2 q3} {
|
||||
catch {
|
||||
report_checks -from [get_ports $from_port] -to [get_ports $to_port]
|
||||
} msg
|
||||
puts "${from_port}->${to_port}: done"
|
||||
}
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Through pin queries for reconvergent paths
|
||||
# Exercises: graph traversal through reconvergent fan-out
|
||||
#---------------------------------------------------------------
|
||||
puts "--- through reconvergent paths ---"
|
||||
catch {report_checks -through [get_pins nand1/ZN]} msg
|
||||
puts "through nand1/ZN: done"
|
||||
|
||||
catch {report_checks -through [get_pins nor1/ZN]} msg
|
||||
puts "through nor1/ZN: done"
|
||||
|
||||
catch {report_checks -through [get_pins and2/ZN]} msg
|
||||
puts "through and2/ZN: done"
|
||||
|
||||
catch {report_checks -through [get_pins or2/ZN]} msg
|
||||
puts "through or2/ZN: done"
|
||||
|
||||
# Through multiple intermediate points
|
||||
catch {report_checks -through [get_pins and1/ZN] -through [get_pins nand1/ZN]} msg
|
||||
puts "through and1->nand1: done"
|
||||
|
||||
catch {report_checks -through [get_pins or1/ZN] -through [get_pins nand1/ZN]} msg
|
||||
puts "through or1->nand1: done"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Timing edge queries for all cells (exercises edge iteration)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- timing edges all cells ---"
|
||||
foreach cell_name {buf1 buf2 inv1 inv2 and1 or1 nand1 nor1 and2 or2 reg1 reg2 reg3 buf3 buf4} {
|
||||
catch {
|
||||
set edges [get_timing_edges -of_objects [get_cells $cell_name]]
|
||||
puts "$cell_name edges: [llength $edges]"
|
||||
} msg
|
||||
}
|
||||
|
||||
# From/to specific pins
|
||||
puts "--- specific edge queries ---"
|
||||
set edges_and1_a1 [get_timing_edges -from [get_pins and1/A1] -to [get_pins and1/ZN]]
|
||||
puts "and1 A1->ZN: [llength $edges_and1_a1]"
|
||||
|
||||
set edges_and1_a2 [get_timing_edges -from [get_pins and1/A2] -to [get_pins and1/ZN]]
|
||||
puts "and1 A2->ZN: [llength $edges_and1_a2]"
|
||||
|
||||
set edges_or1_a1 [get_timing_edges -from [get_pins or1/A1] -to [get_pins or1/ZN]]
|
||||
puts "or1 A1->ZN: [llength $edges_or1_a1]"
|
||||
|
||||
set edges_nand_a1 [get_timing_edges -from [get_pins nand1/A1] -to [get_pins nand1/ZN]]
|
||||
puts "nand1 A1->ZN: [llength $edges_nand_a1]"
|
||||
|
||||
set edges_nor_a1 [get_timing_edges -from [get_pins nor1/A1] -to [get_pins nor1/ZN]]
|
||||
puts "nor1 A1->ZN: [llength $edges_nor_a1]"
|
||||
|
||||
# DFF edges
|
||||
set edges_reg1_ck_q [get_timing_edges -from [get_pins reg1/CK] -to [get_pins reg1/Q]]
|
||||
puts "reg1 CK->Q: [llength $edges_reg1_ck_q]"
|
||||
|
||||
set edges_reg3_ck_q [get_timing_edges -from [get_pins reg3/CK] -to [get_pins reg3/Q]]
|
||||
puts "reg3 CK->Q: [llength $edges_reg3_ck_q]"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Report edges for all cell types
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_edges ---"
|
||||
report_edges -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
puts "PASS: report_edges buf1"
|
||||
|
||||
report_edges -from [get_pins inv1/A] -to [get_pins inv1/ZN]
|
||||
puts "PASS: report_edges inv1"
|
||||
|
||||
report_edges -from [get_pins and1/A1] -to [get_pins and1/ZN]
|
||||
puts "PASS: report_edges and1 A1"
|
||||
|
||||
report_edges -from [get_pins and1/A2] -to [get_pins and1/ZN]
|
||||
puts "PASS: report_edges and1 A2"
|
||||
|
||||
report_edges -from [get_pins or1/A1] -to [get_pins or1/ZN]
|
||||
puts "PASS: report_edges or1 A1"
|
||||
|
||||
report_edges -from [get_pins nand1/A1] -to [get_pins nand1/ZN]
|
||||
puts "PASS: report_edges nand1 A1"
|
||||
|
||||
report_edges -from [get_pins nor1/A1] -to [get_pins nor1/ZN]
|
||||
puts "PASS: report_edges nor1 A1"
|
||||
|
||||
report_edges -from [get_pins reg1/CK] -to [get_pins reg1/Q]
|
||||
puts "PASS: report_edges reg1 CK->Q"
|
||||
|
||||
report_edges -from [get_pins reg3/CK] -to [get_pins reg3/Q]
|
||||
puts "PASS: report_edges reg3 CK->Q"
|
||||
|
||||
# From only
|
||||
report_edges -from [get_ports d1]
|
||||
puts "PASS: report_edges from d1"
|
||||
|
||||
report_edges -from [get_ports d3]
|
||||
puts "PASS: report_edges from d3"
|
||||
|
||||
# To only
|
||||
report_edges -to [get_ports q1]
|
||||
puts "PASS: report_edges to q1"
|
||||
|
||||
report_edges -to [get_ports q2]
|
||||
puts "PASS: report_edges to q2"
|
||||
|
||||
report_edges -to [get_ports q3]
|
||||
puts "PASS: report_edges to q3"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Disable/enable timing on various cells
|
||||
# Exercises: graph edge disable/enable, re-traversal
|
||||
#---------------------------------------------------------------
|
||||
puts "--- disable/enable timing ---"
|
||||
|
||||
# Disable individual cells
|
||||
set_disable_timing [get_cells buf1]
|
||||
report_checks
|
||||
puts "PASS: disable buf1"
|
||||
|
||||
set_disable_timing [get_cells inv1]
|
||||
report_checks
|
||||
puts "PASS: disable buf1+inv1"
|
||||
|
||||
set_disable_timing [get_cells nand1]
|
||||
report_checks
|
||||
puts "PASS: disable buf1+inv1+nand1"
|
||||
|
||||
# Enable back one by one
|
||||
unset_disable_timing [get_cells buf1]
|
||||
report_checks
|
||||
puts "PASS: enable buf1"
|
||||
|
||||
unset_disable_timing [get_cells inv1]
|
||||
report_checks
|
||||
puts "PASS: enable inv1"
|
||||
|
||||
unset_disable_timing [get_cells nand1]
|
||||
report_checks
|
||||
puts "PASS: enable nand1"
|
||||
|
||||
# Disable specific arcs on lib cells
|
||||
set_disable_timing -from A1 -to ZN [get_lib_cells NangateOpenCellLibrary/AND2_X1]
|
||||
report_disabled_edges
|
||||
report_checks
|
||||
puts "PASS: disable and1 A1->ZN arc"
|
||||
|
||||
unset_disable_timing -from A1 -to ZN [get_lib_cells NangateOpenCellLibrary/AND2_X1]
|
||||
report_disabled_edges
|
||||
report_checks
|
||||
puts "PASS: enable and1 A1->ZN arc"
|
||||
|
||||
# Disable/enable on NOR and NAND
|
||||
set_disable_timing -from A1 -to ZN [get_lib_cells NangateOpenCellLibrary/NAND2_X1]
|
||||
report_checks
|
||||
puts "PASS: disable nand1 A1 arc"
|
||||
|
||||
unset_disable_timing -from A1 -to ZN [get_lib_cells NangateOpenCellLibrary/NAND2_X1]
|
||||
report_checks
|
||||
puts "PASS: enable nand1 A1 arc"
|
||||
|
||||
set_disable_timing -from A1 -to ZN [get_lib_cells NangateOpenCellLibrary/NOR2_X1]
|
||||
report_checks
|
||||
puts "PASS: disable nor1 A1 arc"
|
||||
|
||||
unset_disable_timing -from A1 -to ZN [get_lib_cells NangateOpenCellLibrary/NOR2_X1]
|
||||
report_checks
|
||||
puts "PASS: enable nor1 A1 arc"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Case analysis / constant propagation
|
||||
# Exercises: graph constant propagation, re-traversal
|
||||
#---------------------------------------------------------------
|
||||
puts "--- case analysis ---"
|
||||
set_case_analysis 1 [get_ports rst]
|
||||
report_checks
|
||||
puts "PASS: rst=1"
|
||||
|
||||
set_case_analysis 0 [get_ports rst]
|
||||
report_checks
|
||||
puts "PASS: rst=0"
|
||||
|
||||
unset_case_analysis [get_ports rst]
|
||||
report_checks
|
||||
puts "PASS: rst unset"
|
||||
|
||||
# Case analysis on data inputs
|
||||
set_case_analysis 1 [get_ports d3]
|
||||
report_checks
|
||||
puts "PASS: d3=1"
|
||||
|
||||
unset_case_analysis [get_ports d3]
|
||||
report_checks
|
||||
puts "PASS: d3 unset"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Report slews for pins in multi-clock design
|
||||
# Exercises: vertex slew access across corners
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_slews ---"
|
||||
report_slews [get_ports d1]
|
||||
report_slews [get_ports d2]
|
||||
report_slews [get_ports d3]
|
||||
report_slews [get_ports d4]
|
||||
report_slews [get_ports q1]
|
||||
report_slews [get_ports q2]
|
||||
report_slews [get_ports q3]
|
||||
report_slews [get_pins buf1/Z]
|
||||
report_slews [get_pins inv1/ZN]
|
||||
report_slews [get_pins and1/ZN]
|
||||
report_slews [get_pins or1/ZN]
|
||||
report_slews [get_pins nand1/ZN]
|
||||
report_slews [get_pins nor1/ZN]
|
||||
report_slews [get_pins and2/ZN]
|
||||
report_slews [get_pins or2/ZN]
|
||||
report_slews [get_pins reg1/Q]
|
||||
report_slews [get_pins reg2/Q]
|
||||
report_slews [get_pins reg3/Q]
|
||||
puts "PASS: report_slews all pins"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_check_types (exercises check edge categorization)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_check_types ---"
|
||||
report_check_types -max_delay -verbose
|
||||
puts "PASS: check_types max"
|
||||
|
||||
report_check_types -min_delay -verbose
|
||||
puts "PASS: check_types min"
|
||||
|
||||
report_check_types -max_delay -min_delay -verbose
|
||||
puts "PASS: check_types max+min"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_checks with various options
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_checks options ---"
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: all fields"
|
||||
|
||||
report_checks -format full_clock
|
||||
puts "PASS: full_clock"
|
||||
|
||||
report_checks -unconstrained
|
||||
puts "PASS: unconstrained"
|
||||
|
||||
report_checks -group_count 3
|
||||
puts "PASS: group_count 3"
|
||||
|
||||
report_checks -endpoint_count 5
|
||||
puts "PASS: endpoint_count 5"
|
||||
|
||||
report_checks -sort_by_slack
|
||||
puts "PASS: sort_by_slack"
|
||||
|
||||
report_checks -endpoint_count 3 -path_delay min
|
||||
puts "PASS: min endpoint_count 3"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
module graph_test1 (clk, d, q);
|
||||
input clk, d;
|
||||
output q;
|
||||
wire n1;
|
||||
|
||||
DFF_X1 reg1 (.D(d), .CK(clk), .Q(n1));
|
||||
DFF_X1 reg2 (.D(n1), .CK(clk), .Q(q));
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
module graph_test2 (clk, d1, d2, en, q1, q2);
|
||||
input clk, d1, d2, en;
|
||||
output q1, q2;
|
||||
wire n1, n2, n3, n4, n5, n6;
|
||||
|
||||
BUF_X1 buf1 (.A(d1), .Z(n1));
|
||||
BUF_X2 buf2 (.A(d2), .Z(n2));
|
||||
INV_X1 inv1 (.A(n1), .ZN(n3));
|
||||
AND2_X1 and1 (.A1(n3), .A2(en), .ZN(n4));
|
||||
OR2_X1 or1 (.A1(n2), .A2(n4), .ZN(n5));
|
||||
BUF_X1 buf3 (.A(n5), .Z(n6));
|
||||
DFF_X1 reg1 (.D(n4), .CK(clk), .Q(q1));
|
||||
DFF_X1 reg2 (.D(n6), .CK(clk), .Q(q2));
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
// Larger design for graph operations testing: more cell types, fan-in/fan-out,
|
||||
// multiple clock domains, and reconvergent paths.
|
||||
module graph_test3 (clk1, clk2, rst, d1, d2, d3, d4, q1, q2, q3);
|
||||
input clk1, clk2, rst, d1, d2, d3, d4;
|
||||
output q1, q2, q3;
|
||||
wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12;
|
||||
|
||||
// Input stage: buffers and inverters
|
||||
BUF_X1 buf1 (.A(d1), .Z(n1));
|
||||
BUF_X2 buf2 (.A(d2), .Z(n2));
|
||||
INV_X1 inv1 (.A(d3), .ZN(n3));
|
||||
INV_X2 inv2 (.A(d4), .ZN(n4));
|
||||
|
||||
// Middle stage: logic gates
|
||||
AND2_X1 and1 (.A1(n1), .A2(n2), .ZN(n5));
|
||||
OR2_X1 or1 (.A1(n3), .A2(n4), .ZN(n6));
|
||||
NAND2_X1 nand1 (.A1(n5), .A2(n6), .ZN(n7));
|
||||
NOR2_X1 nor1 (.A1(n1), .A2(n3), .ZN(n8));
|
||||
|
||||
// Reconvergent fan-out
|
||||
AND2_X2 and2 (.A1(n7), .A2(n8), .ZN(n9));
|
||||
OR2_X2 or2 (.A1(n7), .A2(n8), .ZN(n10));
|
||||
|
||||
// Clock domain 1 registers
|
||||
DFF_X1 reg1 (.D(n9), .CK(clk1), .Q(n11));
|
||||
DFF_X1 reg2 (.D(n10), .CK(clk1), .Q(q1));
|
||||
|
||||
// Clock domain 2 register (cross-domain)
|
||||
DFF_X1 reg3 (.D(n11), .CK(clk2), .Q(n12));
|
||||
BUF_X1 buf3 (.A(n12), .Z(q2));
|
||||
|
||||
// Combinational output
|
||||
BUF_X4 buf4 (.A(n7), .Z(q3));
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,182 @@
|
|||
--- get_timing_edges -of_objects instance ---
|
||||
reg1 timing edges count: 1
|
||||
--- get_timing_edges -from/-to on instance ---
|
||||
CK->Q edges count: 1
|
||||
--- get_timing_edges -from only ---
|
||||
edges from CK count: 5
|
||||
--- get_timing_edges -to only ---
|
||||
edges to Q count: 1
|
||||
--- report_edges -from/-to ---
|
||||
CK -> Q Reg Clk to Q
|
||||
^ -> ^ 0.08:0.08
|
||||
^ -> v 0.08:0.08
|
||||
--- report_edges -from ---
|
||||
CK -> QN Reg Clk to Q
|
||||
^ -> ^ 0.06:0.06
|
||||
^ -> v 0.06:0.06
|
||||
CK -> Q Reg Clk to Q
|
||||
^ -> ^ 0.08:0.08
|
||||
^ -> v 0.08:0.08
|
||||
CK -> CK width
|
||||
^ -> v 0.05:0.05
|
||||
v -> ^ 0.05:0.05
|
||||
CK -> D setup
|
||||
^ -> ^ 0.03:0.03
|
||||
^ -> v 0.04:0.04
|
||||
CK -> D hold
|
||||
^ -> ^ 0.00:0.00
|
||||
^ -> v 0.00:0.00
|
||||
--- report_edges -to ---
|
||||
CK -> D setup
|
||||
^ -> ^ 0.03:0.03
|
||||
^ -> v 0.04:0.04
|
||||
CK -> D hold
|
||||
^ -> ^ 0.01:0.01
|
||||
^ -> v 0.00:0.00
|
||||
reg1/Q -> D wire
|
||||
^ -> ^ 0.00:0.00
|
||||
v -> v 0.00:0.00
|
||||
--- report_disabled_edges (baseline) ---
|
||||
--- set_disable_timing on instance ---
|
||||
PASS: set_disable_timing on reg1
|
||||
--- report_disabled_edges after disable ---
|
||||
reg1 CK Q constraint
|
||||
reg1 CK QN constraint
|
||||
--- report_checks after disable ---
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ q (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
0.00 10.00 output external delay
|
||||
10.00 data required time
|
||||
---------------------------------------------------------
|
||||
10.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.92 slack (MET)
|
||||
|
||||
|
||||
--- unset_disable_timing on instance ---
|
||||
PASS: unset_disable_timing on reg1
|
||||
--- report_disabled_edges after unset ---
|
||||
--- set_disable_timing with -from/-to on lib cell ---
|
||||
PASS: set_disable_timing -from CK -to Q
|
||||
--- report_disabled_edges after lib cell disable ---
|
||||
reg1 CK Q constraint
|
||||
reg2 CK Q constraint
|
||||
--- unset_disable_timing lib cell ---
|
||||
PASS: unset_disable_timing lib cell
|
||||
--- report_checks baseline ---
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 v reg1/Q (DFF_X1)
|
||||
0.00 0.08 v reg2/D (DFF_X1)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
--- report_checks -path_delay max ---
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 v reg1/Q (DFF_X1)
|
||||
0.00 0.08 v reg2/D (DFF_X1)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
--- report_checks -path_delay min ---
|
||||
Startpoint: d (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ input external delay
|
||||
0.00 0.00 ^ d (in)
|
||||
0.00 0.00 ^ reg1/D (DFF_X1)
|
||||
0.00 data arrival time
|
||||
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg1/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
---------------------------------------------------------
|
||||
0.00 data required time
|
||||
-0.00 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.00 slack (VIOLATED)
|
||||
|
||||
|
||||
--- report_checks from d to q ---
|
||||
No paths found.
|
||||
--- report_edges -from port d ---
|
||||
d -> reg1/D wire
|
||||
^ -> ^ 0.00:0.00
|
||||
v -> v 0.00:0.00
|
||||
--- report_edges -to port q ---
|
||||
reg2/Q -> q wire
|
||||
^ -> ^ 0.00:0.00
|
||||
v -> v 0.00:0.00
|
||||
--- get_timing_edges -of_objects reg2 ---
|
||||
reg2 timing edges count: 1
|
||||
--- report_slews on d port ---
|
||||
d ^ 0.00:0.00 v 0.00:0.00
|
||||
--- report_slews on q port ---
|
||||
q ^ 0.01:0.01 v 0.00:0.00
|
||||
ALL PASSED
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
# Test graph timing edge queries and disable_timing
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog graph_test1.v
|
||||
link_design graph_test1
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 0 [get_ports d]
|
||||
set_output_delay -clock clk 0 [get_ports q]
|
||||
|
||||
puts "--- get_timing_edges -of_objects instance ---"
|
||||
set edges [get_timing_edges -of_objects [get_cells reg1]]
|
||||
puts "reg1 timing edges count: [llength $edges]"
|
||||
|
||||
puts "--- get_timing_edges -from/-to on instance ---"
|
||||
set edges_ft [get_timing_edges -from [get_pins reg1/CK] -to [get_pins reg1/Q]]
|
||||
puts "CK->Q edges count: [llength $edges_ft]"
|
||||
|
||||
puts "--- get_timing_edges -from only ---"
|
||||
set edges_from [get_timing_edges -from [get_pins reg1/CK]]
|
||||
puts "edges from CK count: [llength $edges_from]"
|
||||
|
||||
puts "--- get_timing_edges -to only ---"
|
||||
set edges_to [get_timing_edges -to [get_pins reg1/Q]]
|
||||
puts "edges to Q count: [llength $edges_to]"
|
||||
|
||||
puts "--- report_edges -from/-to ---"
|
||||
report_edges -from [get_pins reg1/CK] -to [get_pins reg1/Q]
|
||||
|
||||
puts "--- report_edges -from ---"
|
||||
report_edges -from [get_pins reg1/CK]
|
||||
|
||||
puts "--- report_edges -to ---"
|
||||
report_edges -to [get_pins reg2/D]
|
||||
|
||||
puts "--- report_disabled_edges (baseline) ---"
|
||||
report_disabled_edges
|
||||
|
||||
puts "--- set_disable_timing on instance ---"
|
||||
set_disable_timing [get_cells reg1]
|
||||
puts "PASS: set_disable_timing on reg1"
|
||||
|
||||
puts "--- report_disabled_edges after disable ---"
|
||||
report_disabled_edges
|
||||
|
||||
puts "--- report_checks after disable ---"
|
||||
report_checks
|
||||
|
||||
puts "--- unset_disable_timing on instance ---"
|
||||
unset_disable_timing [get_cells reg1]
|
||||
puts "PASS: unset_disable_timing on reg1"
|
||||
|
||||
puts "--- report_disabled_edges after unset ---"
|
||||
report_disabled_edges
|
||||
|
||||
puts "--- set_disable_timing with -from/-to on lib cell ---"
|
||||
set_disable_timing -from CK -to Q [get_lib_cells NangateOpenCellLibrary/DFF_X1]
|
||||
puts "PASS: set_disable_timing -from CK -to Q"
|
||||
|
||||
puts "--- report_disabled_edges after lib cell disable ---"
|
||||
report_disabled_edges
|
||||
|
||||
puts "--- unset_disable_timing lib cell ---"
|
||||
unset_disable_timing -from CK -to Q [get_lib_cells NangateOpenCellLibrary/DFF_X1]
|
||||
puts "PASS: unset_disable_timing lib cell"
|
||||
|
||||
puts "--- report_checks baseline ---"
|
||||
report_checks
|
||||
|
||||
puts "--- report_checks -path_delay max ---"
|
||||
report_checks -path_delay max
|
||||
|
||||
puts "--- report_checks -path_delay min ---"
|
||||
report_checks -path_delay min
|
||||
|
||||
puts "--- report_checks from d to q ---"
|
||||
report_checks -from [get_ports d] -to [get_ports q]
|
||||
|
||||
puts "--- report_edges -from port d ---"
|
||||
report_edges -from [get_ports d]
|
||||
|
||||
puts "--- report_edges -to port q ---"
|
||||
report_edges -to [get_ports q]
|
||||
|
||||
puts "--- get_timing_edges -of_objects reg2 ---"
|
||||
set edges_r2 [get_timing_edges -of_objects [get_cells reg2]]
|
||||
puts "reg2 timing edges count: [llength $edges_r2]"
|
||||
|
||||
puts "--- report_slews on d port ---"
|
||||
report_slews [get_ports d]
|
||||
|
||||
puts "--- report_slews on q port ---"
|
||||
report_slews [get_ports q]
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
@ -0,0 +1,978 @@
|
|||
--- Test 1: baseline edge count ---
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: baseline timing
|
||||
buf1 edges: 1
|
||||
buf2 edges: 1
|
||||
inv1 edges: 1
|
||||
and1 edges: 1
|
||||
or1 edges: 1
|
||||
nand1 edges: 1
|
||||
nor1 edges: 1
|
||||
PASS: baseline edge queries
|
||||
--- Test 2: chain add/delete ---
|
||||
PASS: 4-stage chain created
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing with chain
|
||||
chain_buf0 edges: 1
|
||||
chain_buf1 edges: 1
|
||||
chain_buf2 edges: 1
|
||||
chain_buf3 edges: 1
|
||||
PASS: chain deleted
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing after chain delete
|
||||
--- Test 3: fan-out/fan-in ---
|
||||
PASS: fanout-3 net created
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing with fanout
|
||||
fo_drv edges: 1
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: fanout-2 timing
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: fanout-1 timing
|
||||
PASS: fanout cleanup
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing after fanout cleanup
|
||||
--- Test 4: cell replacement cycle ---
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: buf1 replacement cycle
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.13 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.13 ^ reg2/D (DFF_X1)
|
||||
1.13 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.13 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.84 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: and1 replacement cycle
|
||||
--- Test 5: register add/delete ---
|
||||
PASS: 3 registers added
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing with added registers
|
||||
PASS: registers deleted
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing after register deletion
|
||||
--- Test 6: slew and edge reports ---
|
||||
d1 ^ 0.10:0.10 v 0.10:0.10
|
||||
d2 ^ 0.10:0.10 v 0.10:0.10
|
||||
d3 ^ 0.10:0.10 v 0.10:0.10
|
||||
clk ^ 0.10:0.10 v 0.10:0.10
|
||||
PASS: port slews
|
||||
buf1/A ^ 0.10:0.10 v 0.10:0.10
|
||||
buf1/Z ^ 0.01:0.01 v 0.01:0.01
|
||||
and1/A1 ^ 0.01:0.01 v 0.01:0.01
|
||||
and1/ZN ^ 0.01:0.01 v 0.01:0.01
|
||||
inv1/A ^ 0.10:0.10 v 0.10:0.10
|
||||
inv1/ZN ^ 0.02:0.02 v 0.02:0.02
|
||||
nand1/ZN ^ 0.01:0.01 v 0.01:0.01
|
||||
nor1/ZN ^ 0.01:0.01 v 0.01:0.01
|
||||
PASS: pin slews
|
||||
A -> Z combinational
|
||||
^ -> ^ 0.03:0.03
|
||||
v -> v 0.06:0.06
|
||||
A1 -> ZN combinational
|
||||
^ -> ^ 0.04:0.04
|
||||
v -> v 0.03:0.03
|
||||
A -> ZN combinational
|
||||
^ -> v 0.01:0.01
|
||||
v -> ^ 0.04:0.04
|
||||
PASS: edge reports
|
||||
--- Test 7: through-pin queries ---
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d1 (in)
|
||||
0.06 1.06 v buf1/Z (BUF_X1)
|
||||
0.03 1.09 v and1/ZN (AND2_X1)
|
||||
0.02 1.11 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 1.11 ^ reg3/D (DFF_X1)
|
||||
1.11 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg3/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.11 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.86 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.04 1.09 v and1/ZN (AND2_X1)
|
||||
0.02 1.11 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 1.11 ^ reg3/D (DFF_X1)
|
||||
1.11 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg3/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.11 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d3 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d3 (in)
|
||||
0.04 1.04 ^ inv1/ZN (INV_X1)
|
||||
0.03 1.07 ^ or1/ZN (OR2_X1)
|
||||
0.01 1.09 v nand1/ZN (NAND2_X1)
|
||||
0.00 1.09 v reg2/D (DFF_X1)
|
||||
1.09 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-1.09 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.88 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.04 1.09 v and1/ZN (AND2_X1)
|
||||
0.02 1.11 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 1.11 ^ reg3/D (DFF_X1)
|
||||
1.11 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg3/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.11 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v d2 (in)
|
||||
0.06 1.06 v buf2/Z (BUF_X1)
|
||||
0.05 1.11 v or1/ZN (OR2_X1)
|
||||
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.12 ^ reg2/D (DFF_X1)
|
||||
1.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: through-pin queries
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg1/Q (DFF_X1)
|
||||
0.00 0.08 ^ q1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q2 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ q2 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q3 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg3/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg3/Q (DFF_X1)
|
||||
0.00 0.08 ^ q3 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg4 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q4 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg4/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg4/Q (DFF_X1)
|
||||
0.00 0.08 ^ q4 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-1.00 9.00 output external delay
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
PASS: endpoint queries
|
||||
ALL PASSED
|
||||
|
|
@ -0,0 +1,244 @@
|
|||
# Test graph vertex and edge operations in depth: makeVertex, deleteVertex,
|
||||
# makeEdge, deleteEdge, edge arc queries, bidirectional pin handling,
|
||||
# hasFaninOne, vertex iteration, edge linking.
|
||||
# Targets: Graph.cc uncovered:
|
||||
# deleteVertex (lines 476-504): edge cleanup during vertex deletion
|
||||
# deleteInEdge / deleteOutEdge: linked list manipulation for edges
|
||||
# hasFaninOne: single fanin check
|
||||
# pinDrvrVertex / pinLoadVertex: bidirect driver vertex lookup
|
||||
# gateEdgeArc: arc lookup by rise/fall
|
||||
# makePaths / paths / deletePaths: vertex path management
|
||||
# slew / setSlew: slew value access
|
||||
# makeWireEdgesToPin: create wire edges to a pin
|
||||
# isIsolatedNet: isolated net detection
|
||||
# arcDelay / setArcDelay: edge arc delay access
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog graph_delete_modify.v
|
||||
link_design graph_delete_modify
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 1.0 [get_ports {d1 d2 d3 rst}]
|
||||
set_output_delay -clock clk 1.0 [get_ports {q1 q2 q3 q4}]
|
||||
set_input_transition 0.1 [get_ports {d1 d2 d3 rst clk}]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 1: Baseline - build graph and verify edges
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 1: baseline edge count ---"
|
||||
report_checks
|
||||
puts "PASS: baseline timing"
|
||||
|
||||
# Query edges for each cell
|
||||
foreach cell_name {buf1 buf2 inv1 and1 or1 nand1 nor1} {
|
||||
set edges [get_timing_edges -of_objects [get_cells $cell_name]]
|
||||
puts "$cell_name edges: [llength $edges]"
|
||||
}
|
||||
puts "PASS: baseline edge queries"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 2: Add chain of buffers, verify edges, then delete one by one
|
||||
# Exercises: makeVertex, makeEdge, deleteVertex, deleteEdge,
|
||||
# deleteInEdge, deleteOutEdge
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 2: chain add/delete ---"
|
||||
|
||||
# Create 4-stage buffer chain
|
||||
set chain_nets {}
|
||||
set chain_insts {}
|
||||
for {set i 0} {$i < 4} {incr i} {
|
||||
lappend chain_nets [make_net "chain_n$i"]
|
||||
}
|
||||
lappend chain_nets [make_net "chain_n4"]
|
||||
|
||||
for {set i 0} {$i < 4} {incr i} {
|
||||
set inst [make_instance "chain_buf$i" NangateOpenCellLibrary/BUF_X1]
|
||||
lappend chain_insts $inst
|
||||
connect_pin "chain_n$i" "chain_buf$i/A"
|
||||
set j [expr {$i + 1}]
|
||||
connect_pin "chain_n$j" "chain_buf$i/Z"
|
||||
}
|
||||
puts "PASS: 4-stage chain created"
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing with chain"
|
||||
|
||||
# Query chain edges
|
||||
for {set i 0} {$i < 4} {incr i} {
|
||||
set edges [get_timing_edges -of_objects [get_cells "chain_buf$i"]]
|
||||
puts "chain_buf$i edges: [llength $edges]"
|
||||
}
|
||||
|
||||
# Delete chain from end to beginning (exercises reverse cleanup)
|
||||
for {set i 3} {$i >= 0} {incr i -1} {
|
||||
disconnect_pin "chain_n$i" "chain_buf$i/A"
|
||||
set j [expr {$i + 1}]
|
||||
disconnect_pin "chain_n$j" "chain_buf$i/Z"
|
||||
delete_instance "chain_buf$i"
|
||||
}
|
||||
for {set i 0} {$i <= 4} {incr i} {
|
||||
delete_net "chain_n$i"
|
||||
}
|
||||
puts "PASS: chain deleted"
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing after chain delete"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 3: Multiple fan-out and fan-in scenarios
|
||||
# Exercises: makeWireEdgesFromPin with multi-driver nets
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 3: fan-out/fan-in ---"
|
||||
|
||||
set fo_net [make_net "fanout_net"]
|
||||
set fo_drv [make_instance "fo_drv" NangateOpenCellLibrary/BUF_X4]
|
||||
set fo_load1 [make_instance "fo_load1" NangateOpenCellLibrary/BUF_X1]
|
||||
set fo_load2 [make_instance "fo_load2" NangateOpenCellLibrary/BUF_X1]
|
||||
set fo_load3 [make_instance "fo_load3" NangateOpenCellLibrary/BUF_X1]
|
||||
|
||||
set fo_in [make_net "fo_in"]
|
||||
connect_pin fo_in fo_drv/A
|
||||
connect_pin fanout_net fo_drv/Z
|
||||
connect_pin fanout_net fo_load1/A
|
||||
connect_pin fanout_net fo_load2/A
|
||||
connect_pin fanout_net fo_load3/A
|
||||
|
||||
puts "PASS: fanout-3 net created"
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing with fanout"
|
||||
|
||||
# Query edge count on fanout driver
|
||||
set drv_edges [get_timing_edges -of_objects [get_cells fo_drv]]
|
||||
puts "fo_drv edges: [llength $drv_edges]"
|
||||
|
||||
# Disconnect loads one by one
|
||||
disconnect_pin fanout_net fo_load3/A
|
||||
report_checks
|
||||
puts "PASS: fanout-2 timing"
|
||||
|
||||
disconnect_pin fanout_net fo_load2/A
|
||||
report_checks
|
||||
puts "PASS: fanout-1 timing"
|
||||
|
||||
# Cleanup
|
||||
disconnect_pin fanout_net fo_load1/A
|
||||
disconnect_pin fanout_net fo_drv/Z
|
||||
disconnect_pin fo_in fo_drv/A
|
||||
delete_instance fo_load1
|
||||
delete_instance fo_load2
|
||||
delete_instance fo_load3
|
||||
delete_instance fo_drv
|
||||
delete_net fanout_net
|
||||
delete_net fo_in
|
||||
puts "PASS: fanout cleanup"
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing after fanout cleanup"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 4: Replace cell multiple times and verify edge rebuild
|
||||
# Exercises: makeInstanceEdges rebuild, timing arc set changes
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 4: cell replacement cycle ---"
|
||||
|
||||
# Replace buf1 through several sizes
|
||||
foreach lib_cell {BUF_X1 BUF_X2 BUF_X4 BUF_X8 BUF_X4 BUF_X2 BUF_X1} {
|
||||
replace_cell buf1 "NangateOpenCellLibrary/$lib_cell"
|
||||
report_checks -path_delay max
|
||||
}
|
||||
puts "PASS: buf1 replacement cycle"
|
||||
|
||||
# Replace AND gate
|
||||
foreach lib_cell {AND2_X1 AND2_X2 AND2_X4 AND2_X2 AND2_X1} {
|
||||
replace_cell and1 "NangateOpenCellLibrary/$lib_cell"
|
||||
report_checks
|
||||
}
|
||||
puts "PASS: and1 replacement cycle"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 5: Register add/delete to exercise reg_clk_vertices
|
||||
# Exercises: makeVertex is_reg_clk path, reg_clk_vertices_ insert/erase
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 5: register add/delete ---"
|
||||
|
||||
# Add multiple registers
|
||||
for {set i 0} {$i < 3} {incr i} {
|
||||
set rn [make_net "reg_d$i"]
|
||||
set rqn [make_net "reg_q$i"]
|
||||
set ri [make_instance "test_reg$i" NangateOpenCellLibrary/DFF_X1]
|
||||
connect_pin "reg_d$i" "test_reg$i/D"
|
||||
connect_pin "reg_q$i" "test_reg$i/Q"
|
||||
catch {connect_pin clk "test_reg$i/CK"} msg
|
||||
}
|
||||
puts "PASS: 3 registers added"
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing with added registers"
|
||||
|
||||
# Delete the registers
|
||||
for {set i 0} {$i < 3} {incr i} {
|
||||
catch {disconnect_pin clk "test_reg$i/CK"} msg
|
||||
disconnect_pin "reg_d$i" "test_reg$i/D"
|
||||
disconnect_pin "reg_q$i" "test_reg$i/Q"
|
||||
delete_instance "test_reg$i"
|
||||
delete_net "reg_d$i"
|
||||
delete_net "reg_q$i"
|
||||
}
|
||||
puts "PASS: registers deleted"
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing after register deletion"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 6: Slew and timing edge reports
|
||||
# Exercises: slew access, edge arc iteration
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 6: slew and edge reports ---"
|
||||
|
||||
report_slews [get_ports d1]
|
||||
report_slews [get_ports d2]
|
||||
report_slews [get_ports d3]
|
||||
report_slews [get_ports clk]
|
||||
puts "PASS: port slews"
|
||||
|
||||
report_slews [get_pins buf1/A]
|
||||
report_slews [get_pins buf1/Z]
|
||||
report_slews [get_pins and1/A1]
|
||||
report_slews [get_pins and1/ZN]
|
||||
report_slews [get_pins inv1/A]
|
||||
report_slews [get_pins inv1/ZN]
|
||||
report_slews [get_pins nand1/ZN]
|
||||
report_slews [get_pins nor1/ZN]
|
||||
puts "PASS: pin slews"
|
||||
|
||||
# Edge reports
|
||||
report_edges -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
report_edges -from [get_pins and1/A1] -to [get_pins and1/ZN]
|
||||
report_edges -from [get_pins inv1/A] -to [get_pins inv1/ZN]
|
||||
puts "PASS: edge reports"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 7: Through-pin and endpoint queries
|
||||
# Exercises: graph traversal paths
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 7: through-pin queries ---"
|
||||
|
||||
catch {report_checks -through [get_pins buf1/Z]} msg
|
||||
catch {report_checks -through [get_pins and1/ZN]} msg
|
||||
catch {report_checks -through [get_pins inv1/ZN]} msg
|
||||
catch {report_checks -through [get_pins nand1/ZN]} msg
|
||||
catch {report_checks -through [get_pins nor1/ZN]} msg
|
||||
catch {report_checks -through [get_pins or1/ZN]} msg
|
||||
puts "PASS: through-pin queries"
|
||||
|
||||
# Endpoint
|
||||
catch {report_checks -to [get_ports q1]} msg
|
||||
catch {report_checks -to [get_ports q2]} msg
|
||||
catch {report_checks -to [get_ports q3]} msg
|
||||
catch {report_checks -to [get_ports q4]} msg
|
||||
puts "PASS: endpoint queries"
|
||||
|
||||
puts "ALL PASSED"
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,294 @@
|
|||
# Test graph construction, wire/instance edge creation, delay annotation,
|
||||
# slew queries, and edge removal/modification.
|
||||
# Targets:
|
||||
# Graph.cc: makeGraph, makeVertex, makeWireEdge, makeInstEdge,
|
||||
# removeWireEdge, removeInstEdge, arcDelayAnnotated, wireDelayAnnotated,
|
||||
# slew/delay getters for rise/fall combinations, pinVertices,
|
||||
# pinDrvrVertex, pinLoadVertex, vertexCount, edgeCount,
|
||||
# setConstant, clearConstants, regClkVertices, isRegClk,
|
||||
# widthCheckAnnotation, periodCheckAnnotation, setPeriodCheckAnnotation,
|
||||
# hasDownstreamClkPin, minPulseWidthArc
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog graph_test3.v
|
||||
link_design graph_test3
|
||||
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 15 [get_ports clk2]
|
||||
set_input_delay -clock clk1 1.0 [get_ports {d1 d2 d3 d4}]
|
||||
set_output_delay -clock clk1 1.0 [get_ports {q1 q3}]
|
||||
set_output_delay -clock clk2 1.0 [get_ports q2]
|
||||
set_input_transition 0.1 [get_ports {d1 d2 d3 d4 rst clk1 clk2}]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Baseline timing: triggers makeGraph, all vertex/edge construction
|
||||
#---------------------------------------------------------------
|
||||
puts "--- baseline timing ---"
|
||||
report_checks
|
||||
puts "PASS: baseline"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: baseline min"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: baseline max"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Query all timing edges: exercises edge iteration
|
||||
#---------------------------------------------------------------
|
||||
puts "--- timing edges per cell ---"
|
||||
foreach cell_name {buf1 buf2 inv1 inv2 and1 or1 nand1 nor1 and2 or2 reg1 reg2 reg3 buf3 buf4} {
|
||||
set edges [get_timing_edges -of_objects [get_cells $cell_name]]
|
||||
puts "$cell_name edges: [llength $edges]"
|
||||
}
|
||||
puts "PASS: edge queries"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Specific edge queries: from/to pins
|
||||
# Exercises arc delay access for all transition combinations
|
||||
#---------------------------------------------------------------
|
||||
puts "--- specific edge queries ---"
|
||||
|
||||
# BUF edges (rise/rise, fall/fall)
|
||||
report_edges -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
puts "PASS: buf1 edges"
|
||||
|
||||
# INV edges (rise/fall, fall/rise)
|
||||
report_edges -from [get_pins inv1/A] -to [get_pins inv1/ZN]
|
||||
puts "PASS: inv1 edges"
|
||||
|
||||
# NAND edges
|
||||
report_edges -from [get_pins nand1/A1] -to [get_pins nand1/ZN]
|
||||
report_edges -from [get_pins nand1/A2] -to [get_pins nand1/ZN]
|
||||
puts "PASS: nand1 edges"
|
||||
|
||||
# NOR edges
|
||||
report_edges -from [get_pins nor1/A1] -to [get_pins nor1/ZN]
|
||||
report_edges -from [get_pins nor1/A2] -to [get_pins nor1/ZN]
|
||||
puts "PASS: nor1 edges"
|
||||
|
||||
# AND2 edges
|
||||
report_edges -from [get_pins and2/A1] -to [get_pins and2/ZN]
|
||||
report_edges -from [get_pins and2/A2] -to [get_pins and2/ZN]
|
||||
puts "PASS: and2 edges"
|
||||
|
||||
# OR2 edges
|
||||
report_edges -from [get_pins or2/A1] -to [get_pins or2/ZN]
|
||||
report_edges -from [get_pins or2/A2] -to [get_pins or2/ZN]
|
||||
puts "PASS: or2 edges"
|
||||
|
||||
# DFF edges (CK->Q)
|
||||
report_edges -from [get_pins reg1/CK] -to [get_pins reg1/Q]
|
||||
report_edges -from [get_pins reg2/CK] -to [get_pins reg2/Q]
|
||||
report_edges -from [get_pins reg3/CK] -to [get_pins reg3/Q]
|
||||
puts "PASS: DFF edges"
|
||||
|
||||
# Wire edges (port to first gate)
|
||||
report_edges -from [get_ports d1]
|
||||
report_edges -from [get_ports d2]
|
||||
report_edges -from [get_ports d3]
|
||||
report_edges -from [get_ports d4]
|
||||
puts "PASS: wire edges from ports"
|
||||
|
||||
# Wire edges to output ports
|
||||
report_edges -to [get_ports q1]
|
||||
report_edges -to [get_ports q2]
|
||||
report_edges -to [get_ports q3]
|
||||
puts "PASS: wire edges to ports"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Slew queries: exercises slew getters in Graph.cc
|
||||
#---------------------------------------------------------------
|
||||
puts "--- slew queries ---"
|
||||
|
||||
# Input port slews
|
||||
report_slews [get_ports d1]
|
||||
report_slews [get_ports d2]
|
||||
report_slews [get_ports d3]
|
||||
report_slews [get_ports d4]
|
||||
report_slews [get_ports clk1]
|
||||
report_slews [get_ports clk2]
|
||||
puts "PASS: input slews"
|
||||
|
||||
# Output port slews
|
||||
report_slews [get_ports q1]
|
||||
report_slews [get_ports q2]
|
||||
report_slews [get_ports q3]
|
||||
puts "PASS: output slews"
|
||||
|
||||
# Internal pin slews
|
||||
report_slews [get_pins buf1/Z]
|
||||
report_slews [get_pins buf2/Z]
|
||||
report_slews [get_pins inv1/ZN]
|
||||
report_slews [get_pins inv2/ZN]
|
||||
report_slews [get_pins and1/ZN]
|
||||
report_slews [get_pins or1/ZN]
|
||||
report_slews [get_pins nand1/ZN]
|
||||
report_slews [get_pins nor1/ZN]
|
||||
report_slews [get_pins and2/ZN]
|
||||
report_slews [get_pins or2/ZN]
|
||||
report_slews [get_pins reg1/Q]
|
||||
report_slews [get_pins reg2/Q]
|
||||
report_slews [get_pins reg3/Q]
|
||||
report_slews [get_pins buf3/Z]
|
||||
report_slews [get_pins buf4/Z]
|
||||
puts "PASS: internal slews"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Network modification: add/remove instances
|
||||
# Exercises graph incremental update paths
|
||||
#---------------------------------------------------------------
|
||||
puts "--- network modification ---"
|
||||
|
||||
# Add instance and wire
|
||||
set new_buf [make_instance extra_buf NangateOpenCellLibrary/BUF_X1]
|
||||
set new_net [make_net extra_net]
|
||||
set new_net2 [make_net extra_net2]
|
||||
connect_pin extra_net extra_buf/A
|
||||
connect_pin extra_net2 extra_buf/Z
|
||||
puts "PASS: add instance"
|
||||
|
||||
# Timing after addition (exercises incremental graph update)
|
||||
report_checks
|
||||
puts "PASS: timing after add"
|
||||
|
||||
# Disconnect and remove
|
||||
disconnect_pin extra_net extra_buf/A
|
||||
disconnect_pin extra_net2 extra_buf/Z
|
||||
delete_instance extra_buf
|
||||
delete_net extra_net
|
||||
delete_net extra_net2
|
||||
puts "PASS: cleanup"
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing after cleanup"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Replace cell and verify edge update
|
||||
#---------------------------------------------------------------
|
||||
puts "--- replace cell ---"
|
||||
|
||||
replace_cell buf1 NangateOpenCellLibrary/BUF_X4
|
||||
report_checks
|
||||
report_edges -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
puts "PASS: buf1->BUF_X4"
|
||||
|
||||
replace_cell buf1 NangateOpenCellLibrary/BUF_X1
|
||||
report_checks
|
||||
puts "PASS: buf1 restored"
|
||||
|
||||
replace_cell inv1 NangateOpenCellLibrary/INV_X2
|
||||
report_checks
|
||||
puts "PASS: inv1->INV_X2"
|
||||
|
||||
replace_cell inv1 NangateOpenCellLibrary/INV_X1
|
||||
report_checks
|
||||
puts "PASS: inv1 restored"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Disable/enable timing on edges
|
||||
# Exercises graph edge disable traversal
|
||||
#---------------------------------------------------------------
|
||||
puts "--- disable/enable timing ---"
|
||||
|
||||
set_disable_timing [get_cells buf1]
|
||||
report_checks
|
||||
puts "PASS: disable buf1"
|
||||
|
||||
set_disable_timing [get_cells inv1]
|
||||
report_checks
|
||||
puts "PASS: disable inv1"
|
||||
|
||||
set_disable_timing [get_cells nand1]
|
||||
report_checks
|
||||
puts "PASS: disable nand1"
|
||||
|
||||
unset_disable_timing [get_cells buf1]
|
||||
unset_disable_timing [get_cells inv1]
|
||||
unset_disable_timing [get_cells nand1]
|
||||
report_checks
|
||||
puts "PASS: re-enable all"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Case analysis: exercises setConstant, clearConstants
|
||||
#---------------------------------------------------------------
|
||||
puts "--- case analysis ---"
|
||||
|
||||
set_case_analysis 1 [get_ports rst]
|
||||
report_checks
|
||||
puts "PASS: rst=1"
|
||||
|
||||
set_case_analysis 0 [get_ports rst]
|
||||
report_checks
|
||||
puts "PASS: rst=0"
|
||||
|
||||
unset_case_analysis [get_ports rst]
|
||||
report_checks
|
||||
puts "PASS: rst unset"
|
||||
|
||||
set_case_analysis 1 [get_ports d1]
|
||||
report_checks
|
||||
puts "PASS: d1=1"
|
||||
|
||||
set_case_analysis 0 [get_ports d3]
|
||||
report_checks
|
||||
puts "PASS: d3=0"
|
||||
|
||||
unset_case_analysis [get_ports d1]
|
||||
unset_case_analysis [get_ports d3]
|
||||
report_checks
|
||||
puts "PASS: all unset"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Load changes trigger delay recomputation on graph edges
|
||||
#---------------------------------------------------------------
|
||||
puts "--- load changes ---"
|
||||
|
||||
set_load 0.01 [get_ports q1]
|
||||
report_checks
|
||||
puts "PASS: q1 load=0.01"
|
||||
|
||||
set_load 0.05 [get_ports q2]
|
||||
report_checks
|
||||
puts "PASS: q2 load=0.05"
|
||||
|
||||
set_load 0.1 [get_ports q3]
|
||||
report_checks
|
||||
puts "PASS: q3 load=0.1"
|
||||
|
||||
set_load 0 [get_ports q1]
|
||||
set_load 0 [get_ports q2]
|
||||
set_load 0 [get_ports q3]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Through pin paths exercise reconvergent graph traversal
|
||||
#---------------------------------------------------------------
|
||||
puts "--- through pin queries ---"
|
||||
|
||||
catch {report_checks -through [get_pins nand1/ZN]} msg
|
||||
puts "through nand1: done"
|
||||
|
||||
catch {report_checks -through [get_pins nor1/ZN]} msg
|
||||
puts "through nor1: done"
|
||||
|
||||
catch {report_checks -through [get_pins and2/ZN]} msg
|
||||
puts "through and2: done"
|
||||
|
||||
catch {report_checks -through [get_pins or2/ZN]} msg
|
||||
puts "through or2: done"
|
||||
|
||||
puts "PASS: through pin queries"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_check_types exercises check edge categorization
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_check_types ---"
|
||||
report_check_types -max_delay -verbose
|
||||
puts "PASS: check_types max"
|
||||
|
||||
report_check_types -min_delay -verbose
|
||||
puts "PASS: check_types min"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
@ -0,0 +1 @@
|
|||
../../test/regression
|
||||
|
|
@ -0,0 +1,218 @@
|
|||
add_test(
|
||||
NAME tcl.liberty.read_sky130
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_read_sky130
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.liberty.read_sky130 PROPERTIES LABELS "tcl;module_liberty")
|
||||
|
||||
add_test(
|
||||
NAME tcl.liberty.read_nangate
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_read_nangate
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.liberty.read_nangate PROPERTIES LABELS "tcl;module_liberty")
|
||||
|
||||
add_test(
|
||||
NAME tcl.liberty.multi_corner
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_multi_corner
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.liberty.multi_corner PROPERTIES LABELS "tcl;module_liberty")
|
||||
|
||||
add_test(
|
||||
NAME tcl.liberty.read_asap7
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_read_asap7
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.liberty.read_asap7 PROPERTIES LABELS "tcl;module_liberty")
|
||||
|
||||
add_test(
|
||||
NAME tcl.liberty.read_ihp
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_read_ihp
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.liberty.read_ihp PROPERTIES LABELS "tcl;module_liberty")
|
||||
|
||||
add_test(
|
||||
NAME tcl.liberty.equiv_cells
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_equiv_cells
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.liberty.equiv_cells PROPERTIES LABELS "tcl;module_liberty")
|
||||
|
||||
add_test(
|
||||
NAME tcl.liberty.properties
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_properties
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.liberty.properties PROPERTIES LABELS "tcl;module_liberty")
|
||||
|
||||
add_test(
|
||||
NAME tcl.liberty.writer
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_writer
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.liberty.writer PROPERTIES LABELS "tcl;module_liberty")
|
||||
|
||||
add_test(
|
||||
NAME tcl.liberty.power
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_power
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.liberty.power PROPERTIES LABELS "tcl;module_liberty")
|
||||
|
||||
add_test(
|
||||
NAME tcl.liberty.wireload
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_wireload
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.liberty.wireload PROPERTIES LABELS "tcl;module_liberty")
|
||||
|
||||
add_test(
|
||||
NAME tcl.liberty.timing_models
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_timing_models
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.liberty.timing_models PROPERTIES LABELS "tcl;module_liberty")
|
||||
|
||||
add_test(
|
||||
NAME tcl.liberty.func_expr
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_func_expr
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.liberty.func_expr PROPERTIES LABELS "tcl;module_liberty")
|
||||
|
||||
add_test(
|
||||
NAME tcl.liberty.multi_lib_equiv
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_multi_lib_equiv
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.liberty.multi_lib_equiv PROPERTIES LABELS "tcl;module_liberty")
|
||||
|
||||
add_test(
|
||||
NAME tcl.liberty.write_roundtrip
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_write_roundtrip
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.liberty.write_roundtrip PROPERTIES LABELS "tcl;module_liberty")
|
||||
|
||||
add_test(
|
||||
NAME tcl.liberty.opcond_scale
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_opcond_scale
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.liberty.opcond_scale PROPERTIES LABELS "tcl;module_liberty")
|
||||
|
||||
add_test(
|
||||
NAME tcl.liberty.ccsn_ecsm
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_ccsn_ecsm
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.liberty.ccsn_ecsm PROPERTIES LABELS "tcl;module_liberty")
|
||||
|
||||
add_test(
|
||||
NAME tcl.liberty.cell_deep
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_cell_deep
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.liberty.cell_deep PROPERTIES LABELS "tcl;module_liberty")
|
||||
|
||||
add_test(
|
||||
NAME tcl.liberty.sky130_corners
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_sky130_corners
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.liberty.sky130_corners PROPERTIES LABELS "tcl;module_liberty")
|
||||
|
||||
add_test(
|
||||
NAME tcl.liberty.arc_model_deep
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_arc_model_deep
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.liberty.arc_model_deep PROPERTIES LABELS "tcl;module_liberty")
|
||||
|
||||
add_test(
|
||||
NAME tcl.liberty.writer_roundtrip2
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_writer_roundtrip
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.liberty.writer_roundtrip2 PROPERTIES LABELS "tcl;module_liberty")
|
||||
|
||||
add_test(
|
||||
NAME tcl.liberty.equiv_deep
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_equiv_deep
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.liberty.equiv_deep PROPERTIES LABELS "tcl;module_liberty")
|
||||
|
||||
add_test(
|
||||
NAME tcl.liberty.seq_scan_bus
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_seq_scan_bus
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.liberty.seq_scan_bus PROPERTIES LABELS "tcl;module_liberty")
|
||||
|
||||
add_test(
|
||||
NAME tcl.liberty.clkgate_lvlshift
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_clkgate_lvlshift
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.liberty.clkgate_lvlshift PROPERTIES LABELS "tcl;module_liberty")
|
||||
|
||||
add_test(
|
||||
NAME tcl.liberty.scan_signal_types
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_scan_signal_types
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.liberty.scan_signal_types PROPERTIES LABELS "tcl;module_liberty")
|
||||
|
||||
add_test(
|
||||
NAME tcl.liberty.leakage_power_deep
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_leakage_power_deep
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.liberty.leakage_power_deep PROPERTIES LABELS "tcl;module_liberty")
|
||||
|
||||
add_test(
|
||||
NAME tcl.liberty.timing_types_deep
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_timing_types_deep
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.liberty.timing_types_deep PROPERTIES LABELS "tcl;module_liberty")
|
||||
|
||||
add_test(
|
||||
NAME tcl.liberty.pgpin_voltage
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_pgpin_voltage
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.liberty.pgpin_voltage PROPERTIES LABELS "tcl;module_liberty")
|
||||
|
||||
add_test(
|
||||
NAME tcl.liberty.equiv_cross_lib
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_equiv_cross_lib
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.liberty.equiv_cross_lib PROPERTIES LABELS "tcl;module_liberty")
|
||||
|
||||
add_test(
|
||||
NAME tcl.liberty.busport_mem_iter
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_busport_mem_iter
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.liberty.busport_mem_iter PROPERTIES LABELS "tcl;module_liberty")
|
||||
|
||||
add_test(
|
||||
NAME tcl.liberty.equiv_map_libs
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_equiv_map_libs
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.liberty.equiv_map_libs PROPERTIES LABELS "tcl;module_liberty")
|
||||
|
||||
add_test(
|
||||
NAME tcl.liberty.cell_classify_pgpin
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_cell_classify_pgpin
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.liberty.cell_classify_pgpin PROPERTIES LABELS "tcl;module_liberty")
|
||||
|
||||
add_subdirectory(cpp)
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
add_executable(TestLiberty TestLiberty.cc)
|
||||
target_link_libraries(TestLiberty
|
||||
OpenSTA
|
||||
GTest::gtest
|
||||
GTest::gtest_main
|
||||
${TCL_LIBRARY}
|
||||
)
|
||||
target_include_directories(TestLiberty PRIVATE
|
||||
${STA_HOME}/include/sta
|
||||
${STA_HOME}
|
||||
${CMAKE_BINARY_DIR}/include/sta
|
||||
)
|
||||
gtest_discover_tests(TestLiberty
|
||||
WORKING_DIRECTORY ${STA_HOME}
|
||||
PROPERTIES LABELS "cpp;module_liberty"
|
||||
)
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,126 @@
|
|||
PASS: read Nangate45
|
||||
PASS: find_liberty_cells_matching INV_* (6 cells)
|
||||
PASS: find_liberty_cells_matching regexp BUF (6 cells)
|
||||
PASS: find_liberty_cells_matching nocase nand2 (0 cells)
|
||||
INV_X1 is_leaf = 1
|
||||
INV_X1 is_buffer = 0
|
||||
INV_X1 is_inverter = 1
|
||||
PASS: INV_X1 classification
|
||||
BUF_X1 is_leaf = 1
|
||||
BUF_X1 is_buffer = 1
|
||||
BUF_X1 is_inverter = 0
|
||||
PASS: BUF_X1 classification
|
||||
NAND2_X1 is_leaf = 1
|
||||
NAND2_X1 is_buffer = 0
|
||||
NAND2_X1 is_inverter = 0
|
||||
PASS: NAND2_X1 classification
|
||||
DFF_X1 is_leaf = 1
|
||||
DFF_X1 is_buffer = 0
|
||||
DFF_X1 is_inverter = 0
|
||||
PASS: DFF_X1 classification
|
||||
INV_X1 lib name = NangateOpenCellLibrary
|
||||
PASS: cell liberty_library
|
||||
SDFF_X1 has test_cell
|
||||
PASS: test_cell query
|
||||
INV_X1/A function =
|
||||
INV_X1/ZN function = !A
|
||||
PASS: port function
|
||||
TINV_X1/EN function =
|
||||
TINV_X1/ZN tristate_enable = !EN
|
||||
PASS: tristate_enable
|
||||
INV_X1/A bus_name = A
|
||||
PASS: bus_name
|
||||
INV_X1/A is_bus = 0
|
||||
INV_X1/A is_bus_bit = 0
|
||||
INV_X1/A is_bundle = 0
|
||||
INV_X1/A is_bundle_member = 0
|
||||
INV_X1/A has_members = 0
|
||||
PASS: port bus/bundle queries
|
||||
INV_X1/A is_pwr_gnd = 0
|
||||
PASS: is_pwr_gnd
|
||||
INV_X1/A scan_signal_type = none
|
||||
PASS: scan_signal_type
|
||||
SDFF_X1/SI scan_signal_type = none
|
||||
SDFF_X1/SI is_bus = 0
|
||||
PASS: scan port queries
|
||||
INV_X1 all ports = 4
|
||||
PASS: find_liberty_ports_matching *
|
||||
NAND2_X1 A* ports = 2
|
||||
PASS: find_liberty_ports_matching A*
|
||||
NAND2_X1 regexp ports = 2
|
||||
PASS: find_liberty_ports_matching regexp
|
||||
NAND2_X1 nocase zn ports = 0
|
||||
PASS: find_liberty_ports_matching nocase
|
||||
INV_X1 ports via iterator = 4
|
||||
PASS: LibertyCellPortIterator
|
||||
AOI21_X1 ports via iterator = 6
|
||||
PASS: AOI21_X1 port iterator
|
||||
Arc: INV_X1 A -> ZN role=combinational is_check=0
|
||||
sdf_cond=
|
||||
PASS: INV_X1 timing arc sets
|
||||
DFF Arc: DFF_X1 CK -> D role=hold is_check=1
|
||||
DFF Arc: DFF_X1 CK -> D role=setup is_check=1
|
||||
DFF Arc: DFF_X1 CK -> CK role=width is_check=1
|
||||
DFF Arc: DFF_X1 CK -> Q role=Reg Clk to Q is_check=0
|
||||
DFF Arc: DFF_X1 CK -> QN role=Reg Clk to Q is_check=0
|
||||
PASS: DFF_X1 timing arc sets
|
||||
DFFR Arc: DFFR_X1 CK -> D role=hold is_check=1
|
||||
DFFR Arc: DFFR_X1 CK -> D role=setup is_check=1
|
||||
DFFR Arc: DFFR_X1 CK -> RN role=recovery is_check=1
|
||||
DFFR Arc: DFFR_X1 CK -> RN role=removal is_check=1
|
||||
DFFR Arc: DFFR_X1 RN -> RN role=width is_check=1
|
||||
DFFR Arc: DFFR_X1 CK -> CK role=width is_check=1
|
||||
DFFR Arc: DFFR_X1 CK -> Q role=Reg Clk to Q is_check=0
|
||||
DFFR Arc: DFFR_X1 RN -> Q role=Reg Set/Clr is_check=0
|
||||
DFFR Arc: DFFR_X1 RN -> Q role=Reg Set/Clr is_check=0
|
||||
DFFR Arc: DFFR_X1 RN -> Q role=Reg Set/Clr is_check=0
|
||||
DFFR Arc: DFFR_X1 RN -> Q role=Reg Set/Clr is_check=0
|
||||
DFFR Arc: DFFR_X1 CK -> QN role=Reg Clk to Q is_check=0
|
||||
DFFR Arc: DFFR_X1 RN -> QN role=Reg Set/Clr is_check=0
|
||||
DFFR Arc: DFFR_X1 RN -> QN role=Reg Set/Clr is_check=0
|
||||
DFFR Arc: DFFR_X1 RN -> QN role=Reg Set/Clr is_check=0
|
||||
DFFR Arc: DFFR_X1 RN -> QN role=Reg Set/Clr is_check=0
|
||||
PASS: DFFR_X1 timing arc sets
|
||||
Arc detail: A rise -> ZN fall role=combinational
|
||||
Arc detail: A fall -> ZN rise role=combinational
|
||||
PASS: timing arc details
|
||||
DFF arc: rise -> rise role=hold
|
||||
DFF arc: rise -> fall role=hold
|
||||
DFF arc: rise -> rise role=setup
|
||||
DFF arc: rise -> fall role=setup
|
||||
DFF arc: rise -> fall role=width
|
||||
DFF arc: fall -> rise role=width
|
||||
DFF arc: rise -> rise role=Reg Clk to Q
|
||||
DFF arc: rise -> fall role=Reg Clk to Q
|
||||
DFF arc: rise -> rise role=Reg Clk to Q
|
||||
DFF arc: rise -> fall role=Reg Clk to Q
|
||||
PASS: DFF arc edge details
|
||||
Default opcond process = 1.0
|
||||
Default opcond voltage = 1.100000023841858
|
||||
Default opcond temperature = 25.0
|
||||
PASS: operating conditions
|
||||
Typical opcond process = 1.0
|
||||
Typical opcond voltage = 1.100000023841858
|
||||
Typical opcond temperature = 25.0
|
||||
PASS: named operating conditions
|
||||
Found wireload 5K_hvratio_1_1
|
||||
PASS: find_wireload
|
||||
Found wireload selection
|
||||
PASS: find_wireload_selection
|
||||
Library: NangateOpenCellLibrary
|
||||
PASS: liberty_library_iterator (1 libraries)
|
||||
INV_X1/A cap max = 1.700229965024007e-15
|
||||
INV_X1/A cap min = 1.5493600563490969e-15
|
||||
PASS: port capacitance with corner
|
||||
PwrGnd port: VDD dir=power
|
||||
PwrGnd port: VSS dir=ground
|
||||
PASS: pwr_gnd port queries
|
||||
FA_X1 port: VDD dir=power is_bus=0
|
||||
FA_X1 port: VSS dir=ground is_bus=0
|
||||
FA_X1 port: A dir=input is_bus=0
|
||||
FA_X1 port: B dir=input is_bus=0
|
||||
FA_X1 port: CI dir=input is_bus=0
|
||||
FA_X1 port: CO dir=output is_bus=0
|
||||
FA_X1 port: S dir=output is_bus=0
|
||||
PASS: FA_X1 port iterator
|
||||
ALL PASSED
|
||||
|
|
@ -0,0 +1,348 @@
|
|||
# Deep timing arc and model queries exercising uncovered code paths.
|
||||
# Targets:
|
||||
# TimingArc.cc: TimingArcSet full_name, sdf_cond, role, from, to,
|
||||
# timing_arcs iterator, from_edge_name, to_edge_name,
|
||||
# TimingArc from/to/fromEdge/toEdge/role,
|
||||
# timing_role_is_check
|
||||
# TableModel.cc: table model axis queries, value queries
|
||||
# Liberty.cc: findLibertyCell, findLibertyPort, timingArcSets iterator,
|
||||
# find_liberty_cells_matching regexp/nocase,
|
||||
# find_liberty_ports_matching, cell is_leaf/is_buffer/is_inverter,
|
||||
# liberty_library/test_cell/cell methods, port is_bus/is_bus_bit/
|
||||
# is_bundle/is_bundle_member/has_members/is_pwr_gnd/bus_name/
|
||||
# function/tristate_enable/scan_signal_type/set_direction,
|
||||
# LibertyPortMemberIterator, LibertyCellPortIterator
|
||||
# LibertyBuilder.cc: various cell build paths
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
############################################################
|
||||
# Read library
|
||||
############################################################
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
puts "PASS: read Nangate45"
|
||||
|
||||
############################################################
|
||||
# find_liberty_cells_matching with pattern/regexp/nocase
|
||||
############################################################
|
||||
set lib [lindex [get_libs NangateOpenCellLibrary] 0]
|
||||
|
||||
# Glob pattern matching
|
||||
set cells [$lib find_liberty_cells_matching "INV_*" 0 0]
|
||||
puts "PASS: find_liberty_cells_matching INV_* ([llength $cells] cells)"
|
||||
|
||||
# Regexp matching
|
||||
set cells_re [$lib find_liberty_cells_matching {^BUF_X[0-9]+$} 1 0]
|
||||
puts "PASS: find_liberty_cells_matching regexp BUF ([llength $cells_re] cells)"
|
||||
|
||||
# Case-insensitive matching
|
||||
set cells_nc [$lib find_liberty_cells_matching "nand2_*" 0 1]
|
||||
puts "PASS: find_liberty_cells_matching nocase nand2 ([llength $cells_nc] cells)"
|
||||
|
||||
############################################################
|
||||
# Cell property queries: is_leaf, is_buffer, is_inverter
|
||||
############################################################
|
||||
set inv_cell [get_lib_cell NangateOpenCellLibrary/INV_X1]
|
||||
puts "INV_X1 is_leaf = [$inv_cell is_leaf]"
|
||||
puts "INV_X1 is_buffer = [$inv_cell is_buffer]"
|
||||
puts "INV_X1 is_inverter = [$inv_cell is_inverter]"
|
||||
puts "PASS: INV_X1 classification"
|
||||
|
||||
set buf_cell [get_lib_cell NangateOpenCellLibrary/BUF_X1]
|
||||
puts "BUF_X1 is_leaf = [$buf_cell is_leaf]"
|
||||
puts "BUF_X1 is_buffer = [$buf_cell is_buffer]"
|
||||
puts "BUF_X1 is_inverter = [$buf_cell is_inverter]"
|
||||
puts "PASS: BUF_X1 classification"
|
||||
|
||||
set nand_cell [get_lib_cell NangateOpenCellLibrary/NAND2_X1]
|
||||
puts "NAND2_X1 is_leaf = [$nand_cell is_leaf]"
|
||||
puts "NAND2_X1 is_buffer = [$nand_cell is_buffer]"
|
||||
puts "NAND2_X1 is_inverter = [$nand_cell is_inverter]"
|
||||
puts "PASS: NAND2_X1 classification"
|
||||
|
||||
set dff_cell [get_lib_cell NangateOpenCellLibrary/DFF_X1]
|
||||
puts "DFF_X1 is_leaf = [$dff_cell is_leaf]"
|
||||
puts "DFF_X1 is_buffer = [$dff_cell is_buffer]"
|
||||
puts "DFF_X1 is_inverter = [$dff_cell is_inverter]"
|
||||
puts "PASS: DFF_X1 classification"
|
||||
|
||||
############################################################
|
||||
# Cell liberty_library method
|
||||
############################################################
|
||||
set cell_lib [$inv_cell liberty_library]
|
||||
puts "INV_X1 lib name = [$cell_lib name]"
|
||||
puts "PASS: cell liberty_library"
|
||||
|
||||
############################################################
|
||||
# Cell test_cell (for scan cells)
|
||||
############################################################
|
||||
catch {
|
||||
set sdff_cell [get_lib_cell NangateOpenCellLibrary/SDFF_X1]
|
||||
set test_cell [$sdff_cell test_cell]
|
||||
if {$test_cell ne ""} {
|
||||
puts "SDFF_X1 has test_cell"
|
||||
} else {
|
||||
puts "SDFF_X1 test_cell is null"
|
||||
}
|
||||
}
|
||||
puts "PASS: test_cell query"
|
||||
|
||||
############################################################
|
||||
# Port queries: bus_name, function, tristate_enable, scan_signal_type
|
||||
############################################################
|
||||
|
||||
# Function queries
|
||||
set inv_a [$inv_cell find_liberty_port A]
|
||||
set inv_zn [$inv_cell find_liberty_port ZN]
|
||||
puts "INV_X1/A function = [$inv_a function]"
|
||||
puts "INV_X1/ZN function = [$inv_zn function]"
|
||||
puts "PASS: port function"
|
||||
|
||||
# Tristate enable
|
||||
set tinv_cell [get_lib_cell NangateOpenCellLibrary/TINV_X1]
|
||||
set tinv_en [$tinv_cell find_liberty_port EN]
|
||||
set tinv_out [$tinv_cell find_liberty_port ZN]
|
||||
puts "TINV_X1/EN function = [$tinv_en function]"
|
||||
puts "TINV_X1/ZN tristate_enable = [$tinv_out tristate_enable]"
|
||||
puts "PASS: tristate_enable"
|
||||
|
||||
# Bus name (for bus ports - may be same as name for non-bus)
|
||||
puts "INV_X1/A bus_name = [$inv_a bus_name]"
|
||||
puts "PASS: bus_name"
|
||||
|
||||
# Is bus/bundle queries
|
||||
puts "INV_X1/A is_bus = [$inv_a is_bus]"
|
||||
puts "INV_X1/A is_bus_bit = [$inv_a is_bus_bit]"
|
||||
puts "INV_X1/A is_bundle = [$inv_a is_bundle]"
|
||||
puts "INV_X1/A is_bundle_member = [$inv_a is_bundle_member]"
|
||||
puts "INV_X1/A has_members = [$inv_a has_members]"
|
||||
puts "PASS: port bus/bundle queries"
|
||||
|
||||
# is_pwr_gnd
|
||||
puts "INV_X1/A is_pwr_gnd = [$inv_a is_pwr_gnd]"
|
||||
puts "PASS: is_pwr_gnd"
|
||||
|
||||
# scan_signal_type
|
||||
puts "INV_X1/A scan_signal_type = [$inv_a scan_signal_type]"
|
||||
puts "PASS: scan_signal_type"
|
||||
|
||||
# Check SDFF scan port
|
||||
catch {
|
||||
set sdff_cell [get_lib_cell NangateOpenCellLibrary/SDFF_X1]
|
||||
set sdff_si [$sdff_cell find_liberty_port SI]
|
||||
if {$sdff_si ne ""} {
|
||||
puts "SDFF_X1/SI scan_signal_type = [$sdff_si scan_signal_type]"
|
||||
puts "SDFF_X1/SI is_bus = [$sdff_si is_bus]"
|
||||
}
|
||||
}
|
||||
puts "PASS: scan port queries"
|
||||
|
||||
############################################################
|
||||
# find_liberty_ports_matching on a cell
|
||||
############################################################
|
||||
set ports [$inv_cell find_liberty_ports_matching "*" 0 0]
|
||||
puts "INV_X1 all ports = [llength $ports]"
|
||||
puts "PASS: find_liberty_ports_matching *"
|
||||
|
||||
set ports [$nand_cell find_liberty_ports_matching "A*" 0 0]
|
||||
puts "NAND2_X1 A* ports = [llength $ports]"
|
||||
puts "PASS: find_liberty_ports_matching A*"
|
||||
|
||||
# Regexp port matching
|
||||
set ports_re [$nand_cell find_liberty_ports_matching {^A[0-9]$} 1 0]
|
||||
puts "NAND2_X1 regexp ports = [llength $ports_re]"
|
||||
puts "PASS: find_liberty_ports_matching regexp"
|
||||
|
||||
# Case-insensitive port matching
|
||||
set ports_nc [$nand_cell find_liberty_ports_matching "zn" 0 1]
|
||||
puts "NAND2_X1 nocase zn ports = [llength $ports_nc]"
|
||||
puts "PASS: find_liberty_ports_matching nocase"
|
||||
|
||||
############################################################
|
||||
# LibertyCellPortIterator
|
||||
############################################################
|
||||
set port_iter [$inv_cell liberty_port_iterator]
|
||||
set port_count 0
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
incr port_count
|
||||
}
|
||||
$port_iter finish
|
||||
puts "INV_X1 ports via iterator = $port_count"
|
||||
puts "PASS: LibertyCellPortIterator"
|
||||
|
||||
# Port iterator on a more complex cell
|
||||
set aoi_cell [get_lib_cell NangateOpenCellLibrary/AOI21_X1]
|
||||
set port_iter [$aoi_cell liberty_port_iterator]
|
||||
set port_count 0
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
incr port_count
|
||||
}
|
||||
$port_iter finish
|
||||
puts "AOI21_X1 ports via iterator = $port_count"
|
||||
puts "PASS: AOI21_X1 port iterator"
|
||||
|
||||
############################################################
|
||||
# Timing arc set queries: full_name, sdf_cond, role
|
||||
############################################################
|
||||
set arc_sets [$inv_cell timing_arc_sets]
|
||||
foreach arc_set $arc_sets {
|
||||
set fn [$arc_set full_name]
|
||||
set from_port [$arc_set from]
|
||||
set to_port [$arc_set to]
|
||||
set role [$arc_set role]
|
||||
set is_check [sta::timing_role_is_check $role]
|
||||
puts "Arc: $fn role=$role is_check=$is_check"
|
||||
catch {
|
||||
set sdf [$arc_set sdf_cond]
|
||||
puts " sdf_cond=$sdf"
|
||||
}
|
||||
}
|
||||
puts "PASS: INV_X1 timing arc sets"
|
||||
|
||||
# DFF timing arcs (setup/hold/clk-to-q)
|
||||
set arc_sets [$dff_cell timing_arc_sets]
|
||||
foreach arc_set $arc_sets {
|
||||
set fn [$arc_set full_name]
|
||||
set role [$arc_set role]
|
||||
set is_check [sta::timing_role_is_check $role]
|
||||
puts "DFF Arc: $fn role=$role is_check=$is_check"
|
||||
}
|
||||
puts "PASS: DFF_X1 timing arc sets"
|
||||
|
||||
# DFFR has more arcs (recovery/removal)
|
||||
set dffr_cell [get_lib_cell NangateOpenCellLibrary/DFFR_X1]
|
||||
set arc_sets [$dffr_cell timing_arc_sets]
|
||||
foreach arc_set $arc_sets {
|
||||
set fn [$arc_set full_name]
|
||||
set role [$arc_set role]
|
||||
set is_check [sta::timing_role_is_check $role]
|
||||
puts "DFFR Arc: $fn role=$role is_check=$is_check"
|
||||
}
|
||||
puts "PASS: DFFR_X1 timing arc sets"
|
||||
|
||||
############################################################
|
||||
# TimingArc details: from_edge_name, to_edge_name
|
||||
############################################################
|
||||
set arc_sets [$inv_cell timing_arc_sets]
|
||||
foreach arc_set $arc_sets {
|
||||
set arcs [$arc_set timing_arcs]
|
||||
foreach arc $arcs {
|
||||
set from_name [[$arc from] bus_name]
|
||||
set to_name [[$arc to] bus_name]
|
||||
set from_edge [$arc from_edge_name]
|
||||
set to_edge [$arc to_edge_name]
|
||||
set arc_role [$arc role]
|
||||
puts " Arc detail: ${from_name} ${from_edge} -> ${to_name} ${to_edge} role=$arc_role"
|
||||
}
|
||||
}
|
||||
puts "PASS: timing arc details"
|
||||
|
||||
# DFF arc details (different roles: setup, hold, clk-to-q)
|
||||
set arc_sets [$dff_cell timing_arc_sets]
|
||||
foreach arc_set $arc_sets {
|
||||
set arcs [$arc_set timing_arcs]
|
||||
foreach arc $arcs {
|
||||
set from_edge [$arc from_edge_name]
|
||||
set to_edge [$arc to_edge_name]
|
||||
set arc_role [$arc role]
|
||||
puts " DFF arc: ${from_edge} -> ${to_edge} role=$arc_role"
|
||||
}
|
||||
}
|
||||
puts "PASS: DFF arc edge details"
|
||||
|
||||
############################################################
|
||||
# Operating conditions queries
|
||||
############################################################
|
||||
set op_cond [$lib default_operating_conditions]
|
||||
if {$op_cond ne ""} {
|
||||
puts "Default opcond process = [$op_cond process]"
|
||||
puts "Default opcond voltage = [$op_cond voltage]"
|
||||
puts "Default opcond temperature = [$op_cond temperature]"
|
||||
}
|
||||
puts "PASS: operating conditions"
|
||||
|
||||
# Named operating conditions
|
||||
catch {
|
||||
set typical_cond [$lib find_operating_conditions typical]
|
||||
if {$typical_cond ne ""} {
|
||||
puts "Typical opcond process = [$typical_cond process]"
|
||||
puts "Typical opcond voltage = [$typical_cond voltage]"
|
||||
puts "Typical opcond temperature = [$typical_cond temperature]"
|
||||
}
|
||||
}
|
||||
puts "PASS: named operating conditions"
|
||||
|
||||
############################################################
|
||||
# Wireload queries
|
||||
############################################################
|
||||
catch {
|
||||
set wl [$lib find_wireload "5K_hvratio_1_1"]
|
||||
if {$wl ne ""} {
|
||||
puts "Found wireload 5K_hvratio_1_1"
|
||||
}
|
||||
}
|
||||
puts "PASS: find_wireload"
|
||||
|
||||
catch {
|
||||
set wlsel [$lib find_wireload_selection "WiresloaSelection"]
|
||||
if {$wlsel ne ""} {
|
||||
puts "Found wireload selection"
|
||||
}
|
||||
}
|
||||
puts "PASS: find_wireload_selection"
|
||||
|
||||
############################################################
|
||||
# LibertyLibraryIterator
|
||||
############################################################
|
||||
set lib_iter [sta::liberty_library_iterator]
|
||||
set lib_count 0
|
||||
while {[$lib_iter has_next]} {
|
||||
set lib [$lib_iter next]
|
||||
puts "Library: [$lib name]"
|
||||
incr lib_count
|
||||
}
|
||||
$lib_iter finish
|
||||
puts "PASS: liberty_library_iterator ($lib_count libraries)"
|
||||
|
||||
############################################################
|
||||
# Port capacitance with corner/min_max
|
||||
############################################################
|
||||
set corner [lindex [sta::corners] 0]
|
||||
set inv_a_port [$inv_cell find_liberty_port A]
|
||||
catch {
|
||||
set cap_max [$inv_a_port capacitance $corner "max"]
|
||||
puts "INV_X1/A cap max = $cap_max"
|
||||
set cap_min [$inv_a_port capacitance $corner "min"]
|
||||
puts "INV_X1/A cap min = $cap_min"
|
||||
}
|
||||
puts "PASS: port capacitance with corner"
|
||||
|
||||
############################################################
|
||||
# Power ground port queries
|
||||
############################################################
|
||||
set port_iter [$inv_cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
if {[$port is_pwr_gnd]} {
|
||||
puts " PwrGnd port: [$port bus_name] dir=[sta::liberty_port_direction $port]"
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
puts "PASS: pwr_gnd port queries"
|
||||
|
||||
# Check a cell with bus ports (FA_X1 has bus-like ports)
|
||||
catch {
|
||||
set fa_cell [get_lib_cell NangateOpenCellLibrary/FA_X1]
|
||||
set port_iter [$fa_cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
puts " FA_X1 port: [$port bus_name] dir=$dir is_bus=[$port is_bus]"
|
||||
}
|
||||
$port_iter finish
|
||||
}
|
||||
puts "PASS: FA_X1 port iterator"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
@ -0,0 +1,122 @@
|
|||
PASS: read fakeram45_64x7
|
||||
fakeram cell found
|
||||
clk dir=input bus=0 bit=0 bundle=0 bm=0 members=0 func="" tri=""
|
||||
rd_out dir=output bus=1 bit=0 bundle=0 bm=0 members=1 func="" tri=""
|
||||
member[0]: rd_out[6] dir=output bit=1
|
||||
member[1]: rd_out[5] dir=output bit=1
|
||||
member[2]: rd_out[4] dir=output bit=1
|
||||
total members=7
|
||||
we_in dir=input bus=0 bit=0 bundle=0 bm=0 members=0 func="" tri=""
|
||||
ce_in dir=input bus=0 bit=0 bundle=0 bm=0 members=0 func="" tri=""
|
||||
addr_in dir=input bus=1 bit=0 bundle=0 bm=0 members=1 func="" tri=""
|
||||
member[0]: addr_in[5] dir=input bit=1
|
||||
member[1]: addr_in[4] dir=input bit=1
|
||||
member[2]: addr_in[3] dir=input bit=1
|
||||
total members=6
|
||||
wd_in dir=input bus=1 bit=0 bundle=0 bm=0 members=1 func="" tri=""
|
||||
member[0]: wd_in[6] dir=input bit=1
|
||||
member[1]: wd_in[5] dir=input bit=1
|
||||
member[2]: wd_in[4] dir=input bit=1
|
||||
total members=7
|
||||
w_mask_in dir=input bus=1 bit=0 bundle=0 bm=0 members=1 func="" tri=""
|
||||
member[0]: w_mask_in[6] dir=input bit=1
|
||||
member[1]: w_mask_in[5] dir=input bit=1
|
||||
member[2]: w_mask_in[4] dir=input bit=1
|
||||
total members=7
|
||||
PASS: fakeram bus port iteration
|
||||
fakeram45_64x32: bus_ports=4 total_bits=102
|
||||
fakeram45_256x16: bus_ports=4 total_bits=56
|
||||
fakeram45_512x64: bus_ports=4 total_bits=201
|
||||
fakeram45_1024x32: bus_ports=4 total_bits=106
|
||||
fakeram45_64x96: bus_ports=4 total_bits=294
|
||||
PASS: SRAM macro bus ports
|
||||
PASS: read gf180mcu SRAM
|
||||
Warning: liberty_busport_mem_iter.tcl line 1, library 'gf180mcu_fd_ip_sram__sram256x8m8wm1' not found.
|
||||
gf180mcu cells: 0
|
||||
PASS: gf180mcu SRAM bus ports
|
||||
PASS: read Nangate45
|
||||
INV_X1 leaf=1 buf=0 inv=1 area=0.532000 du=0 arcs=1
|
||||
INV_X2 leaf=1 buf=0 inv=1 area=0.798000 du=0 arcs=1
|
||||
BUF_X1 leaf=1 buf=1 inv=0 area=0.798000 du=0 arcs=1
|
||||
BUF_X2 leaf=1 buf=1 inv=0 area=1.064000 du=0 arcs=1
|
||||
CLKBUF_X1 leaf=1 buf=1 inv=0 area=0.798000 du=0 arcs=1
|
||||
NAND2_X1 leaf=1 buf=0 inv=0 area=0.798000 du=0 arcs=2
|
||||
NOR2_X1 leaf=1 buf=0 inv=0 area=0.798000 du=0 arcs=2
|
||||
AND2_X1 leaf=1 buf=0 inv=0 area=1.064000 du=0 arcs=2
|
||||
OR2_X1 leaf=1 buf=0 inv=0 area=1.064000 du=0 arcs=2
|
||||
XOR2_X1 leaf=1 buf=0 inv=0 area=1.596000 du=0 arcs=4
|
||||
MUX2_X1 leaf=1 buf=0 inv=0 area=1.862000 du=0 arcs=6
|
||||
AOI21_X1 leaf=1 buf=0 inv=0 area=1.064000 du=0 arcs=5
|
||||
OAI21_X1 leaf=1 buf=0 inv=0 area=1.064000 du=0 arcs=5
|
||||
AOI22_X1 leaf=1 buf=0 inv=0 area=1.330000 du=0 arcs=12
|
||||
OAI22_X1 leaf=1 buf=0 inv=0 area=1.330000 du=0 arcs=12
|
||||
DFF_X1 leaf=1 buf=0 inv=0 area=4.522000 du=0 arcs=5
|
||||
DFF_X2 leaf=1 buf=0 inv=0 area=5.054000 du=0 arcs=5
|
||||
DFFR_X1 leaf=1 buf=0 inv=0 area=5.320000 du=0 arcs=16
|
||||
DFFS_X1 leaf=1 buf=0 inv=0 area=5.320000 du=0 arcs=16
|
||||
DFFRS_X1 leaf=1 buf=0 inv=0 area=6.384000 du=0 arcs=35
|
||||
SDFF_X1 leaf=1 buf=0 inv=0 area=6.118000 du=0 arcs=9
|
||||
SDFFR_X1 leaf=1 buf=0 inv=0 area=6.650000 du=0 arcs=44
|
||||
SDFFRS_X1 leaf=1 buf=0 inv=0 area=7.714000 du=0 arcs=111
|
||||
TLAT_X1 leaf=1 buf=0 inv=0 area=3.458000 du=0 arcs=7
|
||||
TINV_X1 leaf=1 buf=0 inv=0 area=1.064000 du=0 arcs=3
|
||||
CLKGATETST_X1 leaf=1 buf=0 inv=0 area=3.990000 du=0 arcs=9
|
||||
HA_X1 leaf=1 buf=0 inv=0 area=2.660000 du=0 arcs=6
|
||||
FA_X1 leaf=1 buf=0 inv=0 area=4.256000 du=0 arcs=18
|
||||
ANTENNA_X1 leaf=1 buf=0 inv=0 area=0.266000 du=1 arcs=0
|
||||
FILLCELL_X1 leaf=1 buf=0 inv=0 area=0.266000 du=1 arcs=0
|
||||
FILLCELL_X2 leaf=1 buf=0 inv=0 area=0.266000 du=1 arcs=0
|
||||
LOGIC0_X1 leaf=1 buf=0 inv=0 area=0.532000 du=1 arcs=0
|
||||
LOGIC1_X1 leaf=1 buf=0 inv=0 area=0.532000 du=1 arcs=0
|
||||
PASS: cell classification
|
||||
--- test_cell / scan queries ---
|
||||
SDFF_X1 test_cell is null
|
||||
SDFFR_X1 test_cell is null
|
||||
SDFFRS_X1 test_cell is null
|
||||
DFF_X1 has no test_cell (expected)
|
||||
PASS: test_cell queries
|
||||
--- function and tristate queries ---
|
||||
TINV_X1/VDD dir=power func="" tri=""
|
||||
TINV_X1/VSS dir=ground func="" tri=""
|
||||
TINV_X1/EN dir=input func="" tri=""
|
||||
TINV_X1/I dir=input func="" tri=""
|
||||
TINV_X1/ZN dir=tristate func="!I" tri="!EN"
|
||||
PASS: TINV tristate queries
|
||||
CLKGATETST_X1/VDD dir=power func=""
|
||||
CLKGATETST_X1/VSS dir=ground func=""
|
||||
CLKGATETST_X1/IQ dir=internal func=""
|
||||
CLKGATETST_X1/CK dir=input func=""
|
||||
CLKGATETST_X1/E dir=input func=""
|
||||
CLKGATETST_X1/SE dir=input func=""
|
||||
CLKGATETST_X1/GCK dir=output func=""
|
||||
PASS: CLKGATETST queries
|
||||
INV_X1/ZN func=!A
|
||||
BUF_X1/Z func=A
|
||||
NAND2_X1/ZN func=!(A1*A2)
|
||||
NOR2_X1/ZN func=!(A1+A2)
|
||||
AND2_X1/ZN func=A1*A2
|
||||
OR2_X1/ZN func=A1+A2
|
||||
XOR2_X1/Z func=A^B
|
||||
XNOR2_X1/ZN func=!(A^B)
|
||||
AOI21_X1/ZN func=!(A+(B1*B2))
|
||||
OAI21_X1/ZN func=!(A*(B1+B2))
|
||||
MUX2_X1/Z func=(S*B)+(A*!S)
|
||||
HA_X1/CO func=A*B
|
||||
HA_X1/S func=A^B
|
||||
FA_X1/CO func=(A*B)+(CI*(A+B))
|
||||
FA_X1/S func=CI^(A^B)
|
||||
PASS: output function queries
|
||||
PASS: read Sky130
|
||||
sky130_fd_sc_hd__ebufn_1/A dir=input func="" tri=""
|
||||
sky130_fd_sc_hd__ebufn_1/TE_B dir=input func="" tri=""
|
||||
sky130_fd_sc_hd__ebufn_1/Z dir=tristate func="A" tri="!TE_B"
|
||||
sky130_fd_sc_hd__ebufn_2/A dir=input func="" tri=""
|
||||
sky130_fd_sc_hd__ebufn_2/TE_B dir=input func="" tri=""
|
||||
sky130_fd_sc_hd__ebufn_2/Z dir=tristate func="A" tri="!TE_B"
|
||||
PASS: Sky130 tristate port queries
|
||||
Warning: ../../test/nangate45/fake_macros.lib line 32, default_max_transition is 0.0.
|
||||
PASS: read fake_macros
|
||||
PASS: write_liberty fakeram
|
||||
Warning: /workspace/sta/OpenSTA/liberty/test/results/liberty_busport_mem_iter_write.lib line 1, library fakeram45_64x7 already exists.
|
||||
PASS: read roundtrip library
|
||||
ALL PASSED
|
||||
|
|
@ -0,0 +1,307 @@
|
|||
# Test bus port member iteration, bundle ports, port functions,
|
||||
# tristate enable, sequential queries, and diverse cell classification.
|
||||
# Targets:
|
||||
# Liberty.cc: LibertyPort::isBus, isBundle, isBusBit, isBundleMember,
|
||||
# hasMembers, bundlePort, findLibertyMember,
|
||||
# LibertyPortMemberIterator iteration,
|
||||
# LibertyCell::portCount, isBuffer, isInverter, isClockGate,
|
||||
# isClockGateLatchPosedge, isMacro, isMemory, isPad, isLeaf,
|
||||
# testCell, hasSequentials, timingArcSetCount, findTimingArcSet,
|
||||
# area, footprint, dontUse, setDontUse,
|
||||
# driveResistance, fanoutLoad, capacitanceIsOneValue
|
||||
# LibertyReader.cc: bus port definitions, three_state enable parsing,
|
||||
# test_cell/scan signal parsing, function/tristate_enable visitors,
|
||||
# beginBusPort, endBusPort
|
||||
# LibertyBuilder.cc: cell construction for bus/tristate/sequential
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
############################################################
|
||||
# Read SRAM macro library (has bus ports)
|
||||
############################################################
|
||||
read_liberty ../../test/nangate45/fakeram45_64x7.lib
|
||||
puts "PASS: read fakeram45_64x7"
|
||||
|
||||
# Query bus port properties
|
||||
set cell [get_lib_cell fakeram45_64x7/fakeram45_64x7]
|
||||
puts "fakeram cell found"
|
||||
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set name [get_name $port]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
set is_bus [$port is_bus]
|
||||
set is_bit [$port is_bus_bit]
|
||||
set is_bundle [$port is_bundle]
|
||||
set is_bm [$port is_bundle_member]
|
||||
set has_mem [$port has_members]
|
||||
set func [$port function]
|
||||
set tri [$port tristate_enable]
|
||||
puts " $name dir=$dir bus=$is_bus bit=$is_bit bundle=$is_bundle bm=$is_bm members=$has_mem func=\"$func\" tri=\"$tri\""
|
||||
if {$has_mem} {
|
||||
set mem_iter [$port member_iterator]
|
||||
set count 0
|
||||
while {[$mem_iter has_next]} {
|
||||
set mem [$mem_iter next]
|
||||
set mname [get_name $mem]
|
||||
set mdir [sta::liberty_port_direction $mem]
|
||||
set m_is_bit [$mem is_bus_bit]
|
||||
if {$count < 3} {
|
||||
puts " member[$count]: $mname dir=$mdir bit=$m_is_bit"
|
||||
}
|
||||
incr count
|
||||
}
|
||||
$mem_iter finish
|
||||
puts " total members=$count"
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
puts "PASS: fakeram bus port iteration"
|
||||
|
||||
############################################################
|
||||
# Read other SRAM macros with different bus widths
|
||||
############################################################
|
||||
foreach lib_name {fakeram45_64x32 fakeram45_256x16 fakeram45_512x64
|
||||
fakeram45_1024x32 fakeram45_64x96} {
|
||||
catch {
|
||||
read_liberty ../../test/nangate45/${lib_name}.lib
|
||||
set cell [get_lib_cell ${lib_name}/${lib_name}]
|
||||
if {$cell != "NULL"} {
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
set bus_count 0
|
||||
set bit_count 0
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
if {[$port is_bus]} {
|
||||
incr bus_count
|
||||
set mem_iter [$port member_iterator]
|
||||
while {[$mem_iter has_next]} {
|
||||
set mem [$mem_iter next]
|
||||
incr bit_count
|
||||
}
|
||||
$mem_iter finish
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
puts "$lib_name: bus_ports=$bus_count total_bits=$bit_count"
|
||||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: SRAM macro bus ports"
|
||||
|
||||
############################################################
|
||||
# Read SRAM macro from GF180MCU
|
||||
############################################################
|
||||
read_liberty ../../test/gf180mcu_sram.lib.gz
|
||||
puts "PASS: read gf180mcu SRAM"
|
||||
|
||||
catch {
|
||||
set gf_cells [get_lib_cells gf180mcu_fd_ip_sram__sram256x8m8wm1/*]
|
||||
puts "gf180mcu cells: [llength $gf_cells]"
|
||||
foreach cell_obj $gf_cells {
|
||||
set cname [get_full_name $cell_obj]
|
||||
catch {
|
||||
set cell [get_lib_cell $cname]
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
set bus_count 0
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
if {[$port is_bus] || [$port has_members]} {
|
||||
incr bus_count
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
puts " [get_name $cell_obj]: bus_ports=$bus_count"
|
||||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: gf180mcu SRAM bus ports"
|
||||
|
||||
############################################################
|
||||
# Read Nangate for cell classification queries
|
||||
############################################################
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
puts "PASS: read Nangate45"
|
||||
|
||||
# Cell classification
|
||||
foreach cell_name {INV_X1 INV_X2 BUF_X1 BUF_X2 CLKBUF_X1
|
||||
NAND2_X1 NOR2_X1 AND2_X1 OR2_X1 XOR2_X1
|
||||
MUX2_X1 AOI21_X1 OAI21_X1 AOI22_X1 OAI22_X1
|
||||
DFF_X1 DFF_X2 DFFR_X1 DFFS_X1 DFFRS_X1
|
||||
SDFF_X1 SDFFR_X1 SDFFRS_X1 TLAT_X1
|
||||
TINV_X1 CLKGATETST_X1 HA_X1 FA_X1
|
||||
ANTENNA_X1 FILLCELL_X1 FILLCELL_X2 LOGIC0_X1 LOGIC1_X1} {
|
||||
catch {
|
||||
set cell [get_lib_cell NangateOpenCellLibrary/$cell_name]
|
||||
if {$cell != "NULL"} {
|
||||
set is_leaf [$cell is_leaf]
|
||||
set is_buf [$cell is_buffer]
|
||||
set is_inv [$cell is_inverter]
|
||||
set area [get_property $cell area]
|
||||
set du [get_property $cell dont_use]
|
||||
set arc_sets [$cell timing_arc_sets]
|
||||
set arc_count [llength $arc_sets]
|
||||
puts "$cell_name leaf=$is_leaf buf=$is_buf inv=$is_inv area=$area du=$du arcs=$arc_count"
|
||||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: cell classification"
|
||||
|
||||
############################################################
|
||||
# Test cell and scan signal type queries
|
||||
############################################################
|
||||
puts "--- test_cell / scan queries ---"
|
||||
|
||||
# SDFF has test_cell
|
||||
catch {
|
||||
set sdff [get_lib_cell NangateOpenCellLibrary/SDFF_X1]
|
||||
set tc [$sdff test_cell]
|
||||
if {$tc != "NULL"} {
|
||||
puts "SDFF_X1 has test_cell"
|
||||
} else {
|
||||
puts "SDFF_X1 test_cell is null"
|
||||
}
|
||||
}
|
||||
|
||||
catch {
|
||||
set sdffr [get_lib_cell NangateOpenCellLibrary/SDFFR_X1]
|
||||
set tc [$sdffr test_cell]
|
||||
if {$tc != "NULL"} {
|
||||
puts "SDFFR_X1 has test_cell"
|
||||
} else {
|
||||
puts "SDFFR_X1 test_cell is null"
|
||||
}
|
||||
}
|
||||
|
||||
catch {
|
||||
set sdffrs [get_lib_cell NangateOpenCellLibrary/SDFFRS_X1]
|
||||
set tc [$sdffrs test_cell]
|
||||
if {$tc != "NULL"} {
|
||||
puts "SDFFRS_X1 has test_cell"
|
||||
} else {
|
||||
puts "SDFFRS_X1 test_cell is null"
|
||||
}
|
||||
}
|
||||
|
||||
# Regular DFF should NOT have test_cell
|
||||
catch {
|
||||
set dff [get_lib_cell NangateOpenCellLibrary/DFF_X1]
|
||||
set tc [$dff test_cell]
|
||||
if {$tc != "NULL"} {
|
||||
puts "DFF_X1 has test_cell (unexpected)"
|
||||
} else {
|
||||
puts "DFF_X1 has no test_cell (expected)"
|
||||
}
|
||||
}
|
||||
puts "PASS: test_cell queries"
|
||||
|
||||
############################################################
|
||||
# Port function and tristate enable queries
|
||||
############################################################
|
||||
puts "--- function and tristate queries ---"
|
||||
|
||||
# Tristate inverter
|
||||
catch {
|
||||
set tinv [get_lib_cell NangateOpenCellLibrary/TINV_X1]
|
||||
set port_iter [$tinv liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set name [get_name $port]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
set func [$port function]
|
||||
set tri [$port tristate_enable]
|
||||
puts "TINV_X1/$name dir=$dir func=\"$func\" tri=\"$tri\""
|
||||
}
|
||||
$port_iter finish
|
||||
}
|
||||
puts "PASS: TINV tristate queries"
|
||||
|
||||
# Clock gate tester
|
||||
catch {
|
||||
set clkgt [get_lib_cell NangateOpenCellLibrary/CLKGATETST_X1]
|
||||
set port_iter [$clkgt liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set name [get_name $port]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
set func [$port function]
|
||||
puts "CLKGATETST_X1/$name dir=$dir func=\"$func\""
|
||||
}
|
||||
$port_iter finish
|
||||
}
|
||||
puts "PASS: CLKGATETST queries"
|
||||
|
||||
# Output functions for various logic cells
|
||||
foreach cell_name {INV_X1 BUF_X1 NAND2_X1 NOR2_X1 AND2_X1 OR2_X1
|
||||
XOR2_X1 XNOR2_X1 AOI21_X1 OAI21_X1 MUX2_X1
|
||||
HA_X1 FA_X1} {
|
||||
catch {
|
||||
set cell [get_lib_cell NangateOpenCellLibrary/$cell_name]
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
if {$dir == "output"} {
|
||||
set func [$port function]
|
||||
if {$func != ""} {
|
||||
puts "$cell_name/[get_name $port] func=$func"
|
||||
}
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
}
|
||||
}
|
||||
puts "PASS: output function queries"
|
||||
|
||||
############################################################
|
||||
# Read Sky130 for tristate and latch port queries
|
||||
############################################################
|
||||
read_liberty ../../test/sky130hd/sky130hd_tt.lib
|
||||
puts "PASS: read Sky130"
|
||||
|
||||
# Tristate buffer port queries
|
||||
foreach cell_name {sky130_fd_sc_hd__ebufn_1 sky130_fd_sc_hd__ebufn_2} {
|
||||
catch {
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set name [get_name $port]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
set func [$port function]
|
||||
set tri [$port tristate_enable]
|
||||
set is_pg [$port is_pwr_gnd]
|
||||
if {!$is_pg} {
|
||||
puts "$cell_name/$name dir=$dir func=\"$func\" tri=\"$tri\""
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
}
|
||||
}
|
||||
puts "PASS: Sky130 tristate port queries"
|
||||
|
||||
############################################################
|
||||
# Read fake_macros library for memory/macro classification
|
||||
############################################################
|
||||
catch {
|
||||
read_liberty ../../test/nangate45/fake_macros.lib
|
||||
puts "PASS: read fake_macros"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Write roundtrip with bus ports
|
||||
############################################################
|
||||
set outfile [make_result_file liberty_busport_mem_iter_write.lib]
|
||||
sta::write_liberty fakeram45_64x7 $outfile
|
||||
puts "PASS: write_liberty fakeram"
|
||||
|
||||
# Read back
|
||||
catch {
|
||||
read_liberty $outfile
|
||||
puts "PASS: read roundtrip library"
|
||||
} msg
|
||||
if {[string match "Error*" $msg]} {
|
||||
puts "INFO: roundtrip issue: [string range $msg 0 80]"
|
||||
}
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
@ -0,0 +1,138 @@
|
|||
PASS: read ASAP7 CCSN library
|
||||
PASS: CCSN lib cells total: 1
|
||||
Cell A2O1A1Ixp33_ASAP7_75t_L
|
||||
Library asap7sc7p5t_AO_LVT_FF_ccsn_211120
|
||||
File ../../test/asap7_ccsn.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=((!A1*!B)+(!A2*!B))+!C
|
||||
A1 input 0.49-0.63
|
||||
A2 input 0.53-0.63
|
||||
B input 0.47-0.66
|
||||
C input 0.36-0.63
|
||||
PASS: reported all CCSN cells
|
||||
PASS: read ASAP7 SEQ RVT FF
|
||||
PASS: ASAP7 DFF* cells: 9
|
||||
Cell DFFHQNx1_ASAP7_75t_R
|
||||
Library asap7sc7p5t_SEQ_RVT_FF_nldm_220123
|
||||
File ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
VDD power
|
||||
VSS ground
|
||||
QN output function=IQN
|
||||
CLK input 0.40-0.52
|
||||
D input 0.55-0.62
|
||||
IQN internal
|
||||
IQNN internal
|
||||
PASS: ASAP7 DFF cell report
|
||||
Cell DFFHQNx2_ASAP7_75t_R
|
||||
Library asap7sc7p5t_SEQ_RVT_FF_nldm_220123
|
||||
File ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
VDD power
|
||||
VSS ground
|
||||
QN output function=IQN
|
||||
CLK input 0.40-0.52
|
||||
D input 0.55-0.62
|
||||
IQN internal
|
||||
IQNN internal
|
||||
PASS: ASAP7 DFF x2 cell report
|
||||
Warning: liberty_ccsn_ecsm.tcl line 1, liberty cell 'asap7sc7p5t_SEQ_RVT_FF_nldm_220123/SDFHQNx1_ASAP7_75t_R' not found.
|
||||
PASS: ASAP7 SDFF cell report
|
||||
Warning: liberty_ccsn_ecsm.tcl line 1, liberty cell 'asap7sc7p5t_SEQ_RVT_FF_nldm_220123/SDFHQNx2_ASAP7_75t_R' not found.
|
||||
PASS: ASAP7 SDFF x2 cell report
|
||||
Cell ICGx1_ASAP7_75t_R
|
||||
Library asap7sc7p5t_SEQ_RVT_FF_nldm_220123
|
||||
File ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
VDD power
|
||||
VSS ground
|
||||
IQ internal
|
||||
GCLK output
|
||||
CLK input 1.63-2.39
|
||||
ENA input 0.33-0.47
|
||||
SE input 0.39-0.47
|
||||
PASS: ASAP7 ICG cell report
|
||||
Cell ICGx2_ASAP7_75t_R
|
||||
Library asap7sc7p5t_SEQ_RVT_FF_nldm_220123
|
||||
File ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
VDD power
|
||||
VSS ground
|
||||
IQ internal
|
||||
GCLK output
|
||||
CLK input 1.63-2.39
|
||||
ENA input 0.33-0.47
|
||||
SE input 0.39-0.47
|
||||
PASS: ASAP7 ICG x2 cell report
|
||||
PASS: ASAP7 ASYNC cells: 0
|
||||
PASS: ASAP7 DFFR cells reported
|
||||
PASS: read ASAP7 SEQ SS
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13178, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13211, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13244, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13277, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13310, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13343, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13376, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14772, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14805, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14838, timing group from output port.
|
||||
PASS: read ASAP7 SIMPLE
|
||||
PASS: ASAP7 SIMPLE cells: 56
|
||||
PASS: read ASAP7 AO
|
||||
PASS: ASAP7 AO* cells: 40
|
||||
PASS: read ASAP7 OA
|
||||
PASS: ASAP7 OA* cells: 32
|
||||
PASS: read ASAP7 INVBUF
|
||||
PASS: read IHP sg13g2
|
||||
Cell sg13g2_ebufn_2
|
||||
Library sg13g2_stdcell_typ_1p20V_25C
|
||||
File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
Z tristate enable=!TE_B function=A 4.51-7.42
|
||||
A input 2.58-2.66
|
||||
TE_B input 6.21-6.60
|
||||
PASS: IHP tristate buffer report
|
||||
Cell sg13g2_sdfbbp_1
|
||||
Library sg13g2_stdcell_typ_1p20V_25C
|
||||
File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
Q output function=IQ
|
||||
Q_N output function=IQN
|
||||
CLK input 2.97-3.06
|
||||
D input 1.95-2.01
|
||||
RESET_B input 1.74
|
||||
SCD input 1.96-2.00
|
||||
SCE input 3.18-3.92
|
||||
SET_B input 5.25
|
||||
IQ internal
|
||||
IQN internal
|
||||
PASS: IHP scan DFF report
|
||||
Cell sg13g2_dlhq_1
|
||||
Library sg13g2_stdcell_typ_1p20V_25C
|
||||
File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
Q output function=IQ
|
||||
D input 2.26-2.31
|
||||
GATE input 1.69-2.58
|
||||
IQ internal
|
||||
IQN internal
|
||||
PASS: IHP latch report
|
||||
Cell sg13g2_mux2_1
|
||||
Library sg13g2_stdcell_typ_1p20V_25C
|
||||
File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
X output function=(!S*A0)+(S*A1)
|
||||
A0 input 0.38-3.63
|
||||
A1 input 0.52-3.70
|
||||
S input 5.00-5.09
|
||||
PASS: IHP mux report
|
||||
PASS: read IHP 1.5V
|
||||
PASS: read latch3 library
|
||||
PASS: read backslash_eol library
|
||||
PASS: read float_as_str library
|
||||
Warning: ../../test/liberty_arcs_one2one_1.lib line 48, timing port A and related port Y are different sizes.
|
||||
PASS: read arcs_one2one_1 library
|
||||
Warning: ../../test/liberty_arcs_one2one_2.lib line 48, timing port A and related port Y are different sizes.
|
||||
PASS: read arcs_one2one_2 library
|
||||
PASS: read gf180mcu SRAM library
|
||||
PASS: read ASAP7 SEQ LVT
|
||||
PASS: read ASAP7 SEQ SLVT
|
||||
PASS: read ASAP7 INVBUF LVT
|
||||
PASS: read ASAP7 INVBUF SLVT
|
||||
PASS: write_liberty ASAP7 SEQ
|
||||
PASS: write_liberty IHP
|
||||
ALL PASSED
|
||||
|
|
@ -0,0 +1,243 @@
|
|||
# Test CCSN (current source) models and various timing model types.
|
||||
# Targets:
|
||||
# LibertyReader.cc: beginCcs/endCcs, receiver_capacitance groups,
|
||||
# ECSM waveform handling, timing_type combinations,
|
||||
# beginOutputCurrentRise/Fall, visitReceiverCapacitance,
|
||||
# polynomial model visitors, ccsn noise model visitors,
|
||||
# leakage_power groups, internal_power groups,
|
||||
# max_capacitance/max_transition on pins, min_pulse_width
|
||||
# TableModel.cc: different table axis variables, GateTableModel,
|
||||
# CheckTableModel, 3D tables, receiver model tables
|
||||
# TimingArc.cc: timing arc type queries (removal, recovery,
|
||||
# three_state_enable, rising_edge, min_pulse_width)
|
||||
# Liberty.cc: timing arc set queries, hasTimingArcs, timingArcSets
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 CCSN library (CCS models with receiver_capacitance)
|
||||
############################################################
|
||||
read_liberty ../../test/asap7_ccsn.lib.gz
|
||||
puts "PASS: read ASAP7 CCSN library"
|
||||
|
||||
# Report cells from CCSN library to exercise CCS model paths
|
||||
set ccsn_cells [get_lib_cells */*]
|
||||
puts "PASS: CCSN lib cells total: [llength $ccsn_cells]"
|
||||
|
||||
foreach cell_obj $ccsn_cells {
|
||||
catch {
|
||||
report_lib_cell [get_full_name $cell_obj]
|
||||
}
|
||||
}
|
||||
puts "PASS: reported all CCSN cells"
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 SEQ library (has setup/hold/recovery/removal arcs)
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
puts "PASS: read ASAP7 SEQ RVT FF"
|
||||
|
||||
# Report sequential cells which have diverse timing_type values
|
||||
# DFF cells have setup, hold timing checks
|
||||
set lib_seq [sta::find_liberty asap7sc7p5t_SEQ_RVT_FF_nldm_220123]
|
||||
catch {
|
||||
set seq_cells [$lib_seq find_liberty_cells_matching "DFF*" 0 0]
|
||||
puts "PASS: ASAP7 DFF* cells: [llength $seq_cells]"
|
||||
}
|
||||
|
||||
# Report specific cells to exercise different timing types
|
||||
catch {
|
||||
report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DFFHQNx1_ASAP7_75t_R
|
||||
puts "PASS: ASAP7 DFF cell report"
|
||||
}
|
||||
|
||||
catch {
|
||||
report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DFFHQNx2_ASAP7_75t_R
|
||||
puts "PASS: ASAP7 DFF x2 cell report"
|
||||
}
|
||||
|
||||
# Scan DFF cells (scan_in, scan_enable timing arcs)
|
||||
catch {
|
||||
report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/SDFHQNx1_ASAP7_75t_R
|
||||
puts "PASS: ASAP7 SDFF cell report"
|
||||
}
|
||||
|
||||
catch {
|
||||
report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/SDFHQNx2_ASAP7_75t_R
|
||||
puts "PASS: ASAP7 SDFF x2 cell report"
|
||||
}
|
||||
|
||||
# ICG cells (clock gating - exercises clock gate timing types)
|
||||
catch {
|
||||
report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/ICGx1_ASAP7_75t_R
|
||||
puts "PASS: ASAP7 ICG cell report"
|
||||
}
|
||||
|
||||
catch {
|
||||
report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/ICGx2_ASAP7_75t_R
|
||||
puts "PASS: ASAP7 ICG x2 cell report"
|
||||
}
|
||||
|
||||
# Async set/reset cells (recovery/removal timing types)
|
||||
catch {
|
||||
set async_cells [$lib_seq find_liberty_cells_matching "*ASYNC*" 0 0]
|
||||
puts "PASS: ASAP7 ASYNC cells: [llength $async_cells]"
|
||||
}
|
||||
|
||||
# DFFR cells with reset (recovery/removal)
|
||||
catch {
|
||||
set dffr_cells [$lib_seq find_liberty_cells_matching "DFFR*" 0 0]
|
||||
foreach cell_obj $dffr_cells {
|
||||
report_lib_cell [get_object_name $cell_obj]
|
||||
}
|
||||
puts "PASS: ASAP7 DFFR cells reported"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 SEQ SS corner for different model values
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_SS_nldm_220123.lib
|
||||
puts "PASS: read ASAP7 SEQ SS"
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 SIMPLE library (combinational cells)
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz
|
||||
puts "PASS: read ASAP7 SIMPLE"
|
||||
|
||||
catch {
|
||||
set simple_lib [sta::find_liberty asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120]
|
||||
set simple_cells [$simple_lib find_liberty_cells_matching "*" 0 0]
|
||||
puts "PASS: ASAP7 SIMPLE cells: [llength $simple_cells]"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 AO library (AND-OR complex cells)
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
puts "PASS: read ASAP7 AO"
|
||||
|
||||
catch {
|
||||
set ao_lib [sta::find_liberty asap7sc7p5t_AO_RVT_FF_nldm_211120]
|
||||
set ao_cells [$ao_lib find_liberty_cells_matching "AO*" 0 0]
|
||||
puts "PASS: ASAP7 AO* cells: [llength $ao_cells]"
|
||||
foreach c $ao_cells {
|
||||
catch {report_lib_cell [get_object_name $c]}
|
||||
}
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 OA library (OR-AND complex cells)
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
puts "PASS: read ASAP7 OA"
|
||||
|
||||
catch {
|
||||
set oa_lib [sta::find_liberty asap7sc7p5t_OA_RVT_FF_nldm_211120]
|
||||
set oa_cells [$oa_lib find_liberty_cells_matching "OA*" 0 0]
|
||||
puts "PASS: ASAP7 OA* cells: [llength $oa_cells]"
|
||||
foreach c $oa_cells {
|
||||
catch {report_lib_cell [get_object_name $c]}
|
||||
}
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 INVBUF library
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz
|
||||
puts "PASS: read ASAP7 INVBUF"
|
||||
|
||||
############################################################
|
||||
# Read libraries from different process nodes
|
||||
# Exercises different liberty features/syntax in each library
|
||||
############################################################
|
||||
|
||||
# Read IHP SG13G2 library (has tristate, scan, different timing types)
|
||||
read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
puts "PASS: read IHP sg13g2"
|
||||
|
||||
catch {
|
||||
set ihp_lib [sta::find_liberty sg13g2_stdcell_typ_1p20V_25C]
|
||||
# Report tristate buffer cell (exercises three_state_enable paths)
|
||||
catch {report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_ebufn_2}
|
||||
puts "PASS: IHP tristate buffer report"
|
||||
|
||||
# Report scan flip-flop (exercises scan timing paths)
|
||||
catch {report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_sdfbbp_1}
|
||||
puts "PASS: IHP scan DFF report"
|
||||
|
||||
# Report latch cell
|
||||
catch {report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_dlhq_1}
|
||||
puts "PASS: IHP latch report"
|
||||
|
||||
# MUX cell
|
||||
catch {report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_mux2_1}
|
||||
puts "PASS: IHP mux report"
|
||||
}
|
||||
|
||||
# Read IHP second PVT corner
|
||||
read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p50V_25C.lib
|
||||
puts "PASS: read IHP 1.5V"
|
||||
|
||||
############################################################
|
||||
# Read latch library to exercise latch-specific code
|
||||
############################################################
|
||||
read_liberty ../../test/liberty_latch3.lib
|
||||
puts "PASS: read latch3 library"
|
||||
|
||||
############################################################
|
||||
# Read liberty with backslash-EOL continuation
|
||||
############################################################
|
||||
read_liberty ../../test/liberty_backslash_eol.lib
|
||||
puts "PASS: read backslash_eol library"
|
||||
|
||||
############################################################
|
||||
# Read liberty with float-as-string values
|
||||
############################################################
|
||||
read_liberty ../../test/liberty_float_as_str.lib
|
||||
puts "PASS: read float_as_str library"
|
||||
|
||||
############################################################
|
||||
# Read liberty arcs one2one libraries
|
||||
############################################################
|
||||
read_liberty ../../test/liberty_arcs_one2one_1.lib
|
||||
puts "PASS: read arcs_one2one_1 library"
|
||||
|
||||
read_liberty ../../test/liberty_arcs_one2one_2.lib
|
||||
puts "PASS: read arcs_one2one_2 library"
|
||||
|
||||
############################################################
|
||||
# Read SRAM macro library (exercises macro/memory cells)
|
||||
############################################################
|
||||
read_liberty ../../test/gf180mcu_sram.lib.gz
|
||||
puts "PASS: read gf180mcu SRAM library"
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 SEQ LVT/SLVT (different threshold voltages)
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_LVT_FF_nldm_220123.lib
|
||||
puts "PASS: read ASAP7 SEQ LVT"
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_SLVT_FF_nldm_220123.lib
|
||||
puts "PASS: read ASAP7 SEQ SLVT"
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 INVBUF different Vt flavors
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_LVT_FF_nldm_220122.lib.gz
|
||||
puts "PASS: read ASAP7 INVBUF LVT"
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_SLVT_FF_nldm_220122.lib.gz
|
||||
puts "PASS: read ASAP7 INVBUF SLVT"
|
||||
|
||||
############################################################
|
||||
# Write liberty for ASAP7 SEQ
|
||||
############################################################
|
||||
set outfile [make_result_file liberty_ccsn_ecsm_write.lib]
|
||||
sta::write_liberty asap7sc7p5t_SEQ_RVT_FF_nldm_220123 $outfile
|
||||
puts "PASS: write_liberty ASAP7 SEQ"
|
||||
|
||||
set outfile2 [make_result_file liberty_ccsn_ecsm_write_ihp.lib]
|
||||
sta::write_liberty sg13g2_stdcell_typ_1p20V_25C $outfile2
|
||||
puts "PASS: write_liberty IHP"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
@ -0,0 +1,308 @@
|
|||
PASS: read sky130hd
|
||||
PASS: read Nangate45
|
||||
PASS: read ASAP7 SEQ
|
||||
PASS: read IHP
|
||||
--- Nangate45 cell classification ---
|
||||
BUF_X1 is_buffer = 1
|
||||
BUF_X1 is_inverter = 0
|
||||
BUF_X1 is_leaf = 1
|
||||
INV_X1 is_buffer = 0
|
||||
INV_X1 is_inverter = 1
|
||||
CLKGATETST_X1 is_buffer = 0
|
||||
CLKGATETST_X1 is_inverter = 0
|
||||
DFF_X1 is_buffer = 0
|
||||
DFF_X1 is_inverter = 0
|
||||
DFF_X1 is_leaf = 1
|
||||
SDFF_X1 test_cell = NULL
|
||||
PASS: Nangate45 classification
|
||||
--- port function queries ---
|
||||
INV_X1/ZN func=!A dir=output
|
||||
BUF_X1/Z func=A dir=output
|
||||
NAND2_X1/ZN func=!(A1*A2) dir=output
|
||||
NOR2_X1/ZN func=!(A1+A2) dir=output
|
||||
AND2_X1/ZN func=A1*A2 dir=output
|
||||
OR2_X1/ZN func=A1+A2 dir=output
|
||||
XOR2_X1/Z func=A^B dir=output
|
||||
XNOR2_X1/ZN func=!(A^B) dir=output
|
||||
AOI21_X1/ZN func=!(A+(B1*B2)) dir=output
|
||||
OAI21_X1/ZN func=!(A*(B1+B2)) dir=output
|
||||
MUX2_X1/Z func=(S*B)+(A*!S) dir=output
|
||||
HA_X1/CO func=A*B dir=output
|
||||
HA_X1/S func=A^B dir=output
|
||||
FA_X1/CO func=(A*B)+(CI*(A+B)) dir=output
|
||||
FA_X1/S func=CI^(A^B) dir=output
|
||||
PASS: port function queries
|
||||
--- bus port member iteration ---
|
||||
PASS: bus port member iteration
|
||||
--- port capacitance corner ---
|
||||
PASS: port capacitance corner
|
||||
--- timing arc sets ---
|
||||
INV_X1 arc_sets=1
|
||||
A -> ZN is_check=0
|
||||
rise -> fall
|
||||
fall -> rise
|
||||
BUF_X1 arc_sets=1
|
||||
A -> Z is_check=0
|
||||
rise -> rise
|
||||
fall -> fall
|
||||
DFF_X1 arc_sets=5
|
||||
CK -> D is_check=1
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
CK -> D is_check=1
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
CK -> CK is_check=1
|
||||
rise -> fall
|
||||
fall -> rise
|
||||
CK -> Q is_check=0
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
CK -> QN is_check=0
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
DFFR_X1 arc_sets=16
|
||||
CK -> D is_check=1
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
CK -> D is_check=1
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
CK -> RN is_check=1
|
||||
rise -> rise
|
||||
CK -> RN is_check=1
|
||||
rise -> rise
|
||||
RN -> RN is_check=1
|
||||
fall -> rise
|
||||
CK -> CK is_check=1
|
||||
rise -> fall
|
||||
fall -> rise
|
||||
CK -> Q is_check=0
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
RN -> Q is_check=0
|
||||
fall -> fall
|
||||
RN -> Q is_check=0
|
||||
fall -> fall
|
||||
RN -> Q is_check=0
|
||||
fall -> fall
|
||||
RN -> Q is_check=0
|
||||
fall -> fall
|
||||
CK -> QN is_check=0
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
RN -> QN is_check=0
|
||||
fall -> rise
|
||||
RN -> QN is_check=0
|
||||
fall -> rise
|
||||
RN -> QN is_check=0
|
||||
fall -> rise
|
||||
RN -> QN is_check=0
|
||||
fall -> rise
|
||||
NAND2_X1 arc_sets=2
|
||||
A1 -> ZN is_check=0
|
||||
rise -> fall
|
||||
fall -> rise
|
||||
A2 -> ZN is_check=0
|
||||
rise -> fall
|
||||
fall -> rise
|
||||
AOI21_X1 arc_sets=5
|
||||
A -> ZN is_check=0
|
||||
rise -> fall
|
||||
fall -> rise
|
||||
A -> ZN is_check=0
|
||||
rise -> fall
|
||||
fall -> rise
|
||||
A -> ZN is_check=0
|
||||
rise -> fall
|
||||
fall -> rise
|
||||
B1 -> ZN is_check=0
|
||||
rise -> fall
|
||||
fall -> rise
|
||||
B2 -> ZN is_check=0
|
||||
rise -> fall
|
||||
fall -> rise
|
||||
MUX2_X1 arc_sets=6
|
||||
A -> Z is_check=0
|
||||
rise -> rise
|
||||
fall -> fall
|
||||
A -> Z is_check=0
|
||||
rise -> rise
|
||||
fall -> fall
|
||||
B -> Z is_check=0
|
||||
rise -> rise
|
||||
fall -> fall
|
||||
B -> Z is_check=0
|
||||
rise -> rise
|
||||
fall -> fall
|
||||
S -> Z is_check=0
|
||||
rise -> rise
|
||||
fall -> fall
|
||||
S -> Z is_check=0
|
||||
rise -> fall
|
||||
fall -> rise
|
||||
SDFF_X1 arc_sets=9
|
||||
CK -> D is_check=1
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
CK -> D is_check=1
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
CK -> SE is_check=1
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
CK -> SE is_check=1
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
CK -> SI is_check=1
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
CK -> SI is_check=1
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
CK -> CK is_check=1
|
||||
rise -> fall
|
||||
fall -> rise
|
||||
CK -> Q is_check=0
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
CK -> QN is_check=0
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
CLKGATETST_X1 arc_sets=9
|
||||
CK -> CK is_check=1
|
||||
fall -> rise
|
||||
CK -> E is_check=1
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
CK -> E is_check=1
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
CK -> SE is_check=1
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
CK -> SE is_check=1
|
||||
rise -> rise
|
||||
rise -> fall
|
||||
CK -> GCK is_check=0
|
||||
rise -> rise
|
||||
fall -> fall
|
||||
CK -> GCK is_check=0
|
||||
rise -> rise
|
||||
fall -> fall
|
||||
CK -> GCK is_check=0
|
||||
rise -> rise
|
||||
fall -> fall
|
||||
CK -> GCK is_check=0
|
||||
fall -> fall
|
||||
PASS: timing arc sets
|
||||
--- Sky130 cell queries ---
|
||||
sky130_fd_sc_hd__inv_1 is_buffer=0 is_inverter=1
|
||||
VGND pwr_gnd=1
|
||||
VNB pwr_gnd=1
|
||||
VPB pwr_gnd=1
|
||||
VPWR pwr_gnd=1
|
||||
sky130_fd_sc_hd__inv_2 is_buffer=0 is_inverter=1
|
||||
VGND pwr_gnd=1
|
||||
VNB pwr_gnd=1
|
||||
VPB pwr_gnd=1
|
||||
VPWR pwr_gnd=1
|
||||
sky130_fd_sc_hd__inv_4 is_buffer=0 is_inverter=1
|
||||
VGND pwr_gnd=1
|
||||
VNB pwr_gnd=1
|
||||
VPB pwr_gnd=1
|
||||
VPWR pwr_gnd=1
|
||||
sky130_fd_sc_hd__buf_1 is_buffer=1 is_inverter=0
|
||||
VGND pwr_gnd=1
|
||||
VNB pwr_gnd=1
|
||||
VPB pwr_gnd=1
|
||||
VPWR pwr_gnd=1
|
||||
sky130_fd_sc_hd__buf_2 is_buffer=1 is_inverter=0
|
||||
VGND pwr_gnd=1
|
||||
VNB pwr_gnd=1
|
||||
VPB pwr_gnd=1
|
||||
VPWR pwr_gnd=1
|
||||
sky130_fd_sc_hd__nand2_1 is_buffer=0 is_inverter=0
|
||||
VGND pwr_gnd=1
|
||||
VNB pwr_gnd=1
|
||||
VPB pwr_gnd=1
|
||||
VPWR pwr_gnd=1
|
||||
sky130_fd_sc_hd__nor2_1 is_buffer=0 is_inverter=0
|
||||
VGND pwr_gnd=1
|
||||
VNB pwr_gnd=1
|
||||
VPB pwr_gnd=1
|
||||
VPWR pwr_gnd=1
|
||||
sky130_fd_sc_hd__and2_1 is_buffer=0 is_inverter=0
|
||||
VGND pwr_gnd=1
|
||||
VNB pwr_gnd=1
|
||||
VPB pwr_gnd=1
|
||||
VPWR pwr_gnd=1
|
||||
sky130_fd_sc_hd__or2_1 is_buffer=0 is_inverter=0
|
||||
VGND pwr_gnd=1
|
||||
VNB pwr_gnd=1
|
||||
VPB pwr_gnd=1
|
||||
VPWR pwr_gnd=1
|
||||
sky130_fd_sc_hd__dfxtp_1 is_buffer=0 is_inverter=0
|
||||
VGND pwr_gnd=1
|
||||
VNB pwr_gnd=1
|
||||
VPB pwr_gnd=1
|
||||
VPWR pwr_gnd=1
|
||||
sky130_fd_sc_hd__dfrtp_1 is_buffer=0 is_inverter=0
|
||||
VGND pwr_gnd=1
|
||||
VNB pwr_gnd=1
|
||||
VPB pwr_gnd=1
|
||||
VPWR pwr_gnd=1
|
||||
sky130_fd_sc_hd__mux2_1 is_buffer=0 is_inverter=0
|
||||
VGND pwr_gnd=1
|
||||
VNB pwr_gnd=1
|
||||
VPB pwr_gnd=1
|
||||
VPWR pwr_gnd=1
|
||||
sky130_fd_sc_hd__dlxtp_1 is_buffer=0 is_inverter=0
|
||||
VGND pwr_gnd=1
|
||||
VNB pwr_gnd=1
|
||||
VPB pwr_gnd=1
|
||||
VPWR pwr_gnd=1
|
||||
sky130_fd_sc_hd__ebufn_1 is_buffer=0 is_inverter=0
|
||||
VGND pwr_gnd=1
|
||||
VNB pwr_gnd=1
|
||||
VPB pwr_gnd=1
|
||||
VPWR pwr_gnd=1
|
||||
PASS: Sky130 cell queries
|
||||
--- operating conditions ---
|
||||
Sky130 default OC process=1.0 voltage=1.7999999523162842 temp=25.0
|
||||
PASS: operating conditions
|
||||
--- IHP cell queries ---
|
||||
sg13g2_inv_1 is_buffer=0 is_inverter=1
|
||||
arc_sets=1
|
||||
sg13g2_inv_2 is_buffer=0 is_inverter=1
|
||||
arc_sets=1
|
||||
sg13g2_buf_1 is_buffer=1 is_inverter=0
|
||||
arc_sets=1
|
||||
sg13g2_buf_2 is_buffer=1 is_inverter=0
|
||||
arc_sets=1
|
||||
sg13g2_nand2_1 is_buffer=0 is_inverter=0
|
||||
arc_sets=2
|
||||
sg13g2_nor2_1 is_buffer=0 is_inverter=0
|
||||
arc_sets=2
|
||||
sg13g2_and2_1 is_buffer=0 is_inverter=0
|
||||
arc_sets=2
|
||||
sg13g2_dfrbp_1 is_buffer=0 is_inverter=0
|
||||
arc_sets=10
|
||||
sg13g2_dfrbp_2 is_buffer=0 is_inverter=0
|
||||
arc_sets=10
|
||||
sg13g2_ebufn_2 is_buffer=0 is_inverter=0
|
||||
arc_sets=3
|
||||
PASS: IHP cell queries
|
||||
--- ensure voltage waveforms ---
|
||||
PASS: INV_X1 ensure_voltage_waveforms
|
||||
PASS: DFF_X1 ensure_voltage_waveforms
|
||||
PASS: ensure voltage waveforms
|
||||
--- liberty cell matching ---
|
||||
INV_* matches = 6
|
||||
DFF* matches = 8
|
||||
* matches = 134
|
||||
regex INV_X matches = 6
|
||||
INV_X1 port * matches = 4
|
||||
INV_X1 port A matches = 1
|
||||
PASS: liberty cell matching
|
||||
ALL PASSED
|
||||
|
|
@ -0,0 +1,301 @@
|
|||
# Test cell classification (isBuffer, isInverter, isClockGate, etc.),
|
||||
# pg_pin iteration, bus port member iteration, internal power queries,
|
||||
# and port function queries across multiple PDKs.
|
||||
# Targets:
|
||||
# Liberty.cc: LibertyCell isBuffer, isInverter, isClockGate,
|
||||
# isClockGateLatchPosedge, isClockGateLatchNegedge, isMacro, isPad,
|
||||
# isMemory, hasInternalPower, internalPowers, addInternalPower,
|
||||
# leakagePower, leakagePowers, cellPortBitCount, busPorts,
|
||||
# isDisabledConstraint, pgPins, testCell, setDontUse, dontUse,
|
||||
# LibertyPort isBus, isBusBit, isBundle, hasMembers, bundlePort,
|
||||
# LibertyPortMemberIterator, findLibertyMember,
|
||||
# LibertyLibrary findOperatingConditions, defaultOperatingConditions,
|
||||
# supplyExists, findWireload, findWireloadSelection
|
||||
# FuncExpr.cc: to_string, portTimingSense
|
||||
# InternalPower.cc: InternalPower accessors
|
||||
# LeakagePower.cc: LeakagePower accessors
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
############################################################
|
||||
# Read libraries with pg_pin info (Sky130 has pg_pin groups)
|
||||
############################################################
|
||||
read_liberty ../../test/sky130hd/sky130hd_tt.lib
|
||||
puts "PASS: read sky130hd"
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
puts "PASS: read Nangate45"
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
puts "PASS: read ASAP7 SEQ"
|
||||
|
||||
read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
puts "PASS: read IHP"
|
||||
|
||||
############################################################
|
||||
# Cell classification queries on Nangate45
|
||||
############################################################
|
||||
puts "--- Nangate45 cell classification ---"
|
||||
|
||||
# Buffers
|
||||
set buf_x1 [get_lib_cell NangateOpenCellLibrary/BUF_X1]
|
||||
puts "BUF_X1 is_buffer = [$buf_x1 is_buffer]"
|
||||
puts "BUF_X1 is_inverter = [$buf_x1 is_inverter]"
|
||||
puts "BUF_X1 is_leaf = [$buf_x1 is_leaf]"
|
||||
|
||||
# Inverters
|
||||
set inv_x1 [get_lib_cell NangateOpenCellLibrary/INV_X1]
|
||||
puts "INV_X1 is_buffer = [$inv_x1 is_buffer]"
|
||||
puts "INV_X1 is_inverter = [$inv_x1 is_inverter]"
|
||||
|
||||
# Clock gate cells
|
||||
catch {
|
||||
set clkgate [get_lib_cell NangateOpenCellLibrary/CLKGATETST_X1]
|
||||
puts "CLKGATETST_X1 is_buffer = [$clkgate is_buffer]"
|
||||
puts "CLKGATETST_X1 is_inverter = [$clkgate is_inverter]"
|
||||
}
|
||||
|
||||
# DFF
|
||||
set dff [get_lib_cell NangateOpenCellLibrary/DFF_X1]
|
||||
puts "DFF_X1 is_buffer = [$dff is_buffer]"
|
||||
puts "DFF_X1 is_inverter = [$dff is_inverter]"
|
||||
puts "DFF_X1 is_leaf = [$dff is_leaf]"
|
||||
|
||||
# Test cell for scan DFF
|
||||
catch {
|
||||
set sdff [get_lib_cell NangateOpenCellLibrary/SDFF_X1]
|
||||
set tc [$sdff test_cell]
|
||||
puts "SDFF_X1 test_cell = $tc"
|
||||
}
|
||||
|
||||
puts "PASS: Nangate45 classification"
|
||||
|
||||
############################################################
|
||||
# Port function queries (exercises FuncExpr::to_string)
|
||||
############################################################
|
||||
puts "--- port function queries ---"
|
||||
foreach {lib_name cell_name} {
|
||||
NangateOpenCellLibrary INV_X1
|
||||
NangateOpenCellLibrary BUF_X1
|
||||
NangateOpenCellLibrary NAND2_X1
|
||||
NangateOpenCellLibrary NOR2_X1
|
||||
NangateOpenCellLibrary AND2_X1
|
||||
NangateOpenCellLibrary OR2_X1
|
||||
NangateOpenCellLibrary XOR2_X1
|
||||
NangateOpenCellLibrary XNOR2_X1
|
||||
NangateOpenCellLibrary AOI21_X1
|
||||
NangateOpenCellLibrary OAI21_X1
|
||||
NangateOpenCellLibrary MUX2_X1
|
||||
NangateOpenCellLibrary HA_X1
|
||||
NangateOpenCellLibrary FA_X1
|
||||
} {
|
||||
set cell [get_lib_cell $lib_name/$cell_name]
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set func [$port function]
|
||||
set tri [$port tristate_enable]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
set pwr [$port is_pwr_gnd]
|
||||
if {$func != ""} {
|
||||
puts " $cell_name/[$port bus_name] func=$func dir=$dir"
|
||||
}
|
||||
if {$tri != ""} {
|
||||
puts " $cell_name/[$port bus_name] tristate=$tri"
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
}
|
||||
puts "PASS: port function queries"
|
||||
|
||||
############################################################
|
||||
# Bus port and member iteration
|
||||
############################################################
|
||||
puts "--- bus port member iteration ---"
|
||||
|
||||
# ASAP7 SEQ has bus ports in some cells
|
||||
set asap7_libs [get_libs asap7sc7p5t_SEQ_RVT_FF_nldm_220123]
|
||||
set asap7_seq_lib [lindex $asap7_libs 0]
|
||||
set asap7_cells [get_lib_cells asap7sc7p5t_SEQ_RVT_FF_nldm_220123/*]
|
||||
foreach cell_obj $asap7_cells {
|
||||
set cname [$cell_obj name]
|
||||
set port_iter [$cell_obj liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
if {[$port is_bus]} {
|
||||
puts "$cname/[$port bus_name] is_bus=1 has_members=[$port has_members]"
|
||||
set mem_iter [$port member_iterator]
|
||||
while {[$mem_iter has_next]} {
|
||||
set member [$mem_iter next]
|
||||
puts " member: [$member bus_name] is_bus_bit=[$member is_bus_bit]"
|
||||
}
|
||||
$mem_iter finish
|
||||
}
|
||||
if {[$port is_bundle]} {
|
||||
puts "$cname/[$port bus_name] is_bundle=1"
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
}
|
||||
puts "PASS: bus port member iteration"
|
||||
|
||||
############################################################
|
||||
# Port capacitance with corner/min_max
|
||||
############################################################
|
||||
puts "--- port capacitance corner ---"
|
||||
foreach cell_name {INV_X1 INV_X4 INV_X16 BUF_X1 BUF_X8 NAND2_X1 DFF_X1} {
|
||||
set cell [get_lib_cell NangateOpenCellLibrary/$cell_name]
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
if {$dir == "input"} {
|
||||
catch {
|
||||
set cap [$port capacitance [sta::cmd_corner] [sta::find_min_max "max"]]
|
||||
puts "$cell_name/[$port bus_name] cap(max)=$cap"
|
||||
}
|
||||
catch {
|
||||
set cap [$port capacitance [sta::cmd_corner] [sta::find_min_max "min"]]
|
||||
puts "$cell_name/[$port bus_name] cap(min)=$cap"
|
||||
}
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
}
|
||||
puts "PASS: port capacitance corner"
|
||||
|
||||
############################################################
|
||||
# Timing arc set queries
|
||||
############################################################
|
||||
puts "--- timing arc sets ---"
|
||||
foreach cell_name {INV_X1 BUF_X1 DFF_X1 DFFR_X1 NAND2_X1 AOI21_X1 MUX2_X1 SDFF_X1 CLKGATETST_X1} {
|
||||
set cell [get_lib_cell NangateOpenCellLibrary/$cell_name]
|
||||
set arc_sets [$cell timing_arc_sets]
|
||||
puts "$cell_name arc_sets=[llength $arc_sets]"
|
||||
foreach arc_set $arc_sets {
|
||||
set from_port [$arc_set from]
|
||||
set to_port [$arc_set to]
|
||||
set role [$arc_set role]
|
||||
set is_check [sta::timing_role_is_check $role]
|
||||
set from_name [$from_port bus_name]
|
||||
set to_name [$to_port bus_name]
|
||||
puts " $from_name -> $to_name is_check=$is_check"
|
||||
# Query timing arcs within the set
|
||||
set arcs [$arc_set timing_arcs]
|
||||
foreach arc $arcs {
|
||||
set from_edge [$arc from_edge_name]
|
||||
set to_edge [$arc to_edge_name]
|
||||
puts " $from_edge -> $to_edge"
|
||||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: timing arc sets"
|
||||
|
||||
############################################################
|
||||
# Sky130 cell queries (has pg_pin groups, different features)
|
||||
############################################################
|
||||
puts "--- Sky130 cell queries ---"
|
||||
foreach cell_name {
|
||||
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_4
|
||||
sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_2
|
||||
sky130_fd_sc_hd__nand2_1 sky130_fd_sc_hd__nor2_1
|
||||
sky130_fd_sc_hd__and2_1 sky130_fd_sc_hd__or2_1
|
||||
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfrtp_1
|
||||
sky130_fd_sc_hd__mux2_1
|
||||
sky130_fd_sc_hd__dlxtp_1
|
||||
sky130_fd_sc_hd__ebufn_1
|
||||
} {
|
||||
catch {
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
|
||||
puts "$cell_name is_buffer=[$cell is_buffer] is_inverter=[$cell is_inverter]"
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set func [$port function]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
set pwr [$port is_pwr_gnd]
|
||||
if {$pwr} {
|
||||
puts " [$port bus_name] pwr_gnd=1"
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
}
|
||||
}
|
||||
puts "PASS: Sky130 cell queries"
|
||||
|
||||
############################################################
|
||||
# Operating conditions (exercises find_operating_conditions)
|
||||
############################################################
|
||||
puts "--- operating conditions ---"
|
||||
set sky_lib [lindex [get_libs sky130_fd_sc_hd__tt_025C_1v80] 0]
|
||||
set default_oc [$sky_lib default_operating_conditions]
|
||||
if {$default_oc != "NULL"} {
|
||||
puts "Sky130 default OC process=[$default_oc process] voltage=[$default_oc voltage] temp=[$default_oc temperature]"
|
||||
}
|
||||
puts "PASS: operating conditions"
|
||||
|
||||
############################################################
|
||||
# IHP cell queries (different vendor, might have different features)
|
||||
############################################################
|
||||
puts "--- IHP cell queries ---"
|
||||
foreach cell_name {
|
||||
sg13g2_inv_1 sg13g2_inv_2
|
||||
sg13g2_buf_1 sg13g2_buf_2
|
||||
sg13g2_nand2_1 sg13g2_nor2_1
|
||||
sg13g2_and2_1
|
||||
sg13g2_dfrbp_1 sg13g2_dfrbp_2
|
||||
sg13g2_ebufn_2
|
||||
} {
|
||||
catch {
|
||||
set cell [get_lib_cell sg13g2_stdcell_typ_1p20V_25C/$cell_name]
|
||||
puts "$cell_name is_buffer=[$cell is_buffer] is_inverter=[$cell is_inverter]"
|
||||
set arc_sets [$cell timing_arc_sets]
|
||||
puts " arc_sets=[llength $arc_sets]"
|
||||
}
|
||||
}
|
||||
puts "PASS: IHP cell queries"
|
||||
|
||||
############################################################
|
||||
# Ensure voltage waveforms (exercises ensureVoltageWaveforms)
|
||||
############################################################
|
||||
puts "--- ensure voltage waveforms ---"
|
||||
catch {
|
||||
set inv [get_lib_cell NangateOpenCellLibrary/INV_X1]
|
||||
$inv ensure_voltage_waveforms
|
||||
puts "PASS: INV_X1 ensure_voltage_waveforms"
|
||||
}
|
||||
|
||||
catch {
|
||||
set dff [get_lib_cell NangateOpenCellLibrary/DFF_X1]
|
||||
$dff ensure_voltage_waveforms
|
||||
puts "PASS: DFF_X1 ensure_voltage_waveforms"
|
||||
}
|
||||
puts "PASS: ensure voltage waveforms"
|
||||
|
||||
############################################################
|
||||
# Liberty cell matching with regex patterns
|
||||
############################################################
|
||||
puts "--- liberty cell matching ---"
|
||||
set ng_lib [lindex [get_libs NangateOpenCellLibrary] 0]
|
||||
set inv_matches [$ng_lib find_liberty_cells_matching "INV_*" 0 0]
|
||||
puts "INV_* matches = [llength $inv_matches]"
|
||||
|
||||
set dff_matches [$ng_lib find_liberty_cells_matching "DFF*" 0 0]
|
||||
puts "DFF* matches = [llength $dff_matches]"
|
||||
|
||||
set all_matches [$ng_lib find_liberty_cells_matching "*" 0 0]
|
||||
puts "* matches = [llength $all_matches]"
|
||||
|
||||
# Regex matching
|
||||
set regex_matches [$ng_lib find_liberty_cells_matching {^INV_X[0-9]+$} 1 0]
|
||||
puts "regex INV_X matches = [llength $regex_matches]"
|
||||
|
||||
# Port matching on a cell
|
||||
set inv [get_lib_cell NangateOpenCellLibrary/INV_X1]
|
||||
set port_matches [$inv find_liberty_ports_matching "*" 0 0]
|
||||
puts "INV_X1 port * matches = [llength $port_matches]"
|
||||
|
||||
set port_matches [$inv find_liberty_ports_matching "A" 0 0]
|
||||
puts "INV_X1 port A matches = [llength $port_matches]"
|
||||
puts "PASS: liberty cell matching"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
@ -0,0 +1,320 @@
|
|||
PASS: read Nangate45
|
||||
PASS: read ASAP7 SEQ
|
||||
PASS: read IHP
|
||||
PASS: INV_X1/A capacitance = 1.700230
|
||||
PASS: INV_X1/ZN capacitance = 0.000000
|
||||
PASS: DFF_X1/CK capacitance = 0.949653
|
||||
PASS: DFF_X1/D capacitance = 1.140290
|
||||
INV_X1/A cap = 1.700230
|
||||
INV_X2/A cap = 3.250891
|
||||
INV_X4/A cap = 6.258425
|
||||
INV_X8/A cap = 11.810652
|
||||
INV_X16/A cap = 25.228138
|
||||
INV_X32/A cap = 49.191467
|
||||
PASS: INV capacitance sweep
|
||||
BUF_X1/A cap = 0.974659
|
||||
BUF_X2/A cap = 1.779209
|
||||
BUF_X4/A cap = 3.401892
|
||||
BUF_X8/A cap = 6.585178
|
||||
BUF_X16/A cap = 12.410827
|
||||
BUF_X32/A cap = 26.703922
|
||||
PASS: BUF capacitance sweep
|
||||
INV_X1 area = 0.532000
|
||||
INV_X2 area = 0.798000
|
||||
INV_X4 area = 1.330000
|
||||
INV_X8 area = 2.394000
|
||||
INV_X16 area = 4.522000
|
||||
INV_X32 area = 8.778000
|
||||
BUF_X1 area = 0.798000
|
||||
BUF_X2 area = 1.064000
|
||||
BUF_X4 area = 1.862000
|
||||
BUF_X8 area = 3.458000
|
||||
BUF_X16 area = 6.650000
|
||||
BUF_X32 area = 13.034000
|
||||
DFF_X1 area = 4.522000
|
||||
DFF_X2 area = 5.054000
|
||||
DFFR_X1 area = 5.320000
|
||||
DFFS_X1 area = 5.320000
|
||||
DFFRS_X1 area = 6.384000
|
||||
NAND2_X1 area = 0.798000
|
||||
NAND2_X2 area = 1.330000
|
||||
NAND2_X4 area = 2.394000
|
||||
NOR2_X1 area = 0.798000
|
||||
NOR2_X2 area = 1.330000
|
||||
NOR2_X4 area = 2.394000
|
||||
AOI21_X1 area = 1.064000
|
||||
OAI21_X1 area = 1.064000
|
||||
MUX2_X1 area = 1.862000
|
||||
FA_X1 area = 4.256000
|
||||
HA_X1 area = 2.660000
|
||||
TINV_X1 area = 1.064000
|
||||
CLKGATETST_X1 area = 3.990000
|
||||
PASS: cell area queries
|
||||
INV_X1 dont_use = 0
|
||||
BUF_X1 dont_use = 0
|
||||
DFF_X1 dont_use = 0
|
||||
ANTENNA_X1 dont_use = 1
|
||||
FILLCELL_X1 dont_use = 1
|
||||
PASS: dont_use queries
|
||||
PASS: leakage power queries
|
||||
Warning: liberty_cell_deep.tcl line 1, set_input_delay relative to a clock defined on the same port/pin not allowed.
|
||||
PASS: design with constraints
|
||||
No paths found.
|
||||
PASS: max path report
|
||||
No paths found.
|
||||
PASS: min path report
|
||||
No paths found.
|
||||
PASS: in2->out2 path
|
||||
No paths found.
|
||||
PASS: rise_from path
|
||||
No paths found.
|
||||
PASS: fall_from path
|
||||
No paths found.
|
||||
PASS: rise_to path
|
||||
No paths found.
|
||||
PASS: fall_to path
|
||||
Group Slack
|
||||
--------------------------------------------
|
||||
clk1 2.05
|
||||
clk2 0.08
|
||||
clk1 6.92
|
||||
clk2 9.88
|
||||
|
||||
PASS: report_check_types max/min delay
|
||||
max slew
|
||||
|
||||
Pin Limit Slew Slack
|
||||
------------------------------------------------------------
|
||||
inv1/ZN 0.20 0.02 0.18 (MET)
|
||||
|
||||
max capacitance
|
||||
|
||||
Pin Limit Cap Slack
|
||||
------------------------------------------------------------
|
||||
nor1/ZN 26.70 1.14 25.56 (MET)
|
||||
|
||||
PASS: report_check_types max_slew/cap/fanout
|
||||
Group Slack
|
||||
--------------------------------------------
|
||||
No paths found.
|
||||
|
||||
PASS: report_check_types recovery/removal
|
||||
Required Actual
|
||||
Pin Width Width Slack
|
||||
------------------------------------------------------------
|
||||
reg1/CK (high) 0.05 5.00 4.95 (MET)
|
||||
|
||||
PASS: report_check_types min_pulse_width/min_period
|
||||
Group Slack
|
||||
--------------------------------------------
|
||||
No paths found.
|
||||
|
||||
PASS: report_check_types clock_gating
|
||||
PASS: report_check_types max_skew
|
||||
Group Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
----------------------------------------------------------------
|
||||
Sequential 1.76e-06 6.90e-09 2.36e-07 2.01e-06 85.9%
|
||||
Combinational 1.33e-07 7.11e-08 1.25e-07 3.29e-07 14.1%
|
||||
Clock 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
----------------------------------------------------------------
|
||||
Total 1.90e-06 7.80e-08 3.61e-07 2.33e-06 100.0%
|
||||
81.2% 3.3% 15.5%
|
||||
PASS: report_power
|
||||
Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
--------------------------------------------
|
||||
5.87e-07 6.90e-09 7.86e-08 6.73e-07 reg1
|
||||
5.89e-07 0.00e+00 7.84e-08 6.67e-07 reg2
|
||||
5.87e-07 0.00e+00 7.86e-08 6.65e-07 reg3
|
||||
2.56e-08 2.00e-08 2.51e-08 7.07e-08 and1
|
||||
2.70e-08 2.01e-08 2.27e-08 6.98e-08 or1
|
||||
3.04e-08 1.13e-08 2.14e-08 6.31e-08 buf1
|
||||
2.33e-08 5.90e-09 1.44e-08 4.35e-08 inv1
|
||||
1.46e-08 6.90e-09 1.97e-08 4.11e-08 nor1
|
||||
1.24e-08 6.90e-09 2.18e-08 4.11e-08 nand1
|
||||
PASS: report_power instances
|
||||
PASS: read Sky130
|
||||
Cell sky130_fd_sc_hd__ebufn_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
VGND ground
|
||||
VNB unknown
|
||||
VPB unknown
|
||||
VPWR power
|
||||
A input 1.73-1.88
|
||||
TE_B input 2.93-3.34
|
||||
Z tristate enable=!TE_B function=A 2.26
|
||||
Cell sky130_fd_sc_hd__ebufn_2
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
VGND ground
|
||||
VNB unknown
|
||||
VPB unknown
|
||||
VPWR power
|
||||
A input 1.74-1.89
|
||||
TE_B input 3.75-4.41
|
||||
Z tristate enable=!TE_B function=A 2.75
|
||||
Cell sky130_fd_sc_hd__ebufn_4
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
VGND ground
|
||||
VNB unknown
|
||||
VPB unknown
|
||||
VPWR power
|
||||
A input 2.37-2.60
|
||||
TE_B input 6.26-7.48
|
||||
Z tristate enable=!TE_B function=A 5.20
|
||||
PASS: Sky130 tristate cells
|
||||
Cell sky130_fd_sc_hd__dlxtp_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
IQ internal
|
||||
IQ_N internal
|
||||
VGND ground
|
||||
VNB unknown
|
||||
VPB unknown
|
||||
VPWR power
|
||||
D input 1.70-1.85
|
||||
GATE input 1.68-1.82
|
||||
Q output function=IQ
|
||||
Cell sky130_fd_sc_hd__dlxtn_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
IQ internal
|
||||
IQ_N internal
|
||||
VGND ground
|
||||
VNB unknown
|
||||
VPB unknown
|
||||
VPWR power
|
||||
D input 1.70-1.89
|
||||
GATE_N input 1.66-1.82
|
||||
Q output function=IQ
|
||||
PASS: Sky130 latch cells
|
||||
Cell sky130_fd_sc_hd__sdfxtp_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
IQ internal
|
||||
IQ_N internal
|
||||
VGND ground
|
||||
VNB unknown
|
||||
VPB unknown
|
||||
VPWR power
|
||||
CLK input 1.69-1.86
|
||||
D input 1.62-1.78
|
||||
Q output function=IQ
|
||||
SCD input 1.72-1.90
|
||||
SCE input 3.19-3.58
|
||||
Cell sky130_fd_sc_hd__sdfxbp_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
IQ internal
|
||||
IQ_N internal
|
||||
VGND ground
|
||||
VNB unknown
|
||||
VPB unknown
|
||||
VPWR power
|
||||
CLK input 1.70-1.87
|
||||
D input 1.61-1.78
|
||||
Q output function=IQ
|
||||
Q_N output function=IQ_N
|
||||
SCD input 1.72-1.90
|
||||
SCE input 3.17-3.56
|
||||
PASS: Sky130 scan DFF cells
|
||||
Cell sky130_fd_sc_hd__dfxtp_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
IQ internal
|
||||
IQ_N internal
|
||||
VGND ground
|
||||
VNB unknown
|
||||
VPB unknown
|
||||
VPWR power
|
||||
CLK input 1.71-1.88
|
||||
D input 1.67-1.68
|
||||
Q output function=IQ
|
||||
Cell sky130_fd_sc_hd__dfrtp_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
IQ internal
|
||||
IQ_N internal
|
||||
VGND ground
|
||||
VNB unknown
|
||||
VPB unknown
|
||||
VPWR power
|
||||
CLK input 1.71-1.87
|
||||
D input 1.95-2.01
|
||||
Q output function=IQ
|
||||
RESET_B input 3.56-3.63
|
||||
Cell sky130_fd_sc_hd__dfstp_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
IQ internal
|
||||
IQ_N internal
|
||||
VGND ground
|
||||
VNB unknown
|
||||
VPB unknown
|
||||
VPWR power
|
||||
CLK input 1.69-1.86
|
||||
D input 2.23-2.49
|
||||
Q output function=IQ
|
||||
SET_B input 3.36-3.44
|
||||
Cell sky130_fd_sc_hd__dfbbp_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
IQ internal
|
||||
IQ_N internal
|
||||
VGND ground
|
||||
VNB unknown
|
||||
VPB unknown
|
||||
VPWR power
|
||||
CLK input 1.69-1.89
|
||||
D input 1.49-1.70
|
||||
Q output function=IQ
|
||||
Q_N output function=IQ_N
|
||||
RESET_B input 1.53-1.67
|
||||
SET_B input 3.35-3.53
|
||||
PASS: Sky130 async set/reset DFF cells
|
||||
Cell sky130_fd_sc_hd__mux2_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
VGND ground
|
||||
VNB unknown
|
||||
VPB unknown
|
||||
VPWR power
|
||||
A0 input 1.51-1.61
|
||||
A1 input 1.81-1.96
|
||||
S input 3.29-3.52
|
||||
X output function=(A0*!S)+(A1*S)
|
||||
Cell sky130_fd_sc_hd__mux2i_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
VGND ground
|
||||
VNB unknown
|
||||
VPB unknown
|
||||
VPWR power
|
||||
A0 input 2.10-2.31
|
||||
A1 input 2.15-2.36
|
||||
S input 4.48-4.83
|
||||
Y output function=(!A0*!S)+(!A1*S)
|
||||
Cell sky130_fd_sc_hd__mux4_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
VGND ground
|
||||
VNB unknown
|
||||
VPB unknown
|
||||
VPWR power
|
||||
A0 input 1.48-1.57
|
||||
A1 input 1.40-1.48
|
||||
A2 input 1.42-1.51
|
||||
A3 input 1.44-1.52
|
||||
S0 input 3.70-4.09
|
||||
S1 input 2.61-2.74
|
||||
X output function=((((A0*!S0)*!S1)+((A1*S0)*!S1))+((A2*!S0)*S1))+((A3*S0)*S1)
|
||||
PASS: Sky130 mux cells
|
||||
PASS: write_liberty
|
||||
Warning: /workspace/sta/OpenSTA/liberty/test/results/liberty_cell_deep_write.lib line 1, library NangateOpenCellLibrary already exists.
|
||||
INFO: roundtrip read had issue: Error: /workspace/sta/OpenSTA/liberty/test/results/liberty_cell_deep_write.lib, l
|
||||
ALL PASSED
|
||||
|
|
@ -0,0 +1,235 @@
|
|||
# Deep cell property queries: timing arc traversal, port capacitance,
|
||||
# sequential elements, leakage/internal power, and cell classification.
|
||||
# Targets:
|
||||
# Liberty.cc: hasTimingArcs, timingArcSets (from, to, from+to),
|
||||
# outputPortSequential, hasSequentials, makeTimingArcMap,
|
||||
# findDefaultCondArcs, translatePresetClrCheckRoles,
|
||||
# addInternalPower, internalPowers, addLeakagePower, leakagePower,
|
||||
# LibertyPort capacitance, driveResistance, fanoutLoad,
|
||||
# minPulseWidth, setFunction, tristateEnable,
|
||||
# isClockGate, isClockGateLatchPosedge, isMacro, isMemory, isPad,
|
||||
# LibertyCell area, footprint, setDontUse, dontUse,
|
||||
# LibertyPortMemberIterator, bundlePort, findLibertyMember
|
||||
# TimingArc.cc: TimingArcSet role, sense, cond, timingType,
|
||||
# fromEdge, toEdge, arcCount, TimingArc equiv, isRisingFallingEdge
|
||||
# LibertyBuilder.cc: build different cell structures (tri-state, scan)
|
||||
# FuncExpr.cc: portTimingSense, hasPort, equiv, bitSubExpr
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
############################################################
|
||||
# Read libraries
|
||||
############################################################
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
puts "PASS: read Nangate45"
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
puts "PASS: read ASAP7 SEQ"
|
||||
|
||||
read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
puts "PASS: read IHP"
|
||||
|
||||
############################################################
|
||||
# Port capacitance queries
|
||||
# Exercises: LibertyPort capacitance getters/setters
|
||||
############################################################
|
||||
set inv_a [get_lib_pin NangateOpenCellLibrary/INV_X1/A]
|
||||
set inv_zn [get_lib_pin NangateOpenCellLibrary/INV_X1/ZN]
|
||||
|
||||
set cap_a [get_property $inv_a capacitance]
|
||||
puts "PASS: INV_X1/A capacitance = $cap_a"
|
||||
|
||||
set cap_zn [get_property $inv_zn capacitance]
|
||||
puts "PASS: INV_X1/ZN capacitance = $cap_zn"
|
||||
|
||||
# DFF capacitance queries
|
||||
set dff_ck [get_lib_pin NangateOpenCellLibrary/DFF_X1/CK]
|
||||
set cap_ck [get_property $dff_ck capacitance]
|
||||
puts "PASS: DFF_X1/CK capacitance = $cap_ck"
|
||||
|
||||
set dff_d [get_lib_pin NangateOpenCellLibrary/DFF_X1/D]
|
||||
set cap_d [get_property $dff_d capacitance]
|
||||
puts "PASS: DFF_X1/D capacitance = $cap_d"
|
||||
|
||||
# Larger drive strengths have different capacitances
|
||||
foreach size {1 2 4 8 16 32} {
|
||||
catch {
|
||||
set pin [get_lib_pin NangateOpenCellLibrary/INV_X${size}/A]
|
||||
set cap [get_property $pin capacitance]
|
||||
puts "INV_X${size}/A cap = $cap"
|
||||
}
|
||||
}
|
||||
puts "PASS: INV capacitance sweep"
|
||||
|
||||
foreach size {1 2 4 8 16 32} {
|
||||
catch {
|
||||
set pin [get_lib_pin NangateOpenCellLibrary/BUF_X${size}/A]
|
||||
set cap [get_property $pin capacitance]
|
||||
puts "BUF_X${size}/A cap = $cap"
|
||||
}
|
||||
}
|
||||
puts "PASS: BUF capacitance sweep"
|
||||
|
||||
############################################################
|
||||
# Cell area queries
|
||||
############################################################
|
||||
foreach cell_name {INV_X1 INV_X2 INV_X4 INV_X8 INV_X16 INV_X32
|
||||
BUF_X1 BUF_X2 BUF_X4 BUF_X8 BUF_X16 BUF_X32
|
||||
DFF_X1 DFF_X2 DFFR_X1 DFFS_X1 DFFRS_X1
|
||||
NAND2_X1 NAND2_X2 NAND2_X4
|
||||
NOR2_X1 NOR2_X2 NOR2_X4
|
||||
AOI21_X1 OAI21_X1 MUX2_X1 FA_X1 HA_X1
|
||||
TINV_X1 CLKGATETST_X1} {
|
||||
catch {
|
||||
set cell [get_lib_cell NangateOpenCellLibrary/$cell_name]
|
||||
set area [get_property $cell area]
|
||||
puts "$cell_name area = $area"
|
||||
}
|
||||
}
|
||||
puts "PASS: cell area queries"
|
||||
|
||||
############################################################
|
||||
# Cell dont_use, is_macro, is_memory queries
|
||||
############################################################
|
||||
foreach cell_name {INV_X1 BUF_X1 DFF_X1 ANTENNA_X1 FILLCELL_X1} {
|
||||
catch {
|
||||
set cell [get_lib_cell NangateOpenCellLibrary/$cell_name]
|
||||
set du [get_property $cell dont_use]
|
||||
puts "$cell_name dont_use = $du"
|
||||
}
|
||||
}
|
||||
puts "PASS: dont_use queries"
|
||||
|
||||
############################################################
|
||||
# Leakage power queries
|
||||
############################################################
|
||||
foreach cell_name {INV_X1 BUF_X1 DFF_X1 NAND2_X1 NOR2_X1 AOI21_X1} {
|
||||
catch {
|
||||
set cell [get_lib_cell NangateOpenCellLibrary/$cell_name]
|
||||
set lp [get_property $cell cell_leakage_power]
|
||||
puts "$cell_name leakage_power = $lp"
|
||||
}
|
||||
}
|
||||
puts "PASS: leakage power queries"
|
||||
|
||||
############################################################
|
||||
# Timing arc property queries
|
||||
# Exercises: arc direction, sense, timing_type
|
||||
############################################################
|
||||
|
||||
# Setup a design and run timing to exercise arc evaluation
|
||||
read_verilog ../../sdc/test/sdc_test2.v
|
||||
link_design sdc_test2
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
set_input_delay -clock clk1 2.0 [all_inputs]
|
||||
set_output_delay -clock clk1 3.0 [all_outputs]
|
||||
set_input_transition 0.1 [all_inputs]
|
||||
puts "PASS: design with constraints"
|
||||
|
||||
# Detailed timing reports exercise arc evaluation
|
||||
report_checks -from [get_ports in1] -to [get_ports out1] -path_delay max
|
||||
puts "PASS: max path report"
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out1] -path_delay min
|
||||
puts "PASS: min path report"
|
||||
|
||||
report_checks -from [get_ports in2] -to [get_ports out2]
|
||||
puts "PASS: in2->out2 path"
|
||||
|
||||
# Rise/fall reports exercise different arc transitions
|
||||
report_checks -rise_from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: rise_from path"
|
||||
|
||||
report_checks -fall_from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: fall_from path"
|
||||
|
||||
report_checks -from [get_ports in1] -rise_to [get_ports out1]
|
||||
puts "PASS: rise_to path"
|
||||
|
||||
report_checks -from [get_ports in1] -fall_to [get_ports out1]
|
||||
puts "PASS: fall_to path"
|
||||
|
||||
############################################################
|
||||
# Report check types exercises different check arc types
|
||||
############################################################
|
||||
report_check_types -max_delay -min_delay
|
||||
puts "PASS: report_check_types max/min delay"
|
||||
|
||||
report_check_types -max_slew -max_capacitance -max_fanout
|
||||
puts "PASS: report_check_types max_slew/cap/fanout"
|
||||
|
||||
report_check_types -recovery -removal
|
||||
puts "PASS: report_check_types recovery/removal"
|
||||
|
||||
report_check_types -min_pulse_width -min_period
|
||||
puts "PASS: report_check_types min_pulse_width/min_period"
|
||||
|
||||
report_check_types -clock_gating_setup -clock_gating_hold
|
||||
puts "PASS: report_check_types clock_gating"
|
||||
|
||||
report_check_types -max_skew
|
||||
puts "PASS: report_check_types max_skew"
|
||||
|
||||
############################################################
|
||||
# Report power to exercise internal power model paths
|
||||
############################################################
|
||||
report_power
|
||||
puts "PASS: report_power"
|
||||
|
||||
catch {
|
||||
report_power -instances [get_cells *]
|
||||
puts "PASS: report_power instances"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Sky130 cells - different tristate and latch cells
|
||||
############################################################
|
||||
read_liberty ../../test/sky130hd/sky130hd_tt.lib
|
||||
puts "PASS: read Sky130"
|
||||
|
||||
# Tristate buffer
|
||||
catch {report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__ebufn_1}
|
||||
catch {report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__ebufn_2}
|
||||
catch {report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__ebufn_4}
|
||||
puts "PASS: Sky130 tristate cells"
|
||||
|
||||
# Latch cells
|
||||
catch {report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtp_1}
|
||||
catch {report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_1}
|
||||
puts "PASS: Sky130 latch cells"
|
||||
|
||||
# Scan flip-flops
|
||||
catch {report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxtp_1}
|
||||
catch {report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxbp_1}
|
||||
puts "PASS: Sky130 scan DFF cells"
|
||||
|
||||
# DFF with async set/clear (exercises recovery/removal)
|
||||
catch {report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_1}
|
||||
catch {report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtp_1}
|
||||
catch {report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfstp_1}
|
||||
catch {report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfbbp_1}
|
||||
puts "PASS: Sky130 async set/reset DFF cells"
|
||||
|
||||
# Mux cells
|
||||
catch {report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__mux2_1}
|
||||
catch {report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__mux2i_1}
|
||||
catch {report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__mux4_1}
|
||||
puts "PASS: Sky130 mux cells"
|
||||
|
||||
############################################################
|
||||
# Write roundtrip to exercise all writer cell/arc/model paths
|
||||
############################################################
|
||||
set outfile [make_result_file liberty_cell_deep_write.lib]
|
||||
sta::write_liberty NangateOpenCellLibrary $outfile
|
||||
puts "PASS: write_liberty"
|
||||
|
||||
# Read back and verify roundtrip (may have minor syntax issues)
|
||||
catch {
|
||||
read_liberty $outfile
|
||||
puts "PASS: read roundtrip library"
|
||||
} msg
|
||||
if {[string match "Error*" $msg]} {
|
||||
puts "INFO: roundtrip read had issue: [string range $msg 0 80]"
|
||||
}
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
@ -0,0 +1,85 @@
|
|||
PASS: read Sky130 library
|
||||
PASS: found liberty library
|
||||
--- voltage_map / supply queries ---
|
||||
VPWR exists: 1
|
||||
VGND exists: 1
|
||||
VPB exists: 1
|
||||
VNB exists: 1
|
||||
KAPWR exists: 1
|
||||
LOWLVPWR exists: 1
|
||||
VPWRIN exists: 1
|
||||
VSS exists: 1
|
||||
FAKE_SUPPLY exists: 0
|
||||
PASS: supply voltage queries
|
||||
--- clock gate cell queries ---
|
||||
PASS: dlclkp clock gate cells
|
||||
sky130_fd_sc_hd__sdlclkp_1 area=18.768000
|
||||
VGND dir=ground func=
|
||||
VNB dir=unknown func=
|
||||
VPB dir=unknown func=
|
||||
VPWR dir=power func=
|
||||
CLK dir=input func=
|
||||
GATE dir=input func=
|
||||
GCLK dir=output func=
|
||||
M0 dir=internal func=
|
||||
SCE dir=input func=
|
||||
sky130_fd_sc_hd__sdlclkp_2 area=20.019199
|
||||
VGND dir=ground func=
|
||||
VNB dir=unknown func=
|
||||
VPB dir=unknown func=
|
||||
VPWR dir=power func=
|
||||
CLK dir=input func=
|
||||
GATE dir=input func=
|
||||
GCLK dir=output func=
|
||||
M0 dir=internal func=
|
||||
SCE dir=input func=
|
||||
sky130_fd_sc_hd__sdlclkp_4 area=22.521601
|
||||
VGND dir=ground func=
|
||||
VNB dir=unknown func=
|
||||
VPB dir=unknown func=
|
||||
VPWR dir=power func=
|
||||
CLK dir=input func=
|
||||
GATE dir=input func=
|
||||
GCLK dir=output func=
|
||||
M0 dir=internal func=
|
||||
SCE dir=input func=
|
||||
PASS: sdlclkp clock gate cells with precontrol
|
||||
--- level shifter cell queries ---
|
||||
PASS: level shifter cell queries
|
||||
--- pg_pin queries ---
|
||||
sky130_fd_sc_hd__inv_1: pwr_pins=4 signal_pins=2
|
||||
sky130_fd_sc_hd__buf_1: pwr_pins=4 signal_pins=2
|
||||
sky130_fd_sc_hd__nand2_1: pwr_pins=4 signal_pins=3
|
||||
sky130_fd_sc_hd__dfxtp_1: pwr_pins=4 signal_pins=5
|
||||
sky130_fd_sc_hd__dlclkp_1: pwr_pins=4 signal_pins=4
|
||||
sky130_fd_sc_hd__sdfxtp_1: pwr_pins=4 signal_pins=7
|
||||
PASS: pg_pin queries
|
||||
--- clock gate timing arcs ---
|
||||
dlclkp_1 arc_sets = 4
|
||||
PASS: clock gate timing arcs
|
||||
sdlclkp_1 arc_sets = 6
|
||||
PASS: sdlclkp timing arcs
|
||||
--- level shifter timing arcs ---
|
||||
lsbuf_lh_hl_isowell_tap_1 arcs = 1
|
||||
PASS: level shifter timing arcs
|
||||
--- cell classification ---
|
||||
sky130_fd_sc_hd__inv_1: is_buffer=0 is_inverter=1 is_leaf=1
|
||||
sky130_fd_sc_hd__inv_2: is_buffer=0 is_inverter=1 is_leaf=1
|
||||
sky130_fd_sc_hd__buf_1: is_buffer=1 is_inverter=0 is_leaf=1
|
||||
sky130_fd_sc_hd__buf_2: is_buffer=1 is_inverter=0 is_leaf=1
|
||||
sky130_fd_sc_hd__clkinv_1: is_buffer=0 is_inverter=1 is_leaf=1
|
||||
sky130_fd_sc_hd__clkbuf_1: is_buffer=1 is_inverter=0 is_leaf=1
|
||||
sky130_fd_sc_hd__nand2_1: is_buffer=0 is_inverter=0 is_leaf=1
|
||||
sky130_fd_sc_hd__nor2_1: is_buffer=0 is_inverter=0 is_leaf=1
|
||||
sky130_fd_sc_hd__dfxtp_1: is_buffer=0 is_inverter=0 is_leaf=1
|
||||
sky130_fd_sc_hd__dlclkp_1: is_buffer=0 is_inverter=0 is_leaf=1
|
||||
PASS: cell classification
|
||||
PASS: write_liberty sky130
|
||||
PASS: read IHP library
|
||||
IHP VDD exists: 0
|
||||
IHP sg13g2_inv_1: area=5.443200 buf=0 inv=1
|
||||
IHP sg13g2_buf_1: area=7.257600 buf=1 inv=0
|
||||
IHP sg13g2_nand2_1: area=7.257600 buf=0 inv=0
|
||||
IHP sg13g2_nor2_1: area=7.257600 buf=0 inv=0
|
||||
PASS: IHP cell queries
|
||||
ALL PASSED
|
||||
|
|
@ -0,0 +1,280 @@
|
|||
# Test clock gating cells, level shifter cells, pg_pin attributes,
|
||||
# voltage_map/supply_voltage queries, and related cell classification.
|
||||
# Targets:
|
||||
# LibertyReader.cc: visitClockGatingIntegratedCell (latch_posedge,
|
||||
# latch_posedge_precontrol), visitIsLevelShifter, visitLevelShifterType,
|
||||
# visitLevelShifterDataPin, beginPgPin, endPgPin, visitPgType,
|
||||
# visitVoltageName, visitVoltageMap, visitRelatedBiasPin,
|
||||
# visitClockGateClockPin, visitClockGateEnablePin, visitClockGateOutPin,
|
||||
# visitInputVoltageRange, visitOutputVoltageRange
|
||||
# Liberty.cc: isClockGate, isClockGateLatchPosedge, isClockGateLatchNegedge,
|
||||
# isClockGateOther, isLevelShifter, addSupplyVoltage, supplyVoltage,
|
||||
# supplyExists, LibertyPort::isPwrGnd
|
||||
# LibertyBuilder.cc: clock gate cell construction
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
############################################################
|
||||
# Read Sky130 library (has clock gate cells, level shifters, pg_pins)
|
||||
############################################################
|
||||
read_liberty ../../test/sky130hd/sky130hd_tt.lib
|
||||
puts "PASS: read Sky130 library"
|
||||
|
||||
set lib [sta::find_liberty sky130_fd_sc_hd__tt_025C_1v80]
|
||||
puts "PASS: found liberty library"
|
||||
|
||||
############################################################
|
||||
# Voltage map / supply voltage queries
|
||||
# Exercises: addSupplyVoltage, supplyVoltage, supplyExists
|
||||
############################################################
|
||||
puts "--- voltage_map / supply queries ---"
|
||||
|
||||
set vpwr_exists [sta::liberty_supply_exists VPWR]
|
||||
puts "VPWR exists: $vpwr_exists"
|
||||
|
||||
set vgnd_exists [sta::liberty_supply_exists VGND]
|
||||
puts "VGND exists: $vgnd_exists"
|
||||
|
||||
set vpb_exists [sta::liberty_supply_exists VPB]
|
||||
puts "VPB exists: $vpb_exists"
|
||||
|
||||
set vnb_exists [sta::liberty_supply_exists VNB]
|
||||
puts "VNB exists: $vnb_exists"
|
||||
|
||||
set kapwr_exists [sta::liberty_supply_exists KAPWR]
|
||||
puts "KAPWR exists: $kapwr_exists"
|
||||
|
||||
set lowlv_exists [sta::liberty_supply_exists LOWLVPWR]
|
||||
puts "LOWLVPWR exists: $lowlv_exists"
|
||||
|
||||
set vpwrin_exists [sta::liberty_supply_exists VPWRIN]
|
||||
puts "VPWRIN exists: $vpwrin_exists"
|
||||
|
||||
set vss_exists [sta::liberty_supply_exists VSS]
|
||||
puts "VSS exists: $vss_exists"
|
||||
|
||||
# Non-existent supply
|
||||
set fake_exists [sta::liberty_supply_exists FAKE_SUPPLY]
|
||||
puts "FAKE_SUPPLY exists: $fake_exists"
|
||||
|
||||
puts "PASS: supply voltage queries"
|
||||
|
||||
############################################################
|
||||
# Clock gate cell queries (exercises clock_gating_integrated_cell)
|
||||
# dlclkp cells have latch_posedge type
|
||||
############################################################
|
||||
puts "--- clock gate cell queries ---"
|
||||
|
||||
foreach cell_name {sky130_fd_sc_hd__dlclkp_1 sky130_fd_sc_hd__dlclkp_2
|
||||
sky130_fd_sc_hd__dlclkp_4} {
|
||||
catch {
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
|
||||
if {$cell != "NULL"} {
|
||||
set area [get_property $cell area]
|
||||
set lp [get_property $cell cell_leakage_power]
|
||||
puts "$cell_name area=$area leakage=$lp"
|
||||
|
||||
# Report the cell to exercise arc enumeration
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name
|
||||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: dlclkp clock gate cells"
|
||||
|
||||
# sdlclkp cells have latch_posedge_precontrol type
|
||||
foreach cell_name {sky130_fd_sc_hd__sdlclkp_1 sky130_fd_sc_hd__sdlclkp_2
|
||||
sky130_fd_sc_hd__sdlclkp_4} {
|
||||
catch {
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
|
||||
if {$cell != "NULL"} {
|
||||
set area [get_property $cell area]
|
||||
puts "$cell_name area=$area"
|
||||
|
||||
# Iterate ports to check clock_gate_* pin attributes
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
set func [$port function]
|
||||
puts " [get_name $port] dir=$dir func=$func"
|
||||
}
|
||||
$port_iter finish
|
||||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: sdlclkp clock gate cells with precontrol"
|
||||
|
||||
############################################################
|
||||
# Level shifter cell queries
|
||||
# Exercises: visitIsLevelShifter, visitLevelShifterType
|
||||
############################################################
|
||||
puts "--- level shifter cell queries ---"
|
||||
|
||||
foreach cell_name {sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1
|
||||
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2
|
||||
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4
|
||||
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4
|
||||
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1
|
||||
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2
|
||||
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4} {
|
||||
catch {
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
|
||||
if {$cell != "NULL"} {
|
||||
set area [get_property $cell area]
|
||||
set lp [get_property $cell cell_leakage_power]
|
||||
puts "$cell_name area=$area leakage=$lp"
|
||||
|
||||
# Iterate ports
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
set is_pwr [$port is_pwr_gnd]
|
||||
if {!$is_pwr} {
|
||||
puts " [get_name $port] dir=$dir"
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: level shifter cell queries"
|
||||
|
||||
############################################################
|
||||
# PG pin queries on various cells
|
||||
# Exercises: pg_pin parsing, isPwrGnd, voltage_name
|
||||
############################################################
|
||||
puts "--- pg_pin queries ---"
|
||||
|
||||
foreach cell_name {sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__buf_1
|
||||
sky130_fd_sc_hd__nand2_1 sky130_fd_sc_hd__dfxtp_1
|
||||
sky130_fd_sc_hd__dlclkp_1 sky130_fd_sc_hd__sdfxtp_1} {
|
||||
catch {
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
|
||||
if {$cell != "NULL"} {
|
||||
set pwr_count 0
|
||||
set sig_count 0
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set is_pwr [$port is_pwr_gnd]
|
||||
if {$is_pwr} {
|
||||
incr pwr_count
|
||||
} else {
|
||||
incr sig_count
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
puts "$cell_name: pwr_pins=$pwr_count signal_pins=$sig_count"
|
||||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: pg_pin queries"
|
||||
|
||||
############################################################
|
||||
# Timing arc queries on clock gate cells
|
||||
# Exercises: timing_type for clock gate arcs
|
||||
############################################################
|
||||
puts "--- clock gate timing arcs ---"
|
||||
|
||||
catch {
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlclkp_1]
|
||||
if {$cell != "NULL"} {
|
||||
set arcs [$cell timing_arc_sets]
|
||||
set arc_count [llength $arcs]
|
||||
puts "dlclkp_1 arc_sets = $arc_count"
|
||||
foreach arc $arcs {
|
||||
set from_port [$arc from]
|
||||
set to_port [$arc to]
|
||||
set role [$arc role]
|
||||
puts " [$arc full_name] role=[$role name]"
|
||||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: clock gate timing arcs"
|
||||
|
||||
catch {
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdlclkp_1]
|
||||
if {$cell != "NULL"} {
|
||||
set arcs [$cell timing_arc_sets]
|
||||
set arc_count [llength $arcs]
|
||||
puts "sdlclkp_1 arc_sets = $arc_count"
|
||||
foreach arc $arcs {
|
||||
puts " [$arc full_name] role=[$role name]"
|
||||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: sdlclkp timing arcs"
|
||||
|
||||
############################################################
|
||||
# Timing arc queries on level shifter cells
|
||||
############################################################
|
||||
puts "--- level shifter timing arcs ---"
|
||||
|
||||
catch {
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1]
|
||||
if {$cell != "NULL"} {
|
||||
set arcs [$cell timing_arc_sets]
|
||||
puts "lsbuf_lh_hl_isowell_tap_1 arcs = [llength $arcs]"
|
||||
foreach arc $arcs {
|
||||
puts " [$arc full_name] role=[[$arc role] name]"
|
||||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: level shifter timing arcs"
|
||||
|
||||
############################################################
|
||||
# Buffer/inverter classification on Sky130 cells
|
||||
############################################################
|
||||
puts "--- cell classification ---"
|
||||
|
||||
foreach cell_name {sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_2
|
||||
sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_2
|
||||
sky130_fd_sc_hd__clkinv_1 sky130_fd_sc_hd__clkbuf_1
|
||||
sky130_fd_sc_hd__nand2_1 sky130_fd_sc_hd__nor2_1
|
||||
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dlclkp_1} {
|
||||
catch {
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
|
||||
if {$cell != "NULL"} {
|
||||
set is_buf [$cell is_buffer]
|
||||
set is_inv [$cell is_inverter]
|
||||
set is_leaf [$cell is_leaf]
|
||||
puts "$cell_name: is_buffer=$is_buf is_inverter=$is_inv is_leaf=$is_leaf"
|
||||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: cell classification"
|
||||
|
||||
############################################################
|
||||
# Write liberty for sky130 (exercises writer for pg_pin, level_shifter)
|
||||
############################################################
|
||||
set outfile [make_result_file liberty_clkgate_lvlshift_write.lib]
|
||||
catch {
|
||||
sta::write_liberty sky130_fd_sc_hd__tt_025C_1v80 $outfile
|
||||
puts "PASS: write_liberty sky130"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read IHP library for more voltage_map / pg_pin coverage
|
||||
############################################################
|
||||
read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
puts "PASS: read IHP library"
|
||||
|
||||
# Check supply exists after IHP
|
||||
set ihp_vdd_exists [sta::liberty_supply_exists VDD]
|
||||
puts "IHP VDD exists: $ihp_vdd_exists"
|
||||
|
||||
# Query IHP cells
|
||||
foreach cell_name {sg13g2_inv_1 sg13g2_buf_1 sg13g2_nand2_1 sg13g2_nor2_1} {
|
||||
catch {
|
||||
set cell [get_lib_cell sg13g2_stdcell_typ_1p20V_25C/$cell_name]
|
||||
if {$cell != "NULL"} {
|
||||
set area [get_property $cell area]
|
||||
set is_buf [$cell is_buffer]
|
||||
set is_inv [$cell is_inverter]
|
||||
puts "IHP $cell_name: area=$area buf=$is_buf inv=$is_inv"
|
||||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: IHP cell queries"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
PASS: make_equiv_cells
|
||||
PASS: find_equiv_cells INV_X1 (6 equivs)
|
||||
PASS: find_equiv_cells BUF_X1 (9 equivs)
|
||||
PASS: find_equiv_cells NAND2_X1 (3 equivs)
|
||||
PASS: find_equiv_cells NOR2_X1 (3 equivs)
|
||||
PASS: find_equiv_cells AND2_X1 (3 equivs)
|
||||
PASS: find_equiv_cells OR2_X1 (3 equivs)
|
||||
PASS: find_equiv_cells DFF_X1 (2 equivs)
|
||||
PASS: find_equiv_cells DFFR_X1 (2 equivs)
|
||||
PASS: find_equiv_cells DFFS_X1 (2 equivs)
|
||||
PASS: find_equiv_cells AOI21_X1 (3 equivs)
|
||||
PASS: find_equiv_cells OAI21_X1 (3 equivs)
|
||||
PASS: find_equiv_cells MUX2_X1 (2 equivs)
|
||||
PASS: find_equiv_cells SDFF_X1 (2 equivs)
|
||||
PASS: equiv_cells INV_X1 INV_X2 = 1
|
||||
PASS: equiv_cells BUF_X1 BUF_X2 = 1
|
||||
PASS: equiv_cells INV_X1 BUF_X1 = 0
|
||||
PASS: equiv_cells NAND2_X1 NOR2_X1 = 0
|
||||
PASS: equiv_cells DFF_X1 DFF_X2 = 1
|
||||
PASS: equiv_cells DFF_X1 DFFR_X1 = 0
|
||||
PASS: equiv_cells NAND2_X1 NAND3_X1 = 0
|
||||
PASS: equiv_cells INV_X4 INV_X8 = 1
|
||||
PASS: equiv_cell_ports INV_X1 INV_X2 = 1
|
||||
PASS: equiv_cell_ports INV_X1 BUF_X1 = 0
|
||||
PASS: equiv_cell_ports NAND2_X1 NAND2_X2 = 1
|
||||
PASS: equiv_cell_ports NAND2_X1 NAND3_X1 = 0
|
||||
PASS: equiv_cell_timing_arcs INV_X1 INV_X2 = 1
|
||||
PASS: equiv_cell_timing_arcs BUF_X1 BUF_X2 = 1
|
||||
PASS: equiv_cell_timing_arcs INV_X1 BUF_X1 = 0
|
||||
PASS: find_library_buffers (9 buffers)
|
||||
PASS: find_liberty found
|
||||
PASS: liberty_library_iterator
|
||||
PASS: liberty_supply_exists VDD = 1
|
||||
PASS: liberty_supply_exists VSS = 1
|
||||
PASS: liberty_supply_exists NONEXISTENT = 0
|
||||
PASS: INV_X1/A direction = input
|
||||
PASS: INV_X1/ZN direction = output
|
||||
PASS: DFF_X1/CK direction = input
|
||||
PASS: DFF_X1/Q direction = output
|
||||
PASS: make_equiv_cells fast library
|
||||
PASS: find_equiv_cells fast INV_X1 (6 equivs)
|
||||
PASS: equiv_cells across libraries = 1
|
||||
ALL PASSED
|
||||
|
|
@ -0,0 +1,209 @@
|
|||
# Test equivalent cell finding for EquivCells.cc code coverage
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
|
||||
############################################################
|
||||
# make_equiv_cells / find_equiv_cells / equiv_cells
|
||||
############################################################
|
||||
|
||||
# Make equivalent cells for the Nangate library
|
||||
set lib [lindex [get_libs NangateOpenCellLibrary] 0]
|
||||
sta::make_equiv_cells $lib
|
||||
puts "PASS: make_equiv_cells"
|
||||
|
||||
# Find equiv cells for various cell types
|
||||
# INV_X1 should have equivalents (INV_X2, INV_X4, etc.)
|
||||
set inv_cell [get_lib_cell NangateOpenCellLibrary/INV_X1]
|
||||
set inv_equivs [sta::find_equiv_cells $inv_cell]
|
||||
puts "PASS: find_equiv_cells INV_X1 ([llength $inv_equivs] equivs)"
|
||||
|
||||
set buf_cell [get_lib_cell NangateOpenCellLibrary/BUF_X1]
|
||||
set buf_equivs [sta::find_equiv_cells $buf_cell]
|
||||
puts "PASS: find_equiv_cells BUF_X1 ([llength $buf_equivs] equivs)"
|
||||
|
||||
set nand_cell [get_lib_cell NangateOpenCellLibrary/NAND2_X1]
|
||||
set nand_equivs [sta::find_equiv_cells $nand_cell]
|
||||
puts "PASS: find_equiv_cells NAND2_X1 ([llength $nand_equivs] equivs)"
|
||||
|
||||
set nor_cell [get_lib_cell NangateOpenCellLibrary/NOR2_X1]
|
||||
set nor_equivs [sta::find_equiv_cells $nor_cell]
|
||||
puts "PASS: find_equiv_cells NOR2_X1 ([llength $nor_equivs] equivs)"
|
||||
|
||||
set and_cell [get_lib_cell NangateOpenCellLibrary/AND2_X1]
|
||||
set and_equivs [sta::find_equiv_cells $and_cell]
|
||||
puts "PASS: find_equiv_cells AND2_X1 ([llength $and_equivs] equivs)"
|
||||
|
||||
set or_cell [get_lib_cell NangateOpenCellLibrary/OR2_X1]
|
||||
set or_equivs [sta::find_equiv_cells $or_cell]
|
||||
puts "PASS: find_equiv_cells OR2_X1 ([llength $or_equivs] equivs)"
|
||||
|
||||
# DFF cells
|
||||
set dff_cell [get_lib_cell NangateOpenCellLibrary/DFF_X1]
|
||||
set dff_equivs [sta::find_equiv_cells $dff_cell]
|
||||
puts "PASS: find_equiv_cells DFF_X1 ([llength $dff_equivs] equivs)"
|
||||
|
||||
set dffr_cell [get_lib_cell NangateOpenCellLibrary/DFFR_X1]
|
||||
set dffr_equivs [sta::find_equiv_cells $dffr_cell]
|
||||
puts "PASS: find_equiv_cells DFFR_X1 ([llength $dffr_equivs] equivs)"
|
||||
|
||||
set dffs_cell [get_lib_cell NangateOpenCellLibrary/DFFS_X1]
|
||||
set dffs_equivs [sta::find_equiv_cells $dffs_cell]
|
||||
puts "PASS: find_equiv_cells DFFS_X1 ([llength $dffs_equivs] equivs)"
|
||||
|
||||
# AOI cells
|
||||
set aoi_cell [get_lib_cell NangateOpenCellLibrary/AOI21_X1]
|
||||
set aoi_equivs [sta::find_equiv_cells $aoi_cell]
|
||||
puts "PASS: find_equiv_cells AOI21_X1 ([llength $aoi_equivs] equivs)"
|
||||
|
||||
# OAI cells
|
||||
set oai_cell [get_lib_cell NangateOpenCellLibrary/OAI21_X1]
|
||||
set oai_equivs [sta::find_equiv_cells $oai_cell]
|
||||
puts "PASS: find_equiv_cells OAI21_X1 ([llength $oai_equivs] equivs)"
|
||||
|
||||
# MUX cells
|
||||
set mux_cell [get_lib_cell NangateOpenCellLibrary/MUX2_X1]
|
||||
set mux_equivs [sta::find_equiv_cells $mux_cell]
|
||||
puts "PASS: find_equiv_cells MUX2_X1 ([llength $mux_equivs] equivs)"
|
||||
|
||||
# SDFF cells
|
||||
set sdff_cell [get_lib_cell NangateOpenCellLibrary/SDFF_X1]
|
||||
set sdff_equivs [sta::find_equiv_cells $sdff_cell]
|
||||
puts "PASS: find_equiv_cells SDFF_X1 ([llength $sdff_equivs] equivs)"
|
||||
|
||||
############################################################
|
||||
# equiv_cells comparison
|
||||
############################################################
|
||||
|
||||
# Same-function cells should be equivalent
|
||||
set inv_x1 [get_lib_cell NangateOpenCellLibrary/INV_X1]
|
||||
set inv_x2 [get_lib_cell NangateOpenCellLibrary/INV_X2]
|
||||
set result [sta::equiv_cells $inv_x1 $inv_x2]
|
||||
puts "PASS: equiv_cells INV_X1 INV_X2 = $result"
|
||||
|
||||
set buf_x1 [get_lib_cell NangateOpenCellLibrary/BUF_X1]
|
||||
set buf_x2 [get_lib_cell NangateOpenCellLibrary/BUF_X2]
|
||||
set result [sta::equiv_cells $buf_x1 $buf_x2]
|
||||
puts "PASS: equiv_cells BUF_X1 BUF_X2 = $result"
|
||||
|
||||
# Different-function cells should NOT be equivalent
|
||||
set result [sta::equiv_cells $inv_x1 $buf_x1]
|
||||
puts "PASS: equiv_cells INV_X1 BUF_X1 = $result"
|
||||
|
||||
set result [sta::equiv_cells $nand_cell $nor_cell]
|
||||
puts "PASS: equiv_cells NAND2_X1 NOR2_X1 = $result"
|
||||
|
||||
# DFF equivalence
|
||||
set dff_x1 [get_lib_cell NangateOpenCellLibrary/DFF_X1]
|
||||
set dff_x2 [get_lib_cell NangateOpenCellLibrary/DFF_X2]
|
||||
set result [sta::equiv_cells $dff_x1 $dff_x2]
|
||||
puts "PASS: equiv_cells DFF_X1 DFF_X2 = $result"
|
||||
|
||||
# DFF vs DFFR (different function - has reset)
|
||||
set result [sta::equiv_cells $dff_x1 $dffr_cell]
|
||||
puts "PASS: equiv_cells DFF_X1 DFFR_X1 = $result"
|
||||
|
||||
# NAND2 vs NAND3 (different port count)
|
||||
set nand3_cell [get_lib_cell NangateOpenCellLibrary/NAND3_X1]
|
||||
set result [sta::equiv_cells $nand_cell $nand3_cell]
|
||||
puts "PASS: equiv_cells NAND2_X1 NAND3_X1 = $result"
|
||||
|
||||
# Larger drive strengths
|
||||
set inv_x4 [get_lib_cell NangateOpenCellLibrary/INV_X4]
|
||||
set inv_x8 [get_lib_cell NangateOpenCellLibrary/INV_X8]
|
||||
set result [sta::equiv_cells $inv_x4 $inv_x8]
|
||||
puts "PASS: equiv_cells INV_X4 INV_X8 = $result"
|
||||
|
||||
############################################################
|
||||
# equiv_cell_ports comparison
|
||||
############################################################
|
||||
|
||||
set result [sta::equiv_cell_ports $inv_x1 $inv_x2]
|
||||
puts "PASS: equiv_cell_ports INV_X1 INV_X2 = $result"
|
||||
|
||||
set result [sta::equiv_cell_ports $inv_x1 $buf_x1]
|
||||
puts "PASS: equiv_cell_ports INV_X1 BUF_X1 = $result"
|
||||
|
||||
set nand2_x1 [get_lib_cell NangateOpenCellLibrary/NAND2_X1]
|
||||
set nand2_x2 [get_lib_cell NangateOpenCellLibrary/NAND2_X2]
|
||||
set result [sta::equiv_cell_ports $nand2_x1 $nand2_x2]
|
||||
puts "PASS: equiv_cell_ports NAND2_X1 NAND2_X2 = $result"
|
||||
|
||||
# Different port count cells
|
||||
set nand3_x1 [get_lib_cell NangateOpenCellLibrary/NAND3_X1]
|
||||
set result [sta::equiv_cell_ports $nand2_x1 $nand3_x1]
|
||||
puts "PASS: equiv_cell_ports NAND2_X1 NAND3_X1 = $result"
|
||||
|
||||
############################################################
|
||||
# equiv_cell_timing_arcs comparison
|
||||
############################################################
|
||||
|
||||
set result [sta::equiv_cell_timing_arcs $inv_x1 $inv_x2]
|
||||
puts "PASS: equiv_cell_timing_arcs INV_X1 INV_X2 = $result"
|
||||
|
||||
set result [sta::equiv_cell_timing_arcs $buf_x1 $buf_x2]
|
||||
puts "PASS: equiv_cell_timing_arcs BUF_X1 BUF_X2 = $result"
|
||||
|
||||
set result [sta::equiv_cell_timing_arcs $inv_x1 $buf_x1]
|
||||
puts "PASS: equiv_cell_timing_arcs INV_X1 BUF_X1 = $result"
|
||||
|
||||
############################################################
|
||||
# find_library_buffers
|
||||
############################################################
|
||||
|
||||
set buffers [sta::find_library_buffers $lib]
|
||||
puts "PASS: find_library_buffers ([llength $buffers] buffers)"
|
||||
|
||||
############################################################
|
||||
# Additional library queries
|
||||
############################################################
|
||||
|
||||
set found_lib [sta::find_liberty NangateOpenCellLibrary]
|
||||
puts "PASS: find_liberty found"
|
||||
|
||||
set lib_iter [sta::liberty_library_iterator]
|
||||
puts "PASS: liberty_library_iterator"
|
||||
|
||||
# liberty_supply_exists
|
||||
set result [sta::liberty_supply_exists VDD]
|
||||
puts "PASS: liberty_supply_exists VDD = $result"
|
||||
|
||||
set result [sta::liberty_supply_exists VSS]
|
||||
puts "PASS: liberty_supply_exists VSS = $result"
|
||||
|
||||
set result [sta::liberty_supply_exists NONEXISTENT]
|
||||
puts "PASS: liberty_supply_exists NONEXISTENT = $result"
|
||||
|
||||
# liberty_port_direction on various pins
|
||||
set pin [get_lib_pin NangateOpenCellLibrary/INV_X1/A]
|
||||
set dir [sta::liberty_port_direction $pin]
|
||||
puts "PASS: INV_X1/A direction = $dir"
|
||||
|
||||
set pin [get_lib_pin NangateOpenCellLibrary/INV_X1/ZN]
|
||||
set dir [sta::liberty_port_direction $pin]
|
||||
puts "PASS: INV_X1/ZN direction = $dir"
|
||||
|
||||
set pin [get_lib_pin NangateOpenCellLibrary/DFF_X1/CK]
|
||||
set dir [sta::liberty_port_direction $pin]
|
||||
puts "PASS: DFF_X1/CK direction = $dir"
|
||||
|
||||
set pin [get_lib_pin NangateOpenCellLibrary/DFF_X1/Q]
|
||||
set dir [sta::liberty_port_direction $pin]
|
||||
puts "PASS: DFF_X1/Q direction = $dir"
|
||||
|
||||
############################################################
|
||||
# EquivCells across fast library
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_fast.lib
|
||||
set fast_lib [lindex [get_libs NangateOpenCellLibrary_fast] 0]
|
||||
sta::make_equiv_cells $fast_lib
|
||||
puts "PASS: make_equiv_cells fast library"
|
||||
|
||||
set fast_inv [get_lib_cell NangateOpenCellLibrary_fast/INV_X1]
|
||||
set fast_inv_equivs [sta::find_equiv_cells $fast_inv]
|
||||
puts "PASS: find_equiv_cells fast INV_X1 ([llength $fast_inv_equivs] equivs)"
|
||||
|
||||
# Cross-library equiv check
|
||||
set result [sta::equiv_cells $inv_x1 $fast_inv]
|
||||
puts "PASS: equiv_cells across libraries = $result"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
@ -0,0 +1,85 @@
|
|||
PASS: read ASAP7 INVBUF RVT
|
||||
PASS: read ASAP7 INVBUF LVT
|
||||
PASS: read ASAP7 INVBUF SLVT
|
||||
PASS: make_equiv_cells ASAP7 RVT INVBUF
|
||||
INVx1_ASAP7_75t_R equiv count = 21
|
||||
INVx2_ASAP7_75t_R equiv count = 21
|
||||
INVx3_ASAP7_75t_R equiv count = 21
|
||||
INVx4_ASAP7_75t_R equiv count = 21
|
||||
INVx5_ASAP7_75t_R equiv count = 21
|
||||
INVx8_ASAP7_75t_R equiv count = 21
|
||||
INVx11_ASAP7_75t_R equiv count = 21
|
||||
INVx13_ASAP7_75t_R equiv count = 21
|
||||
Warning: liberty_equiv_cross_lib.tcl line 1, cell 'INVx16_ASAP7_75t_R' not found.
|
||||
Warning: liberty_equiv_cross_lib.tcl line 1, cell 'BUFx1_ASAP7_75t_R' not found.
|
||||
BUFx2_ASAP7_75t_R equiv count = 16
|
||||
BUFx3_ASAP7_75t_R equiv count = 16
|
||||
BUFx4_ASAP7_75t_R equiv count = 16
|
||||
BUFx5_ASAP7_75t_R equiv count = 16
|
||||
BUFx8_ASAP7_75t_R equiv count = 16
|
||||
Warning: liberty_equiv_cross_lib.tcl line 1, cell 'BUFx11_ASAP7_75t_R' not found.
|
||||
Warning: liberty_equiv_cross_lib.tcl line 1, cell 'BUFx13_ASAP7_75t_R' not found.
|
||||
Warning: liberty_equiv_cross_lib.tcl line 1, cell 'BUFx16_ASAP7_75t_R' not found.
|
||||
PASS: ASAP7 RVT INVBUF equiv cells
|
||||
PASS: ASAP7 RVT buffers = 16
|
||||
PASS: make_equiv_cells ASAP7 LVT INVBUF
|
||||
LVT INVx1_ASAP7_75t_L equiv count = 21
|
||||
LVT INVx2_ASAP7_75t_L equiv count = 21
|
||||
LVT INVx4_ASAP7_75t_L equiv count = 21
|
||||
LVT INVx8_ASAP7_75t_L equiv count = 21
|
||||
Warning: liberty_equiv_cross_lib.tcl line 1, cell 'BUFx1_ASAP7_75t_L' not found.
|
||||
LVT BUFx2_ASAP7_75t_L equiv count = 16
|
||||
LVT BUFx4_ASAP7_75t_L equiv count = 16
|
||||
LVT BUFx8_ASAP7_75t_L equiv count = 16
|
||||
PASS: ASAP7 LVT INVBUF equiv cells
|
||||
PASS: ASAP7 LVT buffers = 16
|
||||
PASS: make_equiv_cells ASAP7 SLVT INVBUF
|
||||
PASS: ASAP7 SLVT buffers = 16
|
||||
--- cross-Vt equiv comparisons ---
|
||||
equiv RVT/LVT INVx1 = 1
|
||||
port_equiv RVT/LVT INVx1 = 1
|
||||
arc_equiv RVT/LVT INVx1 = 1
|
||||
PASS: cross-Vt comparisons
|
||||
PASS: read ASAP7 SEQ RVT + LVT
|
||||
PASS: make_equiv_cells SEQ RVT
|
||||
SEQ RVT DFFHQNx1 equiv count = 3
|
||||
equiv: DFFHQNx1_ASAP7_75t_R
|
||||
equiv: DFFHQNx2_ASAP7_75t_R
|
||||
equiv: DFFHQNx3_ASAP7_75t_R
|
||||
PASS: SEQ RVT DFF equiv
|
||||
SEQ RVT ICGx1 equiv count = 10
|
||||
PASS: SEQ RVT ICG equiv
|
||||
SEQ RVT DLLx1 equiv count = 3
|
||||
PASS: SEQ RVT latch equiv
|
||||
Warning: liberty_equiv_cross_lib.tcl line 1, cell 'SDFHQNx1_ASAP7_75t_R' not found.
|
||||
PASS: SEQ RVT SDFF equiv
|
||||
equiv SEQ RVT/LVT DFFHQNx1 = 1
|
||||
port_equiv SEQ RVT/LVT DFFHQNx1 = 1
|
||||
PASS: cross-lib SEQ comparisons
|
||||
PASS: read Sky130
|
||||
PASS: make_equiv_cells Sky130
|
||||
Sky130 inv_1 equiv count = 16
|
||||
equiv: sky130_fd_sc_hd__clkinvlp_2
|
||||
equiv: sky130_fd_sc_hd__inv_1
|
||||
equiv: sky130_fd_sc_hd__clkinv_1
|
||||
equiv: sky130_fd_sc_hd__clkinvlp_4
|
||||
equiv: sky130_fd_sc_hd__inv_2
|
||||
equiv: sky130_fd_sc_hd__clkinv_2
|
||||
equiv: sky130_fd_sc_hd__inv_4
|
||||
equiv: sky130_fd_sc_hd__inv_6
|
||||
equiv: sky130_fd_sc_hd__clkinv_4
|
||||
equiv: sky130_fd_sc_hd__bufinv_8
|
||||
equiv: sky130_fd_sc_hd__inv_8
|
||||
equiv: sky130_fd_sc_hd__clkinv_8
|
||||
equiv: sky130_fd_sc_hd__inv_12
|
||||
equiv: sky130_fd_sc_hd__bufinv_16
|
||||
equiv: sky130_fd_sc_hd__inv_16
|
||||
equiv: sky130_fd_sc_hd__clkinv_16
|
||||
PASS: Sky130 inv equiv
|
||||
Sky130 dfxtp_1 equiv count = 3
|
||||
equiv: sky130_fd_sc_hd__dfxtp_1
|
||||
equiv: sky130_fd_sc_hd__dfxtp_2
|
||||
equiv: sky130_fd_sc_hd__dfxtp_4
|
||||
PASS: Sky130 DFF equiv
|
||||
PASS: Sky130 buffers = 35
|
||||
ALL PASSED
|
||||
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Loading…
Reference in New Issue