rm write_verilog -sort

Signed-off-by: James Cherry <cherry@parallaxsw.com>

doc/ApiChanges.txt

@@ -53,6 +53,9 @@ The following classes now return const objects.
 Liberty PgPorts are now LibertyPorts with additional member functions for
 liberty pg_pins.
 
+The write_verilog command always sorts the verilog file instances.
+The -sort argument is ignored.
+
 Release 2.6.1 2025/03/??
 -------------------------
 

doc/OpenSTA.fodt

@@ -13772,18 +13772,9 @@
       <text:p text:style-name="P29"><text:alphabetical-index-mark-start text:id="IMark53760024032"/><text:span text:style-name="Command_20_Heading">write_verilog</text:span><text:alphabetical-index-mark-end text:id="IMark53760024032"/></text:p>
      </table:table-cell>
      <table:table-cell table:style-name="Table109.A1" office:value-type="string">
-      <text:p text:style-name="P264">[-sort<text:span text:style-name="T22">]</text:span></text:p>
       <text:p text:style-name="P264"><text:span text:style-name="T22">[-include_pwr_gnd]</text:span><text:line-break/>[-remove_cells <text:span text:style-name="T1">lib_cells</text:span><text:span text:style-name="T22">]</text:span><text:line-break/><text:span text:style-name="T1">filename</text:span></text:p>
      </table:table-cell>
     </table:table-row>
-    <table:table-row table:style-name="Table109.1">
-     <table:table-cell table:style-name="Table109.A2" office:value-type="string">
-      <text:p text:style-name="P265"><text:span text:style-name="Command_20_Argument"><text:span text:style-name="T317">-sort</text:span></text:span></text:p>
-     </table:table-cell>
-     <table:table-cell table:style-name="Table109.A2" office:value-type="string">
-      <text:p text:style-name="P29"><text:span text:style-name="Default_20_Paragraph_20_Font">Sort the instances in the netlist.</text:span></text:p>
-     </table:table-cell>
-    </table:table-row>
     <table:table-row table:style-name="Table109.1">
      <table:table-cell table:style-name="Table109.A2" office:value-type="string">
       <text:p text:style-name="P288">-include_pwr_gnd</text:p>
@@ -13809,7 +13800,7 @@
      </table:table-cell>
     </table:table-row>
    </table:table>
-   <text:p text:style-name="P290">The <text:span text:style-name="T7">write_verilog</text:span> command writes a Verilog netlist to <text:span text:style-name="T3">filename</text:span>. Use <text:span text:style-name="T317">-sort</text:span> to sort the instances so the results are reproducible across operating systems. Use <text:span text:style-name="T7">-remove_cells</text:span> to remove instances of <text:span text:style-name="T3">lib_cells</text:span> from the netlist.</text:p>
+   <text:p text:style-name="P290">The <text:span text:style-name="T7">write_verilog</text:span> command writes a Verilog netlist to <text:span text:style-name="T3">filename</text:span>. Instances are always sorted so the results are reproducible across operating systems. Use <text:span text:style-name="T7">-remove_cells</text:span> to remove instances of <text:span text:style-name="T3">lib_cells</text:span> from the netlist.</text:p>
    <text:h text:style-name="Heading_20_1" text:outline-level="1"><text:bookmark-start text:name="__RefHeading___Toc42589_2528141652"/><text:alphabetical-index-mark-start text:id="IMark53760024032"/>Filter Expressions<text:bookmark-end text:name="__RefHeading___Toc42589_2528141652"/><text:alphabetical-index-mark-end text:id="IMark53760024032"/></text:h>
    <text:p text:style-name="P291">The <text:span text:style-name="Example">get_cells</text:span>, <text:span text:style-name="Example">get_pins</text:span>, <text:span text:style-name="Example">get_ports</text:span> and <text:span text:style-name="Example">get_timing_edges</text:span> functions support filtering the returned objects by property values. Supported filter expressions are shown below.</text:p>
    <table:table table:name="Table66" table:style-name="Table66">

include/sta/VerilogWriter.hh

@@ -30,7 +30,6 @@ namespace sta {
 
 void
 writeVerilog(const char *filename,
-	     bool sort,
 	     bool include_pwr_gnd,
 	     CellSeq *remove_cells,
 	     Network *network);

verilog/Verilog.i

@@ -39,14 +39,13 @@ read_verilog_cmd(const char *filename)
 
 void
 write_verilog_cmd(const char *filename,
-		  bool sort,
 		  bool include_pwr_gnd,
 		  CellSeq *remove_cells)
 {
   // This does NOT want the SDC (cmd) network because it wants
   // to see the sta internal names.
   Network *network = Sta::sta()->network();
-  writeVerilog(filename, sort, include_pwr_gnd, remove_cells, network);
+  writeVerilog(filename, include_pwr_gnd, remove_cells, network);
   delete remove_cells;
 }
 

verilog/Verilog.tcl

@@ -31,22 +31,25 @@ proc_redirect read_verilog {
   read_verilog_cmd [file nativename [lindex $args 0]]
 }
 
-define_cmd_args "write_verilog" {[-sort] [-include_pwr_gnd]\
+define_cmd_args "write_verilog" {[-include_pwr_gnd]\
 				   [-remove_cells cells] filename}
 
 proc write_verilog { args } {
+  # -sort deprecated 12/12/2025
   parse_key_args "write_verilog" args keys {-remove_cells} \
     flags {-sort -include_pwr_gnd}
 
+  if { [info exists flags(-sort)] } {
+    sta_warn 1338 "The -sort flag is ignored."
+  }
   set remove_cells {}
   if { [info exists keys(-remove_cells)] } {
     set remove_cells [parse_cell_arg $keys(-remove_cells)]
   }
-  set sort [info exists flags(-sort)]
   set include_pwr_gnd [info exists flags(-include_pwr_gnd)]
   check_argc_eq1 "write_verilog" $args
   set filename [file nativename [lindex $args 0]]
-  write_verilog_cmd $filename $sort $include_pwr_gnd $remove_cells
+  write_verilog_cmd $filename $include_pwr_gnd $remove_cells
 }
 
 # sta namespace end

verilog/VerilogWriter.cc

@@ -45,7 +45,6 @@ class VerilogWriter
 {
 public:
   VerilogWriter(const char *filename,
-		bool sort,
 		bool include_pwr_gnd,
 		CellSeq *remove_cells,
 		FILE *stream,
@@ -81,7 +80,6 @@ protected:
                       const Port *port);
 
   const char *filename_;
-  bool sort_;
   bool include_pwr_gnd_;
   CellSet remove_cells_;
   FILE *stream_;
@@ -91,7 +89,6 @@ protected:
 
 void
 writeVerilog(const char *filename,
-	     bool sort,
 	     bool include_pwr_gnd,
 	     CellSeq *remove_cells,
 	     Network *network)
@@ -99,7 +96,7 @@ writeVerilog(const char *filename,
   if (network->topInstance()) {
     FILE *stream = fopen(filename, "w");
     if (stream) {
-      VerilogWriter writer(filename, sort, include_pwr_gnd,
+      VerilogWriter writer(filename, include_pwr_gnd,
 			   remove_cells, stream, network);
       writer.writeModules();
       fclose(stream);
@@ -110,13 +107,11 @@ writeVerilog(const char *filename,
 }
 
 VerilogWriter::VerilogWriter(const char *filename,
-			     bool sort,
 			     bool include_pwr_gnd,
 			     CellSeq *remove_cells,
 			     FILE *stream,
 			     Network *network) :
   filename_(filename),
-  sort_(sort),
   include_pwr_gnd_(include_pwr_gnd),
   remove_cells_(network),
   stream_(stream),
@@ -146,13 +141,12 @@ VerilogWriter::findHierChildren()
   CellSet cells(network_);
   findHierChildren(network_->topInstance(), children, cells);
 
-  if (sort_)
-    sort(children, [this](const Instance *inst1,
-                          const Instance *inst2) {
-      const char *cell_name1 = network_->cellName(inst1);
-      const char *cell_name2 = network_->cellName(inst2);
-      return stringLess(cell_name1, cell_name2);
-    });
+  sort(children, [this](const Instance *inst1,
+                        const Instance *inst2) {
+    const char *cell_name1 = network_->cellName(inst1);
+    const char *cell_name2 = network_->cellName(inst2);
+    return stringLess(cell_name1, cell_name2);
+  });
 
   return children;
 }
@@ -327,11 +321,10 @@ VerilogWriter::writeChildren(const Instance *inst)
   }
   delete child_iter;
 
-  if (sort_)
-    sort(children, [this](const Instance *inst1,
-                          const Instance *inst2) {
-      return stringLess(network_->name(inst1), network_->name(inst2));
-    });
+  sort(children, [this](const Instance *inst1,
+                        const Instance *inst2) {
+    return stringLess(network_->name(inst1), network_->name(inst2));
+  });
 
   for (auto child : children)
     writeChild(child);