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write_verilog wire dcls for NC w/o liberty resolves #221 

Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry 2025-02-26 16:08:13 -08:00
parent 0f379ffcad
commit ae12d40828
1 changed files with 8 additions and 12 deletions
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20
verilog/VerilogWriter.cc
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@ -508,19 +508,15 @@ VerilogWriter::findPortNCcount(const Instance *inst,
const Port *port)
{
int nc_count = 0;
LibertyPort *lib_port = network_->libertyPort(port);
if (lib_port) {
Cell *cell = network_->cell(inst);
LibertyPortMemberIterator member_iter(lib_port);
while (member_iter.hasNext()) {
LibertyPort *lib_member = member_iter.next();
Port *member = network_->findPort(cell, lib_member->name());
Pin *pin = network_->findPin(inst, member);
if (pin == nullptr
|| network_->net(pin) == nullptr)
nc_count++;
}
PortMemberIterator *member_iter = network_->memberIterator(port);
while (member_iter->hasNext()) {
Port *member = member_iter->next();
Pin *pin = network_->findPin(inst, member);
if (pin == nullptr
|| network_->net(pin) == nullptr)
nc_count++;
}
delete member_iter;
return nc_count;
}