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StdStringSet -> StringSet 

Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry 2026-03-08 15:55:12 -07:00
parent 859982bdc7
commit 28d94b83fa
13 changed files with 27 additions and 27 deletions
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4
include/sta/PathGroup.hh
View File

@ -184,14 +184,14 @@ protected:
bool unique_edges,
float slack_min,
float slack_max,
StdStringSet &group_names,
StringSet &group_names,
bool setup_hold,
bool async,
bool gated_clk,
bool unconstrained,
const MinMax *min_max);
bool reportGroup(const char *group_name,
StdStringSet &group_names) const;
StringSet &group_names) const;
static GroupPath *groupPathTo(const PathEnd *path_end,
const StaState *sta);
StringSeq pathGroupNames();

2
include/sta/StringUtil.hh
View File

@ -35,7 +35,7 @@
namespace sta {
using StringSeq = std::vector<std::string>;
using StdStringSet = std::set<std::string>;
using StringSet = std::set<std::string>;
inline bool
stringEq(const char *str1,

2
include/sta/TclTypeHelpers.hh
View File

@ -39,7 +39,7 @@ tclListSeqStdString(Tcl_Obj *const source,
StringSeq *
tclListSeqStdStringPtr(Tcl_Obj *const source,
Tcl_Interp *interp);
StdStringSet *
StringSet *
tclListSetStdString(Tcl_Obj *const source,
Tcl_Interp *interp);

2
include/sta/VerilogReader.hh
View File

@ -173,7 +173,7 @@ protected:
void makeNamedPortRefCellPorts(Cell *cell,
VerilogModule *module,
VerilogNet *mod_port,
StdStringSet &port_names);
StringSet &port_names);
void checkModuleDcls(VerilogModule *module,
std::set<std::string> &port_names);
void makeModuleInstBody(VerilogModule *module,

6
search/PathGroup.cc
View File

@ -276,7 +276,7 @@ PathGroups::PathGroups(int group_path_count,
slack_min_(slack_min),
slack_max_(slack_max)
{
StdStringSet groups;
StringSet groups;
for (std::string &group_name : group_names)
groups.insert(group_name);
@ -297,7 +297,7 @@ PathGroups::makeGroups(int group_path_count,
bool unique_edges,
float slack_min,
float slack_max,
StdStringSet &group_names,
StringSet &group_names,
bool setup_hold,
bool async,
bool gated_clk,
@ -417,7 +417,7 @@ PathGroups::findPathGroup(const Clock *clock,
bool
PathGroups::reportGroup(const char *group_name,
StdStringSet &group_names) const
StringSet &group_names) const
{
return group_names.empty()
|| group_names.contains(group_name);

2
search/Sta.cc
View File

@ -2601,7 +2601,7 @@ Sta::updateSceneLiberty(Scene *scene,
const StringSeq &liberty_min_files,
const StringSeq &liberty_max_files)
{
StdStringSet warned_files;
StringSet warned_files;
for (const MinMax *min_max : MinMax::range()) {
const StringSeq &liberty_files = min_max == MinMax::min()
? liberty_min_files

10
spice/WritePathSpice.cc
View File

@ -80,8 +80,8 @@ private:
void writeGateStage(Stage stage);
void writeStageParasitics(Stage stage);
void writeSubckts();
StdStringSet findPathCellNames();
void findPathCellSubckts(StdStringSet &path_cell_names);
StringSet findPathCellNames();
void findPathCellSubckts(StringSet &path_cell_names);
float maxTime();
float pathMaxTime();
void writeMeasureDelayStmt(Stage stage,
@ -562,14 +562,14 @@ WritePathSpice::writeStageParasitics(Stage stage)
void
WritePathSpice::writeSubckts()
{
StdStringSet cell_names = findPathCellNames();
StringSet cell_names = findPathCellNames();
writeSubckts(cell_names);
}
StdStringSet
StringSet
WritePathSpice::findPathCellNames()
{
StdStringSet path_cell_names;
StringSet path_cell_names;
for (Stage stage = stageFirst(); stage <= stageLast(); stage++) {
const TimingArc *arc = stageGateArc(stage);
if (arc) {

4
spice/WriteSpice.cc
View File

@ -199,7 +199,7 @@ WriteSpice::writeGnuplotFile(StringSeq &node_nanes)
}
void
WriteSpice::writeSubckts(StdStringSet &cell_names)
WriteSpice::writeSubckts(StringSet &cell_names)
{
findCellSubckts(cell_names);
std::ifstream lib_subckts_stream(lib_subckt_filename_);
@ -278,7 +278,7 @@ WriteSpice::recordSpicePortNames(const char *cell_name,
// Subckts can call subckts (asap7).
void
WriteSpice::findCellSubckts(StdStringSet &cell_names)
WriteSpice::findCellSubckts(StringSet &cell_names)
{
std::ifstream lib_subckts_stream(lib_subckt_filename_);
if (lib_subckts_stream.is_open()) {

4
spice/WriteSpice.hh
View File

@ -65,8 +65,8 @@ protected:
float time_step);
void writePrintStmt(StringSeq &node_names);
void writeGnuplotFile(StringSeq &node_nanes);
void writeSubckts(StdStringSet &cell_names);
void findCellSubckts(StdStringSet &cell_names);
void writeSubckts(StringSet &cell_names);
void findCellSubckts(StringSet &cell_names);
void recordSpicePortNames(const char *cell_name,
StringSeq &tokens);
void writeSubcktInst(const Instance *inst);

4
tcl/StaTclTypes.i
View File

@ -290,7 +290,7 @@ using namespace sta;
Tcl_SetResult(interp, nullptr, TCL_STATIC);
}
%typemap(in) StdStringSet* {
%typemap(in) StringSet* {
$1 = tclListSetStdString($input, interp);
}
@ -307,7 +307,7 @@ using namespace sta;
$1 = tclListSeqStdStringPtr($input, interp);
}
%typemap(in) StdStringSet* {
%typemap(in) StringSet* {
$1 = tclListSetStdString($input, interp);
}

4
tcl/TclTypeHelpers.cc
View File

@ -68,7 +68,7 @@ tclListSeqStdStringPtr(Tcl_Obj *const source,
return nullptr;
}
StdStringSet *
StringSet *
tclListSetStdString(Tcl_Obj *const source,
Tcl_Interp *interp)
{
@ -76,7 +76,7 @@ tclListSetStdString(Tcl_Obj *const source,
Tcl_Obj **argv;
if (Tcl_ListObjGetElements(interp, source, &argc, &argv) == TCL_OK) {
StdStringSet *set = new StdStringSet;
StringSet *set = new StringSet;
for (int i = 0; i < argc; i++) {
int length;
const char *str = Tcl_GetStringFromObj(argv[i], &length);

8
verilog/VerilogReader.cc
View File

@ -285,7 +285,7 @@ VerilogReader::makeCellPorts(Cell *cell,
VerilogModule *module,
VerilogNetSeq *ports)
{
StdStringSet port_names;
StringSet port_names;
for (VerilogNet *mod_port : *ports) {
const std::string &port_name = mod_port->name();
if (!port_names.contains(port_name)) {
@ -335,7 +335,7 @@ void
VerilogReader::makeNamedPortRefCellPorts(Cell *cell,
VerilogModule *module,
VerilogNet *mod_port,
StdStringSet &port_names)
StringSet &port_names)
{
PortSeq *member_ports = new PortSeq;
VerilogNetNameIterator *net_name_iter = mod_port->nameIterator(module,this);
@ -805,7 +805,7 @@ VerilogModule::~VerilogModule()
void
VerilogModule::parseStmts(VerilogReader *reader)
{
StdStringSet inst_names;
StringSet inst_names;
for (VerilogStmt *stmt : *stmts_) {
if (stmt->isDeclaration())
parseDcl(dynamic_cast<VerilogDcl*>(stmt), reader);
@ -861,7 +861,7 @@ VerilogModule::parseDcl(VerilogDcl *dcl,
// expansion so errors are only reported once.
void
VerilogModule::checkInstanceName(VerilogInst *inst,
StdStringSet &inst_names,
StringSet &inst_names,
VerilogReader *reader)
{
std::string inst_name = inst->instanceName();

2
verilog/VerilogReaderPvt.hh
View File

@ -75,7 +75,7 @@ public:
private:
void parseStmts(VerilogReader *reader);
void checkInstanceName(VerilogInst *inst,
StdStringSet &inst_names,
StringSet &inst_names,
VerilogReader *reader);
std::string name_;