luke
/
OpenSTA
mirror of https://github.com/The-OpenROAD-Project/OpenSTA.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Get the pin count from the Liberty cell not the Cell (#334) 

The Cell may come from LEF which doesn't have internal pins that
Liberty does.  This used to work by dumb luck where the extra two
power pins in LEF happened to align to the extra two internal pins
from Liberty.  With the change to pg_pins this no longer works.

Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
This commit is contained in:
Matt Liberty 2025-11-18 22:20:00 +00:00 committed by GitHub
parent c4b94c3ee5
commit 759348402d
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
verilog/VerilogReader.cc
View File

@ -534,7 +534,7 @@ VerilogReader::makeModuleInst(const string *module_vname,
// to reduce the memory footprint of the verilog parser.
if (liberty_cell
&& hasScalarNamedPortRefs(liberty_cell, pins)) {
int port_count = network_->portBitCount(cell);
const int port_count = liberty_cell->portBitCount();
StdStringSeq net_names(port_count);
for (VerilogNet *vnet : *pins) {
VerilogNetPortRefScalarNet *vpin =