test: harden module Tcl coverage tests

Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>

liberty/test/liberty_busport_mem_iter.ok

@@ -102,4 +102,3 @@ sky130_fd_sc_hd__ebufn_2/A dir=input func="" tri=""
 sky130_fd_sc_hd__ebufn_2/TE_B dir=input func="" tri=""
 sky130_fd_sc_hd__ebufn_2/Z dir=tristate func="A" tri="!TE_B"
 Warning 1171: ../../test/nangate45/fake_macros.lib line 32, default_max_transition is 0.0.
-Warning 1140: /workspace/sta/OpenSTA/liberty/test/results/liberty_busport_mem_iter_write.lib line 1, library fakeram45_64x7 already exists.

liberty/test/liberty_busport_mem_iter.tcl

@@ -1,6 +1,7 @@
 # Test bus port member iteration, bundle ports, port functions,
 # tristate enable, sequential queries, and diverse cell classification.
 source ../../test/helpers.tcl
+suppress_msg 1140
 
 ############################################################
 # Read SRAM macro library (has bus ports)

liberty/test/liberty_ecsm.ok

@@ -1,3 +1,5 @@
 ecsm cell count: 2
 ecsm cell: ECSM1
 ecsm cell: ECSM2
+ecsm timing max: ok
+ecsm timing min: ok

liberty/test/liberty_ecsm.tcl

@@ -40,3 +40,35 @@ foreach cell_name $cell_names {
     error "$cell_name has no timing arcs"
   }
 }
+
+# Verify ECSM-tagged library also participates in actual timing paths.
+read_verilog liberty_ecsm_test.v
+link_design liberty_ecsm_test
+
+create_clock -name clk -period 10 [get_ports clk]
+set_input_delay -clock clk 1.0 [get_ports in1]
+set_output_delay -clock clk 1.0 [get_ports out1]
+
+with_output_to_variable max_rep {
+  report_checks -path_delay max -from [get_ports in1] -to [get_ports out1]
+}
+if {![regexp {Startpoint:\s+in1} $max_rep]
+    || ![regexp {Endpoint:\s+out1} $max_rep]
+    || ![regexp {u1/} $max_rep]
+    || ![regexp {u2/} $max_rep]
+    || ![regexp {slack} $max_rep]} {
+  error "ECSM max timing report missing expected path content"
+}
+puts "ecsm timing max: ok"
+
+with_output_to_variable min_rep {
+  report_checks -path_delay min -from [get_ports in1] -to [get_ports out1]
+}
+if {![regexp {Startpoint:\s+in1} $min_rep]
+    || ![regexp {Endpoint:\s+out1} $min_rep]
+    || ![regexp {u1/} $min_rep]
+    || ![regexp {u2/} $min_rep]
+    || ![regexp {slack} $min_rep]} {
+  error "ECSM min timing report missing expected path content"
+}
+puts "ecsm timing min: ok"

liberty/test/liberty_ecsm_test.v

@@ -0,0 +1,19 @@
+module liberty_ecsm_test (
+  input clk,
+  input in1,
+  output out1
+);
+
+  wire n1;
+
+  ECSM1 u1 (
+    .A(in1),
+    .Z(n1)
+  );
+
+  ECSM2 u2 (
+    .A(n1),
+    .Z(out1)
+  );
+
+endmodule

liberty/test/liberty_pgpin_voltage.ok

@@ -162,7 +162,6 @@ Pad                  0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00   0.0%
 ------------------------------------------------------------------------
 Total                1.884780e-06 7.798150e-08 3.607567e-07 2.323518e-06 100.0%
                             81.1%         3.4%        15.5%
-Warning 1140: /workspace/sta/OpenSTA/liberty/test/results/liberty_pgpin_voltage_write.lib line 1, library sky130_fd_sc_hd__tt_025C_1v80 already exists.
 Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfbbn_1 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfbbn_1.
 Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfbbn_1 port IQ_N not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfbbn_1.
 Warning 1110: cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfbbn_2 port IQ not found in cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfbbn_2.

liberty/test/liberty_pgpin_voltage.tcl

@@ -1,5 +1,6 @@
 # Test pg_pin, voltage_map, supply voltage, and power group parsing.
 source ../../test/helpers.tcl
+suppress_msg 1140
 
 ############################################################
 # Read Sky130 library (has pg_pin, voltage_map extensively)

liberty/test/liberty_sky130_corners.ok

@@ -1,5 +1,3 @@
-Warning 1140: ../../test/sky130hd/sky130_fd_sc_hd__ff_n40C_1v95.lib line 1, library sky130_fd_sc_hd__ff_n40C_1v95 already exists.
-Warning 1140: ../../test/sky130hd/sky130_fd_sc_hd__ss_n40C_1v40.lib line 1, library sky130_fd_sc_hd__ss_n40C_1v40 already exists.
 --- Fast corner, max ---
 Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
 Endpoint: out1 (output port clocked by clk)

liberty/test/liberty_sky130_corners.tcl

@@ -1,5 +1,6 @@
 # Test multi-corner library reading and timing analysis with Sky130HD.
 source ../../test/helpers.tcl
+suppress_msg 1140
 
 ############################################################
 # Define corners and read Sky130HD libraries with explicit -max/-min views

liberty/test/liberty_writer.ok

@@ -31,4 +31,3 @@ Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_SLVT_FF_nldm_211120.lib.gz lin
 Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_SLVT_FF_nldm_211120.lib.gz line 14748, timing group from output port.
 Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_SLVT_FF_nldm_211120.lib.gz line 14781, timing group from output port.
 Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_SLVT_FF_nldm_211120.lib.gz line 14814, timing group from output port.
-Warning 1140: ../../test/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib line 1, library sky130_fd_sc_hd__tt_025C_1v80 already exists.

liberty/test/liberty_writer.tcl

@@ -1,6 +1,7 @@
 # Test liberty writer and advanced reading features for code coverage
 # Targets: LibertyWriter.cc, LibertyReader.cc (more paths), LibertyBuilder.cc
 source ../../test/helpers.tcl
+suppress_msg 1140
 
 proc assert_written_liberty {path lib_name} {
   if {![file exists $path]} {

network/test/network_namespace_escape.ok

@@ -106,7 +106,6 @@ Path Type: max
 
 
 --- Test 2: SDC namespace with hierarchical design ---
-Warning 1140: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
 sdc hier cells: 11
 sdc hier pins: 30
 sdc hier nets: 19
@@ -186,7 +185,6 @@ Path Type: max
 
 
 --- Test 3: path divider ---
-Warning 1140: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
 sub1/* pins (default divider): 3
 hier sub1/* pins: 3
 sub1 cell ref: sub_block

network/test/network_namespace_escape.tcl

@@ -13,6 +13,7 @@
 #   ParseBus.cc: parseBusName, isBusName, escapeChars
 
 source ../../test/helpers.tcl
+suppress_msg 1140
 
 read_liberty ../../test/nangate45/Nangate45_typ.lib
 

network/test/network_sdc_adapt_deep.ok

@@ -150,7 +150,6 @@ sdc deep pin sub1/buf_gate/Z: dir=output
 sdc deep pin sub2/and_gate/A1: dir=input
 sdc deep pin sub2/buf_gate/Z: dir=output
 --- Test 6: SDC with bus design ---
-Warning 1140: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
 sdc bus design ports: 11
 sdc data_in[*]: 4
 sdc data_out[*]: 4

network/test/network_sdc_adapt_deep.tcl

@@ -13,6 +13,7 @@
 #   VerilogNamespace.cc: staToVerilog, verilogToSta name conversion
 
 source ../../test/helpers.tcl
+suppress_msg 1140
 
 read_liberty ../../test/nangate45/Nangate45_typ.lib
 read_verilog network_hier_test.v

power/test/power_propagate.ok

@@ -1129,7 +1129,6 @@ Pad                    0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
 Total                  1.74e+06   1.64e+06   9.94e-10   3.38e+06 100.0%
                           51.5%      48.5%       0.0%
 --- Test 6: SAIF power ---
-Warning 1140: ../../test/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib line 1, library sky130_fd_sc_hd__tt_025C_1v80 already exists.
 Annotated 937 pin activities.
 Group                  Internal  Switching    Leakage      Total
                           Power      Power      Power      Power (Watts)
@@ -1153,7 +1152,6 @@ Total                  4.37e-04   1.37e-04   9.91e-10   5.74e-04 100.0%
 saif          937
 unannotated     0
 --- Test 7: power with defaults ---
-Warning 1140: ../../test/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib line 1, library sky130_fd_sc_hd__tt_025C_1v80 already exists.
 Group                  Internal  Switching    Leakage      Total
                           Power      Power      Power      Power (Watts)
 ----------------------------------------------------------------

power/test/power_propagate.tcl

@@ -1,5 +1,6 @@
 # Test power propagation, per-instance power breakdown, and activity querying.
 source ../../test/helpers.tcl
+suppress_msg 1140
 
 #---------------------------------------------------------------
 # Test 1: Power with GCD design and VCD - comprehensive

power/test/power_vcd_detailed.ok

@@ -3583,7 +3583,6 @@ Total                  3.48e+05   3.28e+05   9.94e-10   6.76e+05 100.0%
   }
 }
 --- Test 9: SAIF power ---
-Warning 1140: ../../test/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib line 1, library sky130_fd_sc_hd__tt_025C_1v80 already exists.
 Annotated 937 pin activities.
 saif          937
 unannotated     0

power/test/power_vcd_detailed.tcl

@@ -6,6 +6,7 @@
 #   SaifReader.cc (SAIF reading and activity annotation)
 
 source ../../test/helpers.tcl
+suppress_msg 1140
 
 #---------------------------------------------------------------
 # Test 1: VCD-based power with full reporting

search/test/search_register_filter_combos.ok

@@ -64,7 +64,6 @@ fall clock_pins: 0
 rise output_pins: 4
 --- latch: all_registers -fall_clock -output_pins ---
 fall output_pins: 0
-Warning 1140: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
 --- async: all_registers -async_pins ---
 async pins: 2
   reg1/RN

search/test/search_register_filter_combos.tcl

@@ -132,7 +132,8 @@ puts "fall output_pins: [llength $fall_op]"
 ############################################################
 # Part 2: Async reset DFF design - async pin queries
 ############################################################
-read_liberty ../../test/nangate45/Nangate45_typ.lib
+# Reuse the already-loaded Nangate library from Part 1 to avoid duplicate
+# library redefinition warnings in test output.
 read_verilog search_path_end_types.v
 link_design search_path_end_types
 

search/test/search_timing_model_deep.ok

@@ -3,7 +3,6 @@
 --- write_timing_model -library_name -cell_name ---
 --- write_timing_model -scene ---
 --- Read back generated model ---
-Warning 1140: /workspace/sta/OpenSTA/search/test/results/timing_model_deep1.lib line 1, library search_path_end_types already exists.
 --- min_period_violations ---
 min_period_violations: skipped (API removed)
 --- min_period_check_slack ---

search/test/search_timing_model_deep.tcl

@@ -9,6 +9,7 @@
 #          reportShort/Verbose for MinPeriod and MaxSkew,
 #          ClkSkew.cc ClkSkew copy, findClkSkew
 source ../../test/helpers.tcl
+suppress_msg 1140
 
 read_liberty ../../test/nangate45/Nangate45_typ.lib
 read_verilog search_path_end_types.v

verilog/test/verilog_bus_partselect.ok

@@ -106,7 +106,6 @@ No differences found.
 No differences found.
 No differences found.
 --- Test 4: roundtrip ---
-Warning 1140: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
 roundtrip cells: 38
 Startpoint: data_in[4] (input port clocked by clk)
 Endpoint: reg4 (rising edge-triggered flip-flop clocked by clk)

verilog/test/verilog_bus_partselect.tcl

@@ -3,6 +3,7 @@
 # and write_verilog roundtrip of bus designs.
 
 source ../../test/helpers.tcl
+suppress_msg 1140
 
 #---------------------------------------------------------------
 # Test 1: Read verilog with bus expressions

verilog/test/verilog_const_concat.ok

@@ -269,10 +269,8 @@ Instance reg4
   VDD power (unconnected)
   VSS ground (unconnected)
 --- Test 6: re-read same verilog ---
-Warning 1140: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
 re-read cells: 8
 re-read nets: 14
 --- Test 7: roundtrip ---
-Warning 1140: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
 roundtrip cells: 8
 roundtrip nets: 14

verilog/test/verilog_const_concat.tcl

@@ -1,6 +1,7 @@
 # Test verilog with net constants (1'b0, 1'b1), concatenation and part selects.
 
 source ../../test/helpers.tcl
+suppress_msg 1140
 
 #---------------------------------------------------------------
 # Test 1: Read verilog with constants

verilog/test/verilog_error_paths.ok

@@ -349,6 +349,5 @@ Instance reg3
   VDD power (unconnected)
   VSS ground (unconnected)
 --- Test 7: re-read ---
-Warning 1140: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
 re-read cells: 34
 re-read nets: 55

verilog/test/verilog_error_paths.tcl

@@ -12,6 +12,7 @@
 #     writePortDcls with bus ports
 
 source ../../test/helpers.tcl
+suppress_msg 1140
 
 #---------------------------------------------------------------
 # Test 1: Read hierarchical design with buses and assigns

verilog/test/verilog_escaped_write_bus.ok

@@ -5,7 +5,6 @@ ports: 11
 No differences found.
 No differences found.
 --- Test 2: roundtrip bus design ---
-Warning 1140: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
 roundtrip cells: 12
 roundtrip nets: 19
 roundtrip ports: 11

verilog/test/verilog_escaped_write_bus.tcl

@@ -1,6 +1,7 @@
 # Test 1: Write verilog for bus design (exercises bus wire declarations)
 # Test 2: Read back written bus verilog (roundtrip)
 source ../../test/helpers.tcl
+suppress_msg 1140
 
 #---------------------------------------------------------------
 # Test 1: Write verilog for bus design (exercises bus wire declarations)

verilog/test/verilog_escaped_write_complex.ok

@@ -1,6 +1,5 @@
 --- Test 3: write complex bus design ---
 --- roundtrip complex bus ---
-Warning 1140: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
 complex roundtrip cells: 28
 complex roundtrip ports: 27
 roundtrip data_a[*]: 8

verilog/test/verilog_escaped_write_complex.tcl

@@ -1,6 +1,7 @@
 # Test 3: Write complex bus design
 # Exercises: writeWireDcls with bus nets (isBusName, parseBusName)
 source ../../test/helpers.tcl
+suppress_msg 1140
 
 #---------------------------------------------------------------
 # Test 3: Write complex bus design

verilog/test/verilog_escaped_write_const.ok

@@ -1,4 +1,3 @@
 --- Test 6: write constant design ---
-Warning 1140: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
 const roundtrip cells: 8
 const roundtrip nets: 14

verilog/test/verilog_escaped_write_const.tcl

@@ -1,6 +1,7 @@
 # Test 6: Write constant/concat design
 # Exercises: writeChildren with constant pin connections
 source ../../test/helpers.tcl
+suppress_msg 1140
 
 proc assert_file_nonempty {path} {
   if {![file exists $path] || [file size $path] <= 0} {

verilog/test/verilog_escaped_write_hier.ok

@@ -1,5 +1,4 @@
 --- Test 4: write hierarchical design ---
-Warning 1140: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
 hier roundtrip cells: 7
 hier roundtrip nets: 11
 hier roundtrip ports: 6

verilog/test/verilog_escaped_write_hier.tcl

@@ -1,6 +1,7 @@
 # Test 4: Write hierarchical design
 # Exercises: findHierChildren, writeModule for sub-modules, sorted child output
 source ../../test/helpers.tcl
+suppress_msg 1140
 
 #---------------------------------------------------------------
 # Test 4: Write hierarchical design

verilog/test/verilog_gcd_large.ok

@@ -10,7 +10,6 @@ No differences found.
 No differences found.
 No differences found.
 --- Test 3: re-read ---
-Warning 1140: ../../test/sky130hd/sky130hd_tt.lib line 1, library sky130_fd_sc_hd__tt_025C_1v80 already exists.
 re-read cells: 1292
 --- Test 4: timing ---
 Warning 502: verilog_gcd_large.tcl line 1, report_checks -endpoint_count is deprecated. Use -endpoint_path_count instead.
@@ -713,7 +712,6 @@ Load pins
  _430_/D input (sky130_fd_sc_hd__dfxtp_2) 0.00-0.00
 
 --- Test 7: example1 ---
-Warning 1140: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
 Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
 Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
 Path Group: clk

verilog/test/verilog_gcd_large.tcl

@@ -14,6 +14,7 @@
 #   VerilogLex.ll: tokenization of larger file, bus brackets,
 #     escaped identifiers, string tokens
 source ../../test/helpers.tcl
+suppress_msg 1140
 
 ############################################################
 # Test 1: Read Sky130 library and GCD verilog

verilog/test/verilog_gcd_writer.ok

@@ -9,7 +9,6 @@ Warning 101: verilog_gcd_writer.tcl line 1, object 'sky130_fd_sc_hd__tt_025C_1v8
 No differences found.
 No differences found.
 --- Test 2: roundtrip ---
-Warning 1140: ../../test/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib line 1, library sky130_fd_sc_hd__tt_025C_1v80 already exists.
 roundtrip cells: 1292
 No differences found.
 --- Test 3: timing after roundtrip ---
@@ -138,6 +137,5 @@ No differences found.
 --- Test 5: additional write option ---
 No differences found.
 --- Test 6: modify then write ---
-Warning 1140: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
 No differences found.
 No differences found.

verilog/test/verilog_gcd_writer.tcl

@@ -2,6 +2,7 @@
 # unconnected pins, many cell types, power/ground nets).
 
 source ../../test/helpers.tcl
+suppress_msg 1140
 
 #---------------------------------------------------------------
 # Test 1: Write GCD sky130 with various options

verilog/test/verilog_hier_write.ok

@@ -17,7 +17,6 @@ No differences found.
 No differences found.
 --- Test 4: write_verilog -remove_cells ---
 --- Test 5: read back written verilog ---
-Warning 1140: ../../test/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib line 1, library sky130_fd_sc_hd__tt_025C_1v80 already exists.
 roundtrip cells: 1292
 roundtrip nets: 288
 roundtrip ports: 54

verilog/test/verilog_hier_write.tcl

@@ -6,6 +6,7 @@
 #   makeModuleInst, linkNetwork, various cell types, declaration handling)
 
 source ../../test/helpers.tcl
+suppress_msg 1140
 
 #---------------------------------------------------------------
 # Test 1: Read and write GCD sky130hd design (large design)

verilog/test/verilog_preproc_param.ok

@@ -324,5 +324,4 @@ Load pins
  reg3/D input (DFF_X1) 1.06-1.14
 
 --- Test 5: re-read ---
-Warning 1140: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
 re-read cells: 10

verilog/test/verilog_preproc_param.tcl

@@ -11,6 +11,7 @@
 #     makeModule, makeDcl, linkNetwork
 
 source ../../test/helpers.tcl
+suppress_msg 1140
 
 #---------------------------------------------------------------
 # Test 1: Read verilog with preprocessor/parameter constructs

verilog/test/verilog_remove_cells_basic.ok

@@ -12,9 +12,7 @@ No differences found.
 Warning 101: verilog_remove_cells_basic.tcl line 1, object 'NangateOpenCellLibrary/BUF_X1' not found.
 No differences found.
 --- Test 4: read back removed cells ---
-Warning 1140: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
 roundtrip (buf removed) cells: 2
-Warning 1140: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
 roundtrip basic cells: 2
 Startpoint: in1 (input port clocked by clk)
 Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)

verilog/test/verilog_remove_cells_basic.tcl

@@ -1,6 +1,7 @@
 # Test 1: Write with -remove_cells option (nangate45 design)
 # Test 4: Read back written file with removed cells
 source ../../test/helpers.tcl
+suppress_msg 1140
 
 #---------------------------------------------------------------
 # Test 1: Write with -remove_cells option (nangate45 design)

verilog/test/verilog_remove_cells_complex.ok

@@ -1,4 +1,3 @@
 --- Test 5: complex bus with removes ---
 No differences found.
 No differences found.
-Warning 1140: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.

verilog/test/verilog_remove_cells_complex.tcl

@@ -1,5 +1,6 @@
 # Test 5: Write and re-read complex bus design with removes
 source ../../test/helpers.tcl
+suppress_msg 1140
 
 proc assert_file_nonempty {path} {
   if {![file exists $path]} {

verilog/test/verilog_remove_cells_hier.ok

@@ -1,6 +1,5 @@
 --- Test 7: hierarchical with removes ---
 No differences found.
 No differences found.
-Warning 1140: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
 hier roundtrip cells: 5
 hier roundtrip hier cells: 7

verilog/test/verilog_remove_cells_hier.tcl

@@ -1,6 +1,7 @@
 # Test 7: Write hierarchical design with removes
 # Exercises: findHierChildren, writeChild remove path
 source ../../test/helpers.tcl
+suppress_msg 1140
 
 proc assert_file_nonempty {path} {
   if {![file exists $path]} {

verilog/test/verilog_remove_cells_multigate.ok

@@ -3,4 +3,3 @@ No differences found.
 No differences found.
 No differences found.
 No differences found.
-Warning 1140: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.

verilog/test/verilog_remove_cells_multigate.tcl

@@ -1,5 +1,6 @@
 # Test 2: Write with remove_cells for multi-gate design
 source ../../test/helpers.tcl
+suppress_msg 1140
 
 proc assert_file_nonempty {path} {
   if {![file exists $path]} {

verilog/test/verilog_remove_cells_reread.ok

@@ -1,7 +1,5 @@
 --- Test 3: multiple re-reads ---
 re-read cells: 2
 re-read nets: 4
-Warning 1140: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
 re-read2 cells: 2
-Warning 1140: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
 re-read3 bus cells: 12

verilog/test/verilog_remove_cells_reread.tcl

@@ -1,6 +1,7 @@
 # Test 3: Multiple re-reads of same file
 # Exercises: module re-definition paths in VerilogReader
 source ../../test/helpers.tcl
+suppress_msg 1140
 
 #---------------------------------------------------------------
 # Test 3: Multiple re-reads of same file

verilog/test/verilog_remove_cells_supply.ok

@@ -1,4 +1,3 @@
 --- Test 6: supply/tristate with removes ---
 No differences found.
 No differences found.
-Warning 1140: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.

verilog/test/verilog_remove_cells_supply.tcl

@@ -1,5 +1,6 @@
 # Test 6: Write assign/tristate design with removes
 source ../../test/helpers.tcl
+suppress_msg 1140
 
 proc assert_file_nonempty {path} {
   if {![file exists $path]} {

verilog/test/verilog_supply_tristate.ok

@@ -340,7 +340,6 @@ Instance reg3
   VSS ground (unconnected)
 --- Test 4: write_verilog ---
 --- Test 5: re-read verilog ---
-Warning 1140: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
 re-read cells: 12
 re-read nets: 25
 --- Test 6: fanin/fanout ---

verilog/test/verilog_supply_tristate.tcl

@@ -15,6 +15,7 @@
 #   writePortDcls with tristate direction
 
 source ../../test/helpers.tcl
+suppress_msg 1140
 
 #---------------------------------------------------------------
 # Test 1: Read verilog with supply0/supply1/tri

verilog/test/verilog_write_bus_types.tcl

@@ -17,6 +17,18 @@ proc assert_file_contains {path token} {
   }
 }
 
+proc assert_files_equal {path_a path_b} {
+  set in_a [open $path_a r]
+  set text_a [read $in_a]
+  close $in_a
+  set in_b [open $path_b r]
+  set text_b [read $in_b]
+  close $in_b
+  if {$text_a ne $text_b} {
+    error "expected identical files: $path_a vs $path_b"
+  }
+}
+
 read_liberty ../../test/nangate45/Nangate45_typ.lib
 read_verilog verilog_bus_test.v
 link_design verilog_bus_test
@@ -24,11 +36,13 @@ link_design verilog_bus_test
 set out1 [make_result_file verilog_write_bus_types.v]
 write_verilog $out1
 assert_file_nonempty $out1
-assert_file_contains $out1 "module verilog_bus_test"
-assert_file_contains $out1 "data_in[0]"
-assert_file_contains $out1 "data_out[3]"
+assert_files_equal verilog_bus_out.vok $out1
+assert_file_contains $out1 {input [3:0] data_in;}
+assert_file_contains $out1 {output [3:0] data_out;}
+assert_file_contains $out1 {.A(data_in[0])}
+assert_file_contains $out1 {.Q(data_out[3])}
 
 set out2 [make_result_file verilog_write_bus_types_pwr.v]
 write_verilog -include_pwr_gnd $out2
 assert_file_nonempty $out2
-assert_file_contains $out2 "module verilog_bus_test"
+assert_files_equal $out1 $out2

verilog/test/verilog_write_complex_bus_types.tcl

@@ -17,6 +17,18 @@ proc assert_file_contains {path token} {
   }
 }
 
+proc assert_files_equal {path_a path_b} {
+  set in_a [open $path_a r]
+  set text_a [read $in_a]
+  close $in_a
+  set in_b [open $path_b r]
+  set text_b [read $in_b]
+  close $in_b
+  if {$text_a ne $text_b} {
+    error "expected identical files: $path_a vs $path_b"
+  }
+}
+
 read_liberty ../../test/nangate45/Nangate45_typ.lib
 read_verilog verilog_complex_bus_test.v
 link_design verilog_complex_bus_test
@@ -24,11 +36,13 @@ link_design verilog_complex_bus_test
 set out1 [make_result_file verilog_write_complex_bus_types.v]
 write_verilog $out1
 assert_file_nonempty $out1
-assert_file_contains $out1 "module verilog_complex_bus_test"
-assert_file_contains $out1 "data_a[7]"
-assert_file_contains $out1 "result[0]"
+assert_files_equal verilog_complex_bus_out.vok $out1
+assert_file_contains $out1 {input [7:0] data_a;}
+assert_file_contains $out1 {output [7:0] result;}
+assert_file_contains $out1 {.A(data_a[7])}
+assert_file_contains $out1 {.Q(result[0])}
 
 set out2 [make_result_file verilog_write_complex_bus_types_pwr.v]
 write_verilog -include_pwr_gnd $out2
 assert_file_nonempty $out2
-assert_file_contains $out2 "module verilog_complex_bus_test"
+assert_files_equal $out1 $out2