mirror of
https://github.com/The-OpenROAD-Project/OpenSTA.git
synced 2026-09-07 11:51:47 +02:00
Jaehyun Kim
@@ -0,0 +1,281 @@
|
||||
add_test(
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NAME tcl.sdc.constraints
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||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_constraints
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||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
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||||
set_tests_properties(tcl.sdc.constraints PROPERTIES LABELS "tcl;module_sdc")
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||||
|
||||
add_test(
|
||||
NAME tcl.sdc.clocks
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_clocks
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||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.sdc.clocks PROPERTIES LABELS "tcl;module_sdc")
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||||
|
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add_test(
|
||||
NAME tcl.sdc.exceptions
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||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_exceptions
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||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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||||
)
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||||
set_tests_properties(tcl.sdc.exceptions PROPERTIES LABELS "tcl;module_sdc")
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||||
|
||||
add_test(
|
||||
NAME tcl.sdc.environment
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_environment
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||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
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||||
set_tests_properties(tcl.sdc.environment PROPERTIES LABELS "tcl;module_sdc")
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||||
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||||
add_test(
|
||||
NAME tcl.sdc.write_read
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||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_write_read
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||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
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||||
set_tests_properties(tcl.sdc.write_read PROPERTIES LABELS "tcl;module_sdc")
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||||
add_test(
|
||||
NAME tcl.sdc.write_comprehensive
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_write_comprehensive
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
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||||
set_tests_properties(tcl.sdc.write_comprehensive PROPERTIES LABELS "tcl;module_sdc")
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||||
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add_test(
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NAME tcl.sdc.variables
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||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_variables
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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||||
)
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||||
set_tests_properties(tcl.sdc.variables PROPERTIES LABELS "tcl;module_sdc")
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||||
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add_test(
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NAME tcl.sdc.advanced
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_advanced
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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||||
)
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set_tests_properties(tcl.sdc.advanced PROPERTIES LABELS "tcl;module_sdc")
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add_test(
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NAME tcl.sdc.write_options
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_write_options
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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||||
)
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||||
set_tests_properties(tcl.sdc.write_options PROPERTIES LABELS "tcl;module_sdc")
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add_test(
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NAME tcl.sdc.genclk_advanced
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_genclk_advanced
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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||||
)
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set_tests_properties(tcl.sdc.genclk_advanced PROPERTIES LABELS "tcl;module_sdc")
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add_test(
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NAME tcl.sdc.exception_advanced
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_exception_advanced
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.sdc.exception_advanced PROPERTIES LABELS "tcl;module_sdc")
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add_test(
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NAME tcl.sdc.port_delay_advanced
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_port_delay_advanced
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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||||
)
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set_tests_properties(tcl.sdc.port_delay_advanced PROPERTIES LABELS "tcl;module_sdc")
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add_test(
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NAME tcl.sdc.clock_groups_sense
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_clock_groups_sense
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.sdc.clock_groups_sense PROPERTIES LABELS "tcl;module_sdc")
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add_test(
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NAME tcl.sdc.disable_case
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_disable_case
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.sdc.disable_case PROPERTIES LABELS "tcl;module_sdc")
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add_test(
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NAME tcl.sdc.removal_reset
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_removal_reset
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.sdc.removal_reset PROPERTIES LABELS "tcl;module_sdc")
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add_test(
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NAME tcl.sdc.write_roundtrip
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_write_roundtrip
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.sdc.write_roundtrip PROPERTIES LABELS "tcl;module_sdc")
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add_test(
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NAME tcl.sdc.net_wire_voltage
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_net_wire_voltage
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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||||
)
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set_tests_properties(tcl.sdc.net_wire_voltage PROPERTIES LABELS "tcl;module_sdc")
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add_test(
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NAME tcl.sdc.exception_merge_priority
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_exception_merge_priority
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.sdc.exception_merge_priority PROPERTIES LABELS "tcl;module_sdc")
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add_test(
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NAME tcl.sdc.clock_operations
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_clock_operations
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.sdc.clock_operations PROPERTIES LABELS "tcl;module_sdc")
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add_test(
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NAME tcl.sdc.design_rules_limits
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_design_rules_limits
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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||||
)
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set_tests_properties(tcl.sdc.design_rules_limits PROPERTIES LABELS "tcl;module_sdc")
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add_test(
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NAME tcl.sdc.drive_input_pvt
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_drive_input_pvt
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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||||
)
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set_tests_properties(tcl.sdc.drive_input_pvt PROPERTIES LABELS "tcl;module_sdc")
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add_test(
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NAME tcl.sdc.filter_query
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_filter_query
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.sdc.filter_query PROPERTIES LABELS "tcl;module_sdc")
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add_test(
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NAME tcl.sdc.derate_disable_deep
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||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_derate_disable_deep
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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||||
)
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set_tests_properties(tcl.sdc.derate_disable_deep PROPERTIES LABELS "tcl;module_sdc")
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add_test(
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NAME tcl.sdc.exception_thru_net
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||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_exception_thru_net
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||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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||||
)
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||||
set_tests_properties(tcl.sdc.exception_thru_net PROPERTIES LABELS "tcl;module_sdc")
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add_test(
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NAME tcl.sdc.delay_borrow_group
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||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_delay_borrow_group
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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||||
)
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set_tests_properties(tcl.sdc.delay_borrow_group PROPERTIES LABELS "tcl;module_sdc")
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add_test(
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NAME tcl.sdc.sense_unset_override
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||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_sense_unset_override
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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||||
)
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||||
set_tests_properties(tcl.sdc.sense_unset_override PROPERTIES LABELS "tcl;module_sdc")
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||||
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||||
add_test(
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NAME tcl.sdc.exception_intersect
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||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_exception_intersect
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||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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||||
)
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||||
set_tests_properties(tcl.sdc.exception_intersect PROPERTIES LABELS "tcl;module_sdc")
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||||
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||||
add_test(
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||||
NAME tcl.sdc.remove_clock_gating
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||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_remove_clock_gating
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||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
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||||
set_tests_properties(tcl.sdc.remove_clock_gating PROPERTIES LABELS "tcl;module_sdc")
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||||
add_test(
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||||
NAME tcl.sdc.exception_override_priority
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||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_exception_override_priority
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||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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||||
)
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||||
set_tests_properties(tcl.sdc.exception_override_priority PROPERTIES LABELS "tcl;module_sdc")
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add_test(
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NAME tcl.sdc.write_disabled_groups
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||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_write_disabled_groups
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||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
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||||
set_tests_properties(tcl.sdc.write_disabled_groups PROPERTIES LABELS "tcl;module_sdc")
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||||
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||||
add_test(
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||||
NAME tcl.sdc.clock_removal_cascade
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||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_clock_removal_cascade
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||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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||||
)
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||||
set_tests_properties(tcl.sdc.clock_removal_cascade PROPERTIES LABELS "tcl;module_sdc")
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||||
add_test(
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||||
NAME tcl.sdc.exception_thru_complex
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||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_exception_thru_complex
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||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
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||||
set_tests_properties(tcl.sdc.exception_thru_complex PROPERTIES LABELS "tcl;module_sdc")
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||||
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||||
add_test(
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||||
NAME tcl.sdc.capacitance_propagated
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||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_capacitance_propagated
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||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.sdc.capacitance_propagated PROPERTIES LABELS "tcl;module_sdc")
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||||
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||||
add_test(
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||||
NAME tcl.sdc.write_roundtrip_full
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_write_roundtrip_full
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
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||||
set_tests_properties(tcl.sdc.write_roundtrip_full PROPERTIES LABELS "tcl;module_sdc")
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||||
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||||
add_test(
|
||||
NAME tcl.sdc.cycle_acct_clk_relationships
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_cycle_acct_clk_relationships
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.sdc.cycle_acct_clk_relationships PROPERTIES LABELS "tcl;module_sdc")
|
||||
|
||||
add_test(
|
||||
NAME tcl.sdc.leaf_pin_filter_removal
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_leaf_pin_filter_removal
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||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.sdc.leaf_pin_filter_removal PROPERTIES LABELS "tcl;module_sdc")
|
||||
|
||||
add_test(
|
||||
NAME tcl.sdc.exception_rise_fall_transitions
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_exception_rise_fall_transitions
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.sdc.exception_rise_fall_transitions PROPERTIES LABELS "tcl;module_sdc")
|
||||
|
||||
add_test(
|
||||
NAME tcl.sdc.cycle_acct_genclk
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_cycle_acct_genclk
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.sdc.cycle_acct_genclk PROPERTIES LABELS "tcl;module_sdc")
|
||||
|
||||
add_test(
|
||||
NAME tcl.sdc.exception_thru_override
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_exception_thru_override
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.sdc.exception_thru_override PROPERTIES LABELS "tcl;module_sdc")
|
||||
|
||||
add_test(
|
||||
NAME tcl.sdc.exception_match_filter
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_exception_match_filter
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.sdc.exception_match_filter PROPERTIES LABELS "tcl;module_sdc")
|
||||
|
||||
add_subdirectory(cpp)
|
||||
@@ -0,0 +1,16 @@
|
||||
add_executable(TestSdc TestSdc.cc)
|
||||
target_link_libraries(TestSdc
|
||||
OpenSTA
|
||||
GTest::gtest
|
||||
GTest::gtest_main
|
||||
${TCL_LIBRARY}
|
||||
)
|
||||
target_include_directories(TestSdc PRIVATE
|
||||
${STA_HOME}/include/sta
|
||||
${STA_HOME}
|
||||
${CMAKE_BINARY_DIR}/include/sta
|
||||
)
|
||||
gtest_discover_tests(TestSdc
|
||||
WORKING_DIRECTORY ${STA_HOME}
|
||||
PROPERTIES LABELS "cpp;module_sdc"
|
||||
)
|
||||
+10327
File diff suppressed because it is too large
Load Diff
Symlink
+1
@@ -0,0 +1 @@
|
||||
../../test/regression
|
||||
@@ -0,0 +1,237 @@
|
||||
PASS: basic setup
|
||||
PASS: global timing derate
|
||||
PASS: rise/fall timing derate
|
||||
PASS: data path derate
|
||||
PASS: clock path derate
|
||||
PASS: cell_delay derate
|
||||
PASS: net_delay derate
|
||||
PASS: cell-specific derate
|
||||
PASS: instance-specific derate
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.09 0.09 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.09 ^ out1 (out)
|
||||
0.09 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.09 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.91 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks after derate
|
||||
PASS: unset_timing_derate
|
||||
PASS: disable timing instance buf1
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: report after disable buf1
|
||||
PASS: unset_disable_timing buf1
|
||||
PASS: disable timing pin buf1/A
|
||||
PASS: unset disable pin buf1/A
|
||||
PASS: disable lib cell from/to
|
||||
PASS: unset disable lib cell from/to
|
||||
PASS: disable lib cell all arcs
|
||||
PASS: unset disable lib cell all arcs
|
||||
PASS: set_driving_cell BUF_X1
|
||||
PASS: set_driving_cell INV_X1 -pin ZN
|
||||
PASS: set_driving_cell -rise
|
||||
PASS: set_driving_cell -fall
|
||||
PASS: set_drive 100
|
||||
PASS: set_drive -rise 80
|
||||
PASS: set_drive -fall 120
|
||||
PASS: set_drive 0 (ideal)
|
||||
PASS: input transitions
|
||||
PASS: clock insertion (source latency)
|
||||
PASS: clock insertion -rise -max
|
||||
PASS: clock insertion -fall -min
|
||||
PASS: clock insertion -rise -min
|
||||
PASS: clock insertion -fall -max
|
||||
PASS: clock insertion -early
|
||||
PASS: clock insertion -late
|
||||
PASS: source latency with all corners
|
||||
PASS: network latency with all corners
|
||||
PASS: set_load various options
|
||||
PASS: set_resistance
|
||||
PASS: clock gating check on clock
|
||||
Warning: sdc_advanced.tcl line 1, object 'sdc_test2' not found.
|
||||
Warning: sdc_advanced.tcl line 1, object 'sdc_test2' not found.
|
||||
PASS: clock gating check on design
|
||||
PASS: set_max_time_borrow clock
|
||||
PASS: set_max_time_borrow pin
|
||||
PASS: set_data_check -setup
|
||||
PASS: set_data_check -hold
|
||||
PASS: set_ideal_network
|
||||
PASS: set_ideal_transition
|
||||
PASS: set_wire_load_mode top
|
||||
PASS: set_wire_load_mode enclosed
|
||||
PASS: set_wire_load_mode segmented
|
||||
PASS: set_wire_load_model 1K
|
||||
PASS: set_wire_load_model 5K
|
||||
PASS: set_min_pulse_width clock
|
||||
PASS: set_min_pulse_width -high
|
||||
PASS: set_min_pulse_width -low
|
||||
Startpoint: in1 (input port clocked by clk1)
|
||||
Endpoint: reg2 (falling edge-triggered data to data check clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
1.00 1.00 clock network delay (ideal)
|
||||
2.00 3.00 v input external delay
|
||||
0.00 3.00 v in1 (in)
|
||||
0.03 3.03 v buf1/Z (BUF_X1)
|
||||
0.05 3.08 v or1/ZN (OR2_X1)
|
||||
0.03 3.10 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 3.10 ^ reg2/D (DFF_X1)
|
||||
3.10 data arrival time
|
||||
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.20 0.20 clock network delay (propagated)
|
||||
0.00 0.20 clock reconvergence pessimism
|
||||
0.20 ^ reg1/CK (DFF_X1)
|
||||
0.28 0.48 v reg1/Q (DFF_X1)
|
||||
-0.50 -0.02 data check setup time
|
||||
-0.02 data required time
|
||||
---------------------------------------------------------
|
||||
-0.02 data required time
|
||||
-3.10 data arrival time
|
||||
---------------------------------------------------------
|
||||
-3.13 slack (VIOLATED)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
1.00 11.00 clock network delay (ideal)
|
||||
0.00 11.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 11.08 v reg1/Q (DFF_X1)
|
||||
0.00 11.08 v reg3/D (DFF_X1)
|
||||
11.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.30 20.30 clock network delay (ideal)
|
||||
0.00 20.30 clock reconvergence pessimism
|
||||
20.30 ^ reg3/CK (DFF_X1)
|
||||
-0.04 20.26 library setup time
|
||||
20.26 data required time
|
||||
---------------------------------------------------------
|
||||
20.26 data required time
|
||||
-11.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.18 slack (MET)
|
||||
|
||||
|
||||
PASS: final report_checks
|
||||
max slew
|
||||
|
||||
Pin Limit Slew Slack
|
||||
------------------------------------------------------------
|
||||
nor1/ZN 0.20 0.01 0.18 (MET)
|
||||
|
||||
max capacitance
|
||||
|
||||
Pin Limit Cap Slack
|
||||
------------------------------------------------------------
|
||||
nor1/ZN 26.70 1.45 25.25 (MET)
|
||||
|
||||
PASS: report_check_types
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,295 @@
|
||||
# Test advanced SDC commands for code coverage
|
||||
# Targets: DeratingFactors.cc, DisabledPorts.cc, InputDrive.cc,
|
||||
# ClockInsertion.cc, ClockLatency.cc, Sdc.cc, DataCheck.cc
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
# Setup clocks
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in2]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in3]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 3.0 [get_ports out2]
|
||||
puts "PASS: basic setup"
|
||||
|
||||
############################################################
|
||||
# Timing derate - comprehensive (DeratingFactors.cc)
|
||||
############################################################
|
||||
|
||||
# Global early/late
|
||||
set_timing_derate -early 0.95
|
||||
set_timing_derate -late 1.05
|
||||
puts "PASS: global timing derate"
|
||||
|
||||
# Rise/fall derate
|
||||
set_timing_derate -early -rise 0.96
|
||||
set_timing_derate -late -fall 1.04
|
||||
puts "PASS: rise/fall timing derate"
|
||||
|
||||
# Data path derate
|
||||
set_timing_derate -early -data 0.94
|
||||
set_timing_derate -late -data 1.06
|
||||
puts "PASS: data path derate"
|
||||
|
||||
# Clock path derate
|
||||
set_timing_derate -early -clock 0.97
|
||||
set_timing_derate -late -clock 1.03
|
||||
puts "PASS: clock path derate"
|
||||
|
||||
# Cell type derate
|
||||
set_timing_derate -early -cell_delay 0.93
|
||||
set_timing_derate -late -cell_delay 1.07
|
||||
puts "PASS: cell_delay derate"
|
||||
|
||||
set_timing_derate -early -net_delay 0.92
|
||||
set_timing_derate -late -net_delay 1.08
|
||||
puts "PASS: net_delay derate"
|
||||
|
||||
# Cell-specific derate (value first, then object)
|
||||
set_timing_derate -early -cell_delay 0.91 [get_lib_cells NangateOpenCellLibrary/INV_X1]
|
||||
set_timing_derate -late -cell_delay 1.09 [get_lib_cells NangateOpenCellLibrary/INV_X1]
|
||||
puts "PASS: cell-specific derate"
|
||||
|
||||
# Instance-specific derate
|
||||
set_timing_derate -early -cell_delay 0.90 [get_cells buf1]
|
||||
set_timing_derate -late -cell_delay 1.10 [get_cells buf1]
|
||||
puts "PASS: instance-specific derate"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report_checks after derate"
|
||||
|
||||
# Unset all derating
|
||||
unset_timing_derate
|
||||
puts "PASS: unset_timing_derate"
|
||||
|
||||
############################################################
|
||||
# Disable timing - comprehensive (DisabledPorts.cc, Sdc.cc)
|
||||
############################################################
|
||||
|
||||
# Disable timing on instance
|
||||
set_disable_timing [get_cells buf1]
|
||||
puts "PASS: disable timing instance buf1"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report after disable buf1"
|
||||
|
||||
unset_disable_timing [get_cells buf1]
|
||||
puts "PASS: unset_disable_timing buf1"
|
||||
|
||||
# Disable on pin
|
||||
set_disable_timing [get_pins buf1/A]
|
||||
puts "PASS: disable timing pin buf1/A"
|
||||
|
||||
unset_disable_timing [get_pins buf1/A]
|
||||
puts "PASS: unset disable pin buf1/A"
|
||||
|
||||
# Disable on lib cell from/to
|
||||
set_disable_timing [get_lib_cells NangateOpenCellLibrary/BUF_X1] -from A -to Z
|
||||
puts "PASS: disable lib cell from/to"
|
||||
|
||||
unset_disable_timing [get_lib_cells NangateOpenCellLibrary/BUF_X1] -from A -to Z
|
||||
puts "PASS: unset disable lib cell from/to"
|
||||
|
||||
# Disable on lib cell (all arcs)
|
||||
set_disable_timing [get_lib_cells NangateOpenCellLibrary/INV_X1]
|
||||
puts "PASS: disable lib cell all arcs"
|
||||
|
||||
unset_disable_timing [get_lib_cells NangateOpenCellLibrary/INV_X1]
|
||||
puts "PASS: unset disable lib cell all arcs"
|
||||
|
||||
############################################################
|
||||
# Input drive - comprehensive (InputDrive.cc)
|
||||
############################################################
|
||||
|
||||
# set_driving_cell with various options
|
||||
set_driving_cell -lib_cell BUF_X1 [get_ports in1]
|
||||
puts "PASS: set_driving_cell BUF_X1"
|
||||
|
||||
set_driving_cell -lib_cell INV_X1 -pin ZN [get_ports in2]
|
||||
puts "PASS: set_driving_cell INV_X1 -pin ZN"
|
||||
|
||||
set_driving_cell -lib_cell BUF_X4 -rise [get_ports in3]
|
||||
puts "PASS: set_driving_cell -rise"
|
||||
|
||||
set_driving_cell -lib_cell BUF_X2 -fall [get_ports in3]
|
||||
puts "PASS: set_driving_cell -fall"
|
||||
|
||||
# set_drive (resistance-based drive)
|
||||
set_drive 100 [get_ports in1]
|
||||
puts "PASS: set_drive 100"
|
||||
|
||||
set_drive -rise 80 [get_ports in2]
|
||||
puts "PASS: set_drive -rise 80"
|
||||
|
||||
set_drive -fall 120 [get_ports in2]
|
||||
puts "PASS: set_drive -fall 120"
|
||||
|
||||
set_drive 0 [get_ports in1]
|
||||
puts "PASS: set_drive 0 (ideal)"
|
||||
|
||||
# Input transition
|
||||
set_input_transition 0.15 [get_ports in1]
|
||||
set_input_transition -rise -max 0.12 [get_ports in2]
|
||||
set_input_transition -fall -min 0.08 [get_ports in2]
|
||||
set_input_transition -rise -min 0.06 [get_ports in3]
|
||||
set_input_transition -fall -max 0.18 [get_ports in3]
|
||||
puts "PASS: input transitions"
|
||||
|
||||
############################################################
|
||||
# Clock insertion delay (ClockInsertion.cc) via set_clock_latency -source
|
||||
############################################################
|
||||
|
||||
# set_clock_latency -source exercises ClockInsertion.cc
|
||||
set_clock_latency -source 0.5 [get_clocks clk1]
|
||||
puts "PASS: clock insertion (source latency)"
|
||||
|
||||
set_clock_latency -source -rise -max 0.6 [get_clocks clk1]
|
||||
puts "PASS: clock insertion -rise -max"
|
||||
|
||||
set_clock_latency -source -fall -min 0.3 [get_clocks clk1]
|
||||
puts "PASS: clock insertion -fall -min"
|
||||
|
||||
set_clock_latency -source -rise -min 0.2 [get_clocks clk1]
|
||||
puts "PASS: clock insertion -rise -min"
|
||||
|
||||
set_clock_latency -source -fall -max 0.7 [get_clocks clk1]
|
||||
puts "PASS: clock insertion -fall -max"
|
||||
|
||||
# Source latency with -early/-late
|
||||
set_clock_latency -source -early 0.4 [get_clocks clk2]
|
||||
puts "PASS: clock insertion -early"
|
||||
|
||||
set_clock_latency -source -late 0.6 [get_clocks clk2]
|
||||
puts "PASS: clock insertion -late"
|
||||
|
||||
############################################################
|
||||
# Clock latency with more options (ClockLatency.cc)
|
||||
############################################################
|
||||
|
||||
set_clock_latency -source 0.5 [get_clocks clk2]
|
||||
set_clock_latency -source -rise -min 0.3 [get_clocks clk2]
|
||||
set_clock_latency -source -rise -max 0.7 [get_clocks clk2]
|
||||
set_clock_latency -source -fall -min 0.2 [get_clocks clk2]
|
||||
set_clock_latency -source -fall -max 0.6 [get_clocks clk2]
|
||||
puts "PASS: source latency with all corners"
|
||||
|
||||
set_clock_latency 0.3 [get_clocks clk1]
|
||||
set_clock_latency -rise -min 0.2 [get_clocks clk1]
|
||||
set_clock_latency -rise -max 0.4 [get_clocks clk1]
|
||||
set_clock_latency -fall -min 0.1 [get_clocks clk1]
|
||||
set_clock_latency -fall -max 0.5 [get_clocks clk1]
|
||||
puts "PASS: network latency with all corners"
|
||||
|
||||
############################################################
|
||||
# Port external capacitance (PortExtCap.cc)
|
||||
############################################################
|
||||
|
||||
set_load 0.05 [get_ports out1]
|
||||
set_load -pin_load 0.03 [get_ports out2]
|
||||
set_load -wire_load 0.02 [get_ports out1]
|
||||
set_load -min 0.01 [get_ports out1]
|
||||
set_load -max 0.06 [get_ports out1]
|
||||
puts "PASS: set_load various options"
|
||||
|
||||
############################################################
|
||||
# Net resistance / capacitance (Sdc.cc)
|
||||
############################################################
|
||||
|
||||
set_resistance -min 10.0 [get_nets n1]
|
||||
set_resistance -max 20.0 [get_nets n1]
|
||||
puts "PASS: set_resistance"
|
||||
|
||||
############################################################
|
||||
# Clock gating check (Sdc.cc)
|
||||
############################################################
|
||||
|
||||
set_clock_gating_check -setup 0.5 [get_clocks clk1]
|
||||
set_clock_gating_check -hold 0.3 [get_clocks clk1]
|
||||
puts "PASS: clock gating check on clock"
|
||||
|
||||
set_clock_gating_check -setup 0.4 [current_design]
|
||||
set_clock_gating_check -hold 0.2 [current_design]
|
||||
puts "PASS: clock gating check on design"
|
||||
|
||||
############################################################
|
||||
# Latch borrow limit
|
||||
############################################################
|
||||
|
||||
set_max_time_borrow 2.0 [get_clocks clk1]
|
||||
puts "PASS: set_max_time_borrow clock"
|
||||
|
||||
set_max_time_borrow 1.5 [get_pins reg1/D]
|
||||
puts "PASS: set_max_time_borrow pin"
|
||||
|
||||
############################################################
|
||||
# Data check
|
||||
############################################################
|
||||
|
||||
catch {
|
||||
set_data_check -from [get_pins reg1/Q] -to [get_pins reg2/D] -setup 0.5
|
||||
puts "PASS: set_data_check -setup"
|
||||
}
|
||||
|
||||
catch {
|
||||
set_data_check -from [get_pins reg1/Q] -to [get_pins reg2/D] -hold 0.3
|
||||
puts "PASS: set_data_check -hold"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# set_ideal_network / set_ideal_transition
|
||||
############################################################
|
||||
|
||||
set_ideal_network [get_ports clk1]
|
||||
puts "PASS: set_ideal_network"
|
||||
|
||||
catch {
|
||||
set_ideal_transition 0.0 [get_ports clk1]
|
||||
puts "PASS: set_ideal_transition"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Wire load mode (various modes)
|
||||
############################################################
|
||||
|
||||
set_wire_load_mode top
|
||||
puts "PASS: set_wire_load_mode top"
|
||||
|
||||
set_wire_load_mode enclosed
|
||||
puts "PASS: set_wire_load_mode enclosed"
|
||||
|
||||
set_wire_load_mode segmented
|
||||
puts "PASS: set_wire_load_mode segmented"
|
||||
|
||||
set_wire_load_model -name "1K_hvratio_1_1"
|
||||
puts "PASS: set_wire_load_model 1K"
|
||||
|
||||
set_wire_load_model -name "5K_hvratio_1_1"
|
||||
puts "PASS: set_wire_load_model 5K"
|
||||
|
||||
############################################################
|
||||
# Min pulse width (Sdc.cc)
|
||||
############################################################
|
||||
|
||||
set_min_pulse_width 0.8 [get_clocks clk1]
|
||||
puts "PASS: set_min_pulse_width clock"
|
||||
|
||||
set_min_pulse_width -high 0.5 [get_clocks clk1]
|
||||
puts "PASS: set_min_pulse_width -high"
|
||||
|
||||
set_min_pulse_width -low 0.4 [get_clocks clk1]
|
||||
puts "PASS: set_min_pulse_width -low"
|
||||
|
||||
############################################################
|
||||
# Final report
|
||||
############################################################
|
||||
|
||||
report_checks
|
||||
puts "PASS: final report_checks"
|
||||
|
||||
report_check_types -max_capacitance -max_slew -max_fanout
|
||||
puts "PASS: report_check_types"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,150 @@
|
||||
PASS: setup
|
||||
PASS: set_load basic
|
||||
PASS: set_load -pin_load
|
||||
PASS: set_load -wire_load
|
||||
PASS: set_load out2 pin
|
||||
PASS: set_load rise/fall
|
||||
PASS: set_load wire rise/fall
|
||||
PASS: set_load min/max
|
||||
PASS: set_load pin min/max
|
||||
PASS: port fanout
|
||||
PASS: set_load on nets
|
||||
PASS: max_capacitance design
|
||||
PASS: max_capacitance ports
|
||||
PASS: min_capacitance ports
|
||||
PASS: max_capacitance pin
|
||||
PASS: max_transition
|
||||
PASS: max_fanout
|
||||
PASS: max_area
|
||||
PASS: write_sdc with loads
|
||||
PASS: set_propagated_clock clk1
|
||||
PASS: set_propagated_clock port clk2
|
||||
PASS: write_sdc with propagated
|
||||
PASS: unset_propagated_clock clk1
|
||||
PASS: unset_propagated_clock port clk2
|
||||
PASS: write_sdc after unset propagated
|
||||
PASS: case_analysis 0
|
||||
PASS: case_analysis 1
|
||||
PASS: case_analysis rising
|
||||
PASS: write_sdc with case analysis
|
||||
PASS: unset case_analysis in1
|
||||
PASS: unset case_analysis in2
|
||||
PASS: unset case_analysis in3
|
||||
PASS: case_analysis falling
|
||||
PASS: write_sdc with falling
|
||||
PASS: unset falling
|
||||
PASS: logic values
|
||||
PASS: write_sdc with logic values
|
||||
PASS: read_sdc
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: report after read
|
||||
PASS: write_sdc roundtrip
|
||||
PASS: read_sdc propagated
|
||||
PASS: write_sdc compatible roundtrip
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (propagated)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (propagated)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (propagated)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: final report
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,242 @@
|
||||
# Test port external capacitance, set_load with rise/fall/min/max/corner,
|
||||
# capacitance limits on cell/port/pin, propagated clock set/unset,
|
||||
# and unset_case_analysis from various pin states.
|
||||
# Targets:
|
||||
# Sdc.cc: setPortExtPinCap, setPortExtWireCap, portExtCap (all overloads),
|
||||
# hasPortExtCap, portExtFanout, ensurePortExtPinCap,
|
||||
# setCapacitanceLimit(Cell/Port/Pin), capacitanceLimit(Port/Pin),
|
||||
# setPropagatedClock, removePropagatedClock (clock and pin),
|
||||
# removeCaseAnalysis, setCaseAnalysis (all 4 values),
|
||||
# unsetCaseAnalysis, setLogicValue,
|
||||
# setPortExtFanout, portExtFanout (int overload),
|
||||
# connectedPinCap (via set_load -subtract_pin_load),
|
||||
# findLeafLoadPins, findLeafDriverPins (via input_delay on ports)
|
||||
# WriteSdc.cc: writePortLoads (pin/wire/fanout writing),
|
||||
# writeCaseAnalysis (all values), writeConstants,
|
||||
# writePropagatedClkPins, writeCapacitanceLimits
|
||||
# PortExtCap.cc: pinCap, wireCap, fanout methods
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 -waveform {0 10} [get_ports clk2]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in2]
|
||||
set_input_delay -clock clk2 2.0 [get_ports in3]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 3.0 [get_ports out2]
|
||||
puts "PASS: setup"
|
||||
|
||||
############################################################
|
||||
# Test 1: set_load - basic pin and wire loads
|
||||
############################################################
|
||||
set_load 0.05 [get_ports out1]
|
||||
puts "PASS: set_load basic"
|
||||
|
||||
set_load -pin_load 0.04 [get_ports out1]
|
||||
puts "PASS: set_load -pin_load"
|
||||
|
||||
set_load -wire_load 0.02 [get_ports out1]
|
||||
puts "PASS: set_load -wire_load"
|
||||
|
||||
set_load -pin_load 0.03 [get_ports out2]
|
||||
puts "PASS: set_load out2 pin"
|
||||
|
||||
############################################################
|
||||
# Test 2: set_load with rise/fall
|
||||
############################################################
|
||||
set_load -pin_load -rise 0.045 [get_ports out1]
|
||||
set_load -pin_load -fall 0.055 [get_ports out1]
|
||||
puts "PASS: set_load rise/fall"
|
||||
|
||||
set_load -wire_load -rise 0.015 [get_ports out2]
|
||||
set_load -wire_load -fall 0.025 [get_ports out2]
|
||||
puts "PASS: set_load wire rise/fall"
|
||||
|
||||
############################################################
|
||||
# Test 3: set_load with min/max
|
||||
############################################################
|
||||
set_load -min 0.01 [get_ports out1]
|
||||
set_load -max 0.06 [get_ports out1]
|
||||
puts "PASS: set_load min/max"
|
||||
|
||||
set_load -pin_load -min 0.02 [get_ports out2]
|
||||
set_load -pin_load -max 0.05 [get_ports out2]
|
||||
puts "PASS: set_load pin min/max"
|
||||
|
||||
############################################################
|
||||
# Test 4: Port fanout number
|
||||
############################################################
|
||||
set_port_fanout_number 4 [get_ports out1]
|
||||
set_port_fanout_number 8 [get_ports out2]
|
||||
puts "PASS: port fanout"
|
||||
|
||||
############################################################
|
||||
# Test 5: Net wire cap (set_load on nets)
|
||||
############################################################
|
||||
catch {
|
||||
set_load 0.01 [get_nets n1]
|
||||
set_load 0.02 [get_nets n2]
|
||||
puts "PASS: set_load on nets"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Test 6: Capacitance limits
|
||||
############################################################
|
||||
# Design-level
|
||||
set_max_capacitance 0.25 [current_design]
|
||||
puts "PASS: max_capacitance design"
|
||||
|
||||
# Port-level
|
||||
set_max_capacitance 0.15 [get_ports out1]
|
||||
set_max_capacitance 0.20 [get_ports out2]
|
||||
puts "PASS: max_capacitance ports"
|
||||
|
||||
catch {
|
||||
set_min_capacitance 0.01 [get_ports out1]
|
||||
set_min_capacitance 0.005 [get_ports out2]
|
||||
puts "PASS: min_capacitance ports"
|
||||
}
|
||||
|
||||
# Pin-level
|
||||
catch {
|
||||
set_max_capacitance 0.10 [get_pins reg1/D]
|
||||
puts "PASS: max_capacitance pin"
|
||||
}
|
||||
|
||||
# Transition limits
|
||||
set_max_transition 0.5 [current_design]
|
||||
set_max_transition 0.3 [get_ports out1]
|
||||
set_max_transition -clock_path 0.2 [get_clocks clk1]
|
||||
set_max_transition -data_path 0.4 [get_clocks clk1]
|
||||
puts "PASS: max_transition"
|
||||
|
||||
# Fanout limits
|
||||
set_max_fanout 20 [current_design]
|
||||
set_max_fanout 10 [get_ports in1]
|
||||
puts "PASS: max_fanout"
|
||||
|
||||
set_max_area 200.0
|
||||
puts "PASS: max_area"
|
||||
|
||||
# Write with all capacity/load constraints
|
||||
set sdc1 [make_result_file sdc_cap_prop1.sdc]
|
||||
write_sdc -no_timestamp $sdc1
|
||||
puts "PASS: write_sdc with loads"
|
||||
|
||||
############################################################
|
||||
# Test 7: Propagated clocks - set and unset
|
||||
############################################################
|
||||
|
||||
# Set propagated on clock object
|
||||
set_propagated_clock [get_clocks clk1]
|
||||
puts "PASS: set_propagated_clock clk1"
|
||||
|
||||
# Set propagated on port (pin)
|
||||
set_propagated_clock [get_ports clk2]
|
||||
puts "PASS: set_propagated_clock port clk2"
|
||||
|
||||
# Write with propagated
|
||||
set sdc2 [make_result_file sdc_cap_prop2.sdc]
|
||||
write_sdc -no_timestamp $sdc2
|
||||
puts "PASS: write_sdc with propagated"
|
||||
|
||||
# Unset propagated on clock
|
||||
unset_propagated_clock [get_clocks clk1]
|
||||
puts "PASS: unset_propagated_clock clk1"
|
||||
|
||||
# Unset propagated on pin
|
||||
unset_propagated_clock [get_ports clk2]
|
||||
puts "PASS: unset_propagated_clock port clk2"
|
||||
|
||||
# Verify propagated is removed
|
||||
set sdc3 [make_result_file sdc_cap_prop3.sdc]
|
||||
write_sdc -no_timestamp $sdc3
|
||||
puts "PASS: write_sdc after unset propagated"
|
||||
|
||||
############################################################
|
||||
# Test 8: Case analysis - all 4 values and unset
|
||||
############################################################
|
||||
|
||||
# Value 0
|
||||
set_case_analysis 0 [get_ports in1]
|
||||
puts "PASS: case_analysis 0"
|
||||
|
||||
# Value 1
|
||||
set_case_analysis 1 [get_ports in2]
|
||||
puts "PASS: case_analysis 1"
|
||||
|
||||
# Value rising
|
||||
set_case_analysis rising [get_ports in3]
|
||||
puts "PASS: case_analysis rising"
|
||||
|
||||
# Write with case analysis
|
||||
set sdc4 [make_result_file sdc_cap_prop4.sdc]
|
||||
write_sdc -no_timestamp $sdc4
|
||||
puts "PASS: write_sdc with case analysis"
|
||||
|
||||
# Unset case analysis
|
||||
unset_case_analysis [get_ports in1]
|
||||
puts "PASS: unset case_analysis in1"
|
||||
|
||||
unset_case_analysis [get_ports in2]
|
||||
puts "PASS: unset case_analysis in2"
|
||||
|
||||
unset_case_analysis [get_ports in3]
|
||||
puts "PASS: unset case_analysis in3"
|
||||
|
||||
# Value falling
|
||||
set_case_analysis falling [get_ports in1]
|
||||
puts "PASS: case_analysis falling"
|
||||
|
||||
# Write with falling
|
||||
set sdc5 [make_result_file sdc_cap_prop5.sdc]
|
||||
write_sdc -no_timestamp $sdc5
|
||||
puts "PASS: write_sdc with falling"
|
||||
|
||||
# Unset
|
||||
unset_case_analysis [get_ports in1]
|
||||
puts "PASS: unset falling"
|
||||
|
||||
############################################################
|
||||
# Test 9: Logic values
|
||||
############################################################
|
||||
set_logic_zero [get_ports in1]
|
||||
set_logic_one [get_ports in2]
|
||||
catch {
|
||||
set_logic_dc [get_ports in3]
|
||||
}
|
||||
puts "PASS: logic values"
|
||||
|
||||
set sdc6 [make_result_file sdc_cap_prop6.sdc]
|
||||
write_sdc -no_timestamp $sdc6
|
||||
puts "PASS: write_sdc with logic values"
|
||||
|
||||
############################################################
|
||||
# Test 10: Read back and verify roundtrip
|
||||
############################################################
|
||||
read_sdc $sdc1
|
||||
puts "PASS: read_sdc"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report after read"
|
||||
|
||||
set sdc7 [make_result_file sdc_cap_prop7.sdc]
|
||||
write_sdc -no_timestamp $sdc7
|
||||
puts "PASS: write_sdc roundtrip"
|
||||
|
||||
# Read compatible format
|
||||
read_sdc $sdc2
|
||||
puts "PASS: read_sdc propagated"
|
||||
|
||||
set sdc8 [make_result_file sdc_cap_prop8.sdc]
|
||||
write_sdc -no_timestamp -compatible $sdc8
|
||||
puts "PASS: write_sdc compatible roundtrip"
|
||||
|
||||
report_checks
|
||||
puts "PASS: final report"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,363 @@
|
||||
PASS: clocks created
|
||||
PASS: generated clocks
|
||||
PASS: IO delays
|
||||
PASS: clock_groups -asynchronous
|
||||
PASS: write_sdc with async groups
|
||||
Warning: generated clock gclk1 pin clk1 is in the fanout of multiple clocks.
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1_2x)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
5.00 5.00 clock clk1_2x (rise edge)
|
||||
0.00 5.00 clock network delay (ideal)
|
||||
0.00 5.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 5.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 5.08 ^ out1 (out)
|
||||
5.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-5.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
1.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in1 (input port clocked by clk1)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1_2x)
|
||||
Path Group: clk1_2x
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
2.00 2.00 v input external delay
|
||||
0.00 2.00 v in1 (in)
|
||||
0.02 2.02 v buf1/Z (BUF_X1)
|
||||
0.05 2.07 v or1/ZN (OR2_X1)
|
||||
0.03 2.09 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 2.09 ^ reg2/D (DFF_X1)
|
||||
2.09 data arrival time
|
||||
|
||||
5.00 5.00 clock clk1_2x (rise edge)
|
||||
0.00 5.00 clock network delay (ideal)
|
||||
0.00 5.00 clock reconvergence pessimism
|
||||
5.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 4.97 library setup time
|
||||
4.97 data required time
|
||||
---------------------------------------------------------
|
||||
4.97 data required time
|
||||
-2.09 data arrival time
|
||||
---------------------------------------------------------
|
||||
2.87 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3/Q (clock source 'gclk2')
|
||||
Endpoint: out2 (output port clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
15.00 15.00 clock gclk2 (fall edge)
|
||||
0.00 15.00 clock network delay
|
||||
15.00 v out2 (out)
|
||||
15.00 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
-3.00 17.00 output external delay
|
||||
17.00 data required time
|
||||
---------------------------------------------------------
|
||||
17.00 data required time
|
||||
-15.00 data arrival time
|
||||
---------------------------------------------------------
|
||||
2.00 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks after async groups
|
||||
PASS: unset_clock_groups async
|
||||
PASS: clock_groups -logically_exclusive
|
||||
PASS: write_sdc with logical groups
|
||||
PASS: unset logically_exclusive
|
||||
PASS: clock_groups -physically_exclusive
|
||||
PASS: write_sdc with physical groups
|
||||
PASS: unset physically_exclusive
|
||||
PASS: multiple clock groups simultaneously
|
||||
PASS: write_sdc with multiple groups
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1_2x)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
5.00 5.00 clock clk1_2x (rise edge)
|
||||
0.00 5.00 clock network delay (ideal)
|
||||
0.00 5.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 5.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 5.08 ^ out1 (out)
|
||||
5.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-5.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
1.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in1 (input port clocked by clk1)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1_2x)
|
||||
Path Group: clk1_2x
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
2.00 2.00 v input external delay
|
||||
0.00 2.00 v in1 (in)
|
||||
0.02 2.02 v buf1/Z (BUF_X1)
|
||||
0.05 2.07 v or1/ZN (OR2_X1)
|
||||
0.03 2.09 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 2.09 ^ reg2/D (DFF_X1)
|
||||
2.09 data arrival time
|
||||
|
||||
5.00 5.00 clock clk1_2x (rise edge)
|
||||
0.00 5.00 clock network delay (ideal)
|
||||
0.00 5.00 clock reconvergence pessimism
|
||||
5.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 4.97 library setup time
|
||||
4.97 data required time
|
||||
---------------------------------------------------------
|
||||
4.97 data required time
|
||||
-2.09 data arrival time
|
||||
---------------------------------------------------------
|
||||
2.87 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3/Q (clock source 'gclk2')
|
||||
Endpoint: out2 (output port clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
15.00 15.00 clock gclk2 (fall edge)
|
||||
0.00 15.00 clock network delay
|
||||
15.00 v out2 (out)
|
||||
15.00 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
-3.00 17.00 output external delay
|
||||
17.00 data required time
|
||||
---------------------------------------------------------
|
||||
17.00 data required time
|
||||
-15.00 data arrival time
|
||||
---------------------------------------------------------
|
||||
2.00 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks after multiple groups
|
||||
PASS: unset multiple groups
|
||||
PASS: clock_groups -allow_paths
|
||||
PASS: write_sdc with -allow_paths
|
||||
PASS: unset -allow_paths groups
|
||||
Warning: sdc_clock_groups_sense.tcl line 1, set_clock_sense is deprecated as of SDC 2.1. Use set_sense -type clock.
|
||||
PASS: clock_sense -positive
|
||||
Warning: sdc_clock_groups_sense.tcl line 1, set_clock_sense is deprecated as of SDC 2.1. Use set_sense -type clock.
|
||||
PASS: clock_sense -negative
|
||||
Warning: sdc_clock_groups_sense.tcl line 1, set_clock_sense is deprecated as of SDC 2.1. Use set_sense -type clock.
|
||||
PASS: clock_sense -stop_propagation
|
||||
PASS: write_sdc with clock sense
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1_2x)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
5.00 5.00 clock clk1_2x (rise edge)
|
||||
0.00 5.00 clock network delay (ideal)
|
||||
0.00 5.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 5.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 5.08 ^ out1 (out)
|
||||
5.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-5.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
1.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in1 (input port clocked by clk1)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1_2x)
|
||||
Path Group: clk1_2x
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
2.00 2.00 v input external delay
|
||||
0.00 2.00 v in1 (in)
|
||||
0.02 2.02 v buf1/Z (BUF_X1)
|
||||
0.05 2.07 v or1/ZN (OR2_X1)
|
||||
0.03 2.09 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 2.09 ^ reg2/D (DFF_X1)
|
||||
2.09 data arrival time
|
||||
|
||||
5.00 5.00 clock clk1_2x (rise edge)
|
||||
0.00 5.00 clock network delay (ideal)
|
||||
0.00 5.00 clock reconvergence pessimism
|
||||
5.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 4.97 library setup time
|
||||
4.97 data required time
|
||||
---------------------------------------------------------
|
||||
4.97 data required time
|
||||
-2.09 data arrival time
|
||||
---------------------------------------------------------
|
||||
2.87 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3/Q (clock source 'gclk2')
|
||||
Endpoint: out2 (output port clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
15.00 15.00 clock gclk2 (fall edge)
|
||||
0.00 15.00 clock network delay
|
||||
15.00 v out2 (out)
|
||||
15.00 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
-3.00 17.00 output external delay
|
||||
17.00 data required time
|
||||
---------------------------------------------------------
|
||||
17.00 data required time
|
||||
-15.00 data arrival time
|
||||
---------------------------------------------------------
|
||||
2.00 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks after clock sense
|
||||
PASS: clock_groups without name (auto-named)
|
||||
PASS: unset_clock_groups -all
|
||||
PASS: set_propagated_clock
|
||||
PASS: unset_propagated_clock
|
||||
PASS: clock_uncertainty on pin
|
||||
PASS: clock_uncertainty on reg2/CK
|
||||
PASS: inter-clock uncertainty
|
||||
PASS: write_sdc with uncertainty
|
||||
PASS: unset inter-clock uncertainty
|
||||
PASS: unset pin uncertainty
|
||||
PASS: final write_sdc
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1_2x)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
5.00 5.00 clock clk1_2x (rise edge)
|
||||
0.00 5.00 clock network delay (ideal)
|
||||
0.00 5.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 5.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 5.08 ^ out1 (out)
|
||||
5.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-5.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
1.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in1 (input port clocked by clk1)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1_2x)
|
||||
Path Group: clk1_2x
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
2.00 2.00 v input external delay
|
||||
0.00 2.00 v in1 (in)
|
||||
0.02 2.02 v buf1/Z (BUF_X1)
|
||||
0.05 2.07 v or1/ZN (OR2_X1)
|
||||
0.03 2.09 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 2.09 ^ reg2/D (DFF_X1)
|
||||
2.09 data arrival time
|
||||
|
||||
5.00 5.00 clock clk1_2x (rise edge)
|
||||
0.00 5.00 clock network delay (ideal)
|
||||
-0.20 4.80 clock uncertainty
|
||||
0.00 4.80 clock reconvergence pessimism
|
||||
4.80 ^ reg2/CK (DFF_X1)
|
||||
-0.03 4.77 library setup time
|
||||
4.77 data required time
|
||||
---------------------------------------------------------
|
||||
4.77 data required time
|
||||
-2.09 data arrival time
|
||||
---------------------------------------------------------
|
||||
2.67 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3/Q (clock source 'gclk2')
|
||||
Endpoint: out2 (output port clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
15.00 15.00 clock gclk2 (fall edge)
|
||||
0.00 15.08 v reg3/Q (DFF_X1)
|
||||
0.00 15.08 v out2 (out)
|
||||
15.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (propagated)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
-3.00 17.00 output external delay
|
||||
17.00 data required time
|
||||
---------------------------------------------------------
|
||||
17.00 data required time
|
||||
-15.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
1.92 slack (MET)
|
||||
|
||||
|
||||
PASS: final report_checks
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,231 @@
|
||||
# Test clock groups and clock sense for code coverage
|
||||
# Targets: Sdc.cc (makeClockGroups, makeClkGroupExclusions, sameClockGroup,
|
||||
# setClockSense, clkStopPropagation, removeClockGroups*),
|
||||
# ClockGroups.cc, WriteSdc.cc (writeClockGroups, writeClockSense),
|
||||
# Clock.cc (edge queries, waveform handling)
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
############################################################
|
||||
# Create multiple clocks
|
||||
############################################################
|
||||
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 -waveform {0 10} [get_ports clk2]
|
||||
create_clock -name vclk1 -period 8
|
||||
create_clock -name vclk2 -period 12
|
||||
create_clock -name clk1_2x -period 5 -add [get_ports clk1]
|
||||
puts "PASS: clocks created"
|
||||
|
||||
# Generated clocks
|
||||
create_generated_clock -name gclk1 -source [get_ports clk1] -divide_by 2 [get_pins reg1/Q]
|
||||
create_generated_clock -name gclk2 -source [get_ports clk2] -multiply_by 2 [get_pins reg3/Q]
|
||||
puts "PASS: generated clocks"
|
||||
|
||||
# IO delays
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in2]
|
||||
set_input_delay -clock clk2 2.0 [get_ports in3]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 3.0 [get_ports out2]
|
||||
puts "PASS: IO delays"
|
||||
|
||||
############################################################
|
||||
# Clock groups - asynchronous
|
||||
############################################################
|
||||
|
||||
set_clock_groups -asynchronous -name async_group1 \
|
||||
-group {clk1 clk1_2x gclk1} \
|
||||
-group {clk2 gclk2}
|
||||
puts "PASS: clock_groups -asynchronous"
|
||||
|
||||
# Write SDC with async groups
|
||||
set sdc_file1 [make_result_file sdc_clk_grp_async.sdc]
|
||||
write_sdc -no_timestamp $sdc_file1
|
||||
puts "PASS: write_sdc with async groups"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report_checks after async groups"
|
||||
|
||||
# Remove async groups
|
||||
unset_clock_groups -asynchronous -name async_group1
|
||||
puts "PASS: unset_clock_groups async"
|
||||
|
||||
############################################################
|
||||
# Clock groups - logically exclusive
|
||||
############################################################
|
||||
|
||||
set_clock_groups -logically_exclusive -name logical_group1 \
|
||||
-group {clk1 clk1_2x} \
|
||||
-group {vclk1}
|
||||
puts "PASS: clock_groups -logically_exclusive"
|
||||
|
||||
# Write SDC with logically exclusive groups
|
||||
set sdc_file2 [make_result_file sdc_clk_grp_logical.sdc]
|
||||
write_sdc -no_timestamp $sdc_file2
|
||||
puts "PASS: write_sdc with logical groups"
|
||||
|
||||
# Remove logically exclusive
|
||||
unset_clock_groups -logically_exclusive -name logical_group1
|
||||
puts "PASS: unset logically_exclusive"
|
||||
|
||||
############################################################
|
||||
# Clock groups - physically exclusive
|
||||
############################################################
|
||||
|
||||
set_clock_groups -physically_exclusive -name phys_group1 \
|
||||
-group {clk1} \
|
||||
-group {clk1_2x}
|
||||
puts "PASS: clock_groups -physically_exclusive"
|
||||
|
||||
# Write SDC
|
||||
set sdc_file3 [make_result_file sdc_clk_grp_phys.sdc]
|
||||
write_sdc -no_timestamp $sdc_file3
|
||||
puts "PASS: write_sdc with physical groups"
|
||||
|
||||
# Remove physically exclusive
|
||||
unset_clock_groups -physically_exclusive -name phys_group1
|
||||
puts "PASS: unset physically_exclusive"
|
||||
|
||||
############################################################
|
||||
# Multiple clock groups simultaneously
|
||||
############################################################
|
||||
|
||||
set_clock_groups -asynchronous -name mixed1 \
|
||||
-group {clk1 gclk1} \
|
||||
-group {clk2 gclk2}
|
||||
|
||||
set_clock_groups -logically_exclusive -name mixed2 \
|
||||
-group {vclk1} \
|
||||
-group {vclk2}
|
||||
|
||||
puts "PASS: multiple clock groups simultaneously"
|
||||
|
||||
# Write SDC with multiple groups
|
||||
set sdc_file4 [make_result_file sdc_clk_grp_multi.sdc]
|
||||
write_sdc -no_timestamp $sdc_file4
|
||||
puts "PASS: write_sdc with multiple groups"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report_checks after multiple groups"
|
||||
|
||||
# Remove all
|
||||
unset_clock_groups -asynchronous -name mixed1
|
||||
unset_clock_groups -logically_exclusive -name mixed2
|
||||
puts "PASS: unset multiple groups"
|
||||
|
||||
############################################################
|
||||
# Clock groups using -allow_paths
|
||||
############################################################
|
||||
|
||||
set_clock_groups -asynchronous -name allow_grp \
|
||||
-group {clk1 clk1_2x gclk1} \
|
||||
-group {clk2 gclk2} \
|
||||
-allow_paths
|
||||
|
||||
puts "PASS: clock_groups -allow_paths"
|
||||
|
||||
set sdc_file5 [make_result_file sdc_clk_grp_allow.sdc]
|
||||
write_sdc -no_timestamp $sdc_file5
|
||||
puts "PASS: write_sdc with -allow_paths"
|
||||
|
||||
unset_clock_groups -asynchronous -name allow_grp
|
||||
puts "PASS: unset -allow_paths groups"
|
||||
|
||||
############################################################
|
||||
# Clock sense
|
||||
############################################################
|
||||
|
||||
# Positive sense
|
||||
set_clock_sense -positive -clocks [get_clocks clk1] [get_pins buf1/Z]
|
||||
puts "PASS: clock_sense -positive"
|
||||
|
||||
# Negative sense
|
||||
set_clock_sense -negative -clocks [get_clocks clk2] [get_pins inv1/ZN]
|
||||
puts "PASS: clock_sense -negative"
|
||||
|
||||
# Stop propagation
|
||||
set_clock_sense -stop_propagation -clocks [get_clocks clk1] [get_pins and1/ZN]
|
||||
puts "PASS: clock_sense -stop_propagation"
|
||||
|
||||
# Write SDC with clock sense
|
||||
set sdc_file6 [make_result_file sdc_clk_sense.sdc]
|
||||
write_sdc -no_timestamp $sdc_file6
|
||||
puts "PASS: write_sdc with clock sense"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report_checks after clock sense"
|
||||
|
||||
############################################################
|
||||
# Clock groups without explicit name (auto-naming)
|
||||
############################################################
|
||||
|
||||
set_clock_groups -asynchronous \
|
||||
-group {clk1 gclk1} \
|
||||
-group {clk2 gclk2}
|
||||
puts "PASS: clock_groups without name (auto-named)"
|
||||
|
||||
unset_clock_groups -asynchronous -all
|
||||
puts "PASS: unset_clock_groups -all"
|
||||
|
||||
############################################################
|
||||
# Propagated clock on pins
|
||||
############################################################
|
||||
|
||||
set_propagated_clock [get_clocks clk1]
|
||||
set_propagated_clock [get_clocks clk2]
|
||||
set_propagated_clock [get_pins reg1/CK]
|
||||
puts "PASS: set_propagated_clock"
|
||||
|
||||
unset_propagated_clock [get_clocks clk1]
|
||||
unset_propagated_clock [get_pins reg1/CK]
|
||||
puts "PASS: unset_propagated_clock"
|
||||
|
||||
############################################################
|
||||
# Clock uncertainty on pins
|
||||
############################################################
|
||||
|
||||
set_clock_uncertainty -setup 0.15 [get_pins reg1/CK]
|
||||
set_clock_uncertainty -hold 0.08 [get_pins reg1/CK]
|
||||
puts "PASS: clock_uncertainty on pin"
|
||||
|
||||
set_clock_uncertainty -setup 0.2 [get_pins reg2/CK]
|
||||
puts "PASS: clock_uncertainty on reg2/CK"
|
||||
|
||||
# Inter-clock uncertainty
|
||||
set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -setup 0.3
|
||||
set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -hold 0.15
|
||||
set_clock_uncertainty -from [get_clocks clk2] -to [get_clocks clk1] -setup 0.25
|
||||
set_clock_uncertainty -from [get_clocks clk2] -to [get_clocks clk1] -hold 0.12
|
||||
puts "PASS: inter-clock uncertainty"
|
||||
|
||||
# Write SDC with all uncertainty
|
||||
set sdc_file7 [make_result_file sdc_clk_uncert.sdc]
|
||||
write_sdc -no_timestamp $sdc_file7
|
||||
puts "PASS: write_sdc with uncertainty"
|
||||
|
||||
# Remove inter-clock uncertainty
|
||||
unset_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -setup
|
||||
unset_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -hold
|
||||
puts "PASS: unset inter-clock uncertainty"
|
||||
|
||||
# Remove pin uncertainty
|
||||
unset_clock_uncertainty -setup [get_pins reg1/CK]
|
||||
unset_clock_uncertainty -hold [get_pins reg1/CK]
|
||||
puts "PASS: unset pin uncertainty"
|
||||
|
||||
############################################################
|
||||
# Final write/verify
|
||||
############################################################
|
||||
|
||||
set sdc_final [make_result_file sdc_clk_grp_final.sdc]
|
||||
write_sdc -no_timestamp $sdc_final
|
||||
puts "PASS: final write_sdc"
|
||||
|
||||
report_checks
|
||||
puts "PASS: final report_checks"
|
||||
|
||||
puts "ALL PASSED"
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,251 @@
|
||||
# Test clock operations: removeClock, clock properties,
|
||||
# generated clock edge/invert, clock uncertainty inter-clock,
|
||||
# clock insertion, clock latency source variants,
|
||||
# findClock, clock waveform edge handling.
|
||||
# Targets: Sdc.cc removeClock, makeClockAfter, findClock,
|
||||
# clkFindLeafPins, makeGeneratedClock edge/multiply/divide/invert,
|
||||
# setClockInsertion, removeClockInsertion,
|
||||
# setClockLatency various source/nonsource/early/late,
|
||||
# removeClockLatency,
|
||||
# Clock.cc generated clock operations, waveform edge handling,
|
||||
# addToPins, clkEdgeTimes, clkEdge,
|
||||
# WriteSdc.cc writeClocks, writeGeneratedClock, writeClock,
|
||||
# writeClockSlews, writeClockUncertainty, writeClockLatencies,
|
||||
# writeClockInsertions, writeInterClockUncertainties,
|
||||
# writePropagatedClkPins
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
set_input_delay -clock [create_clock -name clk1 -period 10 [get_ports clk1]] 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in2]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
|
||||
############################################################
|
||||
# Create clocks with different waveforms
|
||||
############################################################
|
||||
puts "--- clock with custom waveform ---"
|
||||
create_clock -name clk2 -period 20 -waveform {5 15} [get_ports clk2]
|
||||
set_input_delay -clock clk2 2.0 [get_ports in3]
|
||||
set_output_delay -clock clk2 3.0 [get_ports out2]
|
||||
report_checks
|
||||
puts "PASS: custom waveform clock"
|
||||
|
||||
puts "--- clock with asymmetric waveform ---"
|
||||
create_clock -name vclk1 -period 8 -waveform {0 3}
|
||||
puts "PASS: asymmetric waveform"
|
||||
|
||||
puts "--- clock with -add ---"
|
||||
create_clock -name clk1_alt -period 5 -add [get_ports clk1]
|
||||
report_checks
|
||||
puts "PASS: clock -add"
|
||||
|
||||
############################################################
|
||||
# Generated clocks with various options
|
||||
############################################################
|
||||
puts "--- generated clock divide_by ---"
|
||||
create_generated_clock -name gclk_div2 -source [get_ports clk1] -divide_by 2 [get_pins reg1/Q]
|
||||
report_checks
|
||||
puts "PASS: genclk divide_by 2"
|
||||
|
||||
puts "--- generated clock multiply_by ---"
|
||||
create_generated_clock -name gclk_mul3 -source [get_ports clk2] -multiply_by 3 [get_pins reg3/Q]
|
||||
report_checks
|
||||
puts "PASS: genclk multiply_by 3"
|
||||
|
||||
puts "--- generated clock edges ---"
|
||||
create_generated_clock -name gclk_edge -source [get_ports clk1] -edges {1 3 5} [get_pins reg2/Q]
|
||||
report_checks
|
||||
puts "PASS: genclk edges"
|
||||
|
||||
puts "--- generated clock invert ---"
|
||||
catch {
|
||||
create_generated_clock -name gclk_inv -source [get_ports clk1] -divide_by 1 -invert [get_pins reg1/Q] -add
|
||||
report_checks
|
||||
}
|
||||
puts "PASS: genclk invert"
|
||||
|
||||
############################################################
|
||||
# Propagated clock
|
||||
############################################################
|
||||
puts "--- set_propagated_clock ---"
|
||||
set_propagated_clock [get_clocks clk1]
|
||||
set_propagated_clock [get_clocks clk2]
|
||||
report_checks
|
||||
puts "PASS: propagated clocks"
|
||||
|
||||
puts "--- set_propagated_clock on pin ---"
|
||||
catch {
|
||||
set_propagated_clock [get_ports clk1]
|
||||
}
|
||||
puts "PASS: propagated clock pin"
|
||||
|
||||
############################################################
|
||||
# Clock slew/transition
|
||||
############################################################
|
||||
puts "--- clock transition ---"
|
||||
set_clock_transition -rise -max 0.15 [get_clocks clk1]
|
||||
set_clock_transition -fall -min 0.08 [get_clocks clk1]
|
||||
set_clock_transition 0.1 [get_clocks clk2]
|
||||
set_clock_transition -rise 0.12 [get_clocks clk1]
|
||||
set_clock_transition -fall 0.09 [get_clocks clk1]
|
||||
report_checks
|
||||
puts "PASS: clock transition"
|
||||
|
||||
############################################################
|
||||
# Clock latency - source and non-source
|
||||
############################################################
|
||||
puts "--- clock latency source ---"
|
||||
set_clock_latency -source 0.5 [get_clocks clk1]
|
||||
set_clock_latency -source -early 0.3 [get_clocks clk1]
|
||||
set_clock_latency -source -late 0.6 [get_clocks clk1]
|
||||
set_clock_latency -source -rise -max 0.65 [get_clocks clk1]
|
||||
set_clock_latency -source -fall -min 0.25 [get_clocks clk1]
|
||||
report_checks
|
||||
puts "PASS: clock latency source"
|
||||
|
||||
puts "--- clock latency non-source ---"
|
||||
set_clock_latency 0.2 [get_clocks clk2]
|
||||
set_clock_latency -rise -max 0.4 [get_clocks clk2]
|
||||
set_clock_latency -fall -min 0.1 [get_clocks clk2]
|
||||
report_checks
|
||||
puts "PASS: clock latency non-source"
|
||||
|
||||
############################################################
|
||||
# Clock insertion
|
||||
############################################################
|
||||
puts "--- clock insertion ---"
|
||||
catch {
|
||||
set_clock_latency -source -rise -early 0.1 [get_clocks clk1]
|
||||
set_clock_latency -source -rise -late 0.3 [get_clocks clk1]
|
||||
set_clock_latency -source -fall -early 0.15 [get_clocks clk1]
|
||||
set_clock_latency -source -fall -late 0.35 [get_clocks clk1]
|
||||
}
|
||||
report_checks
|
||||
puts "PASS: clock insertion"
|
||||
|
||||
############################################################
|
||||
# Clock uncertainty - simple
|
||||
############################################################
|
||||
puts "--- clock uncertainty ---"
|
||||
set_clock_uncertainty -setup 0.2 [get_clocks clk1]
|
||||
set_clock_uncertainty -hold 0.1 [get_clocks clk1]
|
||||
set_clock_uncertainty 0.15 [get_clocks clk2]
|
||||
report_checks
|
||||
puts "PASS: clock uncertainty"
|
||||
|
||||
############################################################
|
||||
# Inter-clock uncertainty
|
||||
############################################################
|
||||
puts "--- inter-clock uncertainty ---"
|
||||
set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -setup 0.3
|
||||
set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -hold 0.15
|
||||
set_clock_uncertainty -from [get_clocks clk2] -to [get_clocks clk1] -setup 0.28
|
||||
set_clock_uncertainty -from [get_clocks clk2] -to [get_clocks clk1] -hold 0.12
|
||||
report_checks
|
||||
puts "PASS: inter-clock uncertainty"
|
||||
|
||||
############################################################
|
||||
# Clock uncertainty on pin
|
||||
############################################################
|
||||
puts "--- clock uncertainty on pin ---"
|
||||
catch {
|
||||
set_clock_uncertainty -setup 0.25 [get_ports clk1]
|
||||
set_clock_uncertainty -hold 0.08 [get_ports clk1]
|
||||
}
|
||||
report_checks
|
||||
puts "PASS: clock uncertainty pin"
|
||||
|
||||
############################################################
|
||||
# Write SDC
|
||||
############################################################
|
||||
puts "--- write_sdc ---"
|
||||
set sdc1 [make_result_file sdc_clock_ops1.sdc]
|
||||
write_sdc -no_timestamp $sdc1
|
||||
puts "PASS: write_sdc"
|
||||
|
||||
puts "--- write_sdc compatible ---"
|
||||
set sdc2 [make_result_file sdc_clock_ops2.sdc]
|
||||
write_sdc -no_timestamp -compatible $sdc2
|
||||
puts "PASS: write_sdc compatible"
|
||||
|
||||
############################################################
|
||||
# Remove clock and re-create
|
||||
############################################################
|
||||
puts "--- remove_clock ---"
|
||||
catch {
|
||||
remove_clock vclk1
|
||||
report_checks
|
||||
}
|
||||
puts "PASS: remove_clock"
|
||||
|
||||
############################################################
|
||||
# Clock properties reporting
|
||||
############################################################
|
||||
puts "--- report_clock_properties ---"
|
||||
report_clock_properties
|
||||
report_clock_properties clk1
|
||||
report_clock_properties clk2
|
||||
puts "PASS: clock properties"
|
||||
|
||||
############################################################
|
||||
# Read SDC back
|
||||
############################################################
|
||||
puts "--- read_sdc ---"
|
||||
read_sdc $sdc1
|
||||
report_checks
|
||||
puts "PASS: read_sdc"
|
||||
|
||||
############################################################
|
||||
# Remove clock latency
|
||||
############################################################
|
||||
puts "--- unset_clock_latency ---"
|
||||
catch {
|
||||
unset_clock_latency -source [get_clocks clk1]
|
||||
report_checks
|
||||
}
|
||||
puts "PASS: unset clock latency"
|
||||
|
||||
############################################################
|
||||
# Remove clock uncertainty
|
||||
############################################################
|
||||
puts "--- unset_clock_uncertainty ---"
|
||||
catch {
|
||||
unset_clock_uncertainty -setup [get_clocks clk1]
|
||||
unset_clock_uncertainty -hold [get_clocks clk1]
|
||||
report_checks
|
||||
}
|
||||
puts "PASS: unset clock uncertainty"
|
||||
|
||||
############################################################
|
||||
# Remove inter-clock uncertainty
|
||||
############################################################
|
||||
puts "--- unset inter-clock uncertainty ---"
|
||||
catch {
|
||||
unset_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -setup
|
||||
unset_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -hold
|
||||
report_checks
|
||||
}
|
||||
puts "PASS: unset inter-clock uncertainty"
|
||||
|
||||
############################################################
|
||||
# Remove propagated clock
|
||||
############################################################
|
||||
puts "--- unset_propagated_clock ---"
|
||||
catch {
|
||||
unset_propagated_clock [get_clocks clk1]
|
||||
unset_propagated_clock [get_clocks clk2]
|
||||
report_checks
|
||||
}
|
||||
puts "PASS: unset propagated clock"
|
||||
|
||||
############################################################
|
||||
# Final write
|
||||
############################################################
|
||||
set sdc3 [make_result_file sdc_clock_ops3.sdc]
|
||||
write_sdc -no_timestamp $sdc3
|
||||
puts "PASS: final write_sdc"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,251 @@
|
||||
PASS: base clocks
|
||||
PASS: generated clocks from clk_master
|
||||
PASS: generated clock from clk_aux
|
||||
PASS: add clock on same port
|
||||
PASS: IO delays
|
||||
PASS: clock latency
|
||||
PASS: clock uncertainty
|
||||
PASS: latch borrow + min pulse width
|
||||
PASS: clock groups
|
||||
PASS: exception paths
|
||||
PASS: propagated clock
|
||||
PASS: clock transitions
|
||||
PASS: clock gating check
|
||||
PASS: write_sdc phase 1
|
||||
Warning: generated clock gclk_div2 pin clk1 is in the fanout of multiple clocks.
|
||||
Warning: generated clock gclk_div4 pin clk1 is in the fanout of multiple clocks.
|
||||
Startpoint: reg3/Q (clock source 'gclk_mul2')
|
||||
Endpoint: out2 (output port clocked by clk_aux)
|
||||
Path Group: clk_aux
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
15.00 15.00 clock gclk_mul2 (fall edge)
|
||||
0.00 15.00 clock network delay
|
||||
15.00 v out2 (out)
|
||||
15.00 data arrival time
|
||||
|
||||
20.00 20.00 clock clk_aux (rise edge)
|
||||
0.20 20.20 clock network delay (ideal)
|
||||
0.00 20.20 clock reconvergence pessimism
|
||||
-2.80 17.40 output external delay
|
||||
17.40 data required time
|
||||
---------------------------------------------------------
|
||||
17.40 data required time
|
||||
-15.00 data arrival time
|
||||
---------------------------------------------------------
|
||||
2.40 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in1 (input port clocked by clk_master)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk_master)
|
||||
Path Group: clk_master
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
5.00 5.00 clock clk_master (fall edge)
|
||||
0.60 5.60 clock network delay (propagated)
|
||||
2.50 8.10 v input external delay
|
||||
0.00 8.10 v in1 (in)
|
||||
0.02 8.12 v buf1/Z (BUF_X1)
|
||||
0.05 8.17 v or1/ZN (OR2_X1)
|
||||
0.03 8.19 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 8.19 ^ reg2/D (DFF_X1)
|
||||
8.19 data arrival time
|
||||
|
||||
10.00 10.00 clock clk_master (rise edge)
|
||||
0.30 10.30 clock network delay (propagated)
|
||||
-0.15 10.15 clock uncertainty
|
||||
0.00 10.15 clock reconvergence pessimism
|
||||
10.15 ^ reg2/CK (DFF_X1)
|
||||
-0.03 10.12 library setup time
|
||||
10.12 data required time
|
||||
---------------------------------------------------------
|
||||
10.12 data required time
|
||||
-8.19 data arrival time
|
||||
---------------------------------------------------------
|
||||
1.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in1 (input port clocked by clk_master)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk_master_alt)
|
||||
Path Group: clk_master_alt
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
5.00 5.00 clock clk_master (fall edge)
|
||||
0.60 5.60 clock network delay (propagated)
|
||||
2.50 8.10 v input external delay
|
||||
0.00 8.10 v in1 (in)
|
||||
0.02 8.12 v buf1/Z (BUF_X1)
|
||||
0.05 8.17 v or1/ZN (OR2_X1)
|
||||
0.03 8.19 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 8.19 ^ reg2/D (DFF_X1)
|
||||
8.19 data arrival time
|
||||
|
||||
10.00 10.00 clock clk_master_alt (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-8.19 data arrival time
|
||||
---------------------------------------------------------
|
||||
1.77 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg2/Q (clock source 'gclk_div4')
|
||||
Endpoint: out1 (output port clocked by gclk_div2)
|
||||
Path Group: gclk_div2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock gclk_div4 (rise edge)
|
||||
0.00 0.00 clock network delay
|
||||
0.00 ^ out1 (out)
|
||||
0.00 data arrival time
|
||||
|
||||
10.00 10.00 clock gclk_div2 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.50 6.50 output external delay
|
||||
6.50 data required time
|
||||
---------------------------------------------------------
|
||||
6.50 data required time
|
||||
-0.00 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.50 slack (MET)
|
||||
|
||||
|
||||
PASS: report phase 1
|
||||
PASS: delete vclk1
|
||||
PASS: delete vclk2
|
||||
Clock Period Waveform
|
||||
----------------------------------------------------
|
||||
clk_master 10.00 0.00 5.00
|
||||
clk_aux 20.00 0.00 10.00
|
||||
gclk_div2 10.00 0.00 5.00 (generated)
|
||||
gclk_div4 20.00 0.00 10.00 (generated)
|
||||
gclk_mul2 10.00 0.00 5.00 (generated)
|
||||
clk_master_alt 5.00 0.00 2.50
|
||||
PASS: report after virtual clock deletion
|
||||
PASS: write_sdc after virtual deletions
|
||||
PASS: delete gclk_div2
|
||||
PASS: delete gclk_div4
|
||||
PASS: delete gclk_mul2
|
||||
Clock Period Waveform
|
||||
----------------------------------------------------
|
||||
clk_master 10.00 0.00 5.00
|
||||
clk_aux 20.00 0.00 10.00
|
||||
clk_master_alt 5.00 0.00 2.50
|
||||
PASS: report after gen clock deletion
|
||||
PASS: delete clk_master_alt
|
||||
PASS: write_sdc after alt clock deletion
|
||||
PASS: delete clk_aux (master)
|
||||
Clock Period Waveform
|
||||
----------------------------------------------------
|
||||
clk_master 10.00 0.00 5.00
|
||||
PASS: report after master deletion
|
||||
PASS: write_sdc after master deletion
|
||||
Startpoint: in1 (input port clocked by clk_master)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk_master)
|
||||
Path Group: clk_master
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
5.00 5.00 clock clk_master (fall edge)
|
||||
0.60 5.60 clock network delay (propagated)
|
||||
2.50 8.10 v input external delay
|
||||
0.00 8.10 v in1 (in)
|
||||
0.02 8.12 v buf1/Z (BUF_X1)
|
||||
0.05 8.17 v or1/ZN (OR2_X1)
|
||||
0.03 8.19 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 8.19 ^ reg2/D (DFF_X1)
|
||||
8.19 data arrival time
|
||||
|
||||
10.00 10.00 clock clk_master (rise edge)
|
||||
0.30 10.30 clock network delay (propagated)
|
||||
-0.15 10.15 clock uncertainty
|
||||
0.00 10.15 clock reconvergence pessimism
|
||||
10.15 ^ reg2/CK (DFF_X1)
|
||||
-0.03 10.12 library setup time
|
||||
10.12 data required time
|
||||
---------------------------------------------------------
|
||||
10.12 data required time
|
||||
-8.19 data arrival time
|
||||
---------------------------------------------------------
|
||||
1.92 slack (MET)
|
||||
|
||||
|
||||
PASS: report checks
|
||||
PASS: recreated clocks
|
||||
PASS: recreated IO delays
|
||||
PASS: recreated groups and uncertainty
|
||||
PASS: recreated false path
|
||||
PASS: write_sdc final
|
||||
Startpoint: in1 (input port clocked by clk_master)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk_master)
|
||||
Path Group: clk_master
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
5.00 5.00 clock clk_master (fall edge)
|
||||
0.60 5.60 clock network delay (propagated)
|
||||
2.50 8.10 v input external delay
|
||||
0.00 8.10 v in1 (in)
|
||||
0.02 8.12 v buf1/Z (BUF_X1)
|
||||
0.05 8.17 v or1/ZN (OR2_X1)
|
||||
0.03 8.19 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 8.19 ^ reg2/D (DFF_X1)
|
||||
8.19 data arrival time
|
||||
|
||||
10.00 10.00 clock clk_master (rise edge)
|
||||
0.30 10.30 clock network delay (propagated)
|
||||
-0.15 10.15 clock uncertainty
|
||||
0.00 10.15 clock reconvergence pessimism
|
||||
10.15 ^ reg2/CK (DFF_X1)
|
||||
-0.03 10.12 library setup time
|
||||
10.12 data required time
|
||||
---------------------------------------------------------
|
||||
10.12 data required time
|
||||
-8.19 data arrival time
|
||||
---------------------------------------------------------
|
||||
1.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk_new)
|
||||
Endpoint: out2 (output port clocked by clk_new)
|
||||
Path Group: clk_new
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk_new (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg3/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg3/Q (DFF_X1)
|
||||
0.00 0.08 ^ out2 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
15.00 15.00 clock clk_new (rise edge)
|
||||
0.00 15.00 clock network delay (ideal)
|
||||
0.00 15.00 clock reconvergence pessimism
|
||||
-3.00 12.00 output external delay
|
||||
12.00 data required time
|
||||
---------------------------------------------------------
|
||||
12.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
11.92 slack (MET)
|
||||
|
||||
|
||||
PASS: read_sdc + report
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,206 @@
|
||||
# Test deep clock removal cascading where deleting a master clock
|
||||
# affects generated clocks, and re-creation exercises full path.
|
||||
# Also tests clock setPeriod/setWaveform via clock re-definition,
|
||||
# delete_clock on master with active generated clocks.
|
||||
# Targets:
|
||||
# Sdc.cc: removeClock (full cascade with generated clock refs),
|
||||
# deleteMasterClkRefs (generated clock loses master),
|
||||
# deleteExceptionsReferencing (removes exceptions on deleted clock),
|
||||
# deleteInputDelaysReferencing, deleteOutputDelaysReferencing,
|
||||
# deleteClockLatenciesReferencing, deleteClockInsertionsReferencing,
|
||||
# deleteInterClockUncertaintiesReferencing,
|
||||
# deleteLatchBorrowLimitsReferencing,
|
||||
# deleteMinPulseWidthReferencing,
|
||||
# clockGroupsDeleteClkRefs (removes clock from groups),
|
||||
# clearCycleAcctings, deleteClkPinMappings,
|
||||
# isLeafPinClock, isLeafPinNonGeneratedClock
|
||||
# Clock.cc: setPeriod, setWaveform (via re-creation),
|
||||
# setClock on multiple pins, generated clock operations,
|
||||
# clock latency/uncertainty after deletion
|
||||
# WriteSdc.cc: writing constraints after clock deletion/re-creation
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
############################################################
|
||||
# Phase 1: Create complex clock hierarchy
|
||||
############################################################
|
||||
create_clock -name clk_master -period 10 [get_ports clk1]
|
||||
create_clock -name clk_aux -period 20 -waveform {0 10} [get_ports clk2]
|
||||
create_clock -name vclk1 -period 5
|
||||
create_clock -name vclk2 -period 8
|
||||
puts "PASS: base clocks"
|
||||
|
||||
# Generated clocks from clk_master
|
||||
create_generated_clock -name gclk_div2 -source [get_ports clk1] -divide_by 2 [get_pins reg1/Q]
|
||||
create_generated_clock -name gclk_div4 -source [get_ports clk1] -divide_by 4 [get_pins reg2/Q]
|
||||
puts "PASS: generated clocks from clk_master"
|
||||
|
||||
# Generated clock from clk_aux
|
||||
create_generated_clock -name gclk_mul2 -source [get_ports clk2] -multiply_by 2 [get_pins reg3/Q]
|
||||
puts "PASS: generated clock from clk_aux"
|
||||
|
||||
# Add clock on same port (exercises -add flag)
|
||||
create_clock -name clk_master_alt -period 5 -add [get_ports clk1]
|
||||
puts "PASS: add clock on same port"
|
||||
|
||||
# IO delays referencing all clocks
|
||||
set_input_delay -clock clk_master 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk_master -clock_fall 2.5 [get_ports in1] -add_delay
|
||||
set_input_delay -clock clk_aux 1.8 [get_ports in2]
|
||||
set_input_delay -clock clk_aux 2.2 [get_ports in3]
|
||||
set_output_delay -clock clk_master 3.0 [get_ports out1]
|
||||
set_output_delay -clock gclk_div2 3.5 [get_ports out1] -add_delay
|
||||
set_output_delay -clock clk_aux 2.8 [get_ports out2]
|
||||
puts "PASS: IO delays"
|
||||
|
||||
# Latency on all clocks
|
||||
set_clock_latency -source 0.5 [get_clocks clk_master]
|
||||
set_clock_latency -source -early 0.3 [get_clocks clk_master]
|
||||
set_clock_latency -source -late 0.6 [get_clocks clk_master]
|
||||
set_clock_latency 0.2 [get_clocks clk_aux]
|
||||
set_clock_latency -source 0.1 [get_clocks vclk1]
|
||||
puts "PASS: clock latency"
|
||||
|
||||
# Inter-clock uncertainties covering all pairs
|
||||
set_clock_uncertainty -from [get_clocks clk_master] -to [get_clocks clk_aux] -setup 0.3
|
||||
set_clock_uncertainty -from [get_clocks clk_master] -to [get_clocks clk_aux] -hold 0.15
|
||||
set_clock_uncertainty -from [get_clocks clk_aux] -to [get_clocks clk_master] -setup 0.28
|
||||
set_clock_uncertainty -from [get_clocks clk_master] -to [get_clocks vclk1] -setup 0.25
|
||||
set_clock_uncertainty -from [get_clocks vclk1] -to [get_clocks vclk2] -setup 0.2
|
||||
set_clock_uncertainty -setup 0.15 [get_clocks clk_master]
|
||||
set_clock_uncertainty -hold 0.08 [get_clocks clk_master]
|
||||
puts "PASS: clock uncertainty"
|
||||
|
||||
# Latch borrow and min pulse width
|
||||
set_max_time_borrow 2.0 [get_clocks clk_master]
|
||||
set_max_time_borrow 1.5 [get_clocks clk_aux]
|
||||
set_min_pulse_width -high 0.6 [get_clocks clk_master]
|
||||
set_min_pulse_width -low 0.4 [get_clocks clk_master]
|
||||
set_min_pulse_width 0.8 [get_clocks clk_aux]
|
||||
puts "PASS: latch borrow + min pulse width"
|
||||
|
||||
# Clock groups
|
||||
set_clock_groups -asynchronous -name async1 \
|
||||
-group {clk_master gclk_div2 gclk_div4 clk_master_alt} \
|
||||
-group {clk_aux gclk_mul2}
|
||||
puts "PASS: clock groups"
|
||||
|
||||
# Exception paths referencing various clocks
|
||||
set_false_path -from [get_clocks clk_master] -to [get_clocks clk_aux]
|
||||
set_false_path -from [get_clocks vclk1] -to [get_clocks vclk2]
|
||||
set_multicycle_path -setup 2 -from [get_clocks clk_master] -to [get_clocks gclk_div2]
|
||||
puts "PASS: exception paths"
|
||||
|
||||
# Propagated clocks
|
||||
set_propagated_clock [get_clocks clk_master]
|
||||
puts "PASS: propagated clock"
|
||||
|
||||
# Clock transition
|
||||
set_clock_transition 0.1 [get_clocks clk_master]
|
||||
set_clock_transition 0.15 [get_clocks clk_aux]
|
||||
puts "PASS: clock transitions"
|
||||
|
||||
# Clock gating check
|
||||
set_clock_gating_check -setup 0.4 [get_clocks clk_master]
|
||||
set_clock_gating_check -hold 0.2 [get_clocks clk_master]
|
||||
puts "PASS: clock gating check"
|
||||
|
||||
# Write complete state
|
||||
set sdc1 [make_result_file sdc_clkremoval1.sdc]
|
||||
write_sdc -no_timestamp $sdc1
|
||||
puts "PASS: write_sdc phase 1"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report phase 1"
|
||||
|
||||
############################################################
|
||||
# Phase 2: Delete virtual clocks (simpler cascade)
|
||||
############################################################
|
||||
delete_clock [get_clocks vclk1]
|
||||
puts "PASS: delete vclk1"
|
||||
|
||||
delete_clock [get_clocks vclk2]
|
||||
puts "PASS: delete vclk2"
|
||||
|
||||
report_clock_properties
|
||||
puts "PASS: report after virtual clock deletion"
|
||||
|
||||
set sdc2 [make_result_file sdc_clkremoval2.sdc]
|
||||
write_sdc -no_timestamp $sdc2
|
||||
puts "PASS: write_sdc after virtual deletions"
|
||||
|
||||
############################################################
|
||||
# Phase 3: Delete generated clocks
|
||||
############################################################
|
||||
delete_generated_clock [get_clocks gclk_div2]
|
||||
puts "PASS: delete gclk_div2"
|
||||
|
||||
delete_generated_clock [get_clocks gclk_div4]
|
||||
puts "PASS: delete gclk_div4"
|
||||
|
||||
delete_generated_clock [get_clocks gclk_mul2]
|
||||
puts "PASS: delete gclk_mul2"
|
||||
|
||||
report_clock_properties
|
||||
puts "PASS: report after gen clock deletion"
|
||||
|
||||
############################################################
|
||||
# Phase 4: Delete the -add clock on clk1 port
|
||||
############################################################
|
||||
delete_clock [get_clocks clk_master_alt]
|
||||
puts "PASS: delete clk_master_alt"
|
||||
|
||||
set sdc3 [make_result_file sdc_clkremoval3.sdc]
|
||||
write_sdc -no_timestamp $sdc3
|
||||
puts "PASS: write_sdc after alt clock deletion"
|
||||
|
||||
############################################################
|
||||
# Phase 5: Delete master clock (cascades to remove all refs)
|
||||
############################################################
|
||||
delete_clock [get_clocks clk_aux]
|
||||
puts "PASS: delete clk_aux (master)"
|
||||
|
||||
report_clock_properties
|
||||
puts "PASS: report after master deletion"
|
||||
|
||||
set sdc4 [make_result_file sdc_clkremoval4.sdc]
|
||||
write_sdc -no_timestamp $sdc4
|
||||
puts "PASS: write_sdc after master deletion"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report checks"
|
||||
|
||||
############################################################
|
||||
# Phase 6: Re-create everything fresh
|
||||
############################################################
|
||||
create_clock -name clk_new -period 15 [get_ports clk2]
|
||||
create_generated_clock -name gclk_new -source [get_ports clk1] -divide_by 3 [get_pins reg1/Q]
|
||||
puts "PASS: recreated clocks"
|
||||
|
||||
set_input_delay -clock clk_master 1.5 [get_ports in2]
|
||||
set_input_delay -clock clk_new 1.8 [get_ports in3]
|
||||
set_output_delay -clock clk_master 2.5 [get_ports out1]
|
||||
set_output_delay -clock clk_new 3.0 [get_ports out2]
|
||||
puts "PASS: recreated IO delays"
|
||||
|
||||
set_clock_uncertainty -from [get_clocks clk_master] -to [get_clocks clk_new] -setup 0.2
|
||||
set_clock_groups -asynchronous -name async_new \
|
||||
-group {clk_master gclk_new} \
|
||||
-group {clk_new}
|
||||
puts "PASS: recreated groups and uncertainty"
|
||||
|
||||
set_false_path -from [get_clocks clk_master] -to [get_clocks clk_new]
|
||||
puts "PASS: recreated false path"
|
||||
|
||||
set sdc5 [make_result_file sdc_clkremoval5.sdc]
|
||||
write_sdc -no_timestamp $sdc5
|
||||
puts "PASS: write_sdc final"
|
||||
|
||||
read_sdc $sdc5
|
||||
report_checks
|
||||
puts "PASS: read_sdc + report"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,66 @@
|
||||
PASS: create_clock clk1
|
||||
PASS: create_clock clk2 with waveform
|
||||
PASS: create_clock virtual clock
|
||||
PASS: create_clock -add
|
||||
Clock Period Waveform
|
||||
----------------------------------------------------
|
||||
clk1 10.00 0.00 5.00
|
||||
clk2 20.00 0.00 10.00
|
||||
vclk 5.00 0.00 2.50
|
||||
clk1_fast 5.00 0.00 2.50
|
||||
PASS: report_clock_properties
|
||||
PASS: create_generated_clock -divide_by
|
||||
PASS: create_generated_clock -multiply_by
|
||||
Warning: generated clock gen_clk_div2 pin clk1 is in the fanout of multiple clocks.
|
||||
Clock Period Waveform
|
||||
----------------------------------------------------
|
||||
clk1 10.00 0.00 5.00
|
||||
clk2 20.00 0.00 10.00
|
||||
vclk 5.00 0.00 2.50
|
||||
clk1_fast 5.00 0.00 2.50
|
||||
gen_clk_div2 10.00 0.00 5.00 (generated)
|
||||
gen_clk_mul3 6.67 0.00 3.33 (generated)
|
||||
PASS: report_clock_properties after generated clocks
|
||||
PASS: set_clock_latency -source
|
||||
PASS: set_clock_latency -source -rise -max
|
||||
PASS: set_clock_latency -source -fall -min
|
||||
PASS: set_clock_latency network
|
||||
PASS: set_clock_latency -rise -max
|
||||
PASS: set_clock_latency -fall -min
|
||||
PASS: set_clock_uncertainty -setup
|
||||
PASS: set_clock_uncertainty -hold
|
||||
PASS: set_clock_uncertainty -from -to -setup
|
||||
PASS: set_clock_uncertainty -from -to -hold
|
||||
PASS: set_clock_transition -rise -max
|
||||
PASS: set_clock_transition -fall -min
|
||||
PASS: set_clock_transition
|
||||
PASS: set_propagated_clock
|
||||
PASS: set_clock_groups -logically_exclusive
|
||||
PASS: unset_clock_groups -logically_exclusive
|
||||
PASS: set_clock_groups -physically_exclusive
|
||||
PASS: unset_clock_groups -physically_exclusive
|
||||
PASS: set_clock_groups -asynchronous
|
||||
PASS: unset_clock_groups -asynchronous
|
||||
Warning: sdc_clocks.tcl line 1, set_clock_sense is deprecated as of SDC 2.1. Use set_sense -type clock.
|
||||
PASS: set_clock_sense -positive
|
||||
No paths found.
|
||||
PASS: report_checks after clock constraints
|
||||
PASS: unset_propagated_clock
|
||||
PASS: unset_clock_latency
|
||||
PASS: unset_clock_latency clk2
|
||||
PASS: unset_clock_latency -source
|
||||
PASS: unset_clock_transition
|
||||
PASS: unset_clock_uncertainty -setup
|
||||
PASS: unset_clock_uncertainty -hold
|
||||
PASS: unset_clock_uncertainty -from -to -setup
|
||||
PASS: unset_clock_uncertainty -from -to -hold
|
||||
PASS: delete_generated_clock gen_clk_div2
|
||||
PASS: delete_generated_clock gen_clk_mul3
|
||||
PASS: delete_clock vclk
|
||||
Clock Period Waveform
|
||||
----------------------------------------------------
|
||||
clk1 10.00 0.00 5.00
|
||||
clk2 20.00 0.00 10.00
|
||||
clk1_fast 5.00 0.00 2.50
|
||||
PASS: final report_clock_properties
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,187 @@
|
||||
# Test comprehensive clock SDC commands for code coverage
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
############################################################
|
||||
# create_clock with various options
|
||||
############################################################
|
||||
|
||||
# Basic clock
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
puts "PASS: create_clock clk1"
|
||||
|
||||
# Clock with waveform
|
||||
create_clock -name clk2 -period 20 -waveform {0 10} [get_ports clk2]
|
||||
puts "PASS: create_clock clk2 with waveform"
|
||||
|
||||
# Virtual clock (no port)
|
||||
create_clock -name vclk -period 5
|
||||
puts "PASS: create_clock virtual clock"
|
||||
|
||||
# Clock with -add on same port (additional clock definition)
|
||||
create_clock -name clk1_fast -period 5 -add [get_ports clk1]
|
||||
puts "PASS: create_clock -add"
|
||||
|
||||
# Report clock properties
|
||||
report_clock_properties
|
||||
puts "PASS: report_clock_properties"
|
||||
|
||||
############################################################
|
||||
# create_generated_clock
|
||||
############################################################
|
||||
|
||||
create_generated_clock -name gen_clk_div2 -source [get_ports clk1] -divide_by 2 [get_pins reg1/Q]
|
||||
puts "PASS: create_generated_clock -divide_by"
|
||||
|
||||
create_generated_clock -name gen_clk_mul3 -source [get_ports clk2] -multiply_by 3 [get_pins reg3/Q]
|
||||
puts "PASS: create_generated_clock -multiply_by"
|
||||
|
||||
report_clock_properties
|
||||
puts "PASS: report_clock_properties after generated clocks"
|
||||
|
||||
############################################################
|
||||
# set_clock_latency
|
||||
############################################################
|
||||
|
||||
# Source latency with rise/fall min/max
|
||||
set_clock_latency -source 0.5 [get_clocks clk1]
|
||||
puts "PASS: set_clock_latency -source"
|
||||
|
||||
set_clock_latency -source -rise -max 0.6 [get_clocks clk1]
|
||||
puts "PASS: set_clock_latency -source -rise -max"
|
||||
|
||||
set_clock_latency -source -fall -min 0.3 [get_clocks clk1]
|
||||
puts "PASS: set_clock_latency -source -fall -min"
|
||||
|
||||
# Network latency
|
||||
set_clock_latency 0.2 [get_clocks clk2]
|
||||
puts "PASS: set_clock_latency network"
|
||||
|
||||
set_clock_latency -rise -max 0.4 [get_clocks clk2]
|
||||
puts "PASS: set_clock_latency -rise -max"
|
||||
|
||||
set_clock_latency -fall -min 0.1 [get_clocks clk2]
|
||||
puts "PASS: set_clock_latency -fall -min"
|
||||
|
||||
############################################################
|
||||
# set_clock_uncertainty
|
||||
############################################################
|
||||
|
||||
# Simple clock uncertainty
|
||||
set_clock_uncertainty -setup 0.2 [get_clocks clk1]
|
||||
puts "PASS: set_clock_uncertainty -setup"
|
||||
|
||||
set_clock_uncertainty -hold 0.1 [get_clocks clk1]
|
||||
puts "PASS: set_clock_uncertainty -hold"
|
||||
|
||||
# Inter-clock uncertainty
|
||||
set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -setup 0.3
|
||||
puts "PASS: set_clock_uncertainty -from -to -setup"
|
||||
|
||||
set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -hold 0.15
|
||||
puts "PASS: set_clock_uncertainty -from -to -hold"
|
||||
|
||||
############################################################
|
||||
# set_clock_transition
|
||||
############################################################
|
||||
|
||||
set_clock_transition -rise -max 0.15 [get_clocks clk1]
|
||||
puts "PASS: set_clock_transition -rise -max"
|
||||
|
||||
set_clock_transition -fall -min 0.08 [get_clocks clk1]
|
||||
puts "PASS: set_clock_transition -fall -min"
|
||||
|
||||
set_clock_transition 0.1 [get_clocks clk2]
|
||||
puts "PASS: set_clock_transition"
|
||||
|
||||
############################################################
|
||||
# set_propagated_clock
|
||||
############################################################
|
||||
|
||||
set_propagated_clock [get_clocks clk1]
|
||||
puts "PASS: set_propagated_clock"
|
||||
|
||||
############################################################
|
||||
# set_clock_groups
|
||||
############################################################
|
||||
|
||||
set_clock_groups -logically_exclusive -group [get_clocks clk1] -group [get_clocks clk2]
|
||||
puts "PASS: set_clock_groups -logically_exclusive"
|
||||
|
||||
# Remove and re-add as physically exclusive
|
||||
unset_clock_groups -logically_exclusive -all
|
||||
puts "PASS: unset_clock_groups -logically_exclusive"
|
||||
|
||||
set_clock_groups -physically_exclusive -group [get_clocks clk1] -group [get_clocks clk2]
|
||||
puts "PASS: set_clock_groups -physically_exclusive"
|
||||
|
||||
unset_clock_groups -physically_exclusive -all
|
||||
puts "PASS: unset_clock_groups -physically_exclusive"
|
||||
|
||||
set_clock_groups -asynchronous -group [get_clocks clk1] -group [get_clocks clk2]
|
||||
puts "PASS: set_clock_groups -asynchronous"
|
||||
|
||||
unset_clock_groups -asynchronous -all
|
||||
puts "PASS: unset_clock_groups -asynchronous"
|
||||
|
||||
############################################################
|
||||
# set_clock_sense
|
||||
############################################################
|
||||
|
||||
set_clock_sense -positive -clocks [get_clocks clk1] [get_pins buf1/Z]
|
||||
puts "PASS: set_clock_sense -positive"
|
||||
|
||||
############################################################
|
||||
# report_checks to verify constraint effects
|
||||
############################################################
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: report_checks after clock constraints"
|
||||
|
||||
############################################################
|
||||
# Unset/cleanup operations
|
||||
############################################################
|
||||
|
||||
unset_propagated_clock [get_clocks clk1]
|
||||
puts "PASS: unset_propagated_clock"
|
||||
|
||||
unset_clock_latency [get_clocks clk1]
|
||||
puts "PASS: unset_clock_latency"
|
||||
|
||||
unset_clock_latency [get_clocks clk2]
|
||||
puts "PASS: unset_clock_latency clk2"
|
||||
|
||||
unset_clock_latency -source [get_clocks clk1]
|
||||
puts "PASS: unset_clock_latency -source"
|
||||
|
||||
unset_clock_transition [get_clocks clk1]
|
||||
puts "PASS: unset_clock_transition"
|
||||
|
||||
unset_clock_uncertainty -setup [get_clocks clk1]
|
||||
puts "PASS: unset_clock_uncertainty -setup"
|
||||
|
||||
unset_clock_uncertainty -hold [get_clocks clk1]
|
||||
puts "PASS: unset_clock_uncertainty -hold"
|
||||
|
||||
unset_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -setup
|
||||
puts "PASS: unset_clock_uncertainty -from -to -setup"
|
||||
|
||||
unset_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -hold
|
||||
puts "PASS: unset_clock_uncertainty -from -to -hold"
|
||||
|
||||
# Delete generated clocks
|
||||
delete_generated_clock [get_clocks gen_clk_div2]
|
||||
puts "PASS: delete_generated_clock gen_clk_div2"
|
||||
|
||||
delete_generated_clock [get_clocks gen_clk_mul3]
|
||||
puts "PASS: delete_generated_clock gen_clk_mul3"
|
||||
|
||||
# Delete regular clocks
|
||||
delete_clock [get_clocks vclk]
|
||||
puts "PASS: delete_clock vclk"
|
||||
|
||||
report_clock_properties
|
||||
puts "PASS: final report_clock_properties"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,35 @@
|
||||
PASS: create_clock
|
||||
PASS: set_input_delay
|
||||
PASS: set_output_delay
|
||||
Clock Period Waveform
|
||||
----------------------------------------------------
|
||||
clk 10.00 0.00 5.00
|
||||
PASS: report_clock_properties
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg1/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks with SDC constraints
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,26 @@
|
||||
# Test SDC constraint commands
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test1.v
|
||||
link_design sdc_test1
|
||||
|
||||
# Create clock
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
puts "PASS: create_clock"
|
||||
|
||||
# Set input delay
|
||||
set_input_delay -clock clk 2.0 [get_ports in1]
|
||||
puts "PASS: set_input_delay"
|
||||
|
||||
# Set output delay
|
||||
set_output_delay -clock clk 3.0 [get_ports out1]
|
||||
puts "PASS: set_output_delay"
|
||||
|
||||
# Report clock properties
|
||||
report_clock_properties
|
||||
puts "PASS: report_clock_properties"
|
||||
|
||||
# Report checks
|
||||
report_checks
|
||||
puts "PASS: report_checks with SDC constraints"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,702 @@
|
||||
PASS: clocks different periods
|
||||
--- multicycle -setup 2 ---
|
||||
Startpoint: in3 (input port clocked by clk2)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
15.00 15.00 clock clk2 (rise edge)
|
||||
0.00 15.00 clock network delay (ideal)
|
||||
3.00 18.00 v input external delay
|
||||
0.00 18.00 v in3 (in)
|
||||
0.05 18.05 v or1/ZN (OR2_X1)
|
||||
0.03 18.07 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 18.07 ^ reg2/D (DFF_X1)
|
||||
18.07 data arrival time
|
||||
|
||||
20.00 20.00 clock clk1 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 19.97 library setup time
|
||||
19.97 data required time
|
||||
---------------------------------------------------------
|
||||
19.97 data required time
|
||||
-18.07 data arrival time
|
||||
---------------------------------------------------------
|
||||
1.89 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Endpoint: out2 (output port clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk2 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg3/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg3/Q (DFF_X1)
|
||||
0.00 0.08 ^ out2 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
15.00 15.00 clock clk2 (rise edge)
|
||||
0.00 15.00 clock network delay (ideal)
|
||||
0.00 15.00 clock reconvergence pessimism
|
||||
-4.00 11.00 output external delay
|
||||
11.00 data required time
|
||||
---------------------------------------------------------
|
||||
11.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
10.92 slack (MET)
|
||||
|
||||
|
||||
PASS: mcp setup 2
|
||||
--- multicycle -hold 1 ---
|
||||
Startpoint: in2 (input port clocked by clk1)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
2.00 2.00 ^ input external delay
|
||||
0.00 2.00 ^ in2 (in)
|
||||
0.00 2.00 v inv1/ZN (INV_X1)
|
||||
0.03 2.03 v and1/ZN (AND2_X1)
|
||||
0.01 2.05 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 2.05 ^ reg1/D (DFF_X1)
|
||||
2.05 data arrival time
|
||||
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg1/CK (DFF_X1)
|
||||
0.01 0.01 library hold time
|
||||
0.01 data required time
|
||||
---------------------------------------------------------
|
||||
0.01 data required time
|
||||
-2.05 data arrival time
|
||||
---------------------------------------------------------
|
||||
2.04 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 v reg1/Q (DFF_X1)
|
||||
0.00 0.08 v reg3/D (DFF_X1)
|
||||
0.08 data arrival time
|
||||
|
||||
5.00 5.00 clock clk2 (rise edge)
|
||||
0.00 5.00 clock network delay (ideal)
|
||||
0.00 5.00 clock reconvergence pessimism
|
||||
5.00 ^ reg3/CK (DFF_X1)
|
||||
0.00 5.00 library hold time
|
||||
5.00 data required time
|
||||
---------------------------------------------------------
|
||||
5.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
-4.92 slack (VIOLATED)
|
||||
|
||||
|
||||
PASS: mcp hold 1
|
||||
--- multicycle -setup 3 -start ---
|
||||
No paths found.
|
||||
PASS: mcp setup 3 start
|
||||
--- multicycle -hold 2 -start ---
|
||||
No paths found.
|
||||
PASS: mcp hold 2 start
|
||||
--- multicycle -setup 4 -end ---
|
||||
No paths found.
|
||||
PASS: mcp setup 4 end
|
||||
--- multicycle -hold 3 -end ---
|
||||
No paths found.
|
||||
PASS: mcp hold 3 end
|
||||
--- unset_path_exceptions ---
|
||||
Startpoint: in3 (input port clocked by clk2)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
15.00 15.00 clock clk2 (rise edge)
|
||||
0.00 15.00 clock network delay (ideal)
|
||||
3.00 18.00 v input external delay
|
||||
0.00 18.00 v in3 (in)
|
||||
0.05 18.05 v or1/ZN (OR2_X1)
|
||||
0.03 18.07 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 18.07 ^ reg2/D (DFF_X1)
|
||||
18.07 data arrival time
|
||||
|
||||
20.00 20.00 clock clk1 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 19.97 library setup time
|
||||
19.97 data required time
|
||||
---------------------------------------------------------
|
||||
19.97 data required time
|
||||
-18.07 data arrival time
|
||||
---------------------------------------------------------
|
||||
1.89 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
15.00 15.00 clock clk2 (rise edge)
|
||||
0.00 15.00 clock network delay (ideal)
|
||||
0.00 15.00 clock reconvergence pessimism
|
||||
15.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 14.96 library setup time
|
||||
14.96 data required time
|
||||
---------------------------------------------------------
|
||||
14.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: unset multicycle
|
||||
--- same domain multicycle ---
|
||||
Startpoint: in3 (input port clocked by clk2)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
15.00 15.00 clock clk2 (rise edge)
|
||||
0.00 15.00 clock network delay (ideal)
|
||||
3.00 18.00 v input external delay
|
||||
0.00 18.00 v in3 (in)
|
||||
0.05 18.05 v or1/ZN (OR2_X1)
|
||||
0.03 18.07 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 18.07 ^ reg2/D (DFF_X1)
|
||||
18.07 data arrival time
|
||||
|
||||
20.00 20.00 clock clk1 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 19.97 library setup time
|
||||
19.97 data required time
|
||||
---------------------------------------------------------
|
||||
19.97 data required time
|
||||
-18.07 data arrival time
|
||||
---------------------------------------------------------
|
||||
1.89 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
15.00 15.00 clock clk2 (rise edge)
|
||||
0.00 15.00 clock network delay (ideal)
|
||||
0.00 15.00 clock reconvergence pessimism
|
||||
15.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 14.96 library setup time
|
||||
14.96 data required time
|
||||
---------------------------------------------------------
|
||||
14.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
4.88 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in2 (input port clocked by clk1)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
2.00 2.00 ^ input external delay
|
||||
0.00 2.00 ^ in2 (in)
|
||||
0.00 2.00 v inv1/ZN (INV_X1)
|
||||
0.03 2.03 v and1/ZN (AND2_X1)
|
||||
0.01 2.05 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 2.05 ^ reg1/D (DFF_X1)
|
||||
2.05 data arrival time
|
||||
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg1/CK (DFF_X1)
|
||||
0.01 0.01 library hold time
|
||||
0.01 data required time
|
||||
---------------------------------------------------------
|
||||
0.01 data required time
|
||||
-2.05 data arrival time
|
||||
---------------------------------------------------------
|
||||
2.04 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 v reg1/Q (DFF_X1)
|
||||
0.00 0.08 v reg3/D (DFF_X1)
|
||||
0.08 data arrival time
|
||||
|
||||
0.00 0.00 clock clk2 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg3/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
---------------------------------------------------------
|
||||
0.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.08 slack (MET)
|
||||
|
||||
|
||||
PASS: same domain mcp
|
||||
--- reclk with non-integer ratio ---
|
||||
Startpoint: in3 (input port clocked by clk_b)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk_a)
|
||||
Path Group: clk_a
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
55.00 55.00 clock clk_b (rise edge)
|
||||
0.00 55.00 clock network delay (ideal)
|
||||
2.00 57.00 v input external delay
|
||||
0.00 57.00 v in3 (in)
|
||||
0.05 57.05 v or1/ZN (OR2_X1)
|
||||
0.03 57.07 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 57.07 ^ reg2/D (DFF_X1)
|
||||
57.07 data arrival time
|
||||
|
||||
56.00 56.00 clock clk_a (rise edge)
|
||||
0.00 56.00 clock network delay (ideal)
|
||||
0.00 56.00 clock reconvergence pessimism
|
||||
56.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 55.97 library setup time
|
||||
55.97 data required time
|
||||
---------------------------------------------------------
|
||||
55.97 data required time
|
||||
-57.07 data arrival time
|
||||
---------------------------------------------------------
|
||||
-1.11 slack (VIOLATED)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk_a)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk_b)
|
||||
Path Group: clk_b
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
21.00 21.00 clock clk_a (rise edge)
|
||||
0.00 21.00 clock network delay (ideal)
|
||||
0.00 21.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 21.08 v reg1/Q (DFF_X1)
|
||||
0.00 21.08 v reg3/D (DFF_X1)
|
||||
21.08 data arrival time
|
||||
|
||||
22.00 22.00 clock clk_b (rise edge)
|
||||
0.00 22.00 clock network delay (ideal)
|
||||
0.00 22.00 clock reconvergence pessimism
|
||||
22.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 21.96 library setup time
|
||||
21.96 data required time
|
||||
---------------------------------------------------------
|
||||
21.96 data required time
|
||||
-21.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.88 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in2 (input port clocked by clk_a)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk_a)
|
||||
Path Group: clk_a
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk_a (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 ^ input external delay
|
||||
0.00 1.00 ^ in2 (in)
|
||||
0.00 1.00 v inv1/ZN (INV_X1)
|
||||
0.03 1.03 v and1/ZN (AND2_X1)
|
||||
0.01 1.05 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.05 ^ reg1/D (DFF_X1)
|
||||
1.05 data arrival time
|
||||
|
||||
0.00 0.00 clock clk_a (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg1/CK (DFF_X1)
|
||||
0.01 0.01 library hold time
|
||||
0.01 data required time
|
||||
---------------------------------------------------------
|
||||
0.01 data required time
|
||||
-1.05 data arrival time
|
||||
---------------------------------------------------------
|
||||
1.04 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk_a)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk_b)
|
||||
Path Group: clk_b
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk_a (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 v reg1/Q (DFF_X1)
|
||||
0.00 0.08 v reg3/D (DFF_X1)
|
||||
0.08 data arrival time
|
||||
|
||||
0.00 0.00 clock clk_b (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg3/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
---------------------------------------------------------
|
||||
0.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.08 slack (MET)
|
||||
|
||||
|
||||
PASS: non-integer ratio clocks
|
||||
--- multicycle on non-integer ratio ---
|
||||
Startpoint: in3 (input port clocked by clk_b)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk_a)
|
||||
Path Group: clk_a
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
55.00 55.00 clock clk_b (rise edge)
|
||||
0.00 55.00 clock network delay (ideal)
|
||||
2.00 57.00 v input external delay
|
||||
0.00 57.00 v in3 (in)
|
||||
0.05 57.05 v or1/ZN (OR2_X1)
|
||||
0.03 57.07 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 57.07 ^ reg2/D (DFF_X1)
|
||||
57.07 data arrival time
|
||||
|
||||
56.00 56.00 clock clk_a (rise edge)
|
||||
0.00 56.00 clock network delay (ideal)
|
||||
0.00 56.00 clock reconvergence pessimism
|
||||
56.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 55.97 library setup time
|
||||
55.97 data required time
|
||||
---------------------------------------------------------
|
||||
55.97 data required time
|
||||
-57.07 data arrival time
|
||||
---------------------------------------------------------
|
||||
-1.11 slack (VIOLATED)
|
||||
|
||||
|
||||
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk_b)
|
||||
Endpoint: out2 (output port clocked by clk_b)
|
||||
Path Group: clk_b
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk_b (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg3/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg3/Q (DFF_X1)
|
||||
0.00 0.08 ^ out2 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
11.00 11.00 clock clk_b (rise edge)
|
||||
0.00 11.00 clock network delay (ideal)
|
||||
0.00 11.00 clock reconvergence pessimism
|
||||
-3.00 8.00 output external delay
|
||||
8.00 data required time
|
||||
---------------------------------------------------------
|
||||
8.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
7.92 slack (MET)
|
||||
|
||||
|
||||
PASS: mcp non-integer ratio
|
||||
--- half-period waveform ---
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk_half)
|
||||
Endpoint: out1 (output port clocked by clk_half)
|
||||
Path Group: clk_half
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk_half (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk_half (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-2.00 8.00 output external delay
|
||||
8.00 data required time
|
||||
---------------------------------------------------------
|
||||
8.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
7.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk_norm)
|
||||
Endpoint: out2 (output port clocked by clk_norm)
|
||||
Path Group: clk_norm
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk_norm (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg3/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg3/Q (DFF_X1)
|
||||
0.00 0.08 ^ out2 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk_norm (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-2.00 8.00 output external delay
|
||||
8.00 data required time
|
||||
---------------------------------------------------------
|
||||
8.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
7.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in3 (input port clocked by clk_norm)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk_half)
|
||||
Path Group: clk_half
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk_norm (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 ^ input external delay
|
||||
0.00 1.00 ^ in3 (in)
|
||||
0.02 1.02 ^ or1/ZN (OR2_X1)
|
||||
0.01 1.03 v nor1/ZN (NOR2_X1)
|
||||
0.00 1.03 v reg2/D (DFF_X1)
|
||||
1.03 data arrival time
|
||||
|
||||
0.00 0.00 clock clk_half (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg2/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
---------------------------------------------------------
|
||||
0.00 data required time
|
||||
-1.03 data arrival time
|
||||
---------------------------------------------------------
|
||||
1.03 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk_half)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk_norm)
|
||||
Path Group: clk_norm
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk_half (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 v reg1/Q (DFF_X1)
|
||||
0.00 0.08 v reg3/D (DFF_X1)
|
||||
0.08 data arrival time
|
||||
|
||||
0.00 0.00 clock clk_norm (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg3/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
---------------------------------------------------------
|
||||
0.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.08 slack (MET)
|
||||
|
||||
|
||||
PASS: half-period waveform
|
||||
--- multicycle half-period ---
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk_half)
|
||||
Endpoint: out1 (output port clocked by clk_half)
|
||||
Path Group: clk_half
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk_half (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk_half (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-2.00 8.00 output external delay
|
||||
8.00 data required time
|
||||
---------------------------------------------------------
|
||||
8.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
7.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk_norm)
|
||||
Endpoint: out2 (output port clocked by clk_norm)
|
||||
Path Group: clk_norm
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk_norm (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg3/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg3/Q (DFF_X1)
|
||||
0.00 0.08 ^ out2 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk_norm (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-2.00 8.00 output external delay
|
||||
8.00 data required time
|
||||
---------------------------------------------------------
|
||||
8.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
7.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in3 (input port clocked by clk_norm)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk_half)
|
||||
Path Group: clk_half
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk_norm (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 ^ input external delay
|
||||
0.00 1.00 ^ in3 (in)
|
||||
0.02 1.02 ^ or1/ZN (OR2_X1)
|
||||
0.01 1.03 v nor1/ZN (NOR2_X1)
|
||||
0.00 1.03 v reg2/D (DFF_X1)
|
||||
1.03 data arrival time
|
||||
|
||||
0.00 0.00 clock clk_half (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg2/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
---------------------------------------------------------
|
||||
0.00 data required time
|
||||
-1.03 data arrival time
|
||||
---------------------------------------------------------
|
||||
1.03 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk_half)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk_norm)
|
||||
Path Group: clk_norm
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk_half (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 v reg1/Q (DFF_X1)
|
||||
0.00 0.08 v reg3/D (DFF_X1)
|
||||
0.08 data arrival time
|
||||
|
||||
0.00 0.00 clock clk_norm (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg3/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
---------------------------------------------------------
|
||||
0.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.08 slack (MET)
|
||||
|
||||
|
||||
PASS: mcp half-period
|
||||
PASS: write_sdc
|
||||
--- report_clock_properties ---
|
||||
Clock Period Waveform
|
||||
----------------------------------------------------
|
||||
clk_half 10.00 0.00 3.00
|
||||
clk_norm 10.00 0.00 5.00
|
||||
PASS: clock_properties
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,153 @@
|
||||
# Test CycleAccting.cc: cycle accounting with clocks of different periods,
|
||||
# multicycle paths (-start/-end), half-period clocks, and clock relationships.
|
||||
# Exercises CycleAccting.cc findDelays with various src/tgt clock edge combos,
|
||||
# findDefaultArrivalSrcDelays, requiredTime, sourceTimeOffset, targetTimeOffset,
|
||||
# maxCycles, reportClkToClkMaxCycleWarnings.
|
||||
# Also exercises Sdc.cc multicyclePath, set_multicycle_path -start/-end,
|
||||
# Clock.cc edge operations with different period clocks.
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
############################################################
|
||||
# Phase 1: Clocks with different periods for cycle accounting
|
||||
############################################################
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 15 [get_ports clk2]
|
||||
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in2]
|
||||
set_input_delay -clock clk2 3.0 [get_ports in3]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 4.0 [get_ports out2]
|
||||
puts "PASS: clocks different periods"
|
||||
|
||||
############################################################
|
||||
# Phase 2: Multicycle path -setup (default -end)
|
||||
############################################################
|
||||
puts "--- multicycle -setup 2 ---"
|
||||
set_multicycle_path -setup 2 -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
report_checks -path_delay max
|
||||
puts "PASS: mcp setup 2"
|
||||
|
||||
puts "--- multicycle -hold 1 ---"
|
||||
set_multicycle_path -hold 1 -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
report_checks -path_delay min
|
||||
puts "PASS: mcp hold 1"
|
||||
|
||||
############################################################
|
||||
# Phase 3: Multicycle with -start
|
||||
############################################################
|
||||
puts "--- multicycle -setup 3 -start ---"
|
||||
set_multicycle_path -setup 3 -start -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
report_checks -path_delay max -from [get_ports in1] -to [get_ports out2]
|
||||
puts "PASS: mcp setup 3 start"
|
||||
|
||||
puts "--- multicycle -hold 2 -start ---"
|
||||
set_multicycle_path -hold 2 -start -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
report_checks -path_delay min -from [get_ports in1] -to [get_ports out2]
|
||||
puts "PASS: mcp hold 2 start"
|
||||
|
||||
############################################################
|
||||
# Phase 4: Multicycle with -end
|
||||
############################################################
|
||||
puts "--- multicycle -setup 4 -end ---"
|
||||
set_multicycle_path -setup 4 -end -from [get_clocks clk2] -to [get_clocks clk1]
|
||||
report_checks -path_delay max -from [get_ports in3] -to [get_ports out1]
|
||||
puts "PASS: mcp setup 4 end"
|
||||
|
||||
puts "--- multicycle -hold 3 -end ---"
|
||||
set_multicycle_path -hold 3 -end -from [get_clocks clk2] -to [get_clocks clk1]
|
||||
report_checks -path_delay min -from [get_ports in3] -to [get_ports out1]
|
||||
puts "PASS: mcp hold 3 end"
|
||||
|
||||
############################################################
|
||||
# Phase 5: Unset and re-do multicycle
|
||||
############################################################
|
||||
puts "--- unset_path_exceptions ---"
|
||||
unset_path_exceptions -setup -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
unset_path_exceptions -hold -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
unset_path_exceptions -setup -from [get_clocks clk2] -to [get_clocks clk1]
|
||||
unset_path_exceptions -hold -from [get_clocks clk2] -to [get_clocks clk1]
|
||||
report_checks -path_delay max
|
||||
puts "PASS: unset multicycle"
|
||||
|
||||
############################################################
|
||||
# Phase 6: Same clock domain multicycle
|
||||
############################################################
|
||||
puts "--- same domain multicycle ---"
|
||||
set_multicycle_path -setup 2 -from [get_clocks clk1] -to [get_clocks clk1]
|
||||
set_multicycle_path -hold 1 -from [get_clocks clk1] -to [get_clocks clk1]
|
||||
report_checks -path_delay max
|
||||
report_checks -path_delay min
|
||||
puts "PASS: same domain mcp"
|
||||
|
||||
############################################################
|
||||
# Phase 7: Re-create clocks with non-integer ratio periods
|
||||
############################################################
|
||||
puts "--- reclk with non-integer ratio ---"
|
||||
delete_clock [get_clocks clk1]
|
||||
delete_clock [get_clocks clk2]
|
||||
|
||||
create_clock -name clk_a -period 7 [get_ports clk1]
|
||||
create_clock -name clk_b -period 11 [get_ports clk2]
|
||||
|
||||
set_input_delay -clock clk_a 1.0 [get_ports in1]
|
||||
set_input_delay -clock clk_a 1.0 [get_ports in2]
|
||||
set_input_delay -clock clk_b 2.0 [get_ports in3]
|
||||
set_output_delay -clock clk_a 2.0 [get_ports out1]
|
||||
set_output_delay -clock clk_b 3.0 [get_ports out2]
|
||||
|
||||
report_checks -path_delay max
|
||||
report_checks -path_delay min
|
||||
puts "PASS: non-integer ratio clocks"
|
||||
|
||||
puts "--- multicycle on non-integer ratio ---"
|
||||
set_multicycle_path -setup 2 -from [get_clocks clk_a] -to [get_clocks clk_b]
|
||||
report_checks -path_delay max
|
||||
puts "PASS: mcp non-integer ratio"
|
||||
|
||||
############################################################
|
||||
# Phase 8: Half-period clock (waveform test)
|
||||
############################################################
|
||||
puts "--- half-period waveform ---"
|
||||
delete_clock [get_clocks clk_a]
|
||||
delete_clock [get_clocks clk_b]
|
||||
|
||||
create_clock -name clk_half -period 10 -waveform {0 3} [get_ports clk1]
|
||||
create_clock -name clk_norm -period 10 [get_ports clk2]
|
||||
|
||||
set_input_delay -clock clk_half 1.0 [get_ports in1]
|
||||
set_input_delay -clock clk_half 1.0 [get_ports in2]
|
||||
set_input_delay -clock clk_norm 1.0 [get_ports in3]
|
||||
set_output_delay -clock clk_half 2.0 [get_ports out1]
|
||||
set_output_delay -clock clk_norm 2.0 [get_ports out2]
|
||||
|
||||
report_checks -path_delay max
|
||||
report_checks -path_delay min
|
||||
puts "PASS: half-period waveform"
|
||||
|
||||
puts "--- multicycle half-period ---"
|
||||
set_multicycle_path -setup 2 -from [get_clocks clk_half] -to [get_clocks clk_norm]
|
||||
set_multicycle_path -hold 1 -from [get_clocks clk_half] -to [get_clocks clk_norm]
|
||||
report_checks -path_delay max
|
||||
report_checks -path_delay min
|
||||
puts "PASS: mcp half-period"
|
||||
|
||||
############################################################
|
||||
# Phase 9: Write SDC
|
||||
############################################################
|
||||
set sdc_out [make_result_file sdc_cycle_acct.sdc]
|
||||
write_sdc -no_timestamp $sdc_out
|
||||
puts "PASS: write_sdc"
|
||||
|
||||
############################################################
|
||||
# Phase 10: report_clock_properties
|
||||
############################################################
|
||||
puts "--- report_clock_properties ---"
|
||||
report_clock_properties
|
||||
puts "PASS: clock_properties"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,869 @@
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by master)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by gen_div2)
|
||||
Path Group: gen_div2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock master (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock gen_div2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in3 (input port clocked by gen_div2)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by master)
|
||||
Path Group: master
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock gen_div2 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
2.00 2.00 v input external delay
|
||||
0.00 2.00 v in3 (in)
|
||||
0.05 2.05 v or1/ZN (OR2_X1)
|
||||
0.03 2.07 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 2.07 ^ reg2/D (DFF_X1)
|
||||
2.07 data arrival time
|
||||
|
||||
10.00 10.00 clock master (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-2.07 data arrival time
|
||||
---------------------------------------------------------
|
||||
7.89 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by master)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by gen_div2)
|
||||
Path Group: gen_div2
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock master (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 v reg1/Q (DFF_X1)
|
||||
0.00 0.08 v reg3/D (DFF_X1)
|
||||
0.08 data arrival time
|
||||
|
||||
0.00 0.00 clock gen_div2 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg3/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
---------------------------------------------------------
|
||||
0.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.08 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in2 (input port clocked by master)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by master)
|
||||
Path Group: master
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock master (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 ^ input external delay
|
||||
0.00 1.00 ^ in2 (in)
|
||||
0.00 1.00 v inv1/ZN (INV_X1)
|
||||
0.03 1.03 v and1/ZN (AND2_X1)
|
||||
0.01 1.05 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.05 ^ reg1/D (DFF_X1)
|
||||
1.05 data arrival time
|
||||
|
||||
0.00 0.00 clock master (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg1/CK (DFF_X1)
|
||||
0.01 0.01 library hold time
|
||||
0.01 data required time
|
||||
---------------------------------------------------------
|
||||
0.01 data required time
|
||||
-1.05 data arrival time
|
||||
---------------------------------------------------------
|
||||
1.04 slack (MET)
|
||||
|
||||
|
||||
PASS: generated clock div2
|
||||
--- mcp setup 2 master -> gen_div2 ---
|
||||
No paths found.
|
||||
PASS: mcp master->gen setup 2
|
||||
--- mcp hold 1 master -> gen_div2 ---
|
||||
No paths found.
|
||||
PASS: mcp master->gen hold 1
|
||||
--- mcp setup 2 gen_div2 -> master ---
|
||||
No paths found.
|
||||
PASS: mcp gen->master setup 2
|
||||
--- odd ratio clocks ---
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk_p7)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk_p13)
|
||||
Path Group: clk_p13
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
77.00 77.00 clock clk_p7 (rise edge)
|
||||
0.00 77.00 clock network delay (ideal)
|
||||
0.00 77.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 77.08 v reg1/Q (DFF_X1)
|
||||
0.00 77.08 v reg3/D (DFF_X1)
|
||||
77.08 data arrival time
|
||||
|
||||
78.00 78.00 clock clk_p13 (rise edge)
|
||||
0.00 78.00 clock network delay (ideal)
|
||||
0.00 78.00 clock reconvergence pessimism
|
||||
78.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 77.96 library setup time
|
||||
77.96 data required time
|
||||
---------------------------------------------------------
|
||||
77.96 data required time
|
||||
-77.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.88 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in3 (input port clocked by clk_p13)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk_p7)
|
||||
Path Group: clk_p7
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
13.00 13.00 clock clk_p13 (rise edge)
|
||||
0.00 13.00 clock network delay (ideal)
|
||||
2.00 15.00 v input external delay
|
||||
0.00 15.00 v in3 (in)
|
||||
0.05 15.05 v or1/ZN (OR2_X1)
|
||||
0.03 15.07 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 15.07 ^ reg2/D (DFF_X1)
|
||||
15.07 data arrival time
|
||||
|
||||
14.00 14.00 clock clk_p7 (rise edge)
|
||||
0.00 14.00 clock network delay (ideal)
|
||||
0.00 14.00 clock reconvergence pessimism
|
||||
14.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 13.97 library setup time
|
||||
13.97 data required time
|
||||
---------------------------------------------------------
|
||||
13.97 data required time
|
||||
-15.07 data arrival time
|
||||
---------------------------------------------------------
|
||||
-1.11 slack (VIOLATED)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk_p7)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk_p13)
|
||||
Path Group: clk_p13
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk_p7 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 v reg1/Q (DFF_X1)
|
||||
0.00 0.08 v reg3/D (DFF_X1)
|
||||
0.08 data arrival time
|
||||
|
||||
0.00 0.00 clock clk_p13 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg3/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
---------------------------------------------------------
|
||||
0.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.08 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in2 (input port clocked by clk_p7)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk_p7)
|
||||
Path Group: clk_p7
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk_p7 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 ^ input external delay
|
||||
0.00 1.00 ^ in2 (in)
|
||||
0.00 1.00 v inv1/ZN (INV_X1)
|
||||
0.03 1.03 v and1/ZN (AND2_X1)
|
||||
0.01 1.05 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.05 ^ reg1/D (DFF_X1)
|
||||
1.05 data arrival time
|
||||
|
||||
0.00 0.00 clock clk_p7 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg1/CK (DFF_X1)
|
||||
0.01 0.01 library hold time
|
||||
0.01 data required time
|
||||
---------------------------------------------------------
|
||||
0.01 data required time
|
||||
-1.05 data arrival time
|
||||
---------------------------------------------------------
|
||||
1.04 slack (MET)
|
||||
|
||||
|
||||
PASS: odd ratio clocks 7:13
|
||||
--- mcp on odd ratio ---
|
||||
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk_p13)
|
||||
Endpoint: out2 (output port clocked by clk_p13)
|
||||
Path Group: clk_p13
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk_p13 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg3/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg3/Q (DFF_X1)
|
||||
0.00 0.08 ^ out2 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
13.00 13.00 clock clk_p13 (rise edge)
|
||||
0.00 13.00 clock network delay (ideal)
|
||||
0.00 13.00 clock reconvergence pessimism
|
||||
-3.00 10.00 output external delay
|
||||
10.00 data required time
|
||||
---------------------------------------------------------
|
||||
10.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in3 (input port clocked by clk_p13)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk_p7)
|
||||
Path Group: clk_p7
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
13.00 13.00 clock clk_p13 (rise edge)
|
||||
0.00 13.00 clock network delay (ideal)
|
||||
2.00 15.00 v input external delay
|
||||
0.00 15.00 v in3 (in)
|
||||
0.05 15.05 v or1/ZN (OR2_X1)
|
||||
0.03 15.07 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 15.07 ^ reg2/D (DFF_X1)
|
||||
15.07 data arrival time
|
||||
|
||||
14.00 14.00 clock clk_p7 (rise edge)
|
||||
0.00 14.00 clock network delay (ideal)
|
||||
0.00 14.00 clock reconvergence pessimism
|
||||
14.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 13.97 library setup time
|
||||
13.97 data required time
|
||||
---------------------------------------------------------
|
||||
13.97 data required time
|
||||
-15.07 data arrival time
|
||||
---------------------------------------------------------
|
||||
-1.11 slack (VIOLATED)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk_p7)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk_p13)
|
||||
Path Group: clk_p13
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk_p7 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 v reg1/Q (DFF_X1)
|
||||
0.00 0.08 v reg3/D (DFF_X1)
|
||||
0.08 data arrival time
|
||||
|
||||
12.00 12.00 clock clk_p13 (rise edge)
|
||||
0.00 12.00 clock network delay (ideal)
|
||||
0.00 12.00 clock reconvergence pessimism
|
||||
12.00 ^ reg3/CK (DFF_X1)
|
||||
0.00 12.00 library hold time
|
||||
12.00 data required time
|
||||
---------------------------------------------------------
|
||||
12.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
-11.92 slack (VIOLATED)
|
||||
|
||||
|
||||
Startpoint: in2 (input port clocked by clk_p7)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk_p7)
|
||||
Path Group: clk_p7
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk_p7 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 ^ input external delay
|
||||
0.00 1.00 ^ in2 (in)
|
||||
0.00 1.00 v inv1/ZN (INV_X1)
|
||||
0.03 1.03 v and1/ZN (AND2_X1)
|
||||
0.01 1.05 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.05 ^ reg1/D (DFF_X1)
|
||||
1.05 data arrival time
|
||||
|
||||
0.00 0.00 clock clk_p7 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg1/CK (DFF_X1)
|
||||
0.01 0.01 library hold time
|
||||
0.01 data required time
|
||||
---------------------------------------------------------
|
||||
0.01 data required time
|
||||
-1.05 data arrival time
|
||||
---------------------------------------------------------
|
||||
1.04 slack (MET)
|
||||
|
||||
|
||||
PASS: mcp odd ratio
|
||||
--- waveform edge offset ---
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk_off)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk_norm)
|
||||
Path Group: clk_norm
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
2.00 2.00 clock clk_off (rise edge)
|
||||
0.00 2.00 clock network delay (ideal)
|
||||
0.00 2.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 2.08 v reg1/Q (DFF_X1)
|
||||
0.00 2.08 v reg3/D (DFF_X1)
|
||||
2.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk_norm (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-2.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
7.88 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in3 (input port clocked by clk_norm)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk_off)
|
||||
Path Group: clk_off
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk_norm (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v in3 (in)
|
||||
0.05 1.05 v or1/ZN (OR2_X1)
|
||||
0.03 1.07 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 1.07 ^ reg2/D (DFF_X1)
|
||||
1.07 data arrival time
|
||||
|
||||
2.00 2.00 clock clk_off (rise edge)
|
||||
0.00 2.00 clock network delay (ideal)
|
||||
0.00 2.00 clock reconvergence pessimism
|
||||
2.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 1.97 library setup time
|
||||
1.97 data required time
|
||||
---------------------------------------------------------
|
||||
1.97 data required time
|
||||
-1.07 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.89 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk_norm)
|
||||
Endpoint: out2 (output port clocked by clk_norm)
|
||||
Path Group: clk_norm
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk_norm (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg3/CK (DFF_X1)
|
||||
0.08 0.08 v reg3/Q (DFF_X1)
|
||||
0.00 0.08 v out2 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
0.00 0.00 clock clk_norm (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
-2.00 -2.00 output external delay
|
||||
-2.00 data required time
|
||||
---------------------------------------------------------
|
||||
-2.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
2.08 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in2 (input port clocked by clk_off)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk_off)
|
||||
Path Group: clk_off
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
2.00 2.00 clock clk_off (rise edge)
|
||||
0.00 2.00 clock network delay (ideal)
|
||||
1.00 3.00 ^ input external delay
|
||||
0.00 3.00 ^ in2 (in)
|
||||
0.00 3.00 v inv1/ZN (INV_X1)
|
||||
0.03 3.03 v and1/ZN (AND2_X1)
|
||||
0.01 3.05 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 3.05 ^ reg1/D (DFF_X1)
|
||||
3.05 data arrival time
|
||||
|
||||
2.00 2.00 clock clk_off (rise edge)
|
||||
0.00 2.00 clock network delay (ideal)
|
||||
0.00 2.00 clock reconvergence pessimism
|
||||
2.00 ^ reg1/CK (DFF_X1)
|
||||
0.01 2.01 library hold time
|
||||
2.01 data required time
|
||||
---------------------------------------------------------
|
||||
2.01 data required time
|
||||
-3.05 data arrival time
|
||||
---------------------------------------------------------
|
||||
1.04 slack (MET)
|
||||
|
||||
|
||||
PASS: waveform edge offset
|
||||
--- mcp waveform edge offset ---
|
||||
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk_norm)
|
||||
Endpoint: out2 (output port clocked by clk_norm)
|
||||
Path Group: clk_norm
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk_norm (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg3/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg3/Q (DFF_X1)
|
||||
0.00 0.08 ^ out2 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk_norm (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-2.00 8.00 output external delay
|
||||
8.00 data required time
|
||||
---------------------------------------------------------
|
||||
8.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
7.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in3 (input port clocked by clk_norm)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk_off)
|
||||
Path Group: clk_off
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk_norm (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v in3 (in)
|
||||
0.05 1.05 v or1/ZN (OR2_X1)
|
||||
0.03 1.07 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 1.07 ^ reg2/D (DFF_X1)
|
||||
1.07 data arrival time
|
||||
|
||||
2.00 2.00 clock clk_off (rise edge)
|
||||
0.00 2.00 clock network delay (ideal)
|
||||
0.00 2.00 clock reconvergence pessimism
|
||||
2.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 1.97 library setup time
|
||||
1.97 data required time
|
||||
---------------------------------------------------------
|
||||
1.97 data required time
|
||||
-1.07 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.89 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk_norm)
|
||||
Endpoint: out2 (output port clocked by clk_norm)
|
||||
Path Group: clk_norm
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk_norm (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg3/CK (DFF_X1)
|
||||
0.08 0.08 v reg3/Q (DFF_X1)
|
||||
0.00 0.08 v out2 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
0.00 0.00 clock clk_norm (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
-2.00 -2.00 output external delay
|
||||
-2.00 data required time
|
||||
---------------------------------------------------------
|
||||
-2.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
2.08 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in2 (input port clocked by clk_off)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk_off)
|
||||
Path Group: clk_off
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
2.00 2.00 clock clk_off (rise edge)
|
||||
0.00 2.00 clock network delay (ideal)
|
||||
1.00 3.00 ^ input external delay
|
||||
0.00 3.00 ^ in2 (in)
|
||||
0.00 3.00 v inv1/ZN (INV_X1)
|
||||
0.03 3.03 v and1/ZN (AND2_X1)
|
||||
0.01 3.05 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 3.05 ^ reg1/D (DFF_X1)
|
||||
3.05 data arrival time
|
||||
|
||||
2.00 2.00 clock clk_off (rise edge)
|
||||
0.00 2.00 clock network delay (ideal)
|
||||
0.00 2.00 clock reconvergence pessimism
|
||||
2.00 ^ reg1/CK (DFF_X1)
|
||||
0.01 2.01 library hold time
|
||||
2.01 data required time
|
||||
---------------------------------------------------------
|
||||
2.01 data required time
|
||||
-3.05 data arrival time
|
||||
---------------------------------------------------------
|
||||
1.04 slack (MET)
|
||||
|
||||
|
||||
PASS: mcp waveform edge offset
|
||||
--- generated clock multiply_by ---
|
||||
Startpoint: in3 (input port clocked by gen_mult)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by base)
|
||||
Path Group: base
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock gen_mult (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
1.00 11.00 v input external delay
|
||||
0.00 11.00 v in3 (in)
|
||||
0.05 11.05 v or1/ZN (OR2_X1)
|
||||
0.03 11.07 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 11.07 ^ reg2/D (DFF_X1)
|
||||
11.07 data arrival time
|
||||
|
||||
20.00 20.00 clock base (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 19.97 library setup time
|
||||
19.97 data required time
|
||||
---------------------------------------------------------
|
||||
19.97 data required time
|
||||
-11.07 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.89 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3 (rising edge-triggered flip-flop clocked by gen_mult)
|
||||
Endpoint: out2 (output port clocked by gen_mult)
|
||||
Path Group: gen_mult
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock gen_mult (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg3/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg3/Q (DFF_X1)
|
||||
0.00 0.08 ^ out2 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock gen_mult (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-2.00 8.00 output external delay
|
||||
8.00 data required time
|
||||
---------------------------------------------------------
|
||||
8.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
7.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in3 (input port clocked by gen_mult)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by base)
|
||||
Path Group: base
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock gen_mult (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 ^ input external delay
|
||||
0.00 1.00 ^ in3 (in)
|
||||
0.02 1.02 ^ or1/ZN (OR2_X1)
|
||||
0.01 1.03 v nor1/ZN (NOR2_X1)
|
||||
0.00 1.03 v reg2/D (DFF_X1)
|
||||
1.03 data arrival time
|
||||
|
||||
0.00 0.00 clock base (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg2/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
---------------------------------------------------------
|
||||
0.00 data required time
|
||||
-1.03 data arrival time
|
||||
---------------------------------------------------------
|
||||
1.03 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by base)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by gen_mult)
|
||||
Path Group: gen_mult
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock base (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 v reg1/Q (DFF_X1)
|
||||
0.00 0.08 v reg3/D (DFF_X1)
|
||||
0.08 data arrival time
|
||||
|
||||
0.00 0.00 clock gen_mult (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg3/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
---------------------------------------------------------
|
||||
0.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.08 slack (MET)
|
||||
|
||||
|
||||
PASS: generated multiply_by 2
|
||||
--- mcp base -> gen_mult ---
|
||||
Startpoint: in3 (input port clocked by gen_mult)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by base)
|
||||
Path Group: base
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock gen_mult (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
1.00 11.00 v input external delay
|
||||
0.00 11.00 v in3 (in)
|
||||
0.05 11.05 v or1/ZN (OR2_X1)
|
||||
0.03 11.07 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 11.07 ^ reg2/D (DFF_X1)
|
||||
11.07 data arrival time
|
||||
|
||||
20.00 20.00 clock base (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 19.97 library setup time
|
||||
19.97 data required time
|
||||
---------------------------------------------------------
|
||||
19.97 data required time
|
||||
-11.07 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.89 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3 (rising edge-triggered flip-flop clocked by gen_mult)
|
||||
Endpoint: out2 (output port clocked by gen_mult)
|
||||
Path Group: gen_mult
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock gen_mult (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg3/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg3/Q (DFF_X1)
|
||||
0.00 0.08 ^ out2 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock gen_mult (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-2.00 8.00 output external delay
|
||||
8.00 data required time
|
||||
---------------------------------------------------------
|
||||
8.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
7.92 slack (MET)
|
||||
|
||||
|
||||
PASS: mcp base->mult
|
||||
--- generated clock edge list ---
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by mclk)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by edge_clk)
|
||||
Path Group: edge_clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock mclk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock edge_clk (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by mclk)
|
||||
Endpoint: out1 (output port clocked by mclk)
|
||||
Path Group: mclk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock mclk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock mclk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-2.00 8.00 output external delay
|
||||
8.00 data required time
|
||||
---------------------------------------------------------
|
||||
8.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
7.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by mclk)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by edge_clk)
|
||||
Path Group: edge_clk
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock mclk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 v reg1/Q (DFF_X1)
|
||||
0.00 0.08 v reg3/D (DFF_X1)
|
||||
0.08 data arrival time
|
||||
|
||||
0.00 0.00 clock edge_clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg3/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
---------------------------------------------------------
|
||||
0.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.08 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in2 (input port clocked by mclk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by mclk)
|
||||
Path Group: mclk
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock mclk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 ^ input external delay
|
||||
0.00 1.00 ^ in2 (in)
|
||||
0.00 1.00 v inv1/ZN (INV_X1)
|
||||
0.03 1.03 v and1/ZN (AND2_X1)
|
||||
0.01 1.05 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.05 ^ reg1/D (DFF_X1)
|
||||
1.05 data arrival time
|
||||
|
||||
0.00 0.00 clock mclk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg1/CK (DFF_X1)
|
||||
0.01 0.01 library hold time
|
||||
0.01 data required time
|
||||
---------------------------------------------------------
|
||||
0.01 data required time
|
||||
-1.05 data arrival time
|
||||
---------------------------------------------------------
|
||||
1.04 slack (MET)
|
||||
|
||||
|
||||
PASS: generated clock edge list
|
||||
--- report_clock_properties ---
|
||||
Clock Period Waveform
|
||||
----------------------------------------------------
|
||||
mclk 10.00 0.00 5.00
|
||||
edge_clk 20.00 0.00 10.00 (generated)
|
||||
PASS: clock_properties
|
||||
PASS: write_sdc
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,172 @@
|
||||
# Test CycleAccting.cc with generated clocks, odd period ratios,
|
||||
# and waveform offsets that stress the cycle accounting convergence loop.
|
||||
# Targets: CycleAccting.cc findDelays with non-trivial period ratios,
|
||||
# firstCycle with edge times, setSetupAccting, setHoldAccting,
|
||||
# setAccting for latchSetup/latchHold/gatedClockSetup/gatedClockHold,
|
||||
# findDefaultArrivalSrcDelays, setDefaultSetupAccting, setDefaultHoldAccting,
|
||||
# maxCyclesExceeded, reportClkToClkMaxCycleWarnings,
|
||||
# CycleAcctingLess, CycleAcctingHash, CycleAcctingEqual,
|
||||
# requiredTime, sourceTimeOffset, targetTimeOffset
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
############################################################
|
||||
# Phase 1: Generated clock from master clock
|
||||
############################################################
|
||||
create_clock -name master -period 10 [get_ports clk1]
|
||||
create_generated_clock -name gen_div2 -source [get_ports clk1] \
|
||||
-divide_by 2 [get_ports clk2]
|
||||
|
||||
set_input_delay -clock master 1.0 [get_ports in1]
|
||||
set_input_delay -clock master 1.0 [get_ports in2]
|
||||
set_input_delay -clock gen_div2 2.0 [get_ports in3]
|
||||
set_output_delay -clock master 2.0 [get_ports out1]
|
||||
set_output_delay -clock gen_div2 3.0 [get_ports out2]
|
||||
|
||||
report_checks -path_delay max
|
||||
report_checks -path_delay min
|
||||
puts "PASS: generated clock div2"
|
||||
|
||||
############################################################
|
||||
# Phase 2: Multicycle on generated clock paths
|
||||
############################################################
|
||||
puts "--- mcp setup 2 master -> gen_div2 ---"
|
||||
set_multicycle_path -setup 2 -from [get_clocks master] -to [get_clocks gen_div2]
|
||||
report_checks -path_delay max -from [get_ports in1] -to [get_ports out2]
|
||||
puts "PASS: mcp master->gen setup 2"
|
||||
|
||||
puts "--- mcp hold 1 master -> gen_div2 ---"
|
||||
set_multicycle_path -hold 1 -from [get_clocks master] -to [get_clocks gen_div2]
|
||||
report_checks -path_delay min -from [get_ports in1] -to [get_ports out2]
|
||||
puts "PASS: mcp master->gen hold 1"
|
||||
|
||||
puts "--- mcp setup 2 gen_div2 -> master ---"
|
||||
set_multicycle_path -setup 2 -from [get_clocks gen_div2] -to [get_clocks master]
|
||||
report_checks -path_delay max -from [get_ports in3] -to [get_ports out1]
|
||||
puts "PASS: mcp gen->master setup 2"
|
||||
|
||||
unset_path_exceptions -setup -from [get_clocks master] -to [get_clocks gen_div2]
|
||||
unset_path_exceptions -hold -from [get_clocks master] -to [get_clocks gen_div2]
|
||||
unset_path_exceptions -setup -from [get_clocks gen_div2] -to [get_clocks master]
|
||||
|
||||
############################################################
|
||||
# Phase 3: Delete and create clocks with odd ratios
|
||||
# Exercises findDelays with non-convergent cycles
|
||||
############################################################
|
||||
puts "--- odd ratio clocks ---"
|
||||
delete_clock [get_clocks master]
|
||||
delete_clock [get_clocks gen_div2]
|
||||
|
||||
create_clock -name clk_p7 -period 7 [get_ports clk1]
|
||||
create_clock -name clk_p13 -period 13 [get_ports clk2]
|
||||
|
||||
set_input_delay -clock clk_p7 1.0 [get_ports in1]
|
||||
set_input_delay -clock clk_p7 1.0 [get_ports in2]
|
||||
set_input_delay -clock clk_p13 2.0 [get_ports in3]
|
||||
set_output_delay -clock clk_p7 2.0 [get_ports out1]
|
||||
set_output_delay -clock clk_p13 3.0 [get_ports out2]
|
||||
|
||||
report_checks -path_delay max
|
||||
report_checks -path_delay min
|
||||
puts "PASS: odd ratio clocks 7:13"
|
||||
|
||||
puts "--- mcp on odd ratio ---"
|
||||
set_multicycle_path -setup 3 -from [get_clocks clk_p7] -to [get_clocks clk_p13]
|
||||
set_multicycle_path -hold 2 -from [get_clocks clk_p7] -to [get_clocks clk_p13]
|
||||
report_checks -path_delay max
|
||||
report_checks -path_delay min
|
||||
puts "PASS: mcp odd ratio"
|
||||
|
||||
############################################################
|
||||
# Phase 4: Waveform with edge offset
|
||||
############################################################
|
||||
puts "--- waveform edge offset ---"
|
||||
delete_clock [get_clocks clk_p7]
|
||||
delete_clock [get_clocks clk_p13]
|
||||
|
||||
# Clock with offset waveform (exercises firstCycle edge time handling)
|
||||
create_clock -name clk_off -period 10 -waveform {2 7} [get_ports clk1]
|
||||
create_clock -name clk_norm -period 10 [get_ports clk2]
|
||||
|
||||
set_input_delay -clock clk_off 1.0 [get_ports in1]
|
||||
set_input_delay -clock clk_off 1.0 [get_ports in2]
|
||||
set_input_delay -clock clk_norm 1.0 [get_ports in3]
|
||||
set_output_delay -clock clk_off 2.0 [get_ports out1]
|
||||
set_output_delay -clock clk_norm 2.0 [get_ports out2]
|
||||
|
||||
report_checks -path_delay max
|
||||
report_checks -path_delay min
|
||||
puts "PASS: waveform edge offset"
|
||||
|
||||
puts "--- mcp waveform edge offset ---"
|
||||
set_multicycle_path -setup 2 -from [get_clocks clk_off] -to [get_clocks clk_norm]
|
||||
set_multicycle_path -hold 1 -from [get_clocks clk_off] -to [get_clocks clk_norm]
|
||||
report_checks -path_delay max
|
||||
report_checks -path_delay min
|
||||
puts "PASS: mcp waveform edge offset"
|
||||
|
||||
############################################################
|
||||
# Phase 5: Generated clock with multiply_by
|
||||
############################################################
|
||||
puts "--- generated clock multiply_by ---"
|
||||
delete_clock [get_clocks clk_off]
|
||||
delete_clock [get_clocks clk_norm]
|
||||
|
||||
create_clock -name base -period 20 [get_ports clk1]
|
||||
create_generated_clock -name gen_mult -source [get_ports clk1] \
|
||||
-multiply_by 2 [get_ports clk2]
|
||||
|
||||
set_input_delay -clock base 2.0 [get_ports in1]
|
||||
set_input_delay -clock base 2.0 [get_ports in2]
|
||||
set_input_delay -clock gen_mult 1.0 [get_ports in3]
|
||||
set_output_delay -clock base 3.0 [get_ports out1]
|
||||
set_output_delay -clock gen_mult 2.0 [get_ports out2]
|
||||
|
||||
report_checks -path_delay max
|
||||
report_checks -path_delay min
|
||||
puts "PASS: generated multiply_by 2"
|
||||
|
||||
puts "--- mcp base -> gen_mult ---"
|
||||
set_multicycle_path -setup 2 -from [get_clocks base] -to [get_clocks gen_mult]
|
||||
report_checks -path_delay max
|
||||
puts "PASS: mcp base->mult"
|
||||
|
||||
############################################################
|
||||
# Phase 6: Generated clock with edge list
|
||||
############################################################
|
||||
puts "--- generated clock edge list ---"
|
||||
delete_clock [get_clocks base]
|
||||
delete_clock [get_clocks gen_mult]
|
||||
|
||||
create_clock -name mclk -period 10 [get_ports clk1]
|
||||
create_generated_clock -name edge_clk -source [get_ports clk1] \
|
||||
-edges {1 3 5} [get_ports clk2]
|
||||
|
||||
set_input_delay -clock mclk 1.0 [get_ports in1]
|
||||
set_input_delay -clock mclk 1.0 [get_ports in2]
|
||||
set_input_delay -clock edge_clk 1.5 [get_ports in3]
|
||||
set_output_delay -clock mclk 2.0 [get_ports out1]
|
||||
set_output_delay -clock edge_clk 2.5 [get_ports out2]
|
||||
|
||||
report_checks -path_delay max
|
||||
report_checks -path_delay min
|
||||
puts "PASS: generated clock edge list"
|
||||
|
||||
############################################################
|
||||
# Phase 7: report_clock_properties
|
||||
############################################################
|
||||
puts "--- report_clock_properties ---"
|
||||
report_clock_properties
|
||||
puts "PASS: clock_properties"
|
||||
|
||||
############################################################
|
||||
# Phase 8: Write SDC roundtrip
|
||||
############################################################
|
||||
set sdc_out [make_result_file sdc_cycle_acct_genclk.sdc]
|
||||
write_sdc -no_timestamp $sdc_out
|
||||
puts "PASS: write_sdc"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,98 @@
|
||||
PASS: clocks created
|
||||
PASS: input delay -source_latency_included
|
||||
PASS: input delay -network_latency_included
|
||||
PASS: input delay -source_latency_included -network_latency_included
|
||||
PASS: input delay -clock_fall -source_latency_included -add_delay
|
||||
PASS: input delay rise/fall with latency flags
|
||||
PASS: output delay -source_latency_included
|
||||
PASS: output delay -network_latency_included
|
||||
PASS: output delay -clock_fall -source_latency_included -add_delay
|
||||
PASS: output delay -clock_fall -network_latency_included -add_delay
|
||||
PASS: output delay 4-way rise/fall min/max
|
||||
PASS: set_propagated_clock clk1
|
||||
PASS: clock latency (removes propagation)
|
||||
PASS: set_propagated_clock on pin clk2
|
||||
PASS: clock latency on pin (removes propagation)
|
||||
PASS: max_time_borrow on clocks
|
||||
PASS: max_time_borrow on pins
|
||||
PASS: max_time_borrow on instance
|
||||
PASS: max_time_borrow on instance reg3
|
||||
PASS: min_pulse_width global
|
||||
PASS: min_pulse_width clock high != low
|
||||
PASS: min_pulse_width clock same
|
||||
PASS: min_pulse_width pin
|
||||
PASS: min_pulse_width pin high/low
|
||||
PASS: min_pulse_width instance
|
||||
PASS: set_max_area
|
||||
PASS: group_path -default
|
||||
PASS: group_path named with -through
|
||||
PASS: group_path named clk-to-clk
|
||||
PASS: group_path duplicate
|
||||
PASS: clock_groups -logically_exclusive
|
||||
PASS: false_path -setup
|
||||
PASS: false_path -hold
|
||||
PASS: multicycle -setup -start
|
||||
PASS: multicycle -hold -end
|
||||
PASS: max_delay -ignore_clock_latency
|
||||
PASS: min_delay
|
||||
PASS: write_sdc
|
||||
PASS: write_sdc -compatible
|
||||
PASS: write_sdc -digits 8
|
||||
PASS: unset_input_delay
|
||||
PASS: unset_output_delay
|
||||
PASS: unset false paths
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.30 0.30 clock network delay (ideal)
|
||||
0.00 0.30 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.38 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.38 ^ out1 (out)
|
||||
0.38 data arrival time
|
||||
|
||||
5.00 5.00 clock clk1 (fall edge)
|
||||
0.30 5.30 clock network delay (ideal)
|
||||
0.00 5.30 clock reconvergence pessimism
|
||||
-3.20 2.10 output external delay
|
||||
2.10 data required time
|
||||
---------------------------------------------------------
|
||||
2.10 data required time
|
||||
-0.38 data arrival time
|
||||
---------------------------------------------------------
|
||||
1.72 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Endpoint: out2 (output port clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk2 (rise edge)
|
||||
0.20 0.20 clock network delay (ideal)
|
||||
0.00 0.20 ^ reg3/CK (DFF_X1)
|
||||
0.08 0.28 ^ reg3/Q (DFF_X1)
|
||||
0.00 0.28 ^ out2 (out)
|
||||
0.28 data arrival time
|
||||
|
||||
10.00 10.00 clock clk2 (fall edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-2.80 7.20 output external delay
|
||||
7.20 data required time
|
||||
---------------------------------------------------------
|
||||
7.20 data required time
|
||||
-0.28 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
PASS: read_sdc + report
|
||||
PASS: write_sdc after re-read
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,257 @@
|
||||
# Test input/output delays with -source_latency_included, -network_latency_included,
|
||||
# latch borrow limits on pin/instance/clock, min pulse width on all targets,
|
||||
# group_path -default with from/through/to, setMaxArea, unset operations,
|
||||
# and write_sdc roundtrip for all of these.
|
||||
# Targets:
|
||||
# Sdc.cc: setInputDelay/setOutputDelay with source_latency_included,
|
||||
# network_latency_included, add_delay+clock_fall combos,
|
||||
# setLatchBorrowLimit (pin, instance, clock), latchBorrowLimit lookup,
|
||||
# setMinPulseWidth (global, pin, instance, clock),
|
||||
# makeGroupPath (named, default, with through),
|
||||
# setMaxArea, maxArea, removePropagatedClock (clock, pin),
|
||||
# removeInputDelay, removeOutputDelay,
|
||||
# clockGroupsAreSame (via set_clock_groups -logically_exclusive),
|
||||
# unsetTimingDerate, setMaxTimeBorrow
|
||||
# WriteSdc.cc: writePortDelay (all 4-way compression paths),
|
||||
# writeLatchBorowLimits (pin, inst, clk),
|
||||
# writeMinPulseWidths (high/low equal/different),
|
||||
# writeMaxArea, writeGroupPaths (default + named w/through),
|
||||
# writeExceptions (group_path default)
|
||||
# ExceptionPath.cc: GroupPath constructor, isDefault, overrides,
|
||||
# fromThruToPriority with through
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
############################################################
|
||||
# Setup clocks
|
||||
############################################################
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 -waveform {0 10} [get_ports clk2]
|
||||
create_clock -name vclk -period 8
|
||||
puts "PASS: clocks created"
|
||||
|
||||
############################################################
|
||||
# Input delays with -source_latency_included
|
||||
############################################################
|
||||
set_input_delay -clock clk1 -source_latency_included 2.0 [get_ports in1]
|
||||
puts "PASS: input delay -source_latency_included"
|
||||
|
||||
set_input_delay -clock clk1 -network_latency_included 1.8 [get_ports in2]
|
||||
puts "PASS: input delay -network_latency_included"
|
||||
|
||||
set_input_delay -clock clk2 -source_latency_included -network_latency_included 1.5 [get_ports in3]
|
||||
puts "PASS: input delay -source_latency_included -network_latency_included"
|
||||
|
||||
# Add delay on top with clock_fall and source_latency_included
|
||||
set_input_delay -clock clk1 -clock_fall -source_latency_included -add_delay 2.2 [get_ports in1]
|
||||
puts "PASS: input delay -clock_fall -source_latency_included -add_delay"
|
||||
|
||||
# Rise/fall with source latency on a different port
|
||||
set_input_delay -clock clk1 -rise -max -source_latency_included 3.0 [get_ports in2] -add_delay
|
||||
set_input_delay -clock clk1 -fall -min -network_latency_included 0.5 [get_ports in2] -add_delay
|
||||
puts "PASS: input delay rise/fall with latency flags"
|
||||
|
||||
############################################################
|
||||
# Output delays with -source_latency_included
|
||||
############################################################
|
||||
set_output_delay -clock clk1 -source_latency_included 3.0 [get_ports out1]
|
||||
puts "PASS: output delay -source_latency_included"
|
||||
|
||||
set_output_delay -clock clk2 -network_latency_included 2.5 [get_ports out2]
|
||||
puts "PASS: output delay -network_latency_included"
|
||||
|
||||
set_output_delay -clock clk1 -clock_fall -source_latency_included -add_delay 3.2 [get_ports out1]
|
||||
puts "PASS: output delay -clock_fall -source_latency_included -add_delay"
|
||||
|
||||
set_output_delay -clock clk2 -clock_fall -network_latency_included -add_delay 2.8 [get_ports out2]
|
||||
puts "PASS: output delay -clock_fall -network_latency_included -add_delay"
|
||||
|
||||
# Rise/fall max/min output delays creating 4-way variant
|
||||
set_output_delay -clock clk1 -rise -max 3.5 [get_ports out1] -add_delay
|
||||
set_output_delay -clock clk1 -rise -min 1.5 [get_ports out1] -add_delay
|
||||
set_output_delay -clock clk1 -fall -max 3.2 [get_ports out1] -add_delay
|
||||
set_output_delay -clock clk1 -fall -min 1.2 [get_ports out1] -add_delay
|
||||
puts "PASS: output delay 4-way rise/fall min/max"
|
||||
|
||||
############################################################
|
||||
# Propagated clock + remove propagated clock
|
||||
############################################################
|
||||
set_propagated_clock [get_clocks clk1]
|
||||
puts "PASS: set_propagated_clock clk1"
|
||||
|
||||
# Setting clock latency removes propagated clock
|
||||
set_clock_latency 0.3 [get_clocks clk1]
|
||||
puts "PASS: clock latency (removes propagation)"
|
||||
|
||||
# Set propagated on pin, then set clock latency on that pin to remove
|
||||
set_propagated_clock [get_ports clk2]
|
||||
puts "PASS: set_propagated_clock on pin clk2"
|
||||
|
||||
set_clock_latency 0.2 [get_ports clk2]
|
||||
puts "PASS: clock latency on pin (removes propagation)"
|
||||
|
||||
############################################################
|
||||
# Latch borrow limits on all three target types
|
||||
############################################################
|
||||
set_max_time_borrow 2.0 [get_clocks clk1]
|
||||
set_max_time_borrow 1.5 [get_clocks clk2]
|
||||
puts "PASS: max_time_borrow on clocks"
|
||||
|
||||
set_max_time_borrow 1.0 [get_pins reg1/D]
|
||||
set_max_time_borrow 0.8 [get_pins reg2/D]
|
||||
puts "PASS: max_time_borrow on pins"
|
||||
|
||||
catch {
|
||||
set_max_time_borrow 1.2 [get_cells reg1]
|
||||
puts "PASS: max_time_borrow on instance"
|
||||
}
|
||||
|
||||
catch {
|
||||
set_max_time_borrow 0.9 [get_cells reg3]
|
||||
puts "PASS: max_time_borrow on instance reg3"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Min pulse width on all targets
|
||||
############################################################
|
||||
# Global
|
||||
set_min_pulse_width 0.5
|
||||
puts "PASS: min_pulse_width global"
|
||||
|
||||
# Clock with different high/low
|
||||
set_min_pulse_width -high 0.6 [get_clocks clk1]
|
||||
set_min_pulse_width -low 0.4 [get_clocks clk1]
|
||||
puts "PASS: min_pulse_width clock high != low"
|
||||
|
||||
# Clock with same high/low (exercises equal path in writer)
|
||||
set_min_pulse_width 0.55 [get_clocks clk2]
|
||||
puts "PASS: min_pulse_width clock same"
|
||||
|
||||
# Pin
|
||||
catch {
|
||||
set_min_pulse_width 0.3 [get_pins reg1/CK]
|
||||
puts "PASS: min_pulse_width pin"
|
||||
}
|
||||
|
||||
catch {
|
||||
set_min_pulse_width -high 0.35 [get_pins reg2/CK]
|
||||
set_min_pulse_width -low 0.25 [get_pins reg2/CK]
|
||||
puts "PASS: min_pulse_width pin high/low"
|
||||
}
|
||||
|
||||
# Instance
|
||||
catch {
|
||||
set_min_pulse_width 0.45 [get_cells reg3]
|
||||
puts "PASS: min_pulse_width instance"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# set_max_area
|
||||
############################################################
|
||||
set_max_area 250.0
|
||||
puts "PASS: set_max_area"
|
||||
|
||||
############################################################
|
||||
# Group paths - default and named with through
|
||||
############################################################
|
||||
group_path -default -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: group_path -default"
|
||||
|
||||
group_path -name grp_thru -from [get_ports in2] \
|
||||
-through [get_pins and1/ZN] -to [get_ports out1]
|
||||
puts "PASS: group_path named with -through"
|
||||
|
||||
group_path -name grp_clk -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
puts "PASS: group_path named clk-to-clk"
|
||||
|
||||
# Duplicate group path (same name, same from/to - exercises hasKey path)
|
||||
group_path -name grp_clk -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
puts "PASS: group_path duplicate"
|
||||
|
||||
############################################################
|
||||
# Clock groups - logically_exclusive (exercises clockGroupsAreSame)
|
||||
############################################################
|
||||
set_clock_groups -logically_exclusive -group {clk1} -group {clk2}
|
||||
puts "PASS: clock_groups -logically_exclusive"
|
||||
|
||||
############################################################
|
||||
# False paths and multicycle with -setup/-hold for exceptions
|
||||
############################################################
|
||||
set_false_path -setup -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
puts "PASS: false_path -setup"
|
||||
|
||||
set_false_path -hold -from [get_clocks clk2] -to [get_clocks clk1]
|
||||
puts "PASS: false_path -hold"
|
||||
|
||||
# Multicycle with -start
|
||||
set_multicycle_path -setup -start 3 -from [get_ports in2] -to [get_ports out1]
|
||||
puts "PASS: multicycle -setup -start"
|
||||
|
||||
# Multicycle with -end for hold
|
||||
set_multicycle_path -hold -end 1 -from [get_ports in2] -to [get_ports out1]
|
||||
puts "PASS: multicycle -hold -end"
|
||||
|
||||
############################################################
|
||||
# Max/min delay with -ignore_clock_latency
|
||||
############################################################
|
||||
set_max_delay -from [get_ports in3] -to [get_ports out2] -ignore_clock_latency 7.0
|
||||
puts "PASS: max_delay -ignore_clock_latency"
|
||||
|
||||
set_min_delay -from [get_ports in3] -to [get_ports out2] 0.5
|
||||
puts "PASS: min_delay"
|
||||
|
||||
############################################################
|
||||
# Min fanout limit (covers setMinFanout through set_min_fanout if available)
|
||||
############################################################
|
||||
catch {
|
||||
set_min_fanout 2 [current_design]
|
||||
puts "PASS: set_min_fanout design"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Write SDC
|
||||
############################################################
|
||||
set sdc1 [make_result_file sdc_delay_borrow_group1.sdc]
|
||||
write_sdc -no_timestamp $sdc1
|
||||
puts "PASS: write_sdc"
|
||||
|
||||
set sdc2 [make_result_file sdc_delay_borrow_group2.sdc]
|
||||
write_sdc -no_timestamp -compatible $sdc2
|
||||
puts "PASS: write_sdc -compatible"
|
||||
|
||||
set sdc3 [make_result_file sdc_delay_borrow_group3.sdc]
|
||||
write_sdc -no_timestamp -digits 8 $sdc3
|
||||
puts "PASS: write_sdc -digits 8"
|
||||
|
||||
############################################################
|
||||
# Remove some constraints and re-write
|
||||
############################################################
|
||||
unset_input_delay -clock clk1 [get_ports in1]
|
||||
puts "PASS: unset_input_delay"
|
||||
|
||||
unset_output_delay -clock clk1 [get_ports out1]
|
||||
puts "PASS: unset_output_delay"
|
||||
|
||||
# Unset path exceptions
|
||||
unset_path_exceptions -setup -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
unset_path_exceptions -hold -from [get_clocks clk2] -to [get_clocks clk1]
|
||||
puts "PASS: unset false paths"
|
||||
|
||||
############################################################
|
||||
# Read back SDC and report
|
||||
############################################################
|
||||
read_sdc $sdc1
|
||||
report_checks
|
||||
puts "PASS: read_sdc + report"
|
||||
|
||||
############################################################
|
||||
# Re-write after read
|
||||
############################################################
|
||||
set sdc4 [make_result_file sdc_delay_borrow_group4.sdc]
|
||||
write_sdc -no_timestamp $sdc4
|
||||
puts "PASS: write_sdc after re-read"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,310 @@
|
||||
PASS: setup
|
||||
PASS: global derate
|
||||
PASS: global derate clock/data
|
||||
PASS: global derate by type
|
||||
PASS: global derate by type/clock_data/rf
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: report after global derate
|
||||
PASS: lib cell derate
|
||||
PASS: instance derate
|
||||
PASS: net derate
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: report after all derates
|
||||
PASS: write_sdc with derates
|
||||
PASS: unset_timing_derate
|
||||
PASS: disable lib cell all
|
||||
PASS: disable lib cell from
|
||||
PASS: disable lib cell to
|
||||
PASS: disable lib cell from/to
|
||||
PASS: disable lib cell from/to second
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: report after lib cell disables
|
||||
PASS: disable instance all
|
||||
PASS: disable instance from/to
|
||||
PASS: disable instance from
|
||||
PASS: disable instance to
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 ^ reg1/Q (DFF_X1)
|
||||
0.00 10.08 ^ reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-4242780356595809627609759744.00 -4242780356595809627609759744.00 library setup time
|
||||
-4242780356595809627609759744.00 data required time
|
||||
---------------------------------------------------------
|
||||
-4242780356595809627609759744.00 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
-4242780356595809627609759744.00 slack (VIOLATED)
|
||||
|
||||
|
||||
PASS: report after instance disables
|
||||
PASS: disable pin
|
||||
PASS: disable port
|
||||
PASS: write_sdc with disables
|
||||
PASS: write_sdc compatible with disables
|
||||
PASS: unset lib cell disables
|
||||
PASS: unset instance disables
|
||||
PASS: unset pin disable
|
||||
Warning: sdc_derate_disable_deep.tcl line 1, object 'sdc_test2' not found.
|
||||
Warning: sdc_derate_disable_deep.tcl line 1, object 'sdc_test2' not found.
|
||||
PASS: clock_gating_check global
|
||||
PASS: clock_gating_check clock
|
||||
PASS: clock_gating_check instance
|
||||
PASS: clock_gating_check pin
|
||||
disabled_edges_sorted count = 1
|
||||
PASS: disabled_edges_sorted
|
||||
PASS: final write_sdc
|
||||
Startpoint: in2 (input port clocked by clk1)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
2.00 2.00 ^ input external delay
|
||||
0.00 2.00 ^ in2 (in)
|
||||
0.00 2.00 v inv1/ZN (INV_X1)
|
||||
0.03 2.03 v and1/ZN (AND2_X1)
|
||||
0.01 2.05 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 2.05 ^ reg1/D (DFF_X1)
|
||||
2.05 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg1/CK (DFF_X1)
|
||||
-4280578177924698267900182528.00 -4280578177924698267900182528.00 library setup time
|
||||
-4280578177924698267900182528.00 data required time
|
||||
---------------------------------------------------------
|
||||
-4280578177924698267900182528.00 data required time
|
||||
-2.05 data arrival time
|
||||
---------------------------------------------------------
|
||||
-4280578177924698267900182528.00 slack (VIOLATED)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: final report
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,246 @@
|
||||
# Test deep derating paths and disable timing with from/to on instances.
|
||||
# Targets:
|
||||
# Sdc.cc: setTimingDerate (global, cell, inst, net with rf/clk_data),
|
||||
# disable (cell from/to, instance from/to, lib port, port, pin),
|
||||
# removeDisable variants, disabledEdgesSorted,
|
||||
# setClockGatingCheck (global, clock, pin, instance)
|
||||
# WriteSdc.cc: writeDeratings (global type-specific, cell, instance, net),
|
||||
# writeDerating (DeratingFactorsGlobal, DeratingFactorsCell,
|
||||
# DeratingFactors with type/early_late/clk_data/rf),
|
||||
# writeDisabledCells (all, from/to, from, to, timingArcSets),
|
||||
# writeDisabledInstances (from/to), writeDisabledPins,
|
||||
# writeDisabledPorts, writeDisabledLibPorts,
|
||||
# timingDerateTypeKeyword
|
||||
# DeratingFactors.cc: isOneValue, factor, hasValue
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in2]
|
||||
set_input_delay -clock clk2 2.0 [get_ports in3]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 3.0 [get_ports out2]
|
||||
puts "PASS: setup"
|
||||
|
||||
############################################################
|
||||
# Timing derate - global with specific types
|
||||
############################################################
|
||||
|
||||
# Global early/late
|
||||
set_timing_derate -early 0.95
|
||||
set_timing_derate -late 1.05
|
||||
puts "PASS: global derate"
|
||||
|
||||
# Global with clock/data separation
|
||||
set_timing_derate -early -clock 0.97
|
||||
set_timing_derate -late -clock 1.03
|
||||
set_timing_derate -early -data 0.94
|
||||
set_timing_derate -late -data 1.06
|
||||
puts "PASS: global derate clock/data"
|
||||
|
||||
# Global with type-specific (cell_delay, cell_check, net_delay)
|
||||
set_timing_derate -early -cell_delay 0.96
|
||||
set_timing_derate -late -cell_delay 1.04
|
||||
set_timing_derate -early -cell_check 0.98
|
||||
set_timing_derate -late -cell_check 1.02
|
||||
set_timing_derate -early -net_delay 0.93
|
||||
set_timing_derate -late -net_delay 1.07
|
||||
puts "PASS: global derate by type"
|
||||
|
||||
# Global with rise/fall
|
||||
set_timing_derate -early -cell_delay -clock -rise 0.96
|
||||
set_timing_derate -late -cell_delay -clock -fall 1.04
|
||||
set_timing_derate -early -cell_delay -data -rise 0.95
|
||||
set_timing_derate -late -cell_delay -data -fall 1.05
|
||||
puts "PASS: global derate by type/clock_data/rf"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report after global derate"
|
||||
|
||||
############################################################
|
||||
# Timing derate on lib cells
|
||||
############################################################
|
||||
set_timing_derate -early -cell_delay 0.91 [get_lib_cells NangateOpenCellLibrary/INV_X1]
|
||||
set_timing_derate -late -cell_delay 1.09 [get_lib_cells NangateOpenCellLibrary/INV_X1]
|
||||
set_timing_derate -early -cell_check 0.90 [get_lib_cells NangateOpenCellLibrary/DFF_X1]
|
||||
set_timing_derate -late -cell_check 1.10 [get_lib_cells NangateOpenCellLibrary/DFF_X1]
|
||||
puts "PASS: lib cell derate"
|
||||
|
||||
############################################################
|
||||
# Timing derate on instances
|
||||
############################################################
|
||||
set_timing_derate -early -cell_delay 0.89 [get_cells buf1]
|
||||
set_timing_derate -late -cell_delay 1.11 [get_cells buf1]
|
||||
set_timing_derate -early -cell_check 0.88 [get_cells reg1]
|
||||
set_timing_derate -late -cell_check 1.12 [get_cells reg1]
|
||||
puts "PASS: instance derate"
|
||||
|
||||
############################################################
|
||||
# Timing derate on nets
|
||||
############################################################
|
||||
set_timing_derate -early -net_delay 0.87 [get_nets n1]
|
||||
set_timing_derate -late -net_delay 1.13 [get_nets n1]
|
||||
set_timing_derate -early -net_delay 0.86 [get_nets n3]
|
||||
set_timing_derate -late -net_delay 1.14 [get_nets n3]
|
||||
puts "PASS: net derate"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report after all derates"
|
||||
|
||||
############################################################
|
||||
# Write SDC (exercises all derating writer paths)
|
||||
############################################################
|
||||
set sdc1 [make_result_file sdc_derate1.sdc]
|
||||
write_sdc -no_timestamp $sdc1
|
||||
puts "PASS: write_sdc with derates"
|
||||
|
||||
############################################################
|
||||
# Reset deratings
|
||||
############################################################
|
||||
unset_timing_derate
|
||||
puts "PASS: unset_timing_derate"
|
||||
|
||||
############################################################
|
||||
# Disable timing - cell from/to variants
|
||||
############################################################
|
||||
|
||||
# Disable entire lib cell
|
||||
set_disable_timing [get_lib_cells NangateOpenCellLibrary/BUF_X1]
|
||||
puts "PASS: disable lib cell all"
|
||||
|
||||
# Disable with from only
|
||||
set_disable_timing [get_lib_cells NangateOpenCellLibrary/INV_X1] -from A
|
||||
puts "PASS: disable lib cell from"
|
||||
|
||||
# Disable with to only
|
||||
set_disable_timing [get_lib_cells NangateOpenCellLibrary/NAND2_X1] -to ZN
|
||||
puts "PASS: disable lib cell to"
|
||||
|
||||
# Disable with from and to
|
||||
set_disable_timing [get_lib_cells NangateOpenCellLibrary/NOR2_X1] -from A1 -to ZN
|
||||
puts "PASS: disable lib cell from/to"
|
||||
|
||||
# Disable with from and to - second arc
|
||||
set_disable_timing [get_lib_cells NangateOpenCellLibrary/NOR2_X1] -from A2 -to ZN
|
||||
puts "PASS: disable lib cell from/to second"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report after lib cell disables"
|
||||
|
||||
############################################################
|
||||
# Disable timing - instance from/to variants
|
||||
############################################################
|
||||
|
||||
# Disable entire instance
|
||||
set_disable_timing [get_cells buf1]
|
||||
puts "PASS: disable instance all"
|
||||
|
||||
# Disable instance with from/to
|
||||
set_disable_timing [get_cells and1] -from A1 -to ZN
|
||||
set_disable_timing [get_cells and1] -from A2 -to ZN
|
||||
puts "PASS: disable instance from/to"
|
||||
|
||||
# Disable instance with from only
|
||||
set_disable_timing [get_cells or1] -from A1
|
||||
puts "PASS: disable instance from"
|
||||
|
||||
# Disable instance with to only
|
||||
set_disable_timing [get_cells nand1] -to ZN
|
||||
puts "PASS: disable instance to"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report after instance disables"
|
||||
|
||||
############################################################
|
||||
# Disable timing - pin
|
||||
############################################################
|
||||
set_disable_timing [get_pins inv1/A]
|
||||
puts "PASS: disable pin"
|
||||
|
||||
############################################################
|
||||
# Disable timing - port
|
||||
############################################################
|
||||
catch {
|
||||
set_disable_timing [get_ports in1]
|
||||
puts "PASS: disable port"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Write SDC with disables
|
||||
############################################################
|
||||
set sdc2 [make_result_file sdc_derate2.sdc]
|
||||
write_sdc -no_timestamp $sdc2
|
||||
puts "PASS: write_sdc with disables"
|
||||
|
||||
set sdc3 [make_result_file sdc_derate3.sdc]
|
||||
write_sdc -no_timestamp -compatible $sdc3
|
||||
puts "PASS: write_sdc compatible with disables"
|
||||
|
||||
############################################################
|
||||
# Unset all disables
|
||||
############################################################
|
||||
unset_disable_timing [get_lib_cells NangateOpenCellLibrary/BUF_X1]
|
||||
unset_disable_timing [get_lib_cells NangateOpenCellLibrary/INV_X1] -from A
|
||||
unset_disable_timing [get_lib_cells NangateOpenCellLibrary/NAND2_X1] -to ZN
|
||||
unset_disable_timing [get_lib_cells NangateOpenCellLibrary/NOR2_X1] -from A1 -to ZN
|
||||
unset_disable_timing [get_lib_cells NangateOpenCellLibrary/NOR2_X1] -from A2 -to ZN
|
||||
puts "PASS: unset lib cell disables"
|
||||
|
||||
unset_disable_timing [get_cells buf1]
|
||||
unset_disable_timing [get_cells and1] -from A1 -to ZN
|
||||
unset_disable_timing [get_cells and1] -from A2 -to ZN
|
||||
unset_disable_timing [get_cells or1] -from A1
|
||||
unset_disable_timing [get_cells nand1] -to ZN
|
||||
puts "PASS: unset instance disables"
|
||||
|
||||
unset_disable_timing [get_pins inv1/A]
|
||||
puts "PASS: unset pin disable"
|
||||
|
||||
############################################################
|
||||
# Clock gating check - global/clock/instance/pin
|
||||
############################################################
|
||||
set_clock_gating_check -setup 0.5 [current_design]
|
||||
set_clock_gating_check -hold 0.3 [current_design]
|
||||
puts "PASS: clock_gating_check global"
|
||||
|
||||
set_clock_gating_check -setup 0.4 [get_clocks clk1]
|
||||
set_clock_gating_check -hold 0.2 [get_clocks clk1]
|
||||
puts "PASS: clock_gating_check clock"
|
||||
|
||||
catch {
|
||||
set_clock_gating_check -setup 0.35 [get_cells reg1]
|
||||
set_clock_gating_check -hold 0.15 [get_cells reg1]
|
||||
puts "PASS: clock_gating_check instance"
|
||||
}
|
||||
|
||||
catch {
|
||||
set_clock_gating_check -setup 0.3 [get_pins reg2/CK]
|
||||
set_clock_gating_check -hold 0.1 [get_pins reg2/CK]
|
||||
puts "PASS: clock_gating_check pin"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Disabled edges sorted
|
||||
############################################################
|
||||
catch {
|
||||
set disabled [sta::disabled_edges_sorted]
|
||||
puts "disabled_edges_sorted count = [llength $disabled]"
|
||||
}
|
||||
puts "PASS: disabled_edges_sorted"
|
||||
|
||||
############################################################
|
||||
# Final write
|
||||
############################################################
|
||||
set sdc4 [make_result_file sdc_derate4.sdc]
|
||||
write_sdc -no_timestamp $sdc4
|
||||
puts "PASS: final write_sdc"
|
||||
|
||||
report_checks
|
||||
puts "PASS: final report"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,106 @@
|
||||
PASS: setup
|
||||
PASS: max_transition design
|
||||
PASS: max_transition ports
|
||||
PASS: max_transition clock clk1 clk_path/data_path
|
||||
PASS: max_transition clock clk2 rise/fall per path type
|
||||
PASS: max_capacitance design
|
||||
PASS: max_capacitance ports
|
||||
PASS: max_capacitance pin
|
||||
PASS: min_capacitance design
|
||||
PASS: min_capacitance port
|
||||
PASS: max_fanout design
|
||||
PASS: max_fanout ports
|
||||
PASS: set_max_area
|
||||
PASS: min_pulse_width global
|
||||
PASS: min_pulse_width clock high/low
|
||||
PASS: min_pulse_width clock same
|
||||
PASS: min_pulse_width pins
|
||||
PASS: min_pulse_width instance
|
||||
PASS: max_time_borrow clocks
|
||||
PASS: max_time_borrow pin
|
||||
PASS: max_time_borrow instance
|
||||
PASS: max_transition input ports
|
||||
PASS: write_sdc
|
||||
PASS: write_sdc compatible
|
||||
PASS: write_sdc digits 8
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: read_sdc roundtrip
|
||||
max slew
|
||||
|
||||
Pin Limit Slew Slack
|
||||
------------------------------------------------------------
|
||||
nor1/ZN 0.20 0.01 0.19 (MET)
|
||||
|
||||
max fanout
|
||||
|
||||
Pin Limit Fanout Slack
|
||||
---------------------------------------------------------
|
||||
in1 10 1 9 (MET)
|
||||
|
||||
max capacitance
|
||||
|
||||
Pin Limit Cap Slack
|
||||
------------------------------------------------------------
|
||||
or1/ZN 0.20 3.32 -3.12 (VIOLATED)
|
||||
|
||||
PASS: report_check_types
|
||||
Required Actual
|
||||
Pin Width Width Slack
|
||||
------------------------------------------------------------
|
||||
reg2/CK (high) 0.35 5.00 4.65 (MET)
|
||||
|
||||
PASS: report_check_types pulse_width
|
||||
PASS: write_sdc after re-read
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,192 @@
|
||||
# Test design rules, limits, and WriteSdc.cc design rules paths.
|
||||
# Targets:
|
||||
# Sdc.cc: setSlewLimit (port, cell, clock with clk_data/rf),
|
||||
# setCapacitanceLimit (port, pin, cell),
|
||||
# setFanoutLimit (port, cell), setMaxArea,
|
||||
# slewLimit, capacitanceLimit, fanoutLimit,
|
||||
# setMinPulseWidth (global, pin, clock, instance),
|
||||
# setLatchBorrowLimit (pin, instance, clock)
|
||||
# WriteSdc.cc: writeDesignRules, writeMinPulseWidths,
|
||||
# writeLatchBorowLimits, writeSlewLimits, writeClkSlewLimits,
|
||||
# writeClkSlewLimit, writeCapLimits (min/max with port/pin),
|
||||
# writeFanoutLimits (min/max with port), writeMaxArea,
|
||||
# writeMinPulseWidth (hi/low variants)
|
||||
# Clock.cc: slewLimit with PathClkOrData
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in2]
|
||||
set_input_delay -clock clk2 2.0 [get_ports in3]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 3.0 [get_ports out2]
|
||||
puts "PASS: setup"
|
||||
|
||||
############################################################
|
||||
# Max/min transition limits on design, ports, and clocks
|
||||
############################################################
|
||||
set_max_transition 0.5 [current_design]
|
||||
puts "PASS: max_transition design"
|
||||
|
||||
set_max_transition 0.3 [get_ports out1]
|
||||
set_max_transition 0.35 [get_ports out2]
|
||||
puts "PASS: max_transition ports"
|
||||
|
||||
# Clock-specific slew limits (exercises writeClkSlewLimits)
|
||||
set_max_transition -clock_path 0.2 [get_clocks clk1]
|
||||
set_max_transition -data_path 0.4 [get_clocks clk1]
|
||||
puts "PASS: max_transition clock clk1 clk_path/data_path"
|
||||
|
||||
# Per-rise/fall on clock data path
|
||||
set_max_transition -clock_path -rise 0.18 [get_clocks clk2]
|
||||
set_max_transition -clock_path -fall 0.22 [get_clocks clk2]
|
||||
set_max_transition -data_path -rise 0.38 [get_clocks clk2]
|
||||
set_max_transition -data_path -fall 0.42 [get_clocks clk2]
|
||||
puts "PASS: max_transition clock clk2 rise/fall per path type"
|
||||
|
||||
############################################################
|
||||
# Max/min capacitance limits
|
||||
############################################################
|
||||
set_max_capacitance 0.2 [current_design]
|
||||
puts "PASS: max_capacitance design"
|
||||
|
||||
set_max_capacitance 0.1 [get_ports out1]
|
||||
set_max_capacitance 0.15 [get_ports out2]
|
||||
puts "PASS: max_capacitance ports"
|
||||
|
||||
# Pin-level cap limits
|
||||
catch {
|
||||
set_max_capacitance 0.08 [get_pins reg1/Q]
|
||||
puts "PASS: max_capacitance pin"
|
||||
}
|
||||
|
||||
# Min capacitance
|
||||
catch {
|
||||
set_min_capacitance 0.001 [current_design]
|
||||
puts "PASS: min_capacitance design"
|
||||
}
|
||||
|
||||
catch {
|
||||
set_min_capacitance 0.0005 [get_ports out1]
|
||||
puts "PASS: min_capacitance port"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Max/min fanout limits
|
||||
############################################################
|
||||
set_max_fanout 20 [current_design]
|
||||
puts "PASS: max_fanout design"
|
||||
|
||||
set_max_fanout 10 [get_ports in1]
|
||||
set_max_fanout 15 [get_ports in2]
|
||||
puts "PASS: max_fanout ports"
|
||||
|
||||
catch {
|
||||
# Cell-level fanout limit
|
||||
set_max_fanout 8 [get_lib_cells NangateOpenCellLibrary/INV_X1]
|
||||
puts "PASS: max_fanout cell"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Max area
|
||||
############################################################
|
||||
set_max_area 500.0
|
||||
puts "PASS: set_max_area"
|
||||
|
||||
############################################################
|
||||
# Min pulse width on various targets
|
||||
############################################################
|
||||
|
||||
# Global min pulse width
|
||||
set_min_pulse_width 0.5
|
||||
puts "PASS: min_pulse_width global"
|
||||
|
||||
# Clock min pulse width with high/low
|
||||
set_min_pulse_width -high 0.6 [get_clocks clk1]
|
||||
set_min_pulse_width -low 0.4 [get_clocks clk1]
|
||||
puts "PASS: min_pulse_width clock high/low"
|
||||
|
||||
# Same value for high and low (exercises equal path)
|
||||
set_min_pulse_width 0.7 [get_clocks clk2]
|
||||
puts "PASS: min_pulse_width clock same"
|
||||
|
||||
# Pin min pulse width
|
||||
catch {
|
||||
set_min_pulse_width 0.3 [get_pins reg1/CK]
|
||||
set_min_pulse_width -high 0.35 [get_pins reg2/CK]
|
||||
set_min_pulse_width -low 0.25 [get_pins reg2/CK]
|
||||
puts "PASS: min_pulse_width pins"
|
||||
}
|
||||
|
||||
# Instance min pulse width
|
||||
catch {
|
||||
set_min_pulse_width 0.45 [get_cells reg3]
|
||||
puts "PASS: min_pulse_width instance"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Latch borrow limits
|
||||
############################################################
|
||||
set_max_time_borrow 2.0 [get_clocks clk1]
|
||||
set_max_time_borrow 1.5 [get_clocks clk2]
|
||||
puts "PASS: max_time_borrow clocks"
|
||||
|
||||
set_max_time_borrow 1.0 [get_pins reg1/D]
|
||||
puts "PASS: max_time_borrow pin"
|
||||
|
||||
catch {
|
||||
set_max_time_borrow 1.2 [get_cells reg2]
|
||||
puts "PASS: max_time_borrow instance"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Port slew limits
|
||||
############################################################
|
||||
set_max_transition 0.25 [get_ports in1]
|
||||
set_max_transition 0.28 [get_ports in2]
|
||||
puts "PASS: max_transition input ports"
|
||||
|
||||
############################################################
|
||||
# Write SDC (exercises all design rule writing paths)
|
||||
############################################################
|
||||
set sdc1 [make_result_file sdc_design_rules1.sdc]
|
||||
write_sdc -no_timestamp $sdc1
|
||||
puts "PASS: write_sdc"
|
||||
|
||||
set sdc2 [make_result_file sdc_design_rules2.sdc]
|
||||
write_sdc -no_timestamp -compatible $sdc2
|
||||
puts "PASS: write_sdc compatible"
|
||||
|
||||
set sdc3 [make_result_file sdc_design_rules3.sdc]
|
||||
write_sdc -no_timestamp -digits 8 $sdc3
|
||||
puts "PASS: write_sdc digits 8"
|
||||
|
||||
############################################################
|
||||
# Read back and verify
|
||||
############################################################
|
||||
read_sdc $sdc1
|
||||
report_checks
|
||||
puts "PASS: read_sdc roundtrip"
|
||||
|
||||
############################################################
|
||||
# Check reporting
|
||||
############################################################
|
||||
report_check_types -max_slew -max_capacitance -max_fanout
|
||||
puts "PASS: report_check_types"
|
||||
|
||||
report_check_types -min_pulse_width -min_period
|
||||
puts "PASS: report_check_types pulse_width"
|
||||
|
||||
############################################################
|
||||
# Final write after read
|
||||
############################################################
|
||||
set sdc4 [make_result_file sdc_design_rules4.sdc]
|
||||
write_sdc -no_timestamp $sdc4
|
||||
puts "PASS: write_sdc after re-read"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,325 @@
|
||||
PASS: setup
|
||||
PASS: disable buf1
|
||||
PASS: disable inv1
|
||||
PASS: disable and1
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: report after disabling instances
|
||||
PASS: unset disable instances
|
||||
PASS: disable pins
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: report after disabling pins
|
||||
PASS: unset disable pins
|
||||
PASS: disable lib cell BUF_X1
|
||||
PASS: disable lib cell INV_X1 from/to
|
||||
PASS: disable lib cell NAND2_X1 from/to
|
||||
PASS: disable lib cell NOR2_X1
|
||||
PASS: disable lib cell AND2_X1 from/to
|
||||
PASS: write_sdc with disable
|
||||
PASS: unset all lib cell disables
|
||||
PASS: case_analysis 0 on in1
|
||||
PASS: case_analysis 1 on in2
|
||||
PASS: case_analysis rising on in3
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: report after case analysis
|
||||
PASS: write_sdc with case analysis
|
||||
PASS: unset case analysis
|
||||
PASS: case_analysis falling on in1
|
||||
PASS: write_sdc with falling case analysis
|
||||
PASS: unset falling case analysis
|
||||
PASS: set_logic_zero in1
|
||||
PASS: set_logic_one in2
|
||||
PASS: set_logic_dc in3
|
||||
PASS: write_sdc with logic values
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: report after logic values
|
||||
PASS: data_check setup
|
||||
PASS: data_check hold
|
||||
PASS: data_check rise_from setup
|
||||
PASS: data_check fall_to hold
|
||||
PASS: write_sdc with data checks
|
||||
Warning: sdc_disable_case.tcl line 1, object 'sdc_test2' not found.
|
||||
Warning: sdc_disable_case.tcl line 1, object 'sdc_test2' not found.
|
||||
PASS: clock_gating_check design
|
||||
PASS: clock_gating_check clocks
|
||||
PASS: clock_gating_check instance
|
||||
PASS: clock_gating_check pin
|
||||
PASS: write_sdc with clock gating
|
||||
PASS: set_ideal_network
|
||||
PASS: set_ideal_transition
|
||||
PASS: min pulse width on clock
|
||||
PASS: min pulse width on clk2
|
||||
PASS: min pulse width on pin
|
||||
PASS: min pulse width on instance
|
||||
PASS: max_time_borrow on clocks
|
||||
PASS: max_time_borrow on pin
|
||||
PASS: max_time_borrow on instance
|
||||
PASS: final write_sdc
|
||||
PASS: final write_sdc -compatible
|
||||
PASS: final write_sdc -digits 6
|
||||
Startpoint: in3 (input port clocked by clk2)
|
||||
Endpoint: reg2 (rising edge-triggered data to data check clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk2 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
2.00 2.00 v input external delay
|
||||
0.00 2.00 v in3 (in)
|
||||
0.05 2.05 v or1/ZN (OR2_X1)
|
||||
0.03 2.07 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 2.07 ^ reg2/D (DFF_X1)
|
||||
2.07 data arrival time
|
||||
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg1/Q (DFF_X1)
|
||||
-0.60 -0.52 data check setup time
|
||||
-0.52 data required time
|
||||
---------------------------------------------------------
|
||||
-0.52 data required time
|
||||
-2.07 data arrival time
|
||||
---------------------------------------------------------
|
||||
-2.59 slack (VIOLATED)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: final report_checks
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,305 @@
|
||||
# Test disable timing, case analysis, logic values, data checks
|
||||
# Targets: Sdc.cc (setDisableTiming, case analysis, logic values,
|
||||
# setDataCheck, removeDataCheck, clockGatingMargin*),
|
||||
# DisabledPorts.cc, DataCheck.cc,
|
||||
# WriteSdc.cc (writeDisables, writeCaseAnalysis, writeConstants,
|
||||
# writeDataChecks, writeClockGatingCheck)
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
# Setup
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in2]
|
||||
set_input_delay -clock clk2 2.0 [get_ports in3]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 3.0 [get_ports out2]
|
||||
puts "PASS: setup"
|
||||
|
||||
############################################################
|
||||
# Disable timing - instances
|
||||
############################################################
|
||||
|
||||
set_disable_timing [get_cells buf1]
|
||||
puts "PASS: disable buf1"
|
||||
|
||||
set_disable_timing [get_cells inv1]
|
||||
puts "PASS: disable inv1"
|
||||
|
||||
set_disable_timing [get_cells and1]
|
||||
puts "PASS: disable and1"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report after disabling instances"
|
||||
|
||||
# Unset and re-enable
|
||||
unset_disable_timing [get_cells buf1]
|
||||
unset_disable_timing [get_cells inv1]
|
||||
unset_disable_timing [get_cells and1]
|
||||
puts "PASS: unset disable instances"
|
||||
|
||||
############################################################
|
||||
# Disable timing - pins
|
||||
############################################################
|
||||
|
||||
set_disable_timing [get_pins buf1/A]
|
||||
set_disable_timing [get_pins inv1/A]
|
||||
set_disable_timing [get_pins and1/A1]
|
||||
puts "PASS: disable pins"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report after disabling pins"
|
||||
|
||||
unset_disable_timing [get_pins buf1/A]
|
||||
unset_disable_timing [get_pins inv1/A]
|
||||
unset_disable_timing [get_pins and1/A1]
|
||||
puts "PASS: unset disable pins"
|
||||
|
||||
############################################################
|
||||
# Disable timing - lib cells
|
||||
############################################################
|
||||
|
||||
set_disable_timing [get_lib_cells NangateOpenCellLibrary/BUF_X1]
|
||||
puts "PASS: disable lib cell BUF_X1"
|
||||
|
||||
set_disable_timing [get_lib_cells NangateOpenCellLibrary/INV_X1] -from A -to ZN
|
||||
puts "PASS: disable lib cell INV_X1 from/to"
|
||||
|
||||
set_disable_timing [get_lib_cells NangateOpenCellLibrary/NAND2_X1] -from A1 -to ZN
|
||||
puts "PASS: disable lib cell NAND2_X1 from/to"
|
||||
|
||||
set_disable_timing [get_lib_cells NangateOpenCellLibrary/NOR2_X1]
|
||||
puts "PASS: disable lib cell NOR2_X1"
|
||||
|
||||
set_disable_timing [get_lib_cells NangateOpenCellLibrary/AND2_X1] -from A1 -to ZN
|
||||
puts "PASS: disable lib cell AND2_X1 from/to"
|
||||
|
||||
# Write SDC with disable timing
|
||||
set sdc_file1 [make_result_file sdc_disable1.sdc]
|
||||
write_sdc -no_timestamp $sdc_file1
|
||||
puts "PASS: write_sdc with disable"
|
||||
|
||||
# Unset all lib cell disables
|
||||
unset_disable_timing [get_lib_cells NangateOpenCellLibrary/BUF_X1]
|
||||
unset_disable_timing [get_lib_cells NangateOpenCellLibrary/INV_X1] -from A -to ZN
|
||||
unset_disable_timing [get_lib_cells NangateOpenCellLibrary/NAND2_X1] -from A1 -to ZN
|
||||
unset_disable_timing [get_lib_cells NangateOpenCellLibrary/NOR2_X1]
|
||||
unset_disable_timing [get_lib_cells NangateOpenCellLibrary/AND2_X1] -from A1 -to ZN
|
||||
puts "PASS: unset all lib cell disables"
|
||||
|
||||
############################################################
|
||||
# Case analysis
|
||||
############################################################
|
||||
|
||||
# case_analysis 0
|
||||
set_case_analysis 0 [get_ports in1]
|
||||
puts "PASS: case_analysis 0 on in1"
|
||||
|
||||
# case_analysis 1
|
||||
set_case_analysis 1 [get_ports in2]
|
||||
puts "PASS: case_analysis 1 on in2"
|
||||
|
||||
# case_analysis rising
|
||||
set_case_analysis rising [get_ports in3]
|
||||
puts "PASS: case_analysis rising on in3"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report after case analysis"
|
||||
|
||||
# Write SDC with case analysis (exercises writeCaseAnalysis)
|
||||
set sdc_file2 [make_result_file sdc_case1.sdc]
|
||||
write_sdc -no_timestamp $sdc_file2
|
||||
puts "PASS: write_sdc with case analysis"
|
||||
|
||||
# Unset case analysis
|
||||
unset_case_analysis [get_ports in1]
|
||||
unset_case_analysis [get_ports in2]
|
||||
unset_case_analysis [get_ports in3]
|
||||
puts "PASS: unset case analysis"
|
||||
|
||||
# case_analysis falling
|
||||
set_case_analysis falling [get_ports in1]
|
||||
puts "PASS: case_analysis falling on in1"
|
||||
|
||||
set sdc_file3 [make_result_file sdc_case2.sdc]
|
||||
write_sdc -no_timestamp $sdc_file3
|
||||
puts "PASS: write_sdc with falling case analysis"
|
||||
|
||||
unset_case_analysis [get_ports in1]
|
||||
puts "PASS: unset falling case analysis"
|
||||
|
||||
############################################################
|
||||
# Logic values (set_logic_zero, set_logic_one, set_logic_dc)
|
||||
############################################################
|
||||
|
||||
set_logic_zero [get_ports in1]
|
||||
puts "PASS: set_logic_zero in1"
|
||||
|
||||
set_logic_one [get_ports in2]
|
||||
puts "PASS: set_logic_one in2"
|
||||
|
||||
# set_logic_dc (don't care)
|
||||
catch {
|
||||
set_logic_dc [get_ports in3]
|
||||
puts "PASS: set_logic_dc in3"
|
||||
}
|
||||
|
||||
# Write SDC with logic values (exercises writeConstants)
|
||||
set sdc_file4 [make_result_file sdc_logic1.sdc]
|
||||
write_sdc -no_timestamp $sdc_file4
|
||||
puts "PASS: write_sdc with logic values"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report after logic values"
|
||||
|
||||
############################################################
|
||||
# Data checks
|
||||
############################################################
|
||||
|
||||
catch {
|
||||
set_data_check -from [get_pins reg1/Q] -to [get_pins reg2/D] -setup 0.5
|
||||
puts "PASS: data_check setup"
|
||||
}
|
||||
|
||||
catch {
|
||||
set_data_check -from [get_pins reg1/Q] -to [get_pins reg2/D] -hold 0.3
|
||||
puts "PASS: data_check hold"
|
||||
}
|
||||
|
||||
catch {
|
||||
set_data_check -rise_from [get_pins reg1/Q] -to [get_pins reg2/D] -setup 0.6
|
||||
puts "PASS: data_check rise_from setup"
|
||||
}
|
||||
|
||||
catch {
|
||||
set_data_check -from [get_pins reg1/Q] -fall_to [get_pins reg2/D] -hold 0.25
|
||||
puts "PASS: data_check fall_to hold"
|
||||
}
|
||||
|
||||
# Write with data checks
|
||||
set sdc_file5 [make_result_file sdc_datacheck1.sdc]
|
||||
write_sdc -no_timestamp $sdc_file5
|
||||
puts "PASS: write_sdc with data checks"
|
||||
|
||||
# Remove data checks
|
||||
catch {
|
||||
remove_data_check -from [get_pins reg1/Q] -to [get_pins reg2/D] -setup
|
||||
puts "PASS: remove_data_check setup"
|
||||
}
|
||||
|
||||
catch {
|
||||
remove_data_check -from [get_pins reg1/Q] -to [get_pins reg2/D] -hold
|
||||
puts "PASS: remove_data_check hold"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Clock gating check (exercises clockGatingMargin paths)
|
||||
############################################################
|
||||
|
||||
# Design-level
|
||||
set_clock_gating_check -setup 0.5 [current_design]
|
||||
set_clock_gating_check -hold 0.3 [current_design]
|
||||
puts "PASS: clock_gating_check design"
|
||||
|
||||
# Clock-level
|
||||
set_clock_gating_check -setup 0.4 [get_clocks clk1]
|
||||
set_clock_gating_check -hold 0.2 [get_clocks clk1]
|
||||
set_clock_gating_check -setup 0.35 [get_clocks clk2]
|
||||
set_clock_gating_check -hold 0.15 [get_clocks clk2]
|
||||
puts "PASS: clock_gating_check clocks"
|
||||
|
||||
# Instance-level
|
||||
catch {
|
||||
set_clock_gating_check -setup 0.3 [get_cells reg1]
|
||||
set_clock_gating_check -hold 0.1 [get_cells reg1]
|
||||
puts "PASS: clock_gating_check instance"
|
||||
}
|
||||
|
||||
# Pin-level
|
||||
catch {
|
||||
set_clock_gating_check -setup 0.25 [get_pins reg1/CK]
|
||||
set_clock_gating_check -hold 0.08 [get_pins reg1/CK]
|
||||
puts "PASS: clock_gating_check pin"
|
||||
}
|
||||
|
||||
# Write SDC with clock gating
|
||||
set sdc_file6 [make_result_file sdc_clkgate1.sdc]
|
||||
write_sdc -no_timestamp $sdc_file6
|
||||
puts "PASS: write_sdc with clock gating"
|
||||
|
||||
############################################################
|
||||
# set_ideal_network / set_ideal_transition
|
||||
############################################################
|
||||
|
||||
set_ideal_network [get_ports clk1]
|
||||
set_ideal_network [get_ports clk2]
|
||||
puts "PASS: set_ideal_network"
|
||||
|
||||
catch {
|
||||
set_ideal_transition 0.0 [get_ports clk1]
|
||||
set_ideal_transition 0.05 [get_ports clk2]
|
||||
puts "PASS: set_ideal_transition"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Min pulse width on various objects
|
||||
############################################################
|
||||
|
||||
set_min_pulse_width 1.0 [get_clocks clk1]
|
||||
set_min_pulse_width -high 0.6 [get_clocks clk1]
|
||||
set_min_pulse_width -low 0.4 [get_clocks clk1]
|
||||
puts "PASS: min pulse width on clock"
|
||||
|
||||
set_min_pulse_width 0.8 [get_clocks clk2]
|
||||
puts "PASS: min pulse width on clk2"
|
||||
|
||||
catch {
|
||||
set_min_pulse_width 0.5 [get_pins reg1/CK]
|
||||
puts "PASS: min pulse width on pin"
|
||||
}
|
||||
|
||||
catch {
|
||||
set_min_pulse_width 0.6 [get_cells reg1]
|
||||
puts "PASS: min pulse width on instance"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Latch borrow limits on various objects
|
||||
############################################################
|
||||
|
||||
set_max_time_borrow 2.0 [get_clocks clk1]
|
||||
set_max_time_borrow 1.5 [get_clocks clk2]
|
||||
puts "PASS: max_time_borrow on clocks"
|
||||
|
||||
set_max_time_borrow 1.0 [get_pins reg1/D]
|
||||
puts "PASS: max_time_borrow on pin"
|
||||
|
||||
catch {
|
||||
set_max_time_borrow 1.2 [get_cells reg2]
|
||||
puts "PASS: max_time_borrow on instance"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Comprehensive write with all constraints
|
||||
############################################################
|
||||
|
||||
set sdc_final [make_result_file sdc_disable_case_final.sdc]
|
||||
write_sdc -no_timestamp $sdc_final
|
||||
puts "PASS: final write_sdc"
|
||||
|
||||
set sdc_compat [make_result_file sdc_disable_case_compat.sdc]
|
||||
write_sdc -no_timestamp -compatible $sdc_compat
|
||||
puts "PASS: final write_sdc -compatible"
|
||||
|
||||
set sdc_d6 [make_result_file sdc_disable_case_d6.sdc]
|
||||
write_sdc -no_timestamp -digits 6 $sdc_d6
|
||||
puts "PASS: final write_sdc -digits 6"
|
||||
|
||||
report_checks
|
||||
puts "PASS: final report_checks"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,303 @@
|
||||
PASS: setup
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: input transition
|
||||
PASS: set_drive in1
|
||||
PASS: set_drive in2 rise/fall
|
||||
PASS: set_drive in3 rise/fall min/max
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: report after drive resistance
|
||||
PASS: set_driving_cell BUF_X1
|
||||
PASS: set_driving_cell INV_X1
|
||||
PASS: set_driving_cell AND2_X1 with from_pin
|
||||
PASS: set_driving_cell BUF_X4 with slews
|
||||
PASS: set_driving_cell with -library
|
||||
PASS: set_driving_cell rise/fall
|
||||
PASS: set_driving_cell min/max
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: report after driving cells
|
||||
PASS: write_sdc
|
||||
PASS: write_sdc compatible
|
||||
PASS: set_operating_conditions typical
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: report after operating conditions
|
||||
PASS: analysis type single
|
||||
PASS: analysis type bc_wc
|
||||
PASS: analysis type ocv
|
||||
PASS: reset to single
|
||||
PASS: operating conditions analysis_type bc_wc
|
||||
PASS: operating conditions analysis_type single
|
||||
PASS: set_pvt buf1
|
||||
PASS: set_pvt inv1
|
||||
PASS: wire_load_model
|
||||
PASS: wire_load_mode enclosed
|
||||
PASS: wire_load_mode top
|
||||
PASS: wire_load_mode segmented
|
||||
PASS: propagate_all_clocks
|
||||
PASS: write_sdc with all environment
|
||||
PASS: write_sdc digits 6
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: read_sdc roundtrip
|
||||
PASS: port ext cap
|
||||
PASS: port fanout number
|
||||
PASS: final write_sdc
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,221 @@
|
||||
# Test input drive, driving cell, input slew, PVT, operating conditions,
|
||||
# analysis type, and their write_sdc paths.
|
||||
# Targets:
|
||||
# InputDrive.cc: setSlew, setDriveResistance, driveResistance,
|
||||
# hasDriveResistance, driveResistanceMinMaxEqual,
|
||||
# setDriveCell, driveCell, hasDriveCell, driveCellsEqual,
|
||||
# slew, InputDriveCell methods (equal, setLibrary, setCell,
|
||||
# setFromPort, setToPort, setFromSlews)
|
||||
# Sdc.cc: setInputSlew, setDriveResistance, setDriveCell,
|
||||
# setOperatingConditions, setAnalysisType, setPvt,
|
||||
# findInputDrive, operatingConditions
|
||||
# WriteSdc.cc: writeDriveResistances, writeDrivingCells,
|
||||
# writeDrivingCell, writeInputTransitions,
|
||||
# writeOperatingConditions, writeVariables
|
||||
# Sdc.i: set_analysis_type_cmd, set_operating_conditions_cmd,
|
||||
# set_instance_pvt, operating_condition_analysis_type,
|
||||
# set_drive_cell_cmd, set_drive_resistance_cmd,
|
||||
# set_input_slew_cmd
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in2]
|
||||
set_input_delay -clock clk2 2.0 [get_ports in3]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 3.0 [get_ports out2]
|
||||
puts "PASS: setup"
|
||||
|
||||
############################################################
|
||||
# Input transition / slew
|
||||
############################################################
|
||||
set_input_transition 0.15 [get_ports in1]
|
||||
set_input_transition -rise -max 0.12 [get_ports in2]
|
||||
set_input_transition -fall -min 0.08 [get_ports in2]
|
||||
set_input_transition -rise 0.10 [get_ports in3]
|
||||
set_input_transition -fall 0.11 [get_ports in3]
|
||||
set_input_transition -rise -min 0.06 [get_ports in1]
|
||||
set_input_transition -fall -max 0.18 [get_ports in1]
|
||||
report_checks
|
||||
puts "PASS: input transition"
|
||||
|
||||
############################################################
|
||||
# Drive resistance
|
||||
############################################################
|
||||
set_drive 100 [get_ports in1]
|
||||
puts "PASS: set_drive in1"
|
||||
|
||||
set_drive -rise 120 [get_ports in2]
|
||||
set_drive -fall 130 [get_ports in2]
|
||||
puts "PASS: set_drive in2 rise/fall"
|
||||
|
||||
set_drive -rise -min 80 [get_ports in3]
|
||||
set_drive -rise -max 100 [get_ports in3]
|
||||
set_drive -fall -min 90 [get_ports in3]
|
||||
set_drive -fall -max 110 [get_ports in3]
|
||||
puts "PASS: set_drive in3 rise/fall min/max"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report after drive resistance"
|
||||
|
||||
############################################################
|
||||
# Driving cells - basic
|
||||
############################################################
|
||||
set_driving_cell -lib_cell BUF_X1 [get_ports in1]
|
||||
puts "PASS: set_driving_cell BUF_X1"
|
||||
|
||||
set_driving_cell -lib_cell INV_X1 -pin ZN [get_ports in2]
|
||||
puts "PASS: set_driving_cell INV_X1"
|
||||
|
||||
# Driving cell with -from_pin
|
||||
set_driving_cell -lib_cell AND2_X1 -from_pin A1 -pin ZN [get_ports in3]
|
||||
puts "PASS: set_driving_cell AND2_X1 with from_pin"
|
||||
|
||||
# Driving cell with input transition slews
|
||||
set_driving_cell -lib_cell BUF_X4 -pin Z \
|
||||
-input_transition_rise 0.05 -input_transition_fall 0.06 \
|
||||
[get_ports in1]
|
||||
puts "PASS: set_driving_cell BUF_X4 with slews"
|
||||
|
||||
# Driving cell with -library
|
||||
set_driving_cell -library NangateOpenCellLibrary -lib_cell INV_X2 -pin ZN \
|
||||
[get_ports in2]
|
||||
puts "PASS: set_driving_cell with -library"
|
||||
|
||||
# Driving cell with rise/fall
|
||||
set_driving_cell -lib_cell BUF_X2 -pin Z -rise [get_ports in3]
|
||||
set_driving_cell -lib_cell BUF_X8 -pin Z -fall [get_ports in3]
|
||||
puts "PASS: set_driving_cell rise/fall"
|
||||
|
||||
# Driving cell with min/max
|
||||
set_driving_cell -lib_cell INV_X4 -pin ZN -min [get_ports in1]
|
||||
set_driving_cell -lib_cell INV_X8 -pin ZN -max [get_ports in1]
|
||||
puts "PASS: set_driving_cell min/max"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report after driving cells"
|
||||
|
||||
############################################################
|
||||
# Write SDC - exercises writing drive resistance and driving cell
|
||||
############################################################
|
||||
set sdc1 [make_result_file sdc_drive_input1.sdc]
|
||||
write_sdc -no_timestamp $sdc1
|
||||
puts "PASS: write_sdc"
|
||||
|
||||
set sdc2 [make_result_file sdc_drive_input2.sdc]
|
||||
write_sdc -no_timestamp -compatible $sdc2
|
||||
puts "PASS: write_sdc compatible"
|
||||
|
||||
############################################################
|
||||
# Operating conditions
|
||||
############################################################
|
||||
set_operating_conditions typical
|
||||
puts "PASS: set_operating_conditions typical"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report after operating conditions"
|
||||
|
||||
############################################################
|
||||
# Analysis type
|
||||
############################################################
|
||||
sta::set_analysis_type_cmd single
|
||||
puts "PASS: analysis type single"
|
||||
|
||||
sta::set_analysis_type_cmd bc_wc
|
||||
puts "PASS: analysis type bc_wc"
|
||||
|
||||
sta::set_analysis_type_cmd on_chip_variation
|
||||
puts "PASS: analysis type ocv"
|
||||
|
||||
# Reset to single
|
||||
sta::set_analysis_type_cmd single
|
||||
puts "PASS: reset to single"
|
||||
|
||||
# Analysis type through set_operating_conditions
|
||||
set_operating_conditions -analysis_type bc_wc
|
||||
puts "PASS: operating conditions analysis_type bc_wc"
|
||||
|
||||
set_operating_conditions -analysis_type single
|
||||
puts "PASS: operating conditions analysis_type single"
|
||||
|
||||
############################################################
|
||||
# PVT settings on instances
|
||||
############################################################
|
||||
catch {
|
||||
set_pvt [get_cells buf1] -process 1.0 -voltage 1.1 -temperature 25.0
|
||||
puts "PASS: set_pvt buf1"
|
||||
}
|
||||
|
||||
catch {
|
||||
set_pvt [get_cells inv1] -process 0.9 -voltage 1.0 -temperature 85.0
|
||||
puts "PASS: set_pvt inv1"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Wire load model and mode
|
||||
############################################################
|
||||
catch {
|
||||
set_wire_load_model -name "5K_hvratio_1_1"
|
||||
puts "PASS: wire_load_model"
|
||||
}
|
||||
|
||||
set_wire_load_mode enclosed
|
||||
puts "PASS: wire_load_mode enclosed"
|
||||
|
||||
set_wire_load_mode top
|
||||
puts "PASS: wire_load_mode top"
|
||||
|
||||
set_wire_load_mode segmented
|
||||
puts "PASS: wire_load_mode segmented"
|
||||
|
||||
############################################################
|
||||
# Propagate all clocks variable
|
||||
############################################################
|
||||
sta::set_propagate_all_clocks 1
|
||||
puts "PASS: propagate_all_clocks"
|
||||
|
||||
############################################################
|
||||
# Write after all environment settings
|
||||
############################################################
|
||||
set sdc3 [make_result_file sdc_drive_input3.sdc]
|
||||
write_sdc -no_timestamp $sdc3
|
||||
puts "PASS: write_sdc with all environment"
|
||||
|
||||
# Write with digits
|
||||
set sdc4 [make_result_file sdc_drive_input4.sdc]
|
||||
write_sdc -no_timestamp -digits 6 $sdc4
|
||||
puts "PASS: write_sdc digits 6"
|
||||
|
||||
############################################################
|
||||
# Read back and verify
|
||||
############################################################
|
||||
read_sdc $sdc1
|
||||
report_checks
|
||||
puts "PASS: read_sdc roundtrip"
|
||||
|
||||
############################################################
|
||||
# Port external capacitance
|
||||
############################################################
|
||||
set_load -pin_load 0.05 [get_ports out1]
|
||||
set_load -wire_load 0.02 [get_ports out1]
|
||||
set_load -pin_load -rise 0.04 [get_ports out2]
|
||||
set_load -pin_load -fall 0.045 [get_ports out2]
|
||||
puts "PASS: port ext cap"
|
||||
|
||||
set_port_fanout_number 4 [get_ports out1]
|
||||
set_port_fanout_number 6 [get_ports out2]
|
||||
puts "PASS: port fanout number"
|
||||
|
||||
############################################################
|
||||
# Final write
|
||||
############################################################
|
||||
set sdc5 [make_result_file sdc_drive_input5.sdc]
|
||||
write_sdc -no_timestamp $sdc5
|
||||
puts "PASS: final write_sdc"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,235 @@
|
||||
PASS: basic setup
|
||||
PASS: set_driving_cell BUF_X1
|
||||
PASS: set_driving_cell INV_X1
|
||||
PASS: set_driving_cell BUF_X4
|
||||
No paths found.
|
||||
PASS: report_checks after set_driving_cell
|
||||
PASS: set_load
|
||||
PASS: set_load -pin_load
|
||||
No paths found.
|
||||
PASS: report_checks after set_load
|
||||
PASS: set_input_transition
|
||||
PASS: set_input_transition -rise
|
||||
PASS: set_input_transition -fall
|
||||
PASS: set_input_transition -min
|
||||
PASS: set_input_transition -max
|
||||
No paths found.
|
||||
PASS: report_checks after set_input_transition
|
||||
PASS: set_max_capacitance port
|
||||
PASS: set_max_capacitance design
|
||||
PASS: set_max_transition port
|
||||
PASS: set_max_transition design
|
||||
PASS: set_max_transition -clock_path
|
||||
PASS: set_max_transition -data_path
|
||||
PASS: set_max_fanout port
|
||||
PASS: set_max_fanout design
|
||||
PASS: set_case_analysis 0
|
||||
No paths found.
|
||||
PASS: report_checks after case_analysis 0
|
||||
PASS: unset_case_analysis
|
||||
PASS: set_case_analysis 1
|
||||
No paths found.
|
||||
PASS: report_checks after case_analysis 1
|
||||
PASS: unset_case_analysis second
|
||||
PASS: set_logic_zero
|
||||
PASS: set_logic_one
|
||||
PASS: set_logic_dc
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks after logic values
|
||||
PASS: set_ideal_network
|
||||
PASS: set_operating_conditions
|
||||
PASS: set_wire_load_model
|
||||
PASS: set_wire_load_mode enclosed
|
||||
PASS: set_timing_derate -early
|
||||
PASS: set_timing_derate -late
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.09 0.09 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.09 ^ out1 (out)
|
||||
0.09 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.09 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.91 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks after timing derate
|
||||
PASS: unset_timing_derate
|
||||
PASS: set_max_area
|
||||
PASS: set_disable_timing instance
|
||||
PASS: unset_disable_timing instance
|
||||
PASS: set_disable_timing pin
|
||||
PASS: unset_disable_timing pin
|
||||
PASS: set_min_pulse_width
|
||||
PASS: set_port_fanout_number
|
||||
PASS: set_resistance -min
|
||||
PASS: set_resistance -max
|
||||
PASS: set_voltage
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: final report_checks
|
||||
max slew
|
||||
|
||||
Pin Limit Slew Slack
|
||||
------------------------------------------------------------
|
||||
nor1/ZN 0.20 0.01 0.18 (MET)
|
||||
|
||||
max fanout
|
||||
|
||||
Pin Limit Fanout Slack
|
||||
---------------------------------------------------------
|
||||
in1 10 1 9 (MET)
|
||||
|
||||
max capacitance
|
||||
|
||||
Pin Limit Cap Slack
|
||||
------------------------------------------------------------
|
||||
or1/ZN 0.20 4.01 -3.81 (VIOLATED)
|
||||
|
||||
PASS: report_check_types
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,235 @@
|
||||
# Test design environment SDC commands for code coverage
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
# Setup clock
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in2]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in3]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 3.0 [get_ports out2]
|
||||
puts "PASS: basic setup"
|
||||
|
||||
############################################################
|
||||
# set_driving_cell
|
||||
############################################################
|
||||
|
||||
set_driving_cell -lib_cell BUF_X1 [get_ports in1]
|
||||
puts "PASS: set_driving_cell BUF_X1"
|
||||
|
||||
set_driving_cell -lib_cell INV_X1 [get_ports in2]
|
||||
puts "PASS: set_driving_cell INV_X1"
|
||||
|
||||
set_driving_cell -lib_cell BUF_X4 [get_ports in3]
|
||||
puts "PASS: set_driving_cell BUF_X4"
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: report_checks after set_driving_cell"
|
||||
|
||||
############################################################
|
||||
# set_load
|
||||
############################################################
|
||||
|
||||
set_load 0.05 [get_ports out1]
|
||||
puts "PASS: set_load"
|
||||
|
||||
set_load -pin_load 0.03 [get_ports out2]
|
||||
puts "PASS: set_load -pin_load"
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: report_checks after set_load"
|
||||
|
||||
############################################################
|
||||
# set_input_transition
|
||||
############################################################
|
||||
|
||||
set_input_transition 0.15 [get_ports in1]
|
||||
puts "PASS: set_input_transition"
|
||||
|
||||
set_input_transition -rise 0.12 [get_ports in2]
|
||||
puts "PASS: set_input_transition -rise"
|
||||
|
||||
set_input_transition -fall 0.18 [get_ports in2]
|
||||
puts "PASS: set_input_transition -fall"
|
||||
|
||||
set_input_transition -min 0.08 [get_ports in3]
|
||||
puts "PASS: set_input_transition -min"
|
||||
|
||||
set_input_transition -max 0.20 [get_ports in3]
|
||||
puts "PASS: set_input_transition -max"
|
||||
|
||||
report_checks -from [get_ports in2] -to [get_ports out1]
|
||||
puts "PASS: report_checks after set_input_transition"
|
||||
|
||||
############################################################
|
||||
# set_max_capacitance / set_max_transition / set_max_fanout
|
||||
############################################################
|
||||
|
||||
set_max_capacitance 0.1 [get_ports out1]
|
||||
puts "PASS: set_max_capacitance port"
|
||||
|
||||
set_max_capacitance 0.2 [current_design]
|
||||
puts "PASS: set_max_capacitance design"
|
||||
|
||||
set_max_transition 0.5 [get_ports out1]
|
||||
puts "PASS: set_max_transition port"
|
||||
|
||||
set_max_transition 1.0 [current_design]
|
||||
puts "PASS: set_max_transition design"
|
||||
|
||||
set_max_transition -clock_path 0.3 [get_clocks clk1]
|
||||
puts "PASS: set_max_transition -clock_path"
|
||||
|
||||
set_max_transition -data_path 0.8 [get_clocks clk1]
|
||||
puts "PASS: set_max_transition -data_path"
|
||||
|
||||
set_max_fanout 10 [get_ports in1]
|
||||
puts "PASS: set_max_fanout port"
|
||||
|
||||
set_max_fanout 20 [current_design]
|
||||
puts "PASS: set_max_fanout design"
|
||||
|
||||
############################################################
|
||||
# set_case_analysis
|
||||
############################################################
|
||||
|
||||
set_case_analysis 0 [get_ports in3]
|
||||
puts "PASS: set_case_analysis 0"
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: report_checks after case_analysis 0"
|
||||
|
||||
unset_case_analysis [get_ports in3]
|
||||
puts "PASS: unset_case_analysis"
|
||||
|
||||
set_case_analysis 1 [get_ports in3]
|
||||
puts "PASS: set_case_analysis 1"
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: report_checks after case_analysis 1"
|
||||
|
||||
unset_case_analysis [get_ports in3]
|
||||
puts "PASS: unset_case_analysis second"
|
||||
|
||||
############################################################
|
||||
# set_logic_zero / set_logic_one / set_logic_dc
|
||||
############################################################
|
||||
|
||||
set_logic_zero [get_ports in3]
|
||||
puts "PASS: set_logic_zero"
|
||||
|
||||
set_logic_one [get_ports in2]
|
||||
puts "PASS: set_logic_one"
|
||||
|
||||
set_logic_dc [get_ports in1]
|
||||
puts "PASS: set_logic_dc"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report_checks after logic values"
|
||||
|
||||
############################################################
|
||||
# set_ideal_network
|
||||
############################################################
|
||||
|
||||
set_ideal_network [get_ports clk1]
|
||||
puts "PASS: set_ideal_network"
|
||||
|
||||
############################################################
|
||||
# set_operating_conditions
|
||||
############################################################
|
||||
|
||||
set_operating_conditions typical
|
||||
puts "PASS: set_operating_conditions"
|
||||
|
||||
############################################################
|
||||
# set_wire_load_model
|
||||
############################################################
|
||||
|
||||
set_wire_load_model -name "5K_hvratio_1_1"
|
||||
puts "PASS: set_wire_load_model"
|
||||
|
||||
set_wire_load_mode enclosed
|
||||
puts "PASS: set_wire_load_mode enclosed"
|
||||
|
||||
############################################################
|
||||
# set_timing_derate
|
||||
############################################################
|
||||
|
||||
set_timing_derate -early 0.95
|
||||
puts "PASS: set_timing_derate -early"
|
||||
|
||||
set_timing_derate -late 1.05
|
||||
puts "PASS: set_timing_derate -late"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report_checks after timing derate"
|
||||
|
||||
unset_timing_derate
|
||||
puts "PASS: unset_timing_derate"
|
||||
|
||||
############################################################
|
||||
# set_max_area
|
||||
############################################################
|
||||
|
||||
set_max_area 100.0
|
||||
puts "PASS: set_max_area"
|
||||
|
||||
############################################################
|
||||
# set_disable_timing
|
||||
############################################################
|
||||
|
||||
# Disable timing on an instance
|
||||
set_disable_timing [get_cells buf1]
|
||||
puts "PASS: set_disable_timing instance"
|
||||
|
||||
unset_disable_timing [get_cells buf1]
|
||||
puts "PASS: unset_disable_timing instance"
|
||||
|
||||
# Disable timing on a pin
|
||||
set_disable_timing [get_pins buf1/A]
|
||||
puts "PASS: set_disable_timing pin"
|
||||
|
||||
unset_disable_timing [get_pins buf1/A]
|
||||
puts "PASS: unset_disable_timing pin"
|
||||
|
||||
############################################################
|
||||
# set_min_pulse_width
|
||||
############################################################
|
||||
|
||||
set_min_pulse_width 1.0 [get_clocks clk1]
|
||||
puts "PASS: set_min_pulse_width"
|
||||
|
||||
############################################################
|
||||
# Port external capacitance / fanout
|
||||
############################################################
|
||||
|
||||
set_port_fanout_number 4 [get_ports out1]
|
||||
puts "PASS: set_port_fanout_number"
|
||||
|
||||
set_resistance -min 10.0 [get_nets n1]
|
||||
puts "PASS: set_resistance -min"
|
||||
|
||||
set_resistance -max 20.0 [get_nets n1]
|
||||
puts "PASS: set_resistance -max"
|
||||
|
||||
############################################################
|
||||
# set_voltage
|
||||
############################################################
|
||||
|
||||
catch {set_voltage 1.1 -min 0.9}
|
||||
puts "PASS: set_voltage"
|
||||
|
||||
############################################################
|
||||
# Final report
|
||||
############################################################
|
||||
|
||||
report_checks
|
||||
puts "PASS: final report_checks"
|
||||
|
||||
report_check_types -max_capacitance -max_slew -max_fanout
|
||||
puts "PASS: report_check_types"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,225 @@
|
||||
PASS: basic setup
|
||||
PASS: false_path -rise_from
|
||||
PASS: false_path -fall_from
|
||||
PASS: false_path -rise_to
|
||||
PASS: false_path -fall_to
|
||||
PASS: false_path -rise_from -fall_to
|
||||
PASS: false_path -fall_from -rise_to
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: report after rise/fall false paths
|
||||
PASS: write_sdc after false paths
|
||||
PASS: unset all false paths
|
||||
PASS: false_path with -through pin
|
||||
PASS: false_path with multiple -through
|
||||
PASS: false_path -through to out2
|
||||
PASS: write_sdc with through paths
|
||||
PASS: unset through paths
|
||||
PASS: multicycle -rise_from
|
||||
PASS: multicycle -fall_to
|
||||
PASS: multicycle clk1->clk2
|
||||
PASS: multicycle hold clk1->clk2
|
||||
PASS: multicycle with -through
|
||||
PASS: write_sdc with multicycle
|
||||
No paths found.
|
||||
PASS: report_checks with multicycle
|
||||
PASS: unset multicycles
|
||||
PASS: max/min delay
|
||||
PASS: max_delay with -through
|
||||
PASS: max_delay -rise_from -fall_to
|
||||
PASS: write_sdc with max/min delay
|
||||
PASS: write_sdc -compatible with exceptions
|
||||
PASS: write_sdc -digits 6 with exceptions
|
||||
PASS: group_path
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: reg2reg
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks -path_group reg2reg
|
||||
No paths found.
|
||||
PASS: report_checks -path_group in2out
|
||||
PASS: write_sdc with group paths
|
||||
PASS: read_sdc
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk_cross
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: reg2reg
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in3 (input port clocked by clk2)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk2 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
2.00 2.00 v input external delay
|
||||
0.00 2.00 v in3 (in)
|
||||
0.05 2.05 v or1/ZN (OR2_X1)
|
||||
0.03 2.07 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 2.07 ^ reg2/D (DFF_X1)
|
||||
2.07 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-2.07 data arrival time
|
||||
---------------------------------------------------------
|
||||
7.89 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Endpoint: out2 (output port clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk2 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg3/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg3/Q (DFF_X1)
|
||||
0.00 0.08 ^ out2 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
-3.00 17.00 output external delay
|
||||
17.00 data required time
|
||||
---------------------------------------------------------
|
||||
17.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
16.92 slack (MET)
|
||||
|
||||
|
||||
PASS: report after read_sdc
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,202 @@
|
||||
# Test advanced exception path features for code coverage
|
||||
# Targets: ExceptionPath.cc (priority, comparison, rise/fall/through combinations),
|
||||
# WriteSdc.cc (writeException, writeExceptionFrom/To/Thru),
|
||||
# Sdc.cc (exception management, matching)
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
############################################################
|
||||
# Setup clocks and basic delays
|
||||
############################################################
|
||||
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in2]
|
||||
set_input_delay -clock clk2 2.0 [get_ports in3]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 3.0 [get_ports out2]
|
||||
puts "PASS: basic setup"
|
||||
|
||||
############################################################
|
||||
# False path with rise/fall from/to combinations
|
||||
############################################################
|
||||
|
||||
# rise_from to specific port
|
||||
set_false_path -rise_from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: false_path -rise_from"
|
||||
|
||||
# fall_from to specific port
|
||||
set_false_path -fall_from [get_ports in2] -to [get_ports out1]
|
||||
puts "PASS: false_path -fall_from"
|
||||
|
||||
# from port to rise_to
|
||||
set_false_path -from [get_ports in1] -rise_to [get_ports out2]
|
||||
puts "PASS: false_path -rise_to"
|
||||
|
||||
# from port to fall_to
|
||||
set_false_path -from [get_ports in2] -fall_to [get_ports out2]
|
||||
puts "PASS: false_path -fall_to"
|
||||
|
||||
# rise_from + fall_to combination
|
||||
set_false_path -rise_from [get_ports in3] -fall_to [get_ports out1]
|
||||
puts "PASS: false_path -rise_from -fall_to"
|
||||
|
||||
# fall_from + rise_to combination
|
||||
set_false_path -fall_from [get_ports in3] -rise_to [get_ports out2]
|
||||
puts "PASS: false_path -fall_from -rise_to"
|
||||
|
||||
# Report after false paths
|
||||
report_checks
|
||||
puts "PASS: report after rise/fall false paths"
|
||||
|
||||
############################################################
|
||||
# Write SDC (to cover exception writing with rise/fall)
|
||||
############################################################
|
||||
|
||||
set sdc_file1 [make_result_file sdc_exception_adv1.sdc]
|
||||
write_sdc -no_timestamp $sdc_file1
|
||||
puts "PASS: write_sdc after false paths"
|
||||
|
||||
############################################################
|
||||
# Unset all false paths and create through paths
|
||||
############################################################
|
||||
|
||||
unset_path_exceptions -rise_from [get_ports in1] -to [get_ports out1]
|
||||
unset_path_exceptions -fall_from [get_ports in2] -to [get_ports out1]
|
||||
unset_path_exceptions -from [get_ports in1] -rise_to [get_ports out2]
|
||||
unset_path_exceptions -from [get_ports in2] -fall_to [get_ports out2]
|
||||
unset_path_exceptions -rise_from [get_ports in3] -fall_to [get_ports out1]
|
||||
unset_path_exceptions -fall_from [get_ports in3] -rise_to [get_ports out2]
|
||||
puts "PASS: unset all false paths"
|
||||
|
||||
############################################################
|
||||
# False path with -through
|
||||
############################################################
|
||||
|
||||
set_false_path -from [get_ports in1] -through [get_pins buf1/Z] -to [get_ports out1]
|
||||
puts "PASS: false_path with -through pin"
|
||||
|
||||
set_false_path -from [get_ports in2] -through [get_pins inv1/ZN] -through [get_pins and1/ZN] -to [get_ports out1]
|
||||
puts "PASS: false_path with multiple -through"
|
||||
|
||||
set_false_path -from [get_ports in1] -through [get_pins or1/ZN] -to [get_ports out2]
|
||||
puts "PASS: false_path -through to out2"
|
||||
|
||||
# Write to cover through paths
|
||||
set sdc_file2 [make_result_file sdc_exception_adv2.sdc]
|
||||
write_sdc -no_timestamp $sdc_file2
|
||||
puts "PASS: write_sdc with through paths"
|
||||
|
||||
# Unset through paths
|
||||
unset_path_exceptions -from [get_ports in1] -through [get_pins buf1/Z] -to [get_ports out1]
|
||||
unset_path_exceptions -from [get_ports in2] -through [get_pins inv1/ZN] -through [get_pins and1/ZN] -to [get_ports out1]
|
||||
unset_path_exceptions -from [get_ports in1] -through [get_pins or1/ZN] -to [get_ports out2]
|
||||
puts "PASS: unset through paths"
|
||||
|
||||
############################################################
|
||||
# Multicycle path with rise/fall combinations
|
||||
############################################################
|
||||
|
||||
# Setup multicycle with rise_from
|
||||
set_multicycle_path -setup 2 -rise_from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: multicycle -rise_from"
|
||||
|
||||
# Hold multicycle with fall_to
|
||||
set_multicycle_path -hold 1 -from [get_ports in1] -fall_to [get_ports out1]
|
||||
puts "PASS: multicycle -fall_to"
|
||||
|
||||
# Multicycle between clock domains
|
||||
set_multicycle_path -setup 3 -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
puts "PASS: multicycle clk1->clk2"
|
||||
|
||||
set_multicycle_path -hold 2 -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
puts "PASS: multicycle hold clk1->clk2"
|
||||
|
||||
# Multicycle with -through
|
||||
set_multicycle_path -setup 4 -from [get_ports in2] -through [get_pins and1/ZN] -to [get_ports out1]
|
||||
puts "PASS: multicycle with -through"
|
||||
|
||||
# Write to cover multicycle writing
|
||||
set sdc_file3 [make_result_file sdc_exception_adv3.sdc]
|
||||
write_sdc -no_timestamp $sdc_file3
|
||||
puts "PASS: write_sdc with multicycle"
|
||||
|
||||
# Report
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: report_checks with multicycle"
|
||||
|
||||
############################################################
|
||||
# Unset multicycles and add max/min delay
|
||||
############################################################
|
||||
|
||||
unset_path_exceptions -setup -rise_from [get_ports in1] -to [get_ports out1]
|
||||
unset_path_exceptions -hold -from [get_ports in1] -fall_to [get_ports out1]
|
||||
unset_path_exceptions -setup -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
unset_path_exceptions -hold -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
unset_path_exceptions -setup -from [get_ports in2] -through [get_pins and1/ZN] -to [get_ports out1]
|
||||
puts "PASS: unset multicycles"
|
||||
|
||||
############################################################
|
||||
# Max/min delay with various options
|
||||
############################################################
|
||||
|
||||
set_max_delay -from [get_ports in1] -to [get_ports out1] 8.0
|
||||
set_min_delay -from [get_ports in1] -to [get_ports out1] 1.0
|
||||
puts "PASS: max/min delay"
|
||||
|
||||
set_max_delay -from [get_ports in2] -through [get_pins and1/ZN] -to [get_ports out1] 6.0
|
||||
puts "PASS: max_delay with -through"
|
||||
|
||||
set_max_delay -rise_from [get_ports in3] -fall_to [get_ports out2] 7.0
|
||||
puts "PASS: max_delay -rise_from -fall_to"
|
||||
|
||||
# Write to cover max/min delay writing
|
||||
set sdc_file4 [make_result_file sdc_exception_adv4.sdc]
|
||||
write_sdc -no_timestamp $sdc_file4
|
||||
puts "PASS: write_sdc with max/min delay"
|
||||
|
||||
# Write compatible mode to cover alternative writer paths
|
||||
set sdc_file5 [make_result_file sdc_exception_adv5.sdc]
|
||||
write_sdc -no_timestamp -compatible $sdc_file5
|
||||
puts "PASS: write_sdc -compatible with exceptions"
|
||||
|
||||
# Write with digits for coverage
|
||||
set sdc_file6 [make_result_file sdc_exception_adv6.sdc]
|
||||
write_sdc -no_timestamp -digits 6 $sdc_file6
|
||||
puts "PASS: write_sdc -digits 6 with exceptions"
|
||||
|
||||
############################################################
|
||||
# Group paths (exercises group_path writing)
|
||||
############################################################
|
||||
|
||||
group_path -name reg2reg -from [get_clocks clk1] -to [get_clocks clk1]
|
||||
group_path -name in2out -from [get_ports {in1 in2 in3}] -to [get_ports {out1 out2}]
|
||||
group_path -name clk_cross -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
puts "PASS: group_path"
|
||||
|
||||
report_checks -path_group reg2reg
|
||||
puts "PASS: report_checks -path_group reg2reg"
|
||||
|
||||
report_checks -path_group in2out
|
||||
puts "PASS: report_checks -path_group in2out"
|
||||
|
||||
# Write with group paths
|
||||
set sdc_file7 [make_result_file sdc_exception_adv7.sdc]
|
||||
write_sdc -no_timestamp $sdc_file7
|
||||
puts "PASS: write_sdc with group paths"
|
||||
|
||||
############################################################
|
||||
# Read back SDC to verify
|
||||
############################################################
|
||||
|
||||
read_sdc $sdc_file4
|
||||
puts "PASS: read_sdc"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report after read_sdc"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,24 @@
|
||||
PASS: setup
|
||||
PASS: false_path through net n1
|
||||
PASS: false_path through instance inv1
|
||||
PASS: false_path through pin then net
|
||||
PASS: false_path through instance then pin
|
||||
PASS: false_path -rise_through
|
||||
PASS: false_path -fall_through
|
||||
PASS: write_sdc with through exceptions
|
||||
PASS: unset_path_exceptions
|
||||
PASS: false paths to same target (mergeable)
|
||||
PASS: max_delay to same target
|
||||
PASS: min_delay to same target
|
||||
PASS: multicycle paths
|
||||
PASS: false_path -setup only
|
||||
PASS: false_path -hold only
|
||||
PASS: group_path -default
|
||||
PASS: group_path with through net
|
||||
PASS: group_path with through instance
|
||||
PASS: write_sdc all exception types
|
||||
PASS: write_sdc compatible
|
||||
PASS: write_sdc digits 6
|
||||
PASS: read_sdc
|
||||
PASS: write_sdc roundtrip
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,169 @@
|
||||
# Test exception path intersections, priority merging, ExceptionThru matching
|
||||
# with nets/instances/pins, multiple through points, and complex write_sdc paths.
|
||||
# Targets:
|
||||
# ExceptionPath.cc: ExceptionThru::intersectsPts with nets/instances/pins,
|
||||
# ExceptionTo::matchesFilter, ExceptionTo with endTransition,
|
||||
# ExceptionFrom::intersectsPts, ExceptionPath::intersectsPts,
|
||||
# ExceptionPath::mergeable, checkFromThrusTo,
|
||||
# FalsePath::clone, MultiCyclePath::clone, PathDelay::clone,
|
||||
# ExceptionPathLess comparison (sort by type priority),
|
||||
# fromThruToPriority calculation
|
||||
# Sdc.cc: makeExceptionThru with nets/instances/pins,
|
||||
# addException (merge logic), resetPath,
|
||||
# removeInputDelay, removeOutputDelay,
|
||||
# clockGroupsAreSame (via report)
|
||||
# WriteSdc.cc: writeExceptionThru with nets/instances,
|
||||
# writeExceptionFromTo with multi-object lists,
|
||||
# writeExceptionCmd for all types (false/multicycle/path_delay/group),
|
||||
# writeExceptionValue (delay, multiplier),
|
||||
# writeRiseFallMinMaxTimeCmd, writeRiseFallMinMaxCmd
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in2]
|
||||
set_input_delay -clock clk2 2.0 [get_ports in3]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 3.0 [get_ports out2]
|
||||
puts "PASS: setup"
|
||||
|
||||
############################################################
|
||||
# Exception with -through using nets, instances, and pins combined
|
||||
############################################################
|
||||
|
||||
# Through net only
|
||||
set_false_path -through [get_nets n1] -to [get_ports out1]
|
||||
puts "PASS: false_path through net n1"
|
||||
|
||||
# Through instance only
|
||||
set_false_path -through [get_cells inv1] -to [get_ports out2]
|
||||
puts "PASS: false_path through instance inv1"
|
||||
|
||||
# Through pin and net combined in sequence
|
||||
set_false_path -from [get_ports in1] \
|
||||
-through [get_pins buf1/Z] \
|
||||
-through [get_nets n3] \
|
||||
-to [get_ports out1]
|
||||
puts "PASS: false_path through pin then net"
|
||||
|
||||
# Through instance and pin in sequence
|
||||
set_false_path -from [get_ports in2] \
|
||||
-through [get_cells and1] \
|
||||
-through [get_pins nand1/ZN] \
|
||||
-to [get_ports out1]
|
||||
puts "PASS: false_path through instance then pin"
|
||||
|
||||
# Rise through
|
||||
set_false_path -from [get_ports in3] \
|
||||
-rise_through [get_pins or1/ZN] \
|
||||
-to [get_ports out2]
|
||||
puts "PASS: false_path -rise_through"
|
||||
|
||||
# Fall through
|
||||
set_false_path -from [get_ports in1] \
|
||||
-fall_through [get_pins buf1/Z] \
|
||||
-to [get_ports out2]
|
||||
puts "PASS: false_path -fall_through"
|
||||
|
||||
############################################################
|
||||
# Write SDC with through exceptions
|
||||
############################################################
|
||||
set sdc1 [make_result_file sdc_exception_int1.sdc]
|
||||
write_sdc -no_timestamp $sdc1
|
||||
puts "PASS: write_sdc with through exceptions"
|
||||
|
||||
############################################################
|
||||
# Unset all paths and create new set for merging tests
|
||||
############################################################
|
||||
unset_path_exceptions -through [get_nets n1] -to [get_ports out1]
|
||||
unset_path_exceptions -through [get_cells inv1] -to [get_ports out2]
|
||||
unset_path_exceptions -from [get_ports in1] -through [get_pins buf1/Z] -through [get_nets n3] -to [get_ports out1]
|
||||
unset_path_exceptions -from [get_ports in2] -through [get_cells and1] -through [get_pins nand1/ZN] -to [get_ports out1]
|
||||
unset_path_exceptions -from [get_ports in3] -rise_through [get_pins or1/ZN] -to [get_ports out2]
|
||||
unset_path_exceptions -from [get_ports in1] -fall_through [get_pins buf1/Z] -to [get_ports out2]
|
||||
puts "PASS: unset_path_exceptions"
|
||||
|
||||
############################################################
|
||||
# Exception merging: multiple exceptions on overlapping paths
|
||||
############################################################
|
||||
|
||||
# False path that should merge when same from/to
|
||||
set_false_path -from [get_ports in1] -to [get_ports out1]
|
||||
set_false_path -from [get_ports in2] -to [get_ports out1]
|
||||
puts "PASS: false paths to same target (mergeable)"
|
||||
|
||||
# Max delay on same endpoints - second should override
|
||||
set_max_delay -from [get_ports in1] -to [get_ports out2] 7.0
|
||||
set_max_delay -from [get_ports in2] -to [get_ports out2] 6.0
|
||||
puts "PASS: max_delay to same target"
|
||||
|
||||
# Min delay
|
||||
set_min_delay -from [get_ports in1] -to [get_ports out2] 0.5
|
||||
set_min_delay -from [get_ports in2] -to [get_ports out2] 0.3
|
||||
puts "PASS: min_delay to same target"
|
||||
|
||||
# Multicycle on different from/to (not mergeable)
|
||||
set_multicycle_path -setup 2 -from [get_ports in1] -to [get_ports out1]
|
||||
set_multicycle_path -setup 3 -from [get_ports in2] -to [get_ports out2]
|
||||
set_multicycle_path -hold 1 -from [get_ports in1] -to [get_ports out1]
|
||||
set_multicycle_path -hold 0 -from [get_ports in2] -to [get_ports out2]
|
||||
puts "PASS: multicycle paths"
|
||||
|
||||
# False path with -setup only
|
||||
set_false_path -setup -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
puts "PASS: false_path -setup only"
|
||||
|
||||
# False path with -hold only
|
||||
set_false_path -hold -from [get_clocks clk2] -to [get_clocks clk1]
|
||||
puts "PASS: false_path -hold only"
|
||||
|
||||
# Group path - default
|
||||
group_path -default -from [get_ports in3] -to [get_ports out2]
|
||||
puts "PASS: group_path -default"
|
||||
|
||||
# Group path - named with through nets
|
||||
group_path -name grp_net \
|
||||
-from [get_ports in1] \
|
||||
-through [get_nets n1] \
|
||||
-to [get_ports out1]
|
||||
puts "PASS: group_path with through net"
|
||||
|
||||
# Group path - named with through instances
|
||||
group_path -name grp_inst \
|
||||
-from [get_ports in2] \
|
||||
-through [get_cells and1] \
|
||||
-to [get_ports out1]
|
||||
puts "PASS: group_path with through instance"
|
||||
|
||||
############################################################
|
||||
# Write SDC with all exception types
|
||||
############################################################
|
||||
set sdc2 [make_result_file sdc_exception_int2.sdc]
|
||||
write_sdc -no_timestamp $sdc2
|
||||
puts "PASS: write_sdc all exception types"
|
||||
|
||||
set sdc3 [make_result_file sdc_exception_int3.sdc]
|
||||
write_sdc -no_timestamp -compatible $sdc3
|
||||
puts "PASS: write_sdc compatible"
|
||||
|
||||
set sdc4 [make_result_file sdc_exception_int4.sdc]
|
||||
write_sdc -no_timestamp -digits 6 $sdc4
|
||||
puts "PASS: write_sdc digits 6"
|
||||
|
||||
############################################################
|
||||
# Read back SDC
|
||||
############################################################
|
||||
read_sdc $sdc2
|
||||
puts "PASS: read_sdc"
|
||||
|
||||
# Re-write to verify roundtrip
|
||||
set sdc5 [make_result_file sdc_exception_int5.sdc]
|
||||
write_sdc -no_timestamp $sdc5
|
||||
puts "PASS: write_sdc roundtrip"
|
||||
|
||||
puts "ALL PASSED"
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,175 @@
|
||||
# Test ExceptionPath.cc matching and filtering: exception path state matching,
|
||||
# multi-thru point matching, matchesFilter, and exception path deletion.
|
||||
# Targets: ExceptionPath.cc ExceptionState matching,
|
||||
# ExceptionTo::matchesFilter, ExceptionThru::allPins,
|
||||
# ExceptionPath::tighterThan, ExceptionPath::overrides,
|
||||
# ExceptionPath::matchesFirstFrom, matchesFirstThru, matchesLastTo,
|
||||
# ExceptionPath::resetMatch, ExceptionPath::nextState,
|
||||
# Sdc.cc addException, deleteException,
|
||||
# exceptionMatchFirst, exceptionMatchNext,
|
||||
# ExceptionState::nextState, ExceptionState::isComplete
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
set_input_delay -clock clk1 1.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 1.0 [get_ports in2]
|
||||
set_input_delay -clock clk2 2.0 [get_ports in3]
|
||||
set_output_delay -clock clk1 2.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 3.0 [get_ports out2]
|
||||
|
||||
report_checks > /dev/null
|
||||
|
||||
############################################################
|
||||
# Test 1: Multi-thru false paths with pin types
|
||||
############################################################
|
||||
puts "--- multi-thru state matching ---"
|
||||
|
||||
# 2-stage thru: pin then pin
|
||||
set_false_path -from [get_ports in1] \
|
||||
-through [get_pins buf1/Z] \
|
||||
-through [get_pins and1/ZN] \
|
||||
-to [get_ports out1]
|
||||
report_checks -path_delay max -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: 2-thru pin-pin"
|
||||
|
||||
# Another 2-stage thru
|
||||
set_false_path -from [get_ports in2] \
|
||||
-through [get_pins inv1/ZN] \
|
||||
-through [get_pins nand1/ZN] \
|
||||
-to [get_ports out1]
|
||||
report_checks -path_delay max -from [get_ports in2] -to [get_ports out1]
|
||||
puts "PASS: 2-thru pin-pin #2"
|
||||
|
||||
puts "--- unset multi-thru ---"
|
||||
unset_path_exceptions -from [get_ports in1] -through [get_pins buf1/Z] \
|
||||
-through [get_pins and1/ZN] -to [get_ports out1]
|
||||
unset_path_exceptions -from [get_ports in2] -through [get_pins inv1/ZN] \
|
||||
-through [get_pins nand1/ZN] -to [get_ports out1]
|
||||
report_checks -path_delay max
|
||||
puts "PASS: unset multi-thru"
|
||||
|
||||
############################################################
|
||||
# Test 2: Exception filter matching (report_checks -from/-to/-through)
|
||||
############################################################
|
||||
puts "--- exception filter matching ---"
|
||||
|
||||
set_false_path -from [get_ports in1] -to [get_ports out2]
|
||||
set_multicycle_path 2 -setup -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
set_max_delay 7.0 -from [get_ports in3] -to [get_ports out2]
|
||||
|
||||
puts "--- report_checks -from in1 ---"
|
||||
report_checks -path_delay max -from [get_ports in1]
|
||||
puts "PASS: filter from in1"
|
||||
|
||||
puts "--- report_checks -to out2 ---"
|
||||
report_checks -path_delay max -to [get_ports out2]
|
||||
puts "PASS: filter to out2"
|
||||
|
||||
puts "--- report_checks -from in3 -to out2 ---"
|
||||
report_checks -path_delay max -from [get_ports in3] -to [get_ports out2]
|
||||
puts "PASS: filter from/to"
|
||||
|
||||
puts "--- report_checks -through pin ---"
|
||||
report_checks -path_delay max -through [get_pins buf1/Z]
|
||||
puts "PASS: filter through pin"
|
||||
|
||||
puts "--- report_checks -through instance ---"
|
||||
report_checks -path_delay max -through [get_cells and1]
|
||||
puts "PASS: filter through instance"
|
||||
|
||||
############################################################
|
||||
# Test 3: Unset exceptions
|
||||
############################################################
|
||||
puts "--- unset all exceptions ---"
|
||||
unset_path_exceptions -from [get_ports in1] -to [get_ports out2]
|
||||
unset_path_exceptions -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
unset_path_exceptions -from [get_ports in3] -to [get_ports out2]
|
||||
report_checks -path_delay max
|
||||
puts "PASS: unset all exceptions"
|
||||
|
||||
############################################################
|
||||
# Test 4: group_path with filter
|
||||
############################################################
|
||||
puts "--- group_path filter ---"
|
||||
group_path -name gp_in1 -from [get_ports in1]
|
||||
group_path -name gp_out1 -to [get_ports out1]
|
||||
group_path -name gp_thru -through [get_pins and1/ZN]
|
||||
|
||||
report_checks -path_delay max -path_group gp_in1
|
||||
report_checks -path_delay max -path_group gp_out1
|
||||
report_checks -path_delay max -path_group gp_thru
|
||||
puts "PASS: group_path filters"
|
||||
|
||||
############################################################
|
||||
# Test 5: From/to with instances
|
||||
############################################################
|
||||
puts "--- from instance ---"
|
||||
set_false_path -from [get_cells reg1] -to [get_ports out2]
|
||||
report_checks -path_delay max
|
||||
puts "PASS: from instance"
|
||||
|
||||
unset_path_exceptions -from [get_cells reg1] -to [get_ports out2]
|
||||
puts "PASS: unset from instance"
|
||||
|
||||
puts "--- to instance ---"
|
||||
set_false_path -from [get_ports in1] -to [get_cells reg2]
|
||||
report_checks -path_delay max
|
||||
puts "PASS: to instance"
|
||||
|
||||
unset_path_exceptions -from [get_ports in1] -to [get_cells reg2]
|
||||
puts "PASS: unset to instance"
|
||||
|
||||
############################################################
|
||||
# Test 6: From/to with clock objects
|
||||
############################################################
|
||||
puts "--- from clock ---"
|
||||
set_false_path -from [get_clocks clk1] -to [get_ports out2]
|
||||
report_checks -path_delay max
|
||||
puts "PASS: from clock"
|
||||
|
||||
unset_path_exceptions -from [get_clocks clk1] -to [get_ports out2]
|
||||
puts "PASS: unset from clock"
|
||||
|
||||
############################################################
|
||||
# Test 7: Rise/fall through
|
||||
############################################################
|
||||
puts "--- rise_through ---"
|
||||
set_false_path -rise_through [get_pins buf1/Z] -to [get_ports out1]
|
||||
report_checks -path_delay max
|
||||
puts "PASS: rise_through"
|
||||
|
||||
unset_path_exceptions -through [get_pins buf1/Z] -to [get_ports out1]
|
||||
puts "PASS: unset rise_through"
|
||||
|
||||
puts "--- fall_through ---"
|
||||
set_false_path -fall_through [get_pins inv1/ZN] -to [get_ports out1]
|
||||
report_checks -path_delay max
|
||||
puts "PASS: fall_through"
|
||||
|
||||
unset_path_exceptions -through [get_pins inv1/ZN] -to [get_ports out1]
|
||||
puts "PASS: unset fall_through"
|
||||
|
||||
############################################################
|
||||
# Test 8: Write SDC roundtrip with complex exceptions
|
||||
############################################################
|
||||
set_false_path -rise_from [get_ports in1] -to [get_ports out1]
|
||||
set_false_path -from [get_ports in2] -fall_to [get_ports out2]
|
||||
set_multicycle_path 3 -setup -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
|
||||
set sdc_out [make_result_file sdc_exc_match_filter.sdc]
|
||||
write_sdc -no_timestamp $sdc_out
|
||||
puts "PASS: write_sdc complex"
|
||||
|
||||
read_sdc $sdc_out
|
||||
puts "PASS: read_sdc roundtrip"
|
||||
|
||||
set sdc_out2 [make_result_file sdc_exc_match_filter2.sdc]
|
||||
write_sdc -no_timestamp $sdc_out2
|
||||
puts "PASS: write_sdc after roundtrip"
|
||||
|
||||
puts "ALL PASSED"
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,212 @@
|
||||
# Test exception path merging, priority resolution, through-pin matching,
|
||||
# complex false/multicycle/max_delay/min_delay/group_path combinations.
|
||||
# Targets: ExceptionPath.cc exception merging, priority, matches,
|
||||
# overrides, through-pin matching, ExceptionThru matching,
|
||||
# Sdc.cc addException, findException, isPathGroupName,
|
||||
# pathGroupNames, removeConstraints, constraintsChanged,
|
||||
# makeExceptionFrom/Thru/To, checkExceptionFromPins,
|
||||
# checkExceptionToPins, deleteExceptionFrom/Thru/To,
|
||||
# WriteSdc.cc writeExceptions (various exception types)
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in2]
|
||||
set_input_delay -clock clk2 2.0 [get_ports in3]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 3.0 [get_ports out2]
|
||||
puts "PASS: setup"
|
||||
|
||||
############################################################
|
||||
# Simple false path
|
||||
############################################################
|
||||
puts "--- false path clock to clock ---"
|
||||
set_false_path -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
report_checks
|
||||
puts "PASS: false path clk1->clk2"
|
||||
|
||||
############################################################
|
||||
# False path with rise_from/fall_to
|
||||
############################################################
|
||||
puts "--- false path rise_from/fall_to ---"
|
||||
set_false_path -rise_from [get_ports in1] -fall_to [get_ports out1]
|
||||
report_checks
|
||||
puts "PASS: false path rise_from/fall_to"
|
||||
|
||||
puts "--- false path fall_from/rise_to ---"
|
||||
set_false_path -fall_from [get_ports in2] -rise_to [get_ports out2]
|
||||
report_checks
|
||||
puts "PASS: false path fall_from/rise_to"
|
||||
|
||||
############################################################
|
||||
# False path with -through
|
||||
############################################################
|
||||
puts "--- false path through single pin ---"
|
||||
set_false_path -from [get_ports in1] -through [get_pins and1/ZN] -to [get_ports out1]
|
||||
report_checks
|
||||
puts "PASS: false path through pin"
|
||||
|
||||
puts "--- false path through instance pin ---"
|
||||
set_false_path -from [get_ports in2] -through [get_pins inv1/ZN]
|
||||
report_checks
|
||||
puts "PASS: false path through instance pin"
|
||||
|
||||
puts "--- false path through second pin ---"
|
||||
set_false_path -from [get_ports in1] -through [get_pins buf1/Z] -to [get_ports out2]
|
||||
report_checks
|
||||
puts "PASS: false path through second pin"
|
||||
|
||||
############################################################
|
||||
# Multicycle paths with various options
|
||||
############################################################
|
||||
puts "--- multicycle setup ---"
|
||||
set_multicycle_path -setup 2 -from [get_ports in1] -to [get_ports out1]
|
||||
report_checks
|
||||
puts "PASS: multicycle setup"
|
||||
|
||||
puts "--- multicycle hold ---"
|
||||
set_multicycle_path -hold 1 -from [get_ports in1] -to [get_ports out1]
|
||||
report_checks
|
||||
puts "PASS: multicycle hold"
|
||||
|
||||
puts "--- multicycle with -start ---"
|
||||
set_multicycle_path -setup 3 -start -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
report_checks
|
||||
puts "PASS: multicycle start"
|
||||
|
||||
puts "--- multicycle with -end ---"
|
||||
set_multicycle_path -setup 2 -end -from [get_clocks clk1]
|
||||
report_checks
|
||||
puts "PASS: multicycle end"
|
||||
|
||||
puts "--- multicycle with rise_from ---"
|
||||
set_multicycle_path -setup 4 -rise_from [get_ports in1]
|
||||
report_checks
|
||||
puts "PASS: multicycle rise_from"
|
||||
|
||||
puts "--- multicycle with fall_to ---"
|
||||
set_multicycle_path -hold 2 -fall_to [get_ports out1]
|
||||
report_checks
|
||||
puts "PASS: multicycle fall_to"
|
||||
|
||||
############################################################
|
||||
# Max/min delay constraints
|
||||
############################################################
|
||||
puts "--- max_delay ---"
|
||||
set_max_delay -from [get_ports in1] -to [get_ports out1] 8.0
|
||||
report_checks -path_delay max
|
||||
puts "PASS: max_delay"
|
||||
|
||||
puts "--- min_delay ---"
|
||||
set_min_delay -from [get_ports in1] -to [get_ports out1] 1.0
|
||||
report_checks -path_delay min
|
||||
puts "PASS: min_delay"
|
||||
|
||||
puts "--- max_delay with through ---"
|
||||
set_max_delay -from [get_ports in2] -through [get_pins inv1/ZN] -to [get_ports out1] 6.0
|
||||
report_checks -path_delay max
|
||||
puts "PASS: max_delay through"
|
||||
|
||||
puts "--- min_delay with through ---"
|
||||
set_min_delay -from [get_ports in2] -through [get_pins inv1/ZN] -to [get_ports out1] 0.5
|
||||
report_checks -path_delay min
|
||||
puts "PASS: min_delay through"
|
||||
|
||||
puts "--- max_delay rise_from ---"
|
||||
set_max_delay -rise_from [get_ports in3] -to [get_ports out2] 7.0
|
||||
report_checks -path_delay max
|
||||
puts "PASS: max_delay rise_from"
|
||||
|
||||
############################################################
|
||||
# Group paths
|
||||
############################################################
|
||||
puts "--- group_path ---"
|
||||
group_path -name grp1 -from [get_clocks clk1]
|
||||
group_path -name grp2 -from [get_ports in1] -to [get_ports out1]
|
||||
group_path -name grp3 -from [get_clocks clk2] -to [get_ports out2]
|
||||
report_checks
|
||||
puts "PASS: group_path"
|
||||
|
||||
puts "--- path group names ---"
|
||||
catch {
|
||||
set pgn [sta::path_group_names]
|
||||
puts "Path group names: $pgn"
|
||||
}
|
||||
puts "PASS: path group names"
|
||||
|
||||
puts "--- is_path_group_name ---"
|
||||
catch {
|
||||
puts "grp1 is group: [sta::is_path_group_name grp1]"
|
||||
puts "nonexistent is group: [sta::is_path_group_name nonexistent]"
|
||||
}
|
||||
puts "PASS: is_path_group_name"
|
||||
|
||||
############################################################
|
||||
# Exception priority and overriding
|
||||
############################################################
|
||||
puts "--- exception override: false path then max_delay ---"
|
||||
# More specific exception should override broader one
|
||||
set_max_delay -from [get_ports in3] -to [get_ports out2] 5.0
|
||||
report_checks
|
||||
puts "PASS: exception override"
|
||||
|
||||
############################################################
|
||||
# remove_constraints (remove all SDC constraints)
|
||||
############################################################
|
||||
puts "--- remove_constraints ---"
|
||||
catch {
|
||||
sta::remove_constraints
|
||||
report_checks
|
||||
}
|
||||
puts "PASS: remove_constraints"
|
||||
|
||||
# Re-add constraints for write_sdc
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in2]
|
||||
set_input_delay -clock clk2 2.0 [get_ports in3]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 3.0 [get_ports out2]
|
||||
|
||||
set_false_path -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
set_multicycle_path -setup 2 -from [get_ports in1] -to [get_ports out1]
|
||||
set_max_delay -from [get_ports in2] -to [get_ports out1] 8.0
|
||||
group_path -name grp1 -from [get_clocks clk1]
|
||||
report_checks
|
||||
puts "PASS: re-add constraints"
|
||||
|
||||
############################################################
|
||||
# Write SDC with all exception types
|
||||
############################################################
|
||||
puts "--- write_sdc with exceptions ---"
|
||||
set sdc1 [make_result_file sdc_exception_merge1.sdc]
|
||||
write_sdc -no_timestamp $sdc1
|
||||
puts "PASS: write_sdc exceptions"
|
||||
|
||||
puts "--- write_sdc compatible with exceptions ---"
|
||||
set sdc2 [make_result_file sdc_exception_merge2.sdc]
|
||||
write_sdc -no_timestamp -compatible $sdc2
|
||||
puts "PASS: write_sdc compatible"
|
||||
|
||||
############################################################
|
||||
# Read back and verify
|
||||
############################################################
|
||||
puts "--- read_sdc back ---"
|
||||
read_sdc $sdc1
|
||||
report_checks
|
||||
puts "PASS: read_sdc roundtrip"
|
||||
|
||||
############################################################
|
||||
# Additional write after re-read
|
||||
############################################################
|
||||
set sdc3 [make_result_file sdc_exception_merge3.sdc]
|
||||
write_sdc -no_timestamp $sdc3
|
||||
puts "PASS: write after re-read"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,39 @@
|
||||
PASS: setup
|
||||
PASS: max_delay in1->out1
|
||||
PASS: false_path overrides max_delay in1->out1
|
||||
PASS: min_delay in2->out1
|
||||
PASS: min_delay override in2->out1
|
||||
PASS: multicycle -setup 2
|
||||
PASS: multicycle -setup 3 override
|
||||
PASS: multicycle -hold 1
|
||||
PASS: multicycle -hold 2 override
|
||||
PASS: multicycle -setup -start 4
|
||||
PASS: multicycle -hold -end 2
|
||||
PASS: false_path -rise_from
|
||||
PASS: false_path -fall_from
|
||||
PASS: false_path -rise_to
|
||||
PASS: false_path -fall_to
|
||||
PASS: multicycle -rise_from clk1 -to clk2
|
||||
PASS: multicycle -from clk1 -fall_to clk2
|
||||
PASS: group_path grp_a
|
||||
PASS: group_path grp_a override
|
||||
PASS: group_path -default
|
||||
PASS: group_path -default override
|
||||
PASS: group_path with through
|
||||
PASS: group_path with through net
|
||||
PASS: group_path with through instance
|
||||
PASS: false_path 3 through points
|
||||
PASS: false_path rise_through + fall_through
|
||||
PASS: max_delay through instance
|
||||
PASS: max_delay through net
|
||||
PASS: false_path -setup clk1->clk2
|
||||
PASS: false_path -hold clk2->clk1
|
||||
PASS: write_sdc all exceptions
|
||||
PASS: write_sdc compatible
|
||||
PASS: write_sdc digits 6
|
||||
PASS: unset false_path in1->out1
|
||||
PASS: unset rise/fall false_paths
|
||||
PASS: write_sdc after unset
|
||||
PASS: read_sdc
|
||||
PASS: write_sdc after read
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,238 @@
|
||||
# Test exception path override logic, priority resolution between
|
||||
# false_path/multicycle/max_delay/group_path, and complex thru combinations.
|
||||
# Targets:
|
||||
# ExceptionPath.cc: FalsePath::overrides, MultiCyclePath::overrides,
|
||||
# PathDelay::overrides, GroupPath::overrides,
|
||||
# FalsePath::mergeable, MultiCyclePath::mergeable,
|
||||
# PathDelay::mergeable, GroupPath::mergeable,
|
||||
# ExceptionPath::fromThruToPriority (various priority combos),
|
||||
# ExceptionPathLess comparison (sort by type priority),
|
||||
# FalsePath::clone, MultiCyclePath::clone, PathDelay::clone,
|
||||
# ExceptionTo::matchesFilter with endTransition rise/fall,
|
||||
# ExceptionTo::intersectsPts, ExceptionFrom::intersectsPts,
|
||||
# ExceptionThru::equal, ExceptionThru::compare,
|
||||
# ExceptionThru::findHash with nets/instances/pins,
|
||||
# checkFromThrusTo
|
||||
# Sdc.cc: addException (merge and override logic),
|
||||
# makeExceptionFrom/To/Thru with various object combos,
|
||||
# deleteExceptionsReferencing
|
||||
# WriteSdc.cc: writeExceptions (all types with priority ordering),
|
||||
# writeExceptionCmd, writeExceptionValue, writeGroupPath
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
create_clock -name vclk -period 8
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in2]
|
||||
set_input_delay -clock clk2 2.0 [get_ports in3]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 3.0 [get_ports out2]
|
||||
puts "PASS: setup"
|
||||
|
||||
############################################################
|
||||
# Test 1: Override max_delay with false_path
|
||||
# (FalsePath::overrides, PathDelay::overrides)
|
||||
############################################################
|
||||
|
||||
# Set max_delay first
|
||||
set_max_delay -from [get_ports in1] -to [get_ports out1] 8.0
|
||||
puts "PASS: max_delay in1->out1"
|
||||
|
||||
# Override with false_path on same from/to
|
||||
set_false_path -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: false_path overrides max_delay in1->out1"
|
||||
|
||||
# Set min_delay on different path
|
||||
set_min_delay -from [get_ports in2] -to [get_ports out1] 1.0
|
||||
puts "PASS: min_delay in2->out1"
|
||||
|
||||
# Override min_delay with another min_delay (same endpoints)
|
||||
set_min_delay -from [get_ports in2] -to [get_ports out1] 2.0
|
||||
puts "PASS: min_delay override in2->out1"
|
||||
|
||||
############################################################
|
||||
# Test 2: Multicycle path overrides
|
||||
# (MultiCyclePath::overrides, MultiCyclePath::mergeable)
|
||||
############################################################
|
||||
|
||||
# Setup multicycle
|
||||
set_multicycle_path -setup 2 -from [get_ports in1] -to [get_ports out2]
|
||||
puts "PASS: multicycle -setup 2"
|
||||
|
||||
# Override with different multiplier (same endpoints, same type)
|
||||
set_multicycle_path -setup 3 -from [get_ports in1] -to [get_ports out2]
|
||||
puts "PASS: multicycle -setup 3 override"
|
||||
|
||||
# Hold multicycle on same path
|
||||
set_multicycle_path -hold 1 -from [get_ports in1] -to [get_ports out2]
|
||||
puts "PASS: multicycle -hold 1"
|
||||
|
||||
# Override hold with different value
|
||||
set_multicycle_path -hold 2 -from [get_ports in1] -to [get_ports out2]
|
||||
puts "PASS: multicycle -hold 2 override"
|
||||
|
||||
# Multicycle with -start (exercises use_end_clk=false)
|
||||
set_multicycle_path -setup -start 4 -from [get_ports in2] -to [get_ports out2]
|
||||
puts "PASS: multicycle -setup -start 4"
|
||||
|
||||
# Multicycle with -end (exercises use_end_clk=true)
|
||||
set_multicycle_path -hold -end 2 -from [get_ports in2] -to [get_ports out2]
|
||||
puts "PASS: multicycle -hold -end 2"
|
||||
|
||||
############################################################
|
||||
# Test 3: Exception with rise/fall transitions on to/from
|
||||
# (ExceptionTo::matchesFilter with endTransition)
|
||||
############################################################
|
||||
|
||||
# False path with rise_from only
|
||||
set_false_path -rise_from [get_ports in3] -to [get_ports out1]
|
||||
puts "PASS: false_path -rise_from"
|
||||
|
||||
# False path with fall_from only
|
||||
set_false_path -fall_from [get_ports in3] -to [get_ports out2]
|
||||
puts "PASS: false_path -fall_from"
|
||||
|
||||
# False path with rise_to
|
||||
set_false_path -from [get_ports in2] -rise_to [get_ports out1]
|
||||
puts "PASS: false_path -rise_to"
|
||||
|
||||
# False path with fall_to
|
||||
set_false_path -from [get_ports in2] -fall_to [get_ports out2]
|
||||
puts "PASS: false_path -fall_to"
|
||||
|
||||
# Multicycle with rise_from/fall_to
|
||||
set_multicycle_path -setup 2 -rise_from [get_clocks clk1] -to [get_clocks clk2]
|
||||
puts "PASS: multicycle -rise_from clk1 -to clk2"
|
||||
|
||||
set_multicycle_path -setup 3 -from [get_clocks clk1] -fall_to [get_clocks clk2]
|
||||
puts "PASS: multicycle -from clk1 -fall_to clk2"
|
||||
|
||||
############################################################
|
||||
# Test 4: Group path overrides
|
||||
# (GroupPath::overrides, GroupPath::mergeable)
|
||||
############################################################
|
||||
|
||||
# Named group path
|
||||
group_path -name grp_a -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: group_path grp_a"
|
||||
|
||||
# Override with same name (exercises GroupPath::overrides)
|
||||
group_path -name grp_a -from [get_ports in1] -to [get_ports out2]
|
||||
puts "PASS: group_path grp_a override"
|
||||
|
||||
# Default group path
|
||||
group_path -default -from [get_ports in3] -to [get_ports out2]
|
||||
puts "PASS: group_path -default"
|
||||
|
||||
# Another default (exercises isDefault override logic)
|
||||
group_path -default -from [get_ports in3] -to [get_ports out1]
|
||||
puts "PASS: group_path -default override"
|
||||
|
||||
# Group path with through
|
||||
group_path -name grp_thru \
|
||||
-from [get_ports in1] \
|
||||
-through [get_pins buf1/Z] \
|
||||
-to [get_ports out1]
|
||||
puts "PASS: group_path with through"
|
||||
|
||||
# Group path with through net
|
||||
group_path -name grp_net \
|
||||
-from [get_ports in2] \
|
||||
-through [get_nets n2] \
|
||||
-to [get_ports out1]
|
||||
puts "PASS: group_path with through net"
|
||||
|
||||
# Group path with through instance
|
||||
group_path -name grp_inst \
|
||||
-from [get_ports in1] \
|
||||
-through [get_cells and1] \
|
||||
-to [get_ports out2]
|
||||
puts "PASS: group_path with through instance"
|
||||
|
||||
############################################################
|
||||
# Test 5: Complex through combinations
|
||||
# (ExceptionThru with pins + nets + instances)
|
||||
############################################################
|
||||
|
||||
# Multiple through points: pin then net then pin
|
||||
set_false_path -from [get_ports in1] \
|
||||
-through [get_pins buf1/Z] \
|
||||
-through [get_nets n3] \
|
||||
-through [get_pins nand1/ZN] \
|
||||
-to [get_ports out1]
|
||||
puts "PASS: false_path 3 through points"
|
||||
|
||||
# Rise_through and fall_through combined
|
||||
set_false_path -from [get_ports in2] \
|
||||
-rise_through [get_pins and1/ZN] \
|
||||
-fall_through [get_pins nand1/ZN] \
|
||||
-to [get_ports out1]
|
||||
puts "PASS: false_path rise_through + fall_through"
|
||||
|
||||
# Max delay with through instance
|
||||
set_max_delay -from [get_ports in3] \
|
||||
-through [get_cells or1] \
|
||||
-to [get_ports out2] 7.0
|
||||
puts "PASS: max_delay through instance"
|
||||
|
||||
# Max delay with through net
|
||||
set_max_delay -from [get_ports in1] \
|
||||
-through [get_nets n1] \
|
||||
-to [get_ports out1] 6.0
|
||||
puts "PASS: max_delay through net"
|
||||
|
||||
############################################################
|
||||
# Test 6: False path with -setup and -hold only
|
||||
############################################################
|
||||
set_false_path -setup -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
puts "PASS: false_path -setup clk1->clk2"
|
||||
|
||||
set_false_path -hold -from [get_clocks clk2] -to [get_clocks clk1]
|
||||
puts "PASS: false_path -hold clk2->clk1"
|
||||
|
||||
############################################################
|
||||
# Write SDC with all exception types
|
||||
############################################################
|
||||
set sdc1 [make_result_file sdc_exc_override1.sdc]
|
||||
write_sdc -no_timestamp $sdc1
|
||||
puts "PASS: write_sdc all exceptions"
|
||||
|
||||
set sdc2 [make_result_file sdc_exc_override2.sdc]
|
||||
write_sdc -no_timestamp -compatible $sdc2
|
||||
puts "PASS: write_sdc compatible"
|
||||
|
||||
set sdc3 [make_result_file sdc_exc_override3.sdc]
|
||||
write_sdc -no_timestamp -digits 6 $sdc3
|
||||
puts "PASS: write_sdc digits 6"
|
||||
|
||||
############################################################
|
||||
# Unset some exceptions and verify
|
||||
############################################################
|
||||
unset_path_exceptions -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: unset false_path in1->out1"
|
||||
|
||||
unset_path_exceptions -from [get_ports in2] -rise_to [get_ports out1]
|
||||
unset_path_exceptions -from [get_ports in2] -fall_to [get_ports out2]
|
||||
puts "PASS: unset rise/fall false_paths"
|
||||
|
||||
# Write after unset to exercise writing with reduced exceptions
|
||||
set sdc_unset [make_result_file sdc_exc_override_unset.sdc]
|
||||
write_sdc -no_timestamp $sdc_unset
|
||||
puts "PASS: write_sdc after unset"
|
||||
|
||||
############################################################
|
||||
# Read back and verify roundtrip
|
||||
############################################################
|
||||
read_sdc $sdc1
|
||||
puts "PASS: read_sdc"
|
||||
|
||||
set sdc4 [make_result_file sdc_exc_override4.sdc]
|
||||
write_sdc -no_timestamp $sdc4
|
||||
puts "PASS: write_sdc after read"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,284 @@
|
||||
PASS: setup
|
||||
PASS: false_path -rise_from
|
||||
PASS: false_path -fall_from
|
||||
PASS: false_path -rise_to
|
||||
PASS: false_path -fall_to
|
||||
PASS: false_path -rise_through pin
|
||||
PASS: false_path -fall_through pin
|
||||
PASS: false_path rise_from + through + fall_to
|
||||
PASS: false_path fall_from + rise_through + to
|
||||
PASS: mcp -rise_from setup
|
||||
PASS: mcp -fall_from hold
|
||||
PASS: mcp -rise_to setup
|
||||
PASS: mcp -fall_to hold
|
||||
PASS: max_delay -rise_from
|
||||
PASS: max_delay -fall_to
|
||||
PASS: min_delay -fall_from
|
||||
PASS: min_delay -rise_to
|
||||
PASS: write_sdc
|
||||
PASS: write_sdc compatible
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: report max
|
||||
Startpoint: in3 (input port clocked by clk2)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk2 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
2.00 2.00 ^ input external delay
|
||||
0.00 2.00 ^ in3 (in)
|
||||
0.02 2.02 ^ or1/ZN (OR2_X1)
|
||||
0.01 2.03 v nor1/ZN (NOR2_X1)
|
||||
0.00 2.03 v reg2/D (DFF_X1)
|
||||
2.03 data arrival time
|
||||
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg2/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
---------------------------------------------------------
|
||||
0.00 data required time
|
||||
-2.03 data arrival time
|
||||
---------------------------------------------------------
|
||||
2.03 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 v reg1/Q (DFF_X1)
|
||||
0.00 0.08 v reg3/D (DFF_X1)
|
||||
0.08 data arrival time
|
||||
|
||||
0.00 0.00 clock clk2 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg3/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
---------------------------------------------------------
|
||||
0.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.08 slack (MET)
|
||||
|
||||
|
||||
PASS: report min
|
||||
Startpoint: in1 (input port clocked by clk1)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
2.00 2.00 v input external delay
|
||||
0.00 2.00 v in1 (in)
|
||||
0.02 2.02 v buf1/Z (BUF_X1)
|
||||
0.05 2.07 v or1/ZN (OR2_X1)
|
||||
0.03 2.09 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 2.09 ^ reg2/D (DFF_X1)
|
||||
2.09 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-2.09 data arrival time
|
||||
---------------------------------------------------------
|
||||
7.87 slack (MET)
|
||||
|
||||
|
||||
PASS: report from in1
|
||||
Startpoint: in2 (input port clocked by clk1)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
2.00 2.00 v input external delay
|
||||
0.00 2.00 v in2 (in)
|
||||
0.01 2.01 ^ inv1/ZN (INV_X1)
|
||||
0.03 2.04 ^ and1/ZN (AND2_X1)
|
||||
0.01 2.05 v nand1/ZN (NAND2_X1)
|
||||
0.00 2.05 v reg1/D (DFF_X1)
|
||||
2.05 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg1/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-2.05 data arrival time
|
||||
---------------------------------------------------------
|
||||
7.91 slack (MET)
|
||||
|
||||
|
||||
PASS: report from in2
|
||||
Startpoint: in3 (input port clocked by clk2)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk2 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
2.00 2.00 v input external delay
|
||||
0.00 2.00 v in3 (in)
|
||||
0.05 2.05 v or1/ZN (OR2_X1)
|
||||
0.03 2.07 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 2.07 ^ reg2/D (DFF_X1)
|
||||
2.07 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-2.07 data arrival time
|
||||
---------------------------------------------------------
|
||||
7.89 slack (MET)
|
||||
|
||||
|
||||
PASS: report from in3
|
||||
PASS: unset rise_from
|
||||
PASS: unset fall_from
|
||||
PASS: unset rise_to
|
||||
PASS: unset fall_to
|
||||
PASS: write after unset
|
||||
PASS: read_sdc
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: report after read
|
||||
PASS: write after read
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,160 @@
|
||||
# Test ExceptionPath.cc: complex multi-through false/multicycle paths
|
||||
# with rise/fall transition specifiers, priority calculation, merging.
|
||||
# Also exercises WriteSdc.cc exception writing with rise/fall transitions,
|
||||
# Sdc.cc resetPath for various exception types.
|
||||
# Targets: ExceptionPath.cc fromThruToPriority with rise/fall combos,
|
||||
# ExceptionPath::intersectsPts, ExceptionPath::mergeable,
|
||||
# ExceptionPathLess comparison, ExceptionThru::matches rise/fall,
|
||||
# ExceptionTo::matches rise/fall, ExceptionFrom::matches rise/fall,
|
||||
# Sdc.cc addException with rise/fall from/thru/to,
|
||||
# WriteSdc.cc writeException with -rise_from/-fall_from/-rise_to/-fall_to
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in2]
|
||||
set_input_delay -clock clk2 2.0 [get_ports in3]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 3.0 [get_ports out2]
|
||||
puts "PASS: setup"
|
||||
|
||||
############################################################
|
||||
# Test 1: false_path with -rise_from / -fall_from
|
||||
############################################################
|
||||
set_false_path -rise_from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: false_path -rise_from"
|
||||
|
||||
set_false_path -fall_from [get_ports in2] -to [get_ports out1]
|
||||
puts "PASS: false_path -fall_from"
|
||||
|
||||
############################################################
|
||||
# Test 2: false_path with -rise_to / -fall_to
|
||||
############################################################
|
||||
set_false_path -from [get_ports in1] -rise_to [get_ports out2]
|
||||
puts "PASS: false_path -rise_to"
|
||||
|
||||
set_false_path -from [get_ports in2] -fall_to [get_ports out2]
|
||||
puts "PASS: false_path -fall_to"
|
||||
|
||||
############################################################
|
||||
# Test 3: false_path with -rise_through / -fall_through
|
||||
############################################################
|
||||
set_false_path -rise_through [get_pins buf1/Z] -to [get_ports out1]
|
||||
puts "PASS: false_path -rise_through pin"
|
||||
|
||||
set_false_path -fall_through [get_pins inv1/ZN] -to [get_ports out2]
|
||||
puts "PASS: false_path -fall_through pin"
|
||||
|
||||
############################################################
|
||||
# Test 4: Combination of rise/fall from + through + to
|
||||
############################################################
|
||||
set_false_path -rise_from [get_ports in3] \
|
||||
-through [get_pins or1/ZN] \
|
||||
-fall_to [get_ports out2]
|
||||
puts "PASS: false_path rise_from + through + fall_to"
|
||||
|
||||
set_false_path -fall_from [get_ports in3] \
|
||||
-rise_through [get_pins or1/ZN] \
|
||||
-to [get_ports out1]
|
||||
puts "PASS: false_path fall_from + rise_through + to"
|
||||
|
||||
############################################################
|
||||
# Test 5: multicycle_path with rise/fall
|
||||
############################################################
|
||||
set_multicycle_path -setup 2 -rise_from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: mcp -rise_from setup"
|
||||
|
||||
set_multicycle_path -hold 1 -fall_from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: mcp -fall_from hold"
|
||||
|
||||
set_multicycle_path -setup 3 -from [get_ports in2] -rise_to [get_ports out1]
|
||||
puts "PASS: mcp -rise_to setup"
|
||||
|
||||
set_multicycle_path -hold 2 -from [get_ports in2] -fall_to [get_ports out1]
|
||||
puts "PASS: mcp -fall_to hold"
|
||||
|
||||
############################################################
|
||||
# Test 6: max_delay with rise/fall
|
||||
############################################################
|
||||
set_max_delay -rise_from [get_ports in1] -to [get_ports out2] 7.0
|
||||
puts "PASS: max_delay -rise_from"
|
||||
|
||||
set_max_delay -from [get_ports in3] -fall_to [get_ports out1] 8.0
|
||||
puts "PASS: max_delay -fall_to"
|
||||
|
||||
set_min_delay -fall_from [get_ports in2] -to [get_ports out2] 0.5
|
||||
puts "PASS: min_delay -fall_from"
|
||||
|
||||
set_min_delay -from [get_ports in3] -rise_to [get_ports out2] 0.3
|
||||
puts "PASS: min_delay -rise_to"
|
||||
|
||||
############################################################
|
||||
# Test 7: Write SDC and verify rise/fall transitions preserved
|
||||
############################################################
|
||||
set sdc1 [make_result_file sdc_exc_risefall1.sdc]
|
||||
write_sdc -no_timestamp $sdc1
|
||||
puts "PASS: write_sdc"
|
||||
|
||||
set sdc2 [make_result_file sdc_exc_risefall2.sdc]
|
||||
write_sdc -no_timestamp -compatible $sdc2
|
||||
puts "PASS: write_sdc compatible"
|
||||
|
||||
############################################################
|
||||
# Test 8: report_checks to validate exceptions applied
|
||||
############################################################
|
||||
report_checks -path_delay max
|
||||
puts "PASS: report max"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: report min"
|
||||
|
||||
report_checks -path_delay max -from [get_ports in1]
|
||||
puts "PASS: report from in1"
|
||||
|
||||
report_checks -path_delay max -from [get_ports in2]
|
||||
puts "PASS: report from in2"
|
||||
|
||||
report_checks -path_delay max -from [get_ports in3]
|
||||
puts "PASS: report from in3"
|
||||
|
||||
############################################################
|
||||
# Test 9: Unset rise/fall exceptions
|
||||
############################################################
|
||||
unset_path_exceptions -rise_from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: unset rise_from"
|
||||
|
||||
unset_path_exceptions -fall_from [get_ports in2] -to [get_ports out1]
|
||||
puts "PASS: unset fall_from"
|
||||
|
||||
unset_path_exceptions -from [get_ports in1] -rise_to [get_ports out2]
|
||||
puts "PASS: unset rise_to"
|
||||
|
||||
unset_path_exceptions -from [get_ports in2] -fall_to [get_ports out2]
|
||||
puts "PASS: unset fall_to"
|
||||
|
||||
############################################################
|
||||
# Test 10: Write after unset
|
||||
############################################################
|
||||
set sdc3 [make_result_file sdc_exc_risefall3.sdc]
|
||||
write_sdc -no_timestamp $sdc3
|
||||
puts "PASS: write after unset"
|
||||
|
||||
############################################################
|
||||
# Test 11: Read back SDC
|
||||
############################################################
|
||||
read_sdc $sdc1
|
||||
puts "PASS: read_sdc"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: report after read"
|
||||
|
||||
set sdc4 [make_result_file sdc_exc_risefall4.sdc]
|
||||
write_sdc -no_timestamp $sdc4
|
||||
puts "PASS: write after read"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,37 @@
|
||||
PASS: setup
|
||||
PASS: false_path through net n1
|
||||
PASS: false_path through net n2
|
||||
PASS: false_path from/through net n3/to
|
||||
PASS: false_path -rise_through net n4
|
||||
PASS: false_path -fall_through net n5
|
||||
PASS: false_path through instance buf1
|
||||
PASS: false_path from/through instance and1/to
|
||||
PASS: false_path -rise_through instance or1
|
||||
PASS: false_path through net then pin
|
||||
PASS: false_path through instance then pin
|
||||
PASS: false_path through pin then net
|
||||
PASS: false_path 3 through: pin, net, instance
|
||||
PASS: false_path multi-pin from/to
|
||||
PASS: false_path mixed clock+pin from
|
||||
PASS: false_path from instance
|
||||
PASS: false_path to instance
|
||||
PASS: max_delay through net
|
||||
PASS: max_delay through instance
|
||||
PASS: max_delay through pin
|
||||
PASS: min_delay through net
|
||||
PASS: max_delay -ignore_clock_latency
|
||||
PASS: multicycle through pin
|
||||
PASS: multicycle hold through pin
|
||||
PASS: group_path through net
|
||||
PASS: group_path through instance
|
||||
PASS: group_path through pin
|
||||
PASS: group_path -default
|
||||
PASS: write_sdc
|
||||
PASS: write_sdc compatible
|
||||
PASS: write_sdc digits 6
|
||||
PASS: unset net through paths
|
||||
PASS: unset instance through paths
|
||||
PASS: write_sdc after unset
|
||||
PASS: read_sdc
|
||||
PASS: write_sdc after read
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,220 @@
|
||||
# Test complex exception thru matching with nets, instances, pins
|
||||
# and the ExceptionThru state machine for multi-through points.
|
||||
# Targets:
|
||||
# ExceptionPath.cc: ExceptionThru::matches with nets/instances/pins,
|
||||
# ExceptionThru::intersectsPts with mixed object types,
|
||||
# ExceptionThru::equal, ExceptionThru::compare,
|
||||
# ExceptionThru::findHash with all object types,
|
||||
# ExceptionThru::allPins (net expansion to pins),
|
||||
# ExceptionTo::matches (with pin/clk/inst matching branches),
|
||||
# ExceptionTo::matchesFilter (report filter path),
|
||||
# ExceptionFrom::intersectsPts (pin/clk/inst branches),
|
||||
# ExceptionPath::intersectsPts,
|
||||
# ExceptionPath::mergeable (complex merge decisions),
|
||||
# fromThruToPriority calculation for various combos,
|
||||
# ExceptionPathLess comparison for sorting
|
||||
# Sdc.cc: makeExceptionThru with nets/instances/pins,
|
||||
# addException (merge logic), resetPath,
|
||||
# makeExceptionFrom with mixed pins/clocks/instances,
|
||||
# makeExceptionTo with mixed pins/clocks/instances
|
||||
# WriteSdc.cc: writeExceptionThru with nets/instances/pins,
|
||||
# writeExceptionFromTo with multi-object lists
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in2]
|
||||
set_input_delay -clock clk2 2.0 [get_ports in3]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 3.0 [get_ports out2]
|
||||
puts "PASS: setup"
|
||||
|
||||
############################################################
|
||||
# Test 1: Through nets (exercises ExceptionThru with nets)
|
||||
############################################################
|
||||
set_false_path -through [get_nets n1] -to [get_ports out1]
|
||||
puts "PASS: false_path through net n1"
|
||||
|
||||
set_false_path -through [get_nets n2] -to [get_ports out2]
|
||||
puts "PASS: false_path through net n2"
|
||||
|
||||
set_false_path -from [get_ports in1] -through [get_nets n3] -to [get_ports out1]
|
||||
puts "PASS: false_path from/through net n3/to"
|
||||
|
||||
# Through net with rise_through
|
||||
set_false_path -rise_through [get_nets n4] -to [get_ports out2]
|
||||
puts "PASS: false_path -rise_through net n4"
|
||||
|
||||
# Through net with fall_through
|
||||
set_false_path -fall_through [get_nets n5] -to [get_ports out1]
|
||||
puts "PASS: false_path -fall_through net n5"
|
||||
|
||||
############################################################
|
||||
# Test 2: Through instances (exercises ExceptionThru with instances)
|
||||
############################################################
|
||||
set_false_path -through [get_cells buf1] -to [get_ports out2]
|
||||
puts "PASS: false_path through instance buf1"
|
||||
|
||||
set_false_path -from [get_ports in2] -through [get_cells and1] -to [get_ports out1]
|
||||
puts "PASS: false_path from/through instance and1/to"
|
||||
|
||||
# Rise through instance
|
||||
set_false_path -from [get_ports in3] -rise_through [get_cells or1] -to [get_ports out2]
|
||||
puts "PASS: false_path -rise_through instance or1"
|
||||
|
||||
############################################################
|
||||
# Test 3: Multiple through points with mixed types
|
||||
# (net then pin, instance then pin, pin then net)
|
||||
############################################################
|
||||
|
||||
# Net then pin
|
||||
set_false_path -from [get_ports in1] \
|
||||
-through [get_nets n1] \
|
||||
-through [get_pins and1/ZN] \
|
||||
-to [get_ports out1]
|
||||
puts "PASS: false_path through net then pin"
|
||||
|
||||
# Instance then pin
|
||||
set_false_path -from [get_ports in2] \
|
||||
-through [get_cells inv1] \
|
||||
-through [get_pins nand1/ZN] \
|
||||
-to [get_ports out1]
|
||||
puts "PASS: false_path through instance then pin"
|
||||
|
||||
# Pin then net
|
||||
set_false_path -from [get_ports in1] \
|
||||
-through [get_pins buf1/Z] \
|
||||
-through [get_nets n3] \
|
||||
-to [get_ports out1]
|
||||
puts "PASS: false_path through pin then net"
|
||||
|
||||
# Three through points: pin, net, instance
|
||||
set_false_path -from [get_ports in2] \
|
||||
-through [get_pins inv1/ZN] \
|
||||
-through [get_nets n3] \
|
||||
-through [get_cells nand1] \
|
||||
-to [get_ports out1]
|
||||
puts "PASS: false_path 3 through: pin, net, instance"
|
||||
|
||||
############################################################
|
||||
# Test 4: From with mixed objects (pins + clocks)
|
||||
############################################################
|
||||
set_false_path -from [list [get_ports in1] [get_ports in2]] \
|
||||
-to [list [get_ports out1] [get_ports out2]]
|
||||
puts "PASS: false_path multi-pin from/to"
|
||||
|
||||
set_false_path -from [list [get_clocks clk1] [get_ports in3]] \
|
||||
-to [get_ports out1]
|
||||
puts "PASS: false_path mixed clock+pin from"
|
||||
|
||||
# From with instances
|
||||
set_false_path -from [get_cells reg1] -to [get_ports out2]
|
||||
puts "PASS: false_path from instance"
|
||||
|
||||
# To with instances
|
||||
set_false_path -from [get_ports in1] -to [get_cells reg2]
|
||||
puts "PASS: false_path to instance"
|
||||
|
||||
############################################################
|
||||
# Test 5: Max/min delay with through
|
||||
############################################################
|
||||
set_max_delay -from [get_ports in1] -through [get_nets n1] -to [get_ports out1] 7.0
|
||||
puts "PASS: max_delay through net"
|
||||
|
||||
set_max_delay -from [get_ports in2] -through [get_cells and1] -to [get_ports out1] 6.5
|
||||
puts "PASS: max_delay through instance"
|
||||
|
||||
set_max_delay -from [get_ports in3] \
|
||||
-through [get_pins or1/ZN] \
|
||||
-to [get_ports out2] 8.0
|
||||
puts "PASS: max_delay through pin"
|
||||
|
||||
set_min_delay -from [get_ports in1] -through [get_nets n1] -to [get_ports out1] 0.5
|
||||
puts "PASS: min_delay through net"
|
||||
|
||||
# Max delay with -ignore_clock_latency
|
||||
set_max_delay -from [get_ports in3] -to [get_ports out2] -ignore_clock_latency 9.0
|
||||
puts "PASS: max_delay -ignore_clock_latency"
|
||||
|
||||
############################################################
|
||||
# Test 6: Multicycle with through
|
||||
############################################################
|
||||
set_multicycle_path -setup 2 -from [get_ports in1] \
|
||||
-through [get_pins buf1/Z] \
|
||||
-to [get_ports out1]
|
||||
puts "PASS: multicycle through pin"
|
||||
|
||||
set_multicycle_path -hold 1 -from [get_ports in1] \
|
||||
-through [get_pins buf1/Z] \
|
||||
-to [get_ports out1]
|
||||
puts "PASS: multicycle hold through pin"
|
||||
|
||||
############################################################
|
||||
# Test 7: Group path with through nets/instances
|
||||
############################################################
|
||||
group_path -name gp_net -from [get_ports in1] \
|
||||
-through [get_nets n1] \
|
||||
-to [get_ports out1]
|
||||
puts "PASS: group_path through net"
|
||||
|
||||
group_path -name gp_inst -from [get_ports in2] \
|
||||
-through [get_cells and1] \
|
||||
-to [get_ports out1]
|
||||
puts "PASS: group_path through instance"
|
||||
|
||||
group_path -name gp_pin -from [get_ports in3] \
|
||||
-through [get_pins or1/ZN] \
|
||||
-to [get_ports out2]
|
||||
puts "PASS: group_path through pin"
|
||||
|
||||
group_path -default -from [get_ports in1] -to [get_ports out2]
|
||||
puts "PASS: group_path -default"
|
||||
|
||||
############################################################
|
||||
# Write SDC
|
||||
############################################################
|
||||
set sdc1 [make_result_file sdc_exc_thru_complex1.sdc]
|
||||
write_sdc -no_timestamp $sdc1
|
||||
puts "PASS: write_sdc"
|
||||
|
||||
set sdc2 [make_result_file sdc_exc_thru_complex2.sdc]
|
||||
write_sdc -no_timestamp -compatible $sdc2
|
||||
puts "PASS: write_sdc compatible"
|
||||
|
||||
set sdc3 [make_result_file sdc_exc_thru_complex3.sdc]
|
||||
write_sdc -no_timestamp -digits 6 $sdc3
|
||||
puts "PASS: write_sdc digits 6"
|
||||
|
||||
############################################################
|
||||
# Unset and verify
|
||||
############################################################
|
||||
unset_path_exceptions -through [get_nets n1] -to [get_ports out1]
|
||||
unset_path_exceptions -through [get_nets n2] -to [get_ports out2]
|
||||
unset_path_exceptions -from [get_ports in1] -through [get_nets n3] -to [get_ports out1]
|
||||
puts "PASS: unset net through paths"
|
||||
|
||||
unset_path_exceptions -through [get_cells buf1] -to [get_ports out2]
|
||||
unset_path_exceptions -from [get_ports in2] -through [get_cells and1] -to [get_ports out1]
|
||||
puts "PASS: unset instance through paths"
|
||||
|
||||
# Write after unset to verify reduced constraints
|
||||
set sdc_unset [make_result_file sdc_exc_thru_complex_unset.sdc]
|
||||
write_sdc -no_timestamp $sdc_unset
|
||||
puts "PASS: write_sdc after unset"
|
||||
|
||||
############################################################
|
||||
# Read back SDC and verify roundtrip
|
||||
############################################################
|
||||
read_sdc $sdc1
|
||||
puts "PASS: read_sdc"
|
||||
|
||||
set sdc4 [make_result_file sdc_exc_thru_complex4.sdc]
|
||||
write_sdc -no_timestamp $sdc4
|
||||
puts "PASS: write_sdc after read"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,27 @@
|
||||
PASS: setup
|
||||
PASS: false_path through net
|
||||
PASS: false_path from/through net/to
|
||||
PASS: false_path through net+pin
|
||||
PASS: false_path through instance
|
||||
PASS: false_path from instance
|
||||
PASS: false_path to instance
|
||||
PASS: false_path multi-object
|
||||
PASS: false_path multi from (clk + pin)
|
||||
PASS: write_sdc with net/inst exceptions
|
||||
PASS: unset exceptions
|
||||
PASS: max_delay -ignore_clock_latency
|
||||
PASS: min_delay
|
||||
PASS: max_delay through net
|
||||
PASS: max_delay through instance
|
||||
PASS: multicycle -setup -start
|
||||
PASS: multicycle -hold -end
|
||||
PASS: group_path -default
|
||||
PASS: group_path with through
|
||||
PASS: write_sdc with all exception types
|
||||
PASS: write_sdc compatible
|
||||
group_path_names = grp_thru
|
||||
PASS: group_path_names
|
||||
is_path_group_name grp_thru = 1
|
||||
is_path_group_name nonexistent = 0
|
||||
PASS: is_path_group_name
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,159 @@
|
||||
# Test exception paths with through nets and instances,
|
||||
# multi-object from/to, group_path default, and write_sdc
|
||||
# exercises exception writing with nets/instances.
|
||||
# Targets:
|
||||
# ExceptionPath.cc: ExceptionPath constructor, fromThruToPriority,
|
||||
# firstPt, matchesFirstPt, asString, typeString,
|
||||
# ExceptionFrom/To/Thru with instances/nets/clks combinations,
|
||||
# ExceptionPathLess comparison, checkFromThrusTo,
|
||||
# setPriority, setId
|
||||
# Sdc.cc: makeFalsePath, makeMulticyclePath, makePathDelay,
|
||||
# makeGroupPath (default), resetPath, makeExceptionFrom/Thru/To,
|
||||
# deleteExceptionFrom/Thru/To, checkExceptionFromPins/ToPins,
|
||||
# isPathGroupName
|
||||
# WriteSdc.cc: writeException, writeExceptionCmd (all types),
|
||||
# writeExceptionFrom/To/Thru with multi-objects,
|
||||
# writeExceptionValue (multicycle multiplier, delay value),
|
||||
# writeGroupPath (default and named),
|
||||
# mapThruHpins
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in2]
|
||||
set_input_delay -clock clk2 2.0 [get_ports in3]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 3.0 [get_ports out2]
|
||||
puts "PASS: setup"
|
||||
|
||||
############################################################
|
||||
# False path with through nets
|
||||
############################################################
|
||||
set_false_path -through [get_nets n1] -to [get_ports out1]
|
||||
puts "PASS: false_path through net"
|
||||
|
||||
set_false_path -from [get_ports in2] -through [get_nets n2] -to [get_ports out1]
|
||||
puts "PASS: false_path from/through net/to"
|
||||
|
||||
# False path through net and pin combined
|
||||
set_false_path -from [get_ports in1] -through [get_nets n3] -through [get_pins nand1/ZN] -to [get_ports out1]
|
||||
puts "PASS: false_path through net+pin"
|
||||
|
||||
############################################################
|
||||
# False path with through instances
|
||||
############################################################
|
||||
set_false_path -from [get_ports in1] -through [get_cells buf1] -to [get_ports out2]
|
||||
puts "PASS: false_path through instance"
|
||||
|
||||
############################################################
|
||||
# False path with from instances
|
||||
############################################################
|
||||
set_false_path -from [get_cells reg1] -to [get_ports out2]
|
||||
puts "PASS: false_path from instance"
|
||||
|
||||
############################################################
|
||||
# False path with to instances
|
||||
############################################################
|
||||
set_false_path -from [get_ports in1] -to [get_cells reg2]
|
||||
puts "PASS: false_path to instance"
|
||||
|
||||
############################################################
|
||||
# Multi-object from/to
|
||||
############################################################
|
||||
set_false_path -from [list [get_ports in1] [get_ports in2]] \
|
||||
-to [list [get_ports out1] [get_ports out2]]
|
||||
puts "PASS: false_path multi-object"
|
||||
|
||||
# Multi-object with clocks
|
||||
set_false_path -setup -from [list [get_clocks clk1] [get_ports in3]] \
|
||||
-to [get_ports out1]
|
||||
puts "PASS: false_path multi from (clk + pin)"
|
||||
|
||||
############################################################
|
||||
# Write to verify exception writing
|
||||
############################################################
|
||||
set sdc1 [make_result_file sdc_exception_thru1.sdc]
|
||||
write_sdc -no_timestamp $sdc1
|
||||
puts "PASS: write_sdc with net/inst exceptions"
|
||||
|
||||
############################################################
|
||||
# Unset all false paths and create new ones
|
||||
############################################################
|
||||
unset_path_exceptions -through [get_nets n1] -to [get_ports out1]
|
||||
unset_path_exceptions -from [get_ports in2] -through [get_nets n2] -to [get_ports out1]
|
||||
unset_path_exceptions -from [get_ports in1] -through [get_nets n3] -through [get_pins nand1/ZN] -to [get_ports out1]
|
||||
unset_path_exceptions -from [get_ports in1] -through [get_cells buf1] -to [get_ports out2]
|
||||
unset_path_exceptions -from [get_cells reg1] -to [get_ports out2]
|
||||
unset_path_exceptions -from [get_ports in1] -to [get_cells reg2]
|
||||
puts "PASS: unset exceptions"
|
||||
|
||||
############################################################
|
||||
# Max/min delay with -ignore_clock_latency
|
||||
############################################################
|
||||
set_max_delay -from [get_ports in1] -to [get_ports out1] -ignore_clock_latency 8.0
|
||||
puts "PASS: max_delay -ignore_clock_latency"
|
||||
|
||||
set_min_delay -from [get_ports in1] -to [get_ports out1] 1.0
|
||||
puts "PASS: min_delay"
|
||||
|
||||
# Max delay with through net
|
||||
set_max_delay -from [get_ports in2] -through [get_nets n2] -to [get_ports out1] 6.0
|
||||
puts "PASS: max_delay through net"
|
||||
|
||||
# Max delay with through instance
|
||||
set_max_delay -from [get_ports in3] -through [get_cells or1] -to [get_ports out2] 7.0
|
||||
puts "PASS: max_delay through instance"
|
||||
|
||||
############################################################
|
||||
# Multicycle path with -start/-end
|
||||
############################################################
|
||||
set_multicycle_path -setup -start 3 -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: multicycle -setup -start"
|
||||
|
||||
set_multicycle_path -hold -end 1 -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: multicycle -hold -end"
|
||||
|
||||
############################################################
|
||||
# Group path - default
|
||||
############################################################
|
||||
group_path -default -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: group_path -default"
|
||||
|
||||
# Named group path with through
|
||||
group_path -name grp_thru -from [get_ports in2] -through [get_pins and1/ZN] -to [get_ports out1]
|
||||
puts "PASS: group_path with through"
|
||||
|
||||
############################################################
|
||||
# Write with all exception types
|
||||
############################################################
|
||||
set sdc2 [make_result_file sdc_exception_thru2.sdc]
|
||||
write_sdc -no_timestamp $sdc2
|
||||
puts "PASS: write_sdc with all exception types"
|
||||
|
||||
set sdc3 [make_result_file sdc_exception_thru3.sdc]
|
||||
write_sdc -no_timestamp -compatible $sdc3
|
||||
puts "PASS: write_sdc compatible"
|
||||
|
||||
############################################################
|
||||
# Group path names query
|
||||
############################################################
|
||||
set gp_names [sta::group_path_names]
|
||||
puts "group_path_names = $gp_names"
|
||||
puts "PASS: group_path_names"
|
||||
|
||||
############################################################
|
||||
# is_path_group_name
|
||||
############################################################
|
||||
set is_gp [sta::is_path_group_name "grp_thru"]
|
||||
puts "is_path_group_name grp_thru = $is_gp"
|
||||
|
||||
set is_gp [sta::is_path_group_name "nonexistent"]
|
||||
puts "is_path_group_name nonexistent = $is_gp"
|
||||
puts "PASS: is_path_group_name"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,783 @@
|
||||
--- set_false_path -rise_from ---
|
||||
Startpoint: in1 (input port clocked by clk1)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v in1 (in)
|
||||
0.02 1.02 v buf1/Z (BUF_X1)
|
||||
0.05 1.07 v or1/ZN (OR2_X1)
|
||||
0.03 1.09 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 1.09 ^ reg2/D (DFF_X1)
|
||||
1.09 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-1.09 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.87 slack (MET)
|
||||
|
||||
|
||||
PASS: false_path rise_from
|
||||
--- set_false_path -fall_from ---
|
||||
Startpoint: in2 (input port clocked by clk1)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v in2 (in)
|
||||
0.01 1.01 ^ inv1/ZN (INV_X1)
|
||||
0.03 1.04 ^ and1/ZN (AND2_X1)
|
||||
0.01 1.05 v nand1/ZN (NAND2_X1)
|
||||
0.00 1.05 v reg1/D (DFF_X1)
|
||||
1.05 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg1/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-1.05 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.91 slack (MET)
|
||||
|
||||
|
||||
PASS: false_path fall_from
|
||||
--- unset rise/fall from ---
|
||||
PASS: unset rise/fall from
|
||||
--- set_false_path -rise_to ---
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-2.00 8.00 output external delay
|
||||
8.00 data required time
|
||||
---------------------------------------------------------
|
||||
8.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
7.92 slack (MET)
|
||||
|
||||
|
||||
PASS: false_path rise_to
|
||||
--- set_false_path -fall_to ---
|
||||
Startpoint: in2 (input port clocked by clk1)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v in2 (in)
|
||||
0.01 1.01 ^ inv1/ZN (INV_X1)
|
||||
0.03 1.04 ^ and1/ZN (AND2_X1)
|
||||
0.01 1.05 v nand1/ZN (NAND2_X1)
|
||||
0.00 1.05 v reg1/D (DFF_X1)
|
||||
1.05 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg1/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-1.05 data arrival time
|
||||
---------------------------------------------------------
|
||||
8.91 slack (MET)
|
||||
|
||||
|
||||
PASS: false_path fall_to
|
||||
--- unset rise/fall to ---
|
||||
PASS: unset rise/fall to
|
||||
--- set_false_path -rise_through ---
|
||||
Startpoint: in3 (input port clocked by clk2)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
15.00 15.00 clock clk2 (rise edge)
|
||||
0.00 15.00 clock network delay (ideal)
|
||||
2.00 17.00 v input external delay
|
||||
0.00 17.00 v in3 (in)
|
||||
0.05 17.05 v or1/ZN (OR2_X1)
|
||||
0.03 17.07 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 17.07 ^ reg2/D (DFF_X1)
|
||||
17.07 data arrival time
|
||||
|
||||
20.00 20.00 clock clk1 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 19.97 library setup time
|
||||
19.97 data required time
|
||||
---------------------------------------------------------
|
||||
19.97 data required time
|
||||
-17.07 data arrival time
|
||||
---------------------------------------------------------
|
||||
2.89 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
15.00 15.00 clock clk2 (rise edge)
|
||||
0.00 15.00 clock network delay (ideal)
|
||||
0.00 15.00 clock reconvergence pessimism
|
||||
15.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 14.96 library setup time
|
||||
14.96 data required time
|
||||
---------------------------------------------------------
|
||||
14.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: false_path rise_through
|
||||
--- set_false_path -fall_through ---
|
||||
Startpoint: in3 (input port clocked by clk2)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
15.00 15.00 clock clk2 (rise edge)
|
||||
0.00 15.00 clock network delay (ideal)
|
||||
2.00 17.00 v input external delay
|
||||
0.00 17.00 v in3 (in)
|
||||
0.05 17.05 v or1/ZN (OR2_X1)
|
||||
0.03 17.07 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 17.07 ^ reg2/D (DFF_X1)
|
||||
17.07 data arrival time
|
||||
|
||||
20.00 20.00 clock clk1 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 19.97 library setup time
|
||||
19.97 data required time
|
||||
---------------------------------------------------------
|
||||
19.97 data required time
|
||||
-17.07 data arrival time
|
||||
---------------------------------------------------------
|
||||
2.89 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
15.00 15.00 clock clk2 (rise edge)
|
||||
0.00 15.00 clock network delay (ideal)
|
||||
0.00 15.00 clock reconvergence pessimism
|
||||
15.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 14.96 library setup time
|
||||
14.96 data required time
|
||||
---------------------------------------------------------
|
||||
14.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: false_path fall_through
|
||||
--- unset rise/fall through ---
|
||||
PASS: unset rise/fall through
|
||||
--- priority: broad false_path ---
|
||||
No paths found.
|
||||
PASS: broad false_path
|
||||
--- priority: narrower multicycle overriding false_path ---
|
||||
No paths found.
|
||||
PASS: narrower mcp overrides
|
||||
--- priority: most specific max_delay ---
|
||||
No paths found.
|
||||
PASS: most specific max_delay
|
||||
--- unset all ---
|
||||
PASS: unset all priority
|
||||
--- false_path from clock ---
|
||||
Startpoint: in3 (input port clocked by clk2)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
15.00 15.00 clock clk2 (rise edge)
|
||||
0.00 15.00 clock network delay (ideal)
|
||||
2.00 17.00 v input external delay
|
||||
0.00 17.00 v in3 (in)
|
||||
0.05 17.05 v or1/ZN (OR2_X1)
|
||||
0.03 17.07 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 17.07 ^ reg2/D (DFF_X1)
|
||||
17.07 data arrival time
|
||||
|
||||
20.00 20.00 clock clk1 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 19.97 library setup time
|
||||
19.97 data required time
|
||||
---------------------------------------------------------
|
||||
19.97 data required time
|
||||
-17.07 data arrival time
|
||||
---------------------------------------------------------
|
||||
2.89 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Endpoint: out2 (output port clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk2 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg3/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg3/Q (DFF_X1)
|
||||
0.00 0.08 ^ out2 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
15.00 15.00 clock clk2 (rise edge)
|
||||
0.00 15.00 clock network delay (ideal)
|
||||
0.00 15.00 clock reconvergence pessimism
|
||||
-3.00 12.00 output external delay
|
||||
12.00 data required time
|
||||
---------------------------------------------------------
|
||||
12.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
11.92 slack (MET)
|
||||
|
||||
|
||||
PASS: false_path clk1->clk2
|
||||
--- unset clock false_path ---
|
||||
Startpoint: in3 (input port clocked by clk2)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
15.00 15.00 clock clk2 (rise edge)
|
||||
0.00 15.00 clock network delay (ideal)
|
||||
2.00 17.00 v input external delay
|
||||
0.00 17.00 v in3 (in)
|
||||
0.05 17.05 v or1/ZN (OR2_X1)
|
||||
0.03 17.07 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 17.07 ^ reg2/D (DFF_X1)
|
||||
17.07 data arrival time
|
||||
|
||||
20.00 20.00 clock clk1 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 19.97 library setup time
|
||||
19.97 data required time
|
||||
---------------------------------------------------------
|
||||
19.97 data required time
|
||||
-17.07 data arrival time
|
||||
---------------------------------------------------------
|
||||
2.89 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
15.00 15.00 clock clk2 (rise edge)
|
||||
0.00 15.00 clock network delay (ideal)
|
||||
0.00 15.00 clock reconvergence pessimism
|
||||
15.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 14.96 library setup time
|
||||
14.96 data required time
|
||||
---------------------------------------------------------
|
||||
14.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: unset clock false_path
|
||||
--- false_path -rise_from clock ---
|
||||
Startpoint: in3 (input port clocked by clk2)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
15.00 15.00 clock clk2 (rise edge)
|
||||
0.00 15.00 clock network delay (ideal)
|
||||
2.00 17.00 v input external delay
|
||||
0.00 17.00 v in3 (in)
|
||||
0.05 17.05 v or1/ZN (OR2_X1)
|
||||
0.03 17.07 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 17.07 ^ reg2/D (DFF_X1)
|
||||
17.07 data arrival time
|
||||
|
||||
20.00 20.00 clock clk1 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 19.97 library setup time
|
||||
19.97 data required time
|
||||
---------------------------------------------------------
|
||||
19.97 data required time
|
||||
-17.07 data arrival time
|
||||
---------------------------------------------------------
|
||||
2.89 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Endpoint: out2 (output port clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk2 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg3/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg3/Q (DFF_X1)
|
||||
0.00 0.08 ^ out2 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
15.00 15.00 clock clk2 (rise edge)
|
||||
0.00 15.00 clock network delay (ideal)
|
||||
0.00 15.00 clock reconvergence pessimism
|
||||
-3.00 12.00 output external delay
|
||||
12.00 data required time
|
||||
---------------------------------------------------------
|
||||
12.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
11.92 slack (MET)
|
||||
|
||||
|
||||
PASS: false_path rise_from clock
|
||||
--- unset rise_from clock ---
|
||||
PASS: unset rise_from clock
|
||||
--- overlapping exceptions ---
|
||||
Startpoint: in3 (input port clocked by clk2)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
15.00 15.00 clock clk2 (rise edge)
|
||||
0.00 15.00 clock network delay (ideal)
|
||||
2.00 17.00 v input external delay
|
||||
0.00 17.00 v in3 (in)
|
||||
0.05 17.05 v or1/ZN (OR2_X1)
|
||||
0.03 17.07 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 17.07 ^ reg2/D (DFF_X1)
|
||||
17.07 data arrival time
|
||||
|
||||
20.00 20.00 clock clk1 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 19.97 library setup time
|
||||
19.97 data required time
|
||||
---------------------------------------------------------
|
||||
19.97 data required time
|
||||
-17.07 data arrival time
|
||||
---------------------------------------------------------
|
||||
2.89 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Endpoint: out2 (output port clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk2 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg3/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg3/Q (DFF_X1)
|
||||
0.00 0.08 ^ out2 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
15.00 15.00 clock clk2 (rise edge)
|
||||
0.00 15.00 clock network delay (ideal)
|
||||
0.00 15.00 clock reconvergence pessimism
|
||||
-3.00 12.00 output external delay
|
||||
12.00 data required time
|
||||
---------------------------------------------------------
|
||||
12.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
11.92 slack (MET)
|
||||
|
||||
|
||||
PASS: overlapping exceptions
|
||||
--- unset overlapping ---
|
||||
Startpoint: in3 (input port clocked by clk2)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
15.00 15.00 clock clk2 (rise edge)
|
||||
0.00 15.00 clock network delay (ideal)
|
||||
2.00 17.00 v input external delay
|
||||
0.00 17.00 v in3 (in)
|
||||
0.05 17.05 v or1/ZN (OR2_X1)
|
||||
0.03 17.07 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 17.07 ^ reg2/D (DFF_X1)
|
||||
17.07 data arrival time
|
||||
|
||||
20.00 20.00 clock clk1 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 19.97 library setup time
|
||||
19.97 data required time
|
||||
---------------------------------------------------------
|
||||
19.97 data required time
|
||||
-17.07 data arrival time
|
||||
---------------------------------------------------------
|
||||
2.89 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Endpoint: out2 (output port clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk2 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg3/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg3/Q (DFF_X1)
|
||||
0.00 0.08 ^ out2 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
15.00 15.00 clock clk2 (rise edge)
|
||||
0.00 15.00 clock network delay (ideal)
|
||||
0.00 15.00 clock reconvergence pessimism
|
||||
-3.00 12.00 output external delay
|
||||
12.00 data required time
|
||||
---------------------------------------------------------
|
||||
12.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
11.92 slack (MET)
|
||||
|
||||
|
||||
PASS: unset overlapping
|
||||
--- mcp -start -rise_from ---
|
||||
Startpoint: in3 (input port clocked by clk2)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
15.00 15.00 clock clk2 (rise edge)
|
||||
0.00 15.00 clock network delay (ideal)
|
||||
2.00 17.00 v input external delay
|
||||
0.00 17.00 v in3 (in)
|
||||
0.05 17.05 v or1/ZN (OR2_X1)
|
||||
0.03 17.07 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 17.07 ^ reg2/D (DFF_X1)
|
||||
17.07 data arrival time
|
||||
|
||||
20.00 20.00 clock clk1 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 19.97 library setup time
|
||||
19.97 data required time
|
||||
---------------------------------------------------------
|
||||
19.97 data required time
|
||||
-17.07 data arrival time
|
||||
---------------------------------------------------------
|
||||
2.89 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Endpoint: out2 (output port clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk2 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg3/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg3/Q (DFF_X1)
|
||||
0.00 0.08 ^ out2 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
15.00 15.00 clock clk2 (rise edge)
|
||||
0.00 15.00 clock network delay (ideal)
|
||||
0.00 15.00 clock reconvergence pessimism
|
||||
-3.00 12.00 output external delay
|
||||
12.00 data required time
|
||||
---------------------------------------------------------
|
||||
12.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
11.92 slack (MET)
|
||||
|
||||
|
||||
PASS: mcp start rise_from
|
||||
--- mcp -end -fall_to ---
|
||||
Startpoint: in3 (input port clocked by clk2)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
15.00 15.00 clock clk2 (rise edge)
|
||||
0.00 15.00 clock network delay (ideal)
|
||||
2.00 17.00 v input external delay
|
||||
0.00 17.00 v in3 (in)
|
||||
0.05 17.05 v or1/ZN (OR2_X1)
|
||||
0.03 17.07 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 17.07 ^ reg2/D (DFF_X1)
|
||||
17.07 data arrival time
|
||||
|
||||
20.00 20.00 clock clk1 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 19.97 library setup time
|
||||
19.97 data required time
|
||||
---------------------------------------------------------
|
||||
19.97 data required time
|
||||
-17.07 data arrival time
|
||||
---------------------------------------------------------
|
||||
2.89 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Endpoint: out2 (output port clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk2 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg3/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg3/Q (DFF_X1)
|
||||
0.00 0.08 ^ out2 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
15.00 15.00 clock clk2 (rise edge)
|
||||
0.00 15.00 clock network delay (ideal)
|
||||
0.00 15.00 clock reconvergence pessimism
|
||||
-3.00 12.00 output external delay
|
||||
12.00 data required time
|
||||
---------------------------------------------------------
|
||||
12.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
11.92 slack (MET)
|
||||
|
||||
|
||||
PASS: mcp end fall_to
|
||||
--- unset mcp ---
|
||||
PASS: unset mcp
|
||||
--- max_delay -rise_from -to ---
|
||||
Startpoint: in3 (input port clocked by clk2)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
15.00 15.00 clock clk2 (rise edge)
|
||||
0.00 15.00 clock network delay (ideal)
|
||||
2.00 17.00 v input external delay
|
||||
0.00 17.00 v in3 (in)
|
||||
0.05 17.05 v or1/ZN (OR2_X1)
|
||||
0.03 17.07 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 17.07 ^ reg2/D (DFF_X1)
|
||||
17.07 data arrival time
|
||||
|
||||
20.00 20.00 clock clk1 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 19.97 library setup time
|
||||
19.97 data required time
|
||||
---------------------------------------------------------
|
||||
19.97 data required time
|
||||
-17.07 data arrival time
|
||||
---------------------------------------------------------
|
||||
2.89 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Endpoint: out2 (output port clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk2 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg3/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg3/Q (DFF_X1)
|
||||
0.00 0.08 ^ out2 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
15.00 15.00 clock clk2 (rise edge)
|
||||
0.00 15.00 clock network delay (ideal)
|
||||
0.00 15.00 clock reconvergence pessimism
|
||||
-3.00 12.00 output external delay
|
||||
12.00 data required time
|
||||
---------------------------------------------------------
|
||||
12.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
11.92 slack (MET)
|
||||
|
||||
|
||||
PASS: max_delay rise_from
|
||||
--- min_delay -from -fall_to ---
|
||||
Startpoint: in2 (input port clocked by clk1)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 ^ input external delay
|
||||
0.00 1.00 ^ in2 (in)
|
||||
0.00 1.00 v inv1/ZN (INV_X1)
|
||||
0.03 1.03 v and1/ZN (AND2_X1)
|
||||
0.01 1.05 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 1.05 ^ reg1/D (DFF_X1)
|
||||
1.05 data arrival time
|
||||
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg1/CK (DFF_X1)
|
||||
0.01 0.01 library hold time
|
||||
0.01 data required time
|
||||
---------------------------------------------------------
|
||||
0.01 data required time
|
||||
-1.05 data arrival time
|
||||
---------------------------------------------------------
|
||||
1.04 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Endpoint: out2 (output port clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk2 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg3/CK (DFF_X1)
|
||||
0.08 0.08 v reg3/Q (DFF_X1)
|
||||
0.00 0.08 v out2 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
0.00 0.00 clock clk2 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
-3.00 -3.00 output external delay
|
||||
-3.00 data required time
|
||||
---------------------------------------------------------
|
||||
-3.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
3.08 slack (MET)
|
||||
|
||||
|
||||
PASS: min_delay fall_to
|
||||
--- unset max/min delays ---
|
||||
PASS: unset max/min delays
|
||||
PASS: write_sdc exceptions
|
||||
PASS: write_sdc compatible
|
||||
PASS: read_sdc exceptions
|
||||
PASS: write_sdc after read
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,208 @@
|
||||
# Test ExceptionPath.cc: exception path overriding, priority ordering,
|
||||
# intersectsPts with rise/fall transitions, equal/compare/hash operations,
|
||||
# and exception merging with complex thru point combinations.
|
||||
# Targets: ExceptionPath.cc ExceptionPath::matches, overrides,
|
||||
# ExceptionPath::intersectsPts with rise/fall pins,
|
||||
# ExceptionPath::mergeable, ExceptionPath::tighterThan,
|
||||
# ExceptionPathLess comparison, ExceptionPath::resetMatch,
|
||||
# ExceptionTo::matches with rise/fall/instance matching,
|
||||
# ExceptionFrom::matches with clock/rise/fall,
|
||||
# ExceptionThru::matches with net/pin/instance combinations,
|
||||
# fromThruToPriority with different specificity levels,
|
||||
# Sdc.cc addException (merge/override), deleteException,
|
||||
# makeExceptionFrom with rise_from/fall_from,
|
||||
# makeExceptionTo with rise_to/fall_to
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 15 [get_ports clk2]
|
||||
set_input_delay -clock clk1 1.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 1.0 [get_ports in2]
|
||||
set_input_delay -clock clk2 2.0 [get_ports in3]
|
||||
set_output_delay -clock clk1 2.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 3.0 [get_ports out2]
|
||||
|
||||
report_checks > /dev/null
|
||||
|
||||
############################################################
|
||||
# Test 1: Rise/fall from exceptions
|
||||
############################################################
|
||||
puts "--- set_false_path -rise_from ---"
|
||||
set_false_path -rise_from [get_ports in1] -to [get_ports out1]
|
||||
report_checks -path_delay max -from [get_ports in1]
|
||||
puts "PASS: false_path rise_from"
|
||||
|
||||
puts "--- set_false_path -fall_from ---"
|
||||
set_false_path -fall_from [get_ports in2] -to [get_ports out1]
|
||||
report_checks -path_delay max -from [get_ports in2]
|
||||
puts "PASS: false_path fall_from"
|
||||
|
||||
puts "--- unset rise/fall from ---"
|
||||
unset_path_exceptions -from [get_ports in1] -to [get_ports out1]
|
||||
unset_path_exceptions -from [get_ports in2] -to [get_ports out1]
|
||||
puts "PASS: unset rise/fall from"
|
||||
|
||||
############################################################
|
||||
# Test 2: Rise/fall to exceptions
|
||||
############################################################
|
||||
puts "--- set_false_path -rise_to ---"
|
||||
set_false_path -from [get_ports in1] -rise_to [get_ports out1]
|
||||
report_checks -path_delay max -to [get_ports out1]
|
||||
puts "PASS: false_path rise_to"
|
||||
|
||||
puts "--- set_false_path -fall_to ---"
|
||||
set_false_path -from [get_ports in2] -fall_to [get_ports out1]
|
||||
report_checks -path_delay max -from [get_ports in2]
|
||||
puts "PASS: false_path fall_to"
|
||||
|
||||
puts "--- unset rise/fall to ---"
|
||||
unset_path_exceptions -from [get_ports in1] -to [get_ports out1]
|
||||
unset_path_exceptions -from [get_ports in2] -to [get_ports out1]
|
||||
puts "PASS: unset rise/fall to"
|
||||
|
||||
############################################################
|
||||
# Test 3: Rise/fall through exceptions
|
||||
############################################################
|
||||
puts "--- set_false_path -rise_through ---"
|
||||
set_false_path -rise_through [get_pins buf1/Z] -to [get_ports out1]
|
||||
report_checks -path_delay max
|
||||
puts "PASS: false_path rise_through"
|
||||
|
||||
puts "--- set_false_path -fall_through ---"
|
||||
set_false_path -fall_through [get_pins inv1/ZN] -to [get_ports out1]
|
||||
report_checks -path_delay max
|
||||
puts "PASS: false_path fall_through"
|
||||
|
||||
puts "--- unset rise/fall through ---"
|
||||
unset_path_exceptions -through [get_pins buf1/Z] -to [get_ports out1]
|
||||
unset_path_exceptions -through [get_pins inv1/ZN] -to [get_ports out1]
|
||||
puts "PASS: unset rise/fall through"
|
||||
|
||||
############################################################
|
||||
# Test 4: Exception priority ordering (more specific overrides less specific)
|
||||
############################################################
|
||||
puts "--- priority: broad false_path ---"
|
||||
set_false_path -from [get_ports in1]
|
||||
report_checks -path_delay max -from [get_ports in1]
|
||||
puts "PASS: broad false_path"
|
||||
|
||||
puts "--- priority: narrower multicycle overriding false_path ---"
|
||||
set_multicycle_path 2 -setup -from [get_ports in1] -to [get_ports out1]
|
||||
report_checks -path_delay max -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: narrower mcp overrides"
|
||||
|
||||
puts "--- priority: most specific max_delay ---"
|
||||
set_max_delay 5.0 -from [get_ports in1] -through [get_pins buf1/Z] -to [get_ports out1]
|
||||
report_checks -path_delay max -from [get_ports in1] -through [get_pins buf1/Z] -to [get_ports out1]
|
||||
puts "PASS: most specific max_delay"
|
||||
|
||||
puts "--- unset all ---"
|
||||
unset_path_exceptions -from [get_ports in1]
|
||||
unset_path_exceptions -from [get_ports in1] -to [get_ports out1]
|
||||
unset_path_exceptions -from [get_ports in1] -through [get_pins buf1/Z] -to [get_ports out1]
|
||||
puts "PASS: unset all priority"
|
||||
|
||||
############################################################
|
||||
# Test 5: Clock-based from/to exceptions
|
||||
############################################################
|
||||
puts "--- false_path from clock ---"
|
||||
set_false_path -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
report_checks -path_delay max
|
||||
puts "PASS: false_path clk1->clk2"
|
||||
|
||||
puts "--- unset clock false_path ---"
|
||||
unset_path_exceptions -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
report_checks -path_delay max
|
||||
puts "PASS: unset clock false_path"
|
||||
|
||||
puts "--- false_path -rise_from clock ---"
|
||||
set_false_path -rise_from [get_clocks clk1] -to [get_clocks clk2]
|
||||
report_checks -path_delay max
|
||||
puts "PASS: false_path rise_from clock"
|
||||
|
||||
puts "--- unset rise_from clock ---"
|
||||
unset_path_exceptions -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
puts "PASS: unset rise_from clock"
|
||||
|
||||
############################################################
|
||||
# Test 6: Multiple overlapping exceptions (merge testing)
|
||||
############################################################
|
||||
puts "--- overlapping exceptions ---"
|
||||
set_false_path -from [get_ports in1] -to [get_ports out1]
|
||||
set_false_path -from [get_ports in1] -to [get_ports out2]
|
||||
set_false_path -from [get_ports in2] -to [get_ports out1]
|
||||
report_checks -path_delay max
|
||||
puts "PASS: overlapping exceptions"
|
||||
|
||||
puts "--- unset overlapping ---"
|
||||
unset_path_exceptions -from [get_ports in1] -to [get_ports out1]
|
||||
unset_path_exceptions -from [get_ports in1] -to [get_ports out2]
|
||||
unset_path_exceptions -from [get_ports in2] -to [get_ports out1]
|
||||
report_checks -path_delay max
|
||||
puts "PASS: unset overlapping"
|
||||
|
||||
############################################################
|
||||
# Test 7: Multicycle with -start/-end and rise/fall
|
||||
############################################################
|
||||
puts "--- mcp -start -rise_from ---"
|
||||
set_multicycle_path 2 -setup -start -rise_from [get_clocks clk1] -to [get_clocks clk2]
|
||||
report_checks -path_delay max
|
||||
puts "PASS: mcp start rise_from"
|
||||
|
||||
puts "--- mcp -end -fall_to ---"
|
||||
set_multicycle_path 3 -setup -end -from [get_clocks clk1] -fall_to [get_clocks clk2]
|
||||
report_checks -path_delay max
|
||||
puts "PASS: mcp end fall_to"
|
||||
|
||||
puts "--- unset mcp ---"
|
||||
unset_path_exceptions -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
puts "PASS: unset mcp"
|
||||
|
||||
############################################################
|
||||
# Test 8: Max/min delay with rise/fall from/to
|
||||
############################################################
|
||||
puts "--- max_delay -rise_from -to ---"
|
||||
set_max_delay 6.0 -rise_from [get_ports in1] -to [get_ports out1]
|
||||
report_checks -path_delay max
|
||||
puts "PASS: max_delay rise_from"
|
||||
|
||||
puts "--- min_delay -from -fall_to ---"
|
||||
set_min_delay 0.1 -from [get_ports in1] -fall_to [get_ports out1]
|
||||
report_checks -path_delay min
|
||||
puts "PASS: min_delay fall_to"
|
||||
|
||||
puts "--- unset max/min delays ---"
|
||||
unset_path_exceptions -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: unset max/min delays"
|
||||
|
||||
############################################################
|
||||
# Test 9: write_sdc with exception paths
|
||||
############################################################
|
||||
set_false_path -rise_from [get_ports in1] -to [get_ports out1]
|
||||
set_false_path -from [get_ports in2] -fall_to [get_ports out2]
|
||||
set_multicycle_path 2 -setup -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
set_max_delay 7.0 -from [get_ports in3] -rise_through [get_pins or1/ZN] -to [get_ports out2]
|
||||
|
||||
set sdc1 [make_result_file sdc_exc_override1.sdc]
|
||||
write_sdc -no_timestamp $sdc1
|
||||
puts "PASS: write_sdc exceptions"
|
||||
|
||||
set sdc2 [make_result_file sdc_exc_override2.sdc]
|
||||
write_sdc -no_timestamp -compatible $sdc2
|
||||
puts "PASS: write_sdc compatible"
|
||||
|
||||
############################################################
|
||||
# Test 10: Read back SDC
|
||||
############################################################
|
||||
read_sdc $sdc1
|
||||
puts "PASS: read_sdc exceptions"
|
||||
|
||||
set sdc3 [make_result_file sdc_exc_override3.sdc]
|
||||
write_sdc -no_timestamp $sdc3
|
||||
puts "PASS: write_sdc after read"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,109 @@
|
||||
PASS: basic setup
|
||||
PASS: set_false_path -from -to
|
||||
PASS: set_false_path -from -through -to
|
||||
PASS: set_false_path -rise_from -fall_to
|
||||
PASS: set_false_path -from clk -to clk
|
||||
No paths found.
|
||||
PASS: report_checks after false_path
|
||||
PASS: unset_path_exceptions specific
|
||||
PASS: unset_path_exceptions with -through
|
||||
PASS: unset_path_exceptions rise_from/fall_to
|
||||
PASS: unset_path_exceptions clock domain
|
||||
PASS: set_multicycle_path -setup 2
|
||||
PASS: set_multicycle_path -hold 1
|
||||
PASS: set_multicycle_path -setup 3 pin-to-pin
|
||||
No paths found.
|
||||
PASS: report_checks after multicycle
|
||||
PASS: unset multicycle setup
|
||||
PASS: unset multicycle hold
|
||||
PASS: unset multicycle pin-to-pin
|
||||
PASS: set_max_delay
|
||||
PASS: set_min_delay
|
||||
No paths found.
|
||||
PASS: report_checks after max/min delay
|
||||
PASS: unset max/min delay paths
|
||||
PASS: group_path -name -from
|
||||
PASS: group_path -name -from -to
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: group_clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks -path_group group_clk1
|
||||
No paths found.
|
||||
PASS: report_checks -path_group group_io
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: group_clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Endpoint: out2 (output port clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk2 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg3/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg3/Q (DFF_X1)
|
||||
0.00 0.08 ^ out2 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
-3.00 17.00 output external delay
|
||||
17.00 data required time
|
||||
---------------------------------------------------------
|
||||
17.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
16.92 slack (MET)
|
||||
|
||||
|
||||
PASS: final report_checks
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,124 @@
|
||||
# Test exception path SDC commands for code coverage
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
# Setup clocks
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
|
||||
# Setup basic delays
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in2]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in3]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 3.0 [get_ports out2]
|
||||
puts "PASS: basic setup"
|
||||
|
||||
############################################################
|
||||
# set_false_path
|
||||
############################################################
|
||||
|
||||
# False path from port to port
|
||||
set_false_path -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: set_false_path -from -to"
|
||||
|
||||
# False path with -through
|
||||
set_false_path -from [get_ports in2] -through [get_pins and1/ZN] -to [get_ports out1]
|
||||
puts "PASS: set_false_path -from -through -to"
|
||||
|
||||
# False path with rise_from/fall_to
|
||||
set_false_path -rise_from [get_ports in3] -fall_to [get_ports out2]
|
||||
puts "PASS: set_false_path -rise_from -fall_to"
|
||||
|
||||
# False path between clock domains
|
||||
set_false_path -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
puts "PASS: set_false_path -from clk -to clk"
|
||||
|
||||
# Report to verify false paths
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: report_checks after false_path"
|
||||
|
||||
############################################################
|
||||
# Reset all exceptions and re-add other types
|
||||
############################################################
|
||||
|
||||
unset_path_exceptions -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: unset_path_exceptions specific"
|
||||
|
||||
unset_path_exceptions -from [get_ports in2] -through [get_pins and1/ZN] -to [get_ports out1]
|
||||
puts "PASS: unset_path_exceptions with -through"
|
||||
|
||||
unset_path_exceptions -rise_from [get_ports in3] -fall_to [get_ports out2]
|
||||
puts "PASS: unset_path_exceptions rise_from/fall_to"
|
||||
|
||||
unset_path_exceptions -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
puts "PASS: unset_path_exceptions clock domain"
|
||||
|
||||
############################################################
|
||||
# set_multicycle_path
|
||||
############################################################
|
||||
|
||||
# Setup multicycle
|
||||
set_multicycle_path -setup 2 -from [get_clocks clk1] -to [get_clocks clk1]
|
||||
puts "PASS: set_multicycle_path -setup 2"
|
||||
|
||||
# Hold multicycle
|
||||
set_multicycle_path -hold 1 -from [get_clocks clk1] -to [get_clocks clk1]
|
||||
puts "PASS: set_multicycle_path -hold 1"
|
||||
|
||||
# Multicycle from specific pin
|
||||
set_multicycle_path -setup 3 -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: set_multicycle_path -setup 3 pin-to-pin"
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: report_checks after multicycle"
|
||||
|
||||
# Unset multicycle paths
|
||||
unset_path_exceptions -setup -from [get_clocks clk1] -to [get_clocks clk1]
|
||||
puts "PASS: unset multicycle setup"
|
||||
|
||||
unset_path_exceptions -hold -from [get_clocks clk1] -to [get_clocks clk1]
|
||||
puts "PASS: unset multicycle hold"
|
||||
|
||||
unset_path_exceptions -setup -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: unset multicycle pin-to-pin"
|
||||
|
||||
############################################################
|
||||
# set_max_delay / set_min_delay
|
||||
############################################################
|
||||
|
||||
set_max_delay -from [get_ports in1] -to [get_ports out1] 8.0
|
||||
puts "PASS: set_max_delay"
|
||||
|
||||
set_min_delay -from [get_ports in1] -to [get_ports out1] 1.0
|
||||
puts "PASS: set_min_delay"
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: report_checks after max/min delay"
|
||||
|
||||
# Unset the delay constraints
|
||||
unset_path_exceptions -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: unset max/min delay paths"
|
||||
|
||||
############################################################
|
||||
# group_path
|
||||
############################################################
|
||||
|
||||
group_path -name group_clk1 -from [get_clocks clk1]
|
||||
puts "PASS: group_path -name -from"
|
||||
|
||||
group_path -name group_io -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: group_path -name -from -to"
|
||||
|
||||
report_checks -path_group group_clk1
|
||||
puts "PASS: report_checks -path_group group_clk1"
|
||||
|
||||
report_checks -path_group group_io
|
||||
puts "PASS: report_checks -path_group group_io"
|
||||
|
||||
# Final report
|
||||
report_checks
|
||||
puts "PASS: final report_checks"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,58 @@
|
||||
PASS: setup
|
||||
all_inputs count = 5
|
||||
PASS: all_inputs
|
||||
all_inputs -no_clocks count = 3
|
||||
PASS: all_inputs -no_clocks
|
||||
all_outputs count = 2
|
||||
PASS: all_outputs
|
||||
find_clocks_matching clk* = 2
|
||||
PASS: find_clocks_matching glob
|
||||
find_clocks_matching regexp = 2
|
||||
PASS: find_clocks_matching regexp
|
||||
find_clocks_matching nocase = 0
|
||||
PASS: find_clocks_matching nocase
|
||||
clk1 is_clock_src = 1
|
||||
clk1 is_clock = 0
|
||||
clk1 is_ideal_clock = 0
|
||||
PASS: clock pin queries
|
||||
in1 is_clock_src = 0
|
||||
in1 is_clock = 0
|
||||
PASS: non-clock pin queries
|
||||
default_arrival_clock exists
|
||||
PASS: default_arrival_clock
|
||||
clk_thru_tristate_enabled = 0
|
||||
clk_thru_tristate_enabled after set = 1
|
||||
PASS: clk_thru_tristate
|
||||
pin clk1 constrained = 1
|
||||
pin in1 constrained = 1
|
||||
instance buf1 constrained = 0
|
||||
net n1 constrained = 0
|
||||
PASS: constrained queries
|
||||
in1 case_logic_value = 0
|
||||
in1 logic_value = X
|
||||
in3 logic_value = 0
|
||||
PASS: case/logic value queries
|
||||
group_path_names = grp_io grp_reg2reg
|
||||
PASS: group_path_names
|
||||
is_path_group_name grp_reg2reg = 1
|
||||
is_path_group_name nonexistent = 0
|
||||
PASS: is_path_group_name
|
||||
filter_ports direction == input: 5
|
||||
PASS: filter_ports
|
||||
filter_clocks period == 10: 0
|
||||
PASS: filter_clocks
|
||||
filter_lib_cells is_buffer: 9
|
||||
PASS: filter_lib_cells
|
||||
filter_insts ref_name =~ BUF*: 1
|
||||
PASS: filter_insts
|
||||
filter_pins direction == input: 1
|
||||
PASS: filter_pins
|
||||
filter_nets full_name =~ n*: 7
|
||||
PASS: filter_nets
|
||||
PASS: write_sdc
|
||||
PASS: unset case analysis
|
||||
PASS: remove_constraints
|
||||
No paths found.
|
||||
PASS: report after remove_constraints
|
||||
PASS: write_sdc after re-constrain
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,252 @@
|
||||
# Test filter commands, constrained queries, all_inputs/all_outputs,
|
||||
# and various query/utility commands for code coverage.
|
||||
# Targets:
|
||||
# Sdc.cc: allInputs, allOutputs, isConstrained (pin, instance, net),
|
||||
# findClocksMatching, sortedClocks, findClock,
|
||||
# isClockSrc, isClock, isIdealClock,
|
||||
# clkThruTristateEnabled, setClkThruTristateEnabled,
|
||||
# removeConstraints
|
||||
# Sdc.i: all_inputs_cmd, all_outputs_cmd, filter_ports, filter_insts,
|
||||
# filter_pins, filter_clocks, filter_lib_cells, filter_lib_pins,
|
||||
# filter_liberty_libraries, filter_nets, filter_timing_arcs,
|
||||
# group_path_names, pin_is_constrained, instance_is_constrained,
|
||||
# net_is_constrained, is_clock_src, is_clock, is_ideal_clock,
|
||||
# clk_thru_tristate_enabled, set_clk_thru_tristate_enabled,
|
||||
# find_clocks_matching, default_arrival_clock,
|
||||
# pin_case_logic_value, pin_logic_value, remove_constraints
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
create_clock -name vclk -period 5
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in2]
|
||||
set_input_delay -clock clk2 2.0 [get_ports in3]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 3.0 [get_ports out2]
|
||||
puts "PASS: setup"
|
||||
|
||||
############################################################
|
||||
# all_inputs / all_outputs
|
||||
############################################################
|
||||
set inputs [all_inputs]
|
||||
puts "all_inputs count = [llength $inputs]"
|
||||
puts "PASS: all_inputs"
|
||||
|
||||
set inputs_no_clk [all_inputs -no_clocks]
|
||||
puts "all_inputs -no_clocks count = [llength $inputs_no_clk]"
|
||||
puts "PASS: all_inputs -no_clocks"
|
||||
|
||||
set outputs [all_outputs]
|
||||
puts "all_outputs count = [llength $outputs]"
|
||||
puts "PASS: all_outputs"
|
||||
|
||||
############################################################
|
||||
# find_clocks_matching
|
||||
############################################################
|
||||
set clks [sta::find_clocks_matching "clk*" 0 0]
|
||||
puts "find_clocks_matching clk* = [llength $clks]"
|
||||
puts "PASS: find_clocks_matching glob"
|
||||
|
||||
set clks [sta::find_clocks_matching {^clk[0-9]+$} 1 0]
|
||||
puts "find_clocks_matching regexp = [llength $clks]"
|
||||
puts "PASS: find_clocks_matching regexp"
|
||||
|
||||
set clks [sta::find_clocks_matching "CLK*" 0 1]
|
||||
puts "find_clocks_matching nocase = [llength $clks]"
|
||||
puts "PASS: find_clocks_matching nocase"
|
||||
|
||||
############################################################
|
||||
# Clock source queries
|
||||
############################################################
|
||||
set clk1_pin [sta::find_pin clk1]
|
||||
puts "clk1 is_clock_src = [sta::is_clock_src $clk1_pin]"
|
||||
puts "clk1 is_clock = [sta::is_clock $clk1_pin]"
|
||||
puts "clk1 is_ideal_clock = [sta::is_ideal_clock $clk1_pin]"
|
||||
puts "PASS: clock pin queries"
|
||||
|
||||
set in1_pin [sta::find_pin in1]
|
||||
puts "in1 is_clock_src = [sta::is_clock_src $in1_pin]"
|
||||
puts "in1 is_clock = [sta::is_clock $in1_pin]"
|
||||
puts "PASS: non-clock pin queries"
|
||||
|
||||
############################################################
|
||||
# Default arrival clock
|
||||
############################################################
|
||||
catch {
|
||||
set def_clk [sta::default_arrival_clock]
|
||||
if {$def_clk ne ""} {
|
||||
puts "default_arrival_clock exists"
|
||||
} else {
|
||||
puts "default_arrival_clock is null"
|
||||
}
|
||||
}
|
||||
puts "PASS: default_arrival_clock"
|
||||
|
||||
############################################################
|
||||
# Clock thru tristate
|
||||
############################################################
|
||||
set val [sta::clk_thru_tristate_enabled]
|
||||
puts "clk_thru_tristate_enabled = $val"
|
||||
sta::set_clk_thru_tristate_enabled 1
|
||||
set val [sta::clk_thru_tristate_enabled]
|
||||
puts "clk_thru_tristate_enabled after set = $val"
|
||||
sta::set_clk_thru_tristate_enabled 0
|
||||
puts "PASS: clk_thru_tristate"
|
||||
|
||||
############################################################
|
||||
# Constrained queries
|
||||
############################################################
|
||||
set clk1_pin [sta::find_pin clk1]
|
||||
puts "pin clk1 constrained = [sta::pin_is_constrained $clk1_pin]"
|
||||
|
||||
set in1_pin [sta::find_pin in1]
|
||||
puts "pin in1 constrained = [sta::pin_is_constrained $in1_pin]"
|
||||
|
||||
catch {
|
||||
set inst [lindex [get_cells buf1] 0]
|
||||
puts "instance buf1 constrained = [sta::instance_is_constrained $inst]"
|
||||
}
|
||||
|
||||
catch {
|
||||
set net [lindex [get_nets n1] 0]
|
||||
puts "net n1 constrained = [sta::net_is_constrained $net]"
|
||||
}
|
||||
puts "PASS: constrained queries"
|
||||
|
||||
############################################################
|
||||
# Case analysis and logic value queries
|
||||
############################################################
|
||||
set_case_analysis 0 [get_ports in1]
|
||||
set_case_analysis 1 [get_ports in2]
|
||||
|
||||
set pin_in1 [lindex [get_pins buf1/A] 0]
|
||||
catch {
|
||||
set val [sta::pin_case_logic_value $in1_pin]
|
||||
puts "in1 case_logic_value = $val"
|
||||
}
|
||||
|
||||
catch {
|
||||
set val [sta::pin_logic_value $in1_pin]
|
||||
puts "in1 logic_value = $val"
|
||||
}
|
||||
|
||||
# Set logic values
|
||||
set_logic_zero [get_ports in3]
|
||||
|
||||
catch {
|
||||
set in3_pin [sta::find_pin in3]
|
||||
set val [sta::pin_logic_value $in3_pin]
|
||||
puts "in3 logic_value = $val"
|
||||
}
|
||||
puts "PASS: case/logic value queries"
|
||||
|
||||
############################################################
|
||||
# Group paths and group_path_names
|
||||
############################################################
|
||||
group_path -name grp_reg2reg -from [get_clocks clk1] -to [get_clocks clk1]
|
||||
group_path -name grp_io -from [get_ports {in1 in2}] -to [get_ports out1]
|
||||
|
||||
set gp_names [sta::group_path_names]
|
||||
puts "group_path_names = $gp_names"
|
||||
puts "PASS: group_path_names"
|
||||
|
||||
set is_gp [sta::is_path_group_name "grp_reg2reg"]
|
||||
puts "is_path_group_name grp_reg2reg = $is_gp"
|
||||
|
||||
set is_gp [sta::is_path_group_name "nonexistent"]
|
||||
puts "is_path_group_name nonexistent = $is_gp"
|
||||
puts "PASS: is_path_group_name"
|
||||
|
||||
############################################################
|
||||
# Filter commands
|
||||
############################################################
|
||||
|
||||
# filter_ports
|
||||
set all_ports [get_ports *]
|
||||
catch {
|
||||
set filtered [sta::filter_ports direction == input $all_ports]
|
||||
puts "filter_ports direction == input: [llength $filtered]"
|
||||
}
|
||||
puts "PASS: filter_ports"
|
||||
|
||||
# filter_clocks
|
||||
set all_clks [get_clocks *]
|
||||
catch {
|
||||
set filtered [sta::filter_clocks period == 10.000 $all_clks]
|
||||
puts "filter_clocks period == 10: [llength $filtered]"
|
||||
}
|
||||
puts "PASS: filter_clocks"
|
||||
|
||||
# filter_lib_cells
|
||||
set all_cells [get_lib_cells NangateOpenCellLibrary/*]
|
||||
catch {
|
||||
set filtered [sta::filter_lib_cells is_buffer == 1 $all_cells]
|
||||
puts "filter_lib_cells is_buffer: [llength $filtered]"
|
||||
}
|
||||
puts "PASS: filter_lib_cells"
|
||||
|
||||
# filter_insts
|
||||
set all_insts [get_cells *]
|
||||
catch {
|
||||
set filtered [sta::filter_insts ref_name =~ "BUF*" $all_insts]
|
||||
puts "filter_insts ref_name =~ BUF*: [llength $filtered]"
|
||||
}
|
||||
puts "PASS: filter_insts"
|
||||
|
||||
# filter_pins
|
||||
set all_pins [get_pins buf1/*]
|
||||
catch {
|
||||
set filtered [sta::filter_pins direction == input $all_pins]
|
||||
puts "filter_pins direction == input: [llength $filtered]"
|
||||
}
|
||||
puts "PASS: filter_pins"
|
||||
|
||||
# filter_nets
|
||||
set all_nets [get_nets *]
|
||||
catch {
|
||||
set filtered [sta::filter_nets full_name =~ n* $all_nets]
|
||||
puts "filter_nets full_name =~ n*: [llength $filtered]"
|
||||
}
|
||||
puts "PASS: filter_nets"
|
||||
|
||||
############################################################
|
||||
# Write SDC with all constraints
|
||||
############################################################
|
||||
set sdc1 [make_result_file sdc_filter_query1.sdc]
|
||||
write_sdc -no_timestamp $sdc1
|
||||
puts "PASS: write_sdc"
|
||||
|
||||
############################################################
|
||||
# Unset case analysis
|
||||
############################################################
|
||||
unset_case_analysis [get_ports in1]
|
||||
unset_case_analysis [get_ports in2]
|
||||
puts "PASS: unset case analysis"
|
||||
|
||||
############################################################
|
||||
# remove_constraints
|
||||
############################################################
|
||||
sta::remove_constraints
|
||||
puts "PASS: remove_constraints"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report after remove_constraints"
|
||||
|
||||
############################################################
|
||||
# Re-apply constraints for final write
|
||||
############################################################
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
|
||||
set sdc2 [make_result_file sdc_filter_query2.sdc]
|
||||
write_sdc -no_timestamp $sdc2
|
||||
puts "PASS: write_sdc after re-constrain"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,61 @@
|
||||
PASS: base clocks
|
||||
PASS: virtual clock
|
||||
PASS: clock -add on same port
|
||||
PASS: asymmetric waveform clock
|
||||
Clock Period Waveform
|
||||
----------------------------------------------------
|
||||
clk1 10.00 0.00 5.00
|
||||
clk2 20.00 0.00 10.00
|
||||
vclk 8.00 0.00 4.00
|
||||
clk1_2x 5.00 0.00 2.50
|
||||
clk_asym 12.00 0.00 3.00
|
||||
PASS: report_clock_properties initial
|
||||
PASS: generated clock -divide_by 2
|
||||
PASS: generated clock -divide_by 3
|
||||
PASS: generated clock -multiply_by 2
|
||||
Warning: generated clock gclk_div2 pin clk1 is in the fanout of multiple clocks.
|
||||
Warning: generated clock gclk_div3 pin clk2 is in the fanout of multiple clocks.
|
||||
Warning: generated clock gclk_mul2 pin clk1 is in the fanout of multiple clocks.
|
||||
Clock Period Waveform
|
||||
----------------------------------------------------
|
||||
clk1 10.00 0.00 5.00
|
||||
clk2 20.00 0.00 10.00
|
||||
vclk 8.00 0.00 4.00
|
||||
clk1_2x 5.00 0.00 2.50
|
||||
clk_asym 12.00 0.00 3.00
|
||||
gclk_div2 10.00 0.00 5.00 (generated)
|
||||
gclk_div3 36.00 0.00 9.00 (generated)
|
||||
gclk_mul2 2.50 0.00 1.25 (generated)
|
||||
PASS: report_clock_properties with generated
|
||||
PASS: source latency on generated clock
|
||||
PASS: network latency on generated clock
|
||||
PASS: uncertainty on generated clock
|
||||
PASS: inter-clock uncertainty with generated
|
||||
PASS: transition on generated clock
|
||||
PASS: propagated on generated clock
|
||||
PASS: input delay with generated clock
|
||||
PASS: output delay with generated clock
|
||||
PASS: clock groups with generated clocks
|
||||
PASS: false path between generated clocks
|
||||
PASS: multicycle to generated clock
|
||||
PASS: write_sdc with generated clocks
|
||||
PASS: write_sdc -compatible with generated clocks
|
||||
PASS: write_sdc -digits 6 with generated clocks
|
||||
No paths found.
|
||||
PASS: report_checks with generated clocks
|
||||
No paths found.
|
||||
PASS: report_checks path 2
|
||||
PASS: unset clock groups
|
||||
PASS: delete gclk_mul2
|
||||
PASS: unset latencies on gclk_div2
|
||||
PASS: delete gclk_div2
|
||||
PASS: delete gclk_div3
|
||||
PASS: delete virtual clock
|
||||
Clock Period Waveform
|
||||
----------------------------------------------------
|
||||
clk1 10.00 0.00 5.00
|
||||
clk2 20.00 0.00 10.00
|
||||
clk1_2x 5.00 0.00 2.50
|
||||
clk_asym 12.00 0.00 3.00
|
||||
PASS: report_clock_properties after deletions
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,199 @@
|
||||
# Test advanced generated clock options and clock model queries for code coverage
|
||||
# Targets: Clock.cc (generated clock model, edge-based, master clock),
|
||||
# WriteSdc.cc (writeGeneratedClock, writeClockPins),
|
||||
# Sdc.cc (clock creation and deletion paths)
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
############################################################
|
||||
# Multiple clocks on same port and various generated clocks
|
||||
############################################################
|
||||
|
||||
# Base clocks
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 -waveform {0 10} [get_ports clk2]
|
||||
puts "PASS: base clocks"
|
||||
|
||||
# Virtual clock (no pin)
|
||||
create_clock -name vclk -period 8
|
||||
puts "PASS: virtual clock"
|
||||
|
||||
# Multiple clocks on same port (-add)
|
||||
create_clock -name clk1_2x -period 5 -add [get_ports clk1]
|
||||
puts "PASS: clock -add on same port"
|
||||
|
||||
# Asymmetric waveform clock
|
||||
create_clock -name clk_asym -period 12 -waveform {0 3} -add [get_ports clk2]
|
||||
puts "PASS: asymmetric waveform clock"
|
||||
|
||||
# Report clock properties
|
||||
report_clock_properties
|
||||
puts "PASS: report_clock_properties initial"
|
||||
|
||||
############################################################
|
||||
# Generated clocks - divide_by
|
||||
############################################################
|
||||
|
||||
create_generated_clock -name gclk_div2 -source [get_ports clk1] -divide_by 2 [get_pins reg1/Q]
|
||||
puts "PASS: generated clock -divide_by 2"
|
||||
|
||||
create_generated_clock -name gclk_div3 -source [get_ports clk2] -divide_by 3 [get_pins reg3/Q]
|
||||
puts "PASS: generated clock -divide_by 3"
|
||||
|
||||
############################################################
|
||||
# Generated clocks - multiply_by
|
||||
############################################################
|
||||
|
||||
create_generated_clock -name gclk_mul2 -source [get_ports clk1] -multiply_by 2 [get_pins reg2/Q]
|
||||
puts "PASS: generated clock -multiply_by 2"
|
||||
|
||||
############################################################
|
||||
# Generated clocks - edges
|
||||
############################################################
|
||||
|
||||
# Edge-based generated clock
|
||||
catch {
|
||||
create_generated_clock -name gclk_edge -source [get_ports clk1] -edges {1 3 5} [get_pins reg1/Q] -add
|
||||
puts "PASS: generated clock -edges"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Generated clock - edge shift
|
||||
############################################################
|
||||
|
||||
catch {
|
||||
create_generated_clock -name gclk_shift -source [get_ports clk2] -edges {1 3 5} -edge_shift {0.0 0.5 1.0} [get_pins reg3/Q] -add
|
||||
puts "PASS: generated clock -edge_shift"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Report clock properties after generated clocks
|
||||
############################################################
|
||||
|
||||
report_clock_properties
|
||||
puts "PASS: report_clock_properties with generated"
|
||||
|
||||
############################################################
|
||||
# Clock constraints on generated clocks
|
||||
############################################################
|
||||
|
||||
# Source latency on generated clock
|
||||
set_clock_latency -source 0.3 [get_clocks gclk_div2]
|
||||
set_clock_latency -source -rise -max 0.4 [get_clocks gclk_div2]
|
||||
set_clock_latency -source -fall -min 0.1 [get_clocks gclk_div2]
|
||||
puts "PASS: source latency on generated clock"
|
||||
|
||||
# Network latency on generated clock
|
||||
set_clock_latency 0.15 [get_clocks gclk_div3]
|
||||
puts "PASS: network latency on generated clock"
|
||||
|
||||
# Clock uncertainty on generated clocks
|
||||
set_clock_uncertainty -setup 0.15 [get_clocks gclk_div2]
|
||||
set_clock_uncertainty -hold 0.08 [get_clocks gclk_div2]
|
||||
puts "PASS: uncertainty on generated clock"
|
||||
|
||||
# Inter-clock uncertainty between generated and base
|
||||
set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks gclk_div2] -setup 0.2
|
||||
set_clock_uncertainty -from [get_clocks gclk_div2] -to [get_clocks clk2] -hold 0.1
|
||||
puts "PASS: inter-clock uncertainty with generated"
|
||||
|
||||
# Clock transition on generated clock
|
||||
set_clock_transition 0.12 [get_clocks gclk_div2]
|
||||
set_clock_transition -rise -max 0.15 [get_clocks gclk_mul2]
|
||||
puts "PASS: transition on generated clock"
|
||||
|
||||
# Propagated clock on generated
|
||||
set_propagated_clock [get_clocks gclk_div2]
|
||||
puts "PASS: propagated on generated clock"
|
||||
|
||||
############################################################
|
||||
# IO delays referencing generated clocks
|
||||
############################################################
|
||||
|
||||
set_input_delay -clock gclk_div2 3.0 [get_ports in1]
|
||||
set_input_delay -clock gclk_div2 -rise -max 3.5 [get_ports in2]
|
||||
set_input_delay -clock gclk_div2 -fall -min 1.5 [get_ports in2]
|
||||
puts "PASS: input delay with generated clock"
|
||||
|
||||
set_output_delay -clock gclk_mul2 2.0 [get_ports out1]
|
||||
set_output_delay -clock gclk_div3 2.5 [get_ports out2]
|
||||
puts "PASS: output delay with generated clock"
|
||||
|
||||
############################################################
|
||||
# Clock groups involving generated clocks
|
||||
############################################################
|
||||
|
||||
set_clock_groups -asynchronous -group {clk1 clk1_2x gclk_div2 gclk_mul2} -group {clk2 gclk_div3}
|
||||
puts "PASS: clock groups with generated clocks"
|
||||
|
||||
############################################################
|
||||
# Exception paths referencing generated clocks
|
||||
############################################################
|
||||
|
||||
set_false_path -from [get_clocks gclk_div2] -to [get_clocks gclk_div3]
|
||||
puts "PASS: false path between generated clocks"
|
||||
|
||||
set_multicycle_path -setup 3 -from [get_clocks clk1] -to [get_clocks gclk_div2]
|
||||
puts "PASS: multicycle to generated clock"
|
||||
|
||||
############################################################
|
||||
# Write SDC (exercises generated clock writing)
|
||||
############################################################
|
||||
|
||||
set sdc_file1 [make_result_file sdc_genclk_native.sdc]
|
||||
write_sdc -no_timestamp $sdc_file1
|
||||
puts "PASS: write_sdc with generated clocks"
|
||||
|
||||
set sdc_file2 [make_result_file sdc_genclk_compat.sdc]
|
||||
write_sdc -no_timestamp -compatible $sdc_file2
|
||||
puts "PASS: write_sdc -compatible with generated clocks"
|
||||
|
||||
set sdc_file3 [make_result_file sdc_genclk_d6.sdc]
|
||||
write_sdc -no_timestamp -digits 6 $sdc_file3
|
||||
puts "PASS: write_sdc -digits 6 with generated clocks"
|
||||
|
||||
############################################################
|
||||
# Report checks
|
||||
############################################################
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: report_checks with generated clocks"
|
||||
|
||||
report_checks -from [get_ports in2] -to [get_ports out2]
|
||||
puts "PASS: report_checks path 2"
|
||||
|
||||
############################################################
|
||||
# Delete and re-create clocks (exercises Clock.cc deletion)
|
||||
############################################################
|
||||
|
||||
# Remove clock groups first
|
||||
unset_clock_groups -asynchronous -all
|
||||
puts "PASS: unset clock groups"
|
||||
|
||||
# Delete generated clocks
|
||||
delete_generated_clock [get_clocks gclk_mul2]
|
||||
puts "PASS: delete gclk_mul2"
|
||||
|
||||
# Unset latencies on gclk_div2 before delete
|
||||
unset_clock_latency [get_clocks gclk_div2]
|
||||
unset_clock_latency -source [get_clocks gclk_div2]
|
||||
unset_propagated_clock [get_clocks gclk_div2]
|
||||
puts "PASS: unset latencies on gclk_div2"
|
||||
|
||||
delete_generated_clock [get_clocks gclk_div2]
|
||||
puts "PASS: delete gclk_div2"
|
||||
|
||||
delete_generated_clock [get_clocks gclk_div3]
|
||||
puts "PASS: delete gclk_div3"
|
||||
|
||||
# Delete virtual clock
|
||||
delete_clock [get_clocks vclk]
|
||||
puts "PASS: delete virtual clock"
|
||||
|
||||
report_clock_properties
|
||||
puts "PASS: report_clock_properties after deletions"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,332 @@
|
||||
--- net properties ---
|
||||
PASS: net properties
|
||||
--- port properties ---
|
||||
PASS: port properties
|
||||
--- instance properties ---
|
||||
PASS: instance properties
|
||||
--- pin properties ---
|
||||
pin buf1/A: direction=input is_clock=0
|
||||
pin buf1/Z: direction=output is_clock=0
|
||||
PASS: pin properties
|
||||
--- disable timing arc ---
|
||||
Startpoint: in2 (input port clocked by clk1)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
2.00 2.00 v input external delay
|
||||
0.00 2.00 v in2 (in)
|
||||
0.01 2.01 ^ inv1/ZN (INV_X1)
|
||||
0.03 2.04 ^ and1/ZN (AND2_X1)
|
||||
0.01 2.05 v nand1/ZN (NAND2_X1)
|
||||
0.00 2.05 v reg1/D (DFF_X1)
|
||||
2.05 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg1/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-2.05 data arrival time
|
||||
---------------------------------------------------------
|
||||
7.91 slack (MET)
|
||||
|
||||
|
||||
PASS: disable arc
|
||||
--- re-enable timing arc ---
|
||||
Startpoint: in1 (input port clocked by clk1)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
2.00 2.00 v input external delay
|
||||
0.00 2.00 v in1 (in)
|
||||
0.02 2.02 v buf1/Z (BUF_X1)
|
||||
0.03 2.05 v and1/ZN (AND2_X1)
|
||||
0.02 2.07 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 2.07 ^ reg2/D (DFF_X1)
|
||||
2.07 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-2.07 data arrival time
|
||||
---------------------------------------------------------
|
||||
7.90 slack (MET)
|
||||
|
||||
|
||||
PASS: re-enable arc
|
||||
--- constraint setup ---
|
||||
PASS: constraint setup
|
||||
--- write_sdc before removal ---
|
||||
PASS: write before removal
|
||||
--- remove false_path ---
|
||||
PASS: remove false path
|
||||
--- remove multicycle ---
|
||||
PASS: remove multicycle
|
||||
--- remove max/min delay ---
|
||||
PASS: remove max/min delay
|
||||
--- remove clock_groups ---
|
||||
PASS: remove clock_groups
|
||||
--- remove clock_uncertainty ---
|
||||
PASS: remove clock_uncertainty
|
||||
--- write_sdc after removal ---
|
||||
PASS: write after removal
|
||||
--- filter queries ---
|
||||
BUF_X1 cells: 1
|
||||
PASS: filter ref_name
|
||||
DFF_X1 cells: 3
|
||||
PASS: filter DFF
|
||||
input ports: 5
|
||||
PASS: filter input ports
|
||||
output ports: 2
|
||||
PASS: filter output ports
|
||||
--- report_net_load ---
|
||||
Net clk1
|
||||
Pin capacitance: 1.71-1.90
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 1.71-1.90
|
||||
Number of drivers: 1
|
||||
Number of loads: 2
|
||||
Number of pins: 3
|
||||
|
||||
Driver pins
|
||||
clk1 input port
|
||||
|
||||
Load pins
|
||||
reg1/CK input (DFF_X1) 0.86-0.95
|
||||
reg2/CK input (DFF_X1) 0.86-0.95
|
||||
|
||||
Net clk2
|
||||
Pin capacitance: 0.86-0.95
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 0.86-0.95
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
clk2 input port
|
||||
|
||||
Load pins
|
||||
reg3/CK input (DFF_X1) 0.86-0.95
|
||||
|
||||
Net in1
|
||||
Pin capacitance: 0.88-0.97
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 0.88-0.97
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
in1 input port
|
||||
|
||||
Load pins
|
||||
buf1/A input (BUF_X1) 0.88-0.97
|
||||
|
||||
Net in2
|
||||
Pin capacitance: 1.55-1.70
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 1.55-1.70
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
in2 input port
|
||||
|
||||
Load pins
|
||||
inv1/A input (INV_X1) 1.55-1.70
|
||||
|
||||
Net in3
|
||||
Pin capacitance: 0.90-0.94
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 0.90-0.94
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
in3 input port
|
||||
|
||||
Load pins
|
||||
or1/A2 input (OR2_X1) 0.90-0.94
|
||||
|
||||
Net n1
|
||||
Pin capacitance: 1.67-1.86
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 1.67-1.86
|
||||
Number of drivers: 1
|
||||
Number of loads: 2
|
||||
Number of pins: 3
|
||||
|
||||
Driver pins
|
||||
buf1/Z output (BUF_X1)
|
||||
|
||||
Load pins
|
||||
and1/A1 input (AND2_X1) 0.87-0.92
|
||||
or1/A1 input (OR2_X1) 0.79-0.95
|
||||
|
||||
Net n2
|
||||
Pin capacitance: 0.89-0.97
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 0.89-0.97
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
inv1/ZN output (INV_X1)
|
||||
|
||||
Load pins
|
||||
and1/A2 input (AND2_X1) 0.89-0.97
|
||||
|
||||
Net n3
|
||||
Pin capacitance: 2.94-3.31
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 2.94-3.31
|
||||
Number of drivers: 1
|
||||
Number of loads: 2
|
||||
Number of pins: 3
|
||||
|
||||
Driver pins
|
||||
and1/ZN output (AND2_X1)
|
||||
|
||||
Load pins
|
||||
nand1/A1 input (NAND2_X1) 1.53-1.60
|
||||
nor1/A1 input (NOR2_X1) 1.41-1.71
|
||||
|
||||
Net n4
|
||||
Pin capacitance: 3.07-3.32
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 3.07-3.32
|
||||
Number of drivers: 1
|
||||
Number of loads: 2
|
||||
Number of pins: 3
|
||||
|
||||
Driver pins
|
||||
or1/ZN output (OR2_X1)
|
||||
|
||||
Load pins
|
||||
nand1/A2 input (NAND2_X1) 1.50-1.66
|
||||
nor1/A2 input (NOR2_X1) 1.56-1.65
|
||||
|
||||
Net n5
|
||||
Pin capacitance: 1.06-1.14
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 1.06-1.14
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
nand1/ZN output (NAND2_X1)
|
||||
|
||||
Load pins
|
||||
reg1/D input (DFF_X1) 1.06-1.14
|
||||
|
||||
Net n6
|
||||
Pin capacitance: 1.06-1.14
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 1.06-1.14
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
nor1/ZN output (NOR2_X1)
|
||||
|
||||
Load pins
|
||||
reg2/D input (DFF_X1) 1.06-1.14
|
||||
|
||||
Net n7
|
||||
Pin capacitance: 1.06-1.14
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 1.06-1.14
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
reg1/Q output (DFF_X1)
|
||||
|
||||
Load pins
|
||||
reg3/D input (DFF_X1) 1.06-1.14
|
||||
|
||||
Net out1
|
||||
Pin capacitance: 0.00
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 0.00
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
reg2/Q output (DFF_X1)
|
||||
|
||||
Load pins
|
||||
out1 output port
|
||||
|
||||
Net out2
|
||||
Pin capacitance: 0.00
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 0.00
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
reg3/Q output (DFF_X1)
|
||||
|
||||
Load pins
|
||||
out2 output port
|
||||
|
||||
PASS: report_net
|
||||
--- delete clocks and rebuild ---
|
||||
PASS: delete clocks
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk_new)
|
||||
Endpoint: out1 (output port clocked by clk_new)
|
||||
Path Group: clk_new
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk_new (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
8.00 8.00 clock clk_new (rise edge)
|
||||
0.00 8.00 clock network delay (ideal)
|
||||
0.00 8.00 clock reconvergence pessimism
|
||||
-2.00 6.00 output external delay
|
||||
6.00 data required time
|
||||
---------------------------------------------------------
|
||||
6.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
5.92 slack (MET)
|
||||
|
||||
|
||||
PASS: rebuilt constraints
|
||||
PASS: write after rebuild
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,191 @@
|
||||
# Test Sdc.cc leaf pin queries, filter matching, constraint removal cascades,
|
||||
# findLeafLoadPins/findLeafDriverPins, net properties.
|
||||
# Also exercises Property.cc Net properties (is_power, is_ground, connected_count),
|
||||
# TimingArcSet properties (is_disabled_cond), and Sdc.cc filter matching.
|
||||
# Targets: Sdc.cc findLeafLoadPins, findLeafDriverPins, isLeafPinClock,
|
||||
# isLeafPinNonGeneratedClock, deleteConstraints, clkStopPropagation,
|
||||
# matchFilter, makeExceptionFrom/To/Thru with instances/nets/pins,
|
||||
# Property.cc net_is_power, net_is_ground, net_connected_count,
|
||||
# timing_arc_set_is_disabled_cond
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in2]
|
||||
set_input_delay -clock clk2 2.0 [get_ports in3]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 3.0 [get_ports out2]
|
||||
|
||||
report_checks > /dev/null
|
||||
|
||||
############################################################
|
||||
# Net properties
|
||||
############################################################
|
||||
puts "--- net properties ---"
|
||||
set nets [get_nets *]
|
||||
foreach n $nets {
|
||||
set name [get_full_name $n]
|
||||
catch {
|
||||
set is_pwr [get_property $n is_power]
|
||||
set is_gnd [get_property $n is_ground]
|
||||
puts " net $name: is_power=$is_pwr is_ground=$is_gnd"
|
||||
}
|
||||
}
|
||||
puts "PASS: net properties"
|
||||
|
||||
############################################################
|
||||
# Pin/port properties
|
||||
############################################################
|
||||
puts "--- port properties ---"
|
||||
set ports [get_ports *]
|
||||
foreach p $ports {
|
||||
set name [get_full_name $p]
|
||||
catch {
|
||||
set dir [get_property $p direction]
|
||||
set is_clk [get_property $p is_clock]
|
||||
puts " port $name: direction=$dir is_clock=$is_clk"
|
||||
}
|
||||
}
|
||||
puts "PASS: port properties"
|
||||
|
||||
############################################################
|
||||
# Instance properties
|
||||
############################################################
|
||||
puts "--- instance properties ---"
|
||||
set insts [get_cells *]
|
||||
foreach i $insts {
|
||||
set name [get_full_name $i]
|
||||
catch {
|
||||
set ref [get_property $i ref_name]
|
||||
set lib_name [get_property $i liberty_cell_name]
|
||||
puts " inst $name: ref=$ref lib=$lib_name"
|
||||
}
|
||||
}
|
||||
puts "PASS: instance properties"
|
||||
|
||||
############################################################
|
||||
# Pin properties (timing arc set disabled)
|
||||
############################################################
|
||||
puts "--- pin properties ---"
|
||||
foreach p [get_pins buf1/*] {
|
||||
set name [get_full_name $p]
|
||||
catch {
|
||||
set dir [get_property $p direction]
|
||||
set is_clk [get_property $p is_clock]
|
||||
puts " pin $name: direction=$dir is_clock=$is_clk"
|
||||
}
|
||||
}
|
||||
puts "PASS: pin properties"
|
||||
|
||||
############################################################
|
||||
# Disable timing on arc and check property
|
||||
############################################################
|
||||
puts "--- disable timing arc ---"
|
||||
set_disable_timing -from A1 -to ZN [get_cells and1]
|
||||
report_checks -through [get_pins and1/ZN]
|
||||
puts "PASS: disable arc"
|
||||
|
||||
puts "--- re-enable timing arc ---"
|
||||
unset_disable_timing -from A1 -to ZN [get_cells and1]
|
||||
report_checks -through [get_pins and1/ZN]
|
||||
puts "PASS: re-enable arc"
|
||||
|
||||
############################################################
|
||||
# Constraint removal cascades: add many constraints then remove
|
||||
############################################################
|
||||
puts "--- constraint setup ---"
|
||||
set_false_path -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
set_multicycle_path -setup 2 -from [get_ports in1] -to [get_ports out1]
|
||||
set_max_delay -from [get_ports in2] -to [get_ports out1] 8.0
|
||||
set_min_delay -from [get_ports in2] -to [get_ports out1] 0.5
|
||||
set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -setup 0.3
|
||||
set_clock_groups -asynchronous -name grp1 \
|
||||
-group {clk1} -group {clk2}
|
||||
puts "PASS: constraint setup"
|
||||
|
||||
puts "--- write_sdc before removal ---"
|
||||
set sdc1 [make_result_file sdc_leaf_pin1.sdc]
|
||||
write_sdc -no_timestamp $sdc1
|
||||
puts "PASS: write before removal"
|
||||
|
||||
puts "--- remove false_path ---"
|
||||
unset_path_exceptions -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
puts "PASS: remove false path"
|
||||
|
||||
puts "--- remove multicycle ---"
|
||||
unset_path_exceptions -setup -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: remove multicycle"
|
||||
|
||||
puts "--- remove max/min delay ---"
|
||||
unset_path_exceptions -from [get_ports in2] -to [get_ports out1]
|
||||
puts "PASS: remove max/min delay"
|
||||
|
||||
puts "--- remove clock_groups ---"
|
||||
unset_clock_groups -asynchronous -name grp1
|
||||
puts "PASS: remove clock_groups"
|
||||
|
||||
puts "--- remove clock_uncertainty ---"
|
||||
unset_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -setup
|
||||
puts "PASS: remove clock_uncertainty"
|
||||
|
||||
puts "--- write_sdc after removal ---"
|
||||
set sdc2 [make_result_file sdc_leaf_pin2.sdc]
|
||||
write_sdc -no_timestamp $sdc2
|
||||
puts "PASS: write after removal"
|
||||
|
||||
############################################################
|
||||
# Filter queries: get_* with -filter
|
||||
############################################################
|
||||
puts "--- filter queries ---"
|
||||
|
||||
set bufs [get_cells -filter "ref_name == BUF_X1"]
|
||||
puts "BUF_X1 cells: [llength $bufs]"
|
||||
puts "PASS: filter ref_name"
|
||||
|
||||
set dffs [get_cells -filter "ref_name == DFF_X1"]
|
||||
puts "DFF_X1 cells: [llength $dffs]"
|
||||
puts "PASS: filter DFF"
|
||||
|
||||
set in_ports [get_ports -filter "direction == input"]
|
||||
puts "input ports: [llength $in_ports]"
|
||||
puts "PASS: filter input ports"
|
||||
|
||||
set out_ports [get_ports -filter "direction == output"]
|
||||
puts "output ports: [llength $out_ports]"
|
||||
puts "PASS: filter output ports"
|
||||
|
||||
############################################################
|
||||
# findLeafLoadPins / findLeafDriverPins via reporting
|
||||
############################################################
|
||||
puts "--- report_net_load ---"
|
||||
catch {
|
||||
foreach n [get_nets *] {
|
||||
report_net [get_full_name $n]
|
||||
}
|
||||
}
|
||||
puts "PASS: report_net"
|
||||
|
||||
############################################################
|
||||
# Delete clocks and re-create constraints
|
||||
############################################################
|
||||
puts "--- delete clocks and rebuild ---"
|
||||
delete_clock [get_clocks clk2]
|
||||
delete_clock [get_clocks clk1]
|
||||
puts "PASS: delete clocks"
|
||||
|
||||
create_clock -name clk_new -period 8 [get_ports clk1]
|
||||
set_input_delay -clock clk_new 1.0 [get_ports in1]
|
||||
set_output_delay -clock clk_new 2.0 [get_ports out1]
|
||||
report_checks
|
||||
puts "PASS: rebuilt constraints"
|
||||
|
||||
set sdc3 [make_result_file sdc_leaf_pin3.sdc]
|
||||
write_sdc -no_timestamp $sdc3
|
||||
puts "PASS: write after rebuild"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,669 @@
|
||||
PASS: basic setup
|
||||
--- set net wire cap ---
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: net wire cap
|
||||
--- port loads ---
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: port loads
|
||||
--- port fanout ---
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: port fanout
|
||||
--- net resistance ---
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: net resistance
|
||||
--- voltage ---
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: voltage global
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: voltage on net
|
||||
--- timing derate global ---
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.09 0.09 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.09 ^ out1 (out)
|
||||
0.09 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.09 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.91 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: global derating
|
||||
--- timing derate lib cell ---
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.09 0.09 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.09 ^ out1 (out)
|
||||
0.09 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.09 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.91 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: lib cell derating
|
||||
--- timing derate instance ---
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.09 0.09 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.09 ^ out1 (out)
|
||||
0.09 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.09 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.91 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: instance derating
|
||||
--- timing derate net ---
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.09 0.09 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.09 ^ out1 (out)
|
||||
0.09 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.09 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.91 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: net derating
|
||||
--- write_sdc native ---
|
||||
PASS: write_sdc native
|
||||
--- write_sdc compatible ---
|
||||
PASS: write_sdc compatible
|
||||
--- write_sdc digits 8 ---
|
||||
PASS: write_sdc digits 8
|
||||
--- read_sdc back ---
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.09 0.09 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.09 ^ out1 (out)
|
||||
0.09 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.09 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.91 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: read_sdc roundtrip
|
||||
PASS: write_sdc after re-read
|
||||
--- reset deratings ---
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: reset deratings
|
||||
PASS: write after clear deratings
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,178 @@
|
||||
# Test SDC net wire caps, voltage, net deratings, port loads/fanout,
|
||||
# net resistance writing, timing deratings on instances/lib_cells/nets.
|
||||
# Targets: Sdc.cc setNetWireCap, setVoltage, removeNetLoadCaps,
|
||||
# derating factors on nets/instances/cells,
|
||||
# WriteSdc.cc writeNetLoads, writeNetLoad, writePortLoads,
|
||||
# writeNetResistances, writeNetResistance, writeVoltages,
|
||||
# writeDeratings (global, net, instance, cell variants),
|
||||
# writeConstants, writeCaseAnalysis
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in2]
|
||||
set_input_delay -clock clk2 2.0 [get_ports in3]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 3.0 [get_ports out2]
|
||||
puts "PASS: basic setup"
|
||||
|
||||
############################################################
|
||||
# Net wire capacitance
|
||||
############################################################
|
||||
puts "--- set net wire cap ---"
|
||||
catch {
|
||||
set_load 0.01 [get_nets n1]
|
||||
set_load 0.02 [get_nets n2]
|
||||
set_load 0.005 [get_nets n3]
|
||||
set_load 0.015 [get_nets n4]
|
||||
set_load 0.03 [get_nets n5]
|
||||
}
|
||||
report_checks
|
||||
puts "PASS: net wire cap"
|
||||
|
||||
############################################################
|
||||
# Port loads (pin_load and wire_load)
|
||||
############################################################
|
||||
puts "--- port loads ---"
|
||||
set_load -pin_load 0.04 [get_ports out1]
|
||||
set_load -wire_load 0.02 [get_ports out1]
|
||||
set_load -pin_load 0.03 [get_ports out2]
|
||||
set_load -wire_load 0.01 [get_ports out2]
|
||||
report_checks
|
||||
puts "PASS: port loads"
|
||||
|
||||
############################################################
|
||||
# Port fanout
|
||||
############################################################
|
||||
puts "--- port fanout ---"
|
||||
set_port_fanout_number 4 [get_ports out1]
|
||||
set_port_fanout_number 6 [get_ports out2]
|
||||
report_checks
|
||||
puts "PASS: port fanout"
|
||||
|
||||
############################################################
|
||||
# Net resistance
|
||||
############################################################
|
||||
puts "--- net resistance ---"
|
||||
set_resistance -min 10.0 [get_nets n1]
|
||||
set_resistance -max 20.0 [get_nets n1]
|
||||
set_resistance -min 5.0 [get_nets n2]
|
||||
set_resistance -max 15.0 [get_nets n2]
|
||||
set_resistance 12.0 [get_nets n3]
|
||||
report_checks
|
||||
puts "PASS: net resistance"
|
||||
|
||||
############################################################
|
||||
# Voltage settings
|
||||
############################################################
|
||||
puts "--- voltage ---"
|
||||
catch {
|
||||
set_voltage 1.1 -min 0.9
|
||||
report_checks
|
||||
}
|
||||
puts "PASS: voltage global"
|
||||
|
||||
catch {
|
||||
set_voltage 1.2 -min 1.0 -object_list [get_nets n1]
|
||||
report_checks
|
||||
}
|
||||
puts "PASS: voltage on net"
|
||||
|
||||
############################################################
|
||||
# Timing deratings: global
|
||||
############################################################
|
||||
puts "--- timing derate global ---"
|
||||
set_timing_derate -early 0.95
|
||||
set_timing_derate -late 1.05
|
||||
set_timing_derate -early -clock 0.97
|
||||
set_timing_derate -late -clock 1.03
|
||||
report_checks
|
||||
puts "PASS: global derating"
|
||||
|
||||
############################################################
|
||||
# Timing deratings: on lib cells
|
||||
############################################################
|
||||
puts "--- timing derate lib cell ---"
|
||||
set_timing_derate -early -cell_delay 0.91 [get_lib_cells NangateOpenCellLibrary/INV_X1]
|
||||
set_timing_derate -late -cell_delay 1.09 [get_lib_cells NangateOpenCellLibrary/INV_X1]
|
||||
set_timing_derate -early -cell_delay 0.92 [get_lib_cells NangateOpenCellLibrary/BUF_X1]
|
||||
set_timing_derate -late -cell_delay 1.08 [get_lib_cells NangateOpenCellLibrary/BUF_X1]
|
||||
report_checks
|
||||
puts "PASS: lib cell derating"
|
||||
|
||||
############################################################
|
||||
# Timing deratings: on instances
|
||||
############################################################
|
||||
puts "--- timing derate instance ---"
|
||||
set_timing_derate -early -cell_delay 0.90 [get_cells buf1]
|
||||
set_timing_derate -late -cell_delay 1.10 [get_cells buf1]
|
||||
set_timing_derate -early -cell_delay 0.93 [get_cells inv1]
|
||||
set_timing_derate -late -cell_delay 1.07 [get_cells inv1]
|
||||
report_checks
|
||||
puts "PASS: instance derating"
|
||||
|
||||
############################################################
|
||||
# Timing deratings: on nets
|
||||
############################################################
|
||||
puts "--- timing derate net ---"
|
||||
set_timing_derate -early -net_delay 0.88 [get_nets n1]
|
||||
set_timing_derate -late -net_delay 1.12 [get_nets n1]
|
||||
set_timing_derate -early -net_delay 0.89 [get_nets n3]
|
||||
set_timing_derate -late -net_delay 1.11 [get_nets n3]
|
||||
report_checks
|
||||
puts "PASS: net derating"
|
||||
|
||||
############################################################
|
||||
# Write SDC and verify all sections are written
|
||||
############################################################
|
||||
puts "--- write_sdc native ---"
|
||||
set sdc1 [make_result_file sdc_net_wire_voltage1.sdc]
|
||||
write_sdc -no_timestamp $sdc1
|
||||
puts "PASS: write_sdc native"
|
||||
|
||||
puts "--- write_sdc compatible ---"
|
||||
set sdc2 [make_result_file sdc_net_wire_voltage2.sdc]
|
||||
write_sdc -no_timestamp -compatible $sdc2
|
||||
puts "PASS: write_sdc compatible"
|
||||
|
||||
puts "--- write_sdc digits 8 ---"
|
||||
set sdc3 [make_result_file sdc_net_wire_voltage3.sdc]
|
||||
write_sdc -no_timestamp -digits 8 $sdc3
|
||||
puts "PASS: write_sdc digits 8"
|
||||
|
||||
############################################################
|
||||
# Read back and verify constraints survive roundtrip
|
||||
############################################################
|
||||
puts "--- read_sdc back ---"
|
||||
read_sdc $sdc1
|
||||
report_checks
|
||||
puts "PASS: read_sdc roundtrip"
|
||||
|
||||
############################################################
|
||||
# Write after re-read
|
||||
############################################################
|
||||
set sdc4 [make_result_file sdc_net_wire_voltage4.sdc]
|
||||
write_sdc -no_timestamp $sdc4
|
||||
puts "PASS: write_sdc after re-read"
|
||||
|
||||
############################################################
|
||||
# Reset deratings
|
||||
############################################################
|
||||
puts "--- reset deratings ---"
|
||||
unset_timing_derate
|
||||
report_checks
|
||||
puts "PASS: reset deratings"
|
||||
|
||||
############################################################
|
||||
# Final write with cleared deratings
|
||||
############################################################
|
||||
set sdc5 [make_result_file sdc_net_wire_voltage5.sdc]
|
||||
write_sdc -no_timestamp $sdc5
|
||||
puts "PASS: write after clear deratings"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,237 @@
|
||||
PASS: clocks created
|
||||
PASS: basic input delay
|
||||
PASS: input delay rise/fall min/max
|
||||
PASS: input delay -clock_fall
|
||||
PASS: input delay -add_delay
|
||||
PASS: input delay -clock_fall -rise/-fall -add_delay
|
||||
PASS: basic output delay
|
||||
PASS: output delay rise/fall min/max
|
||||
PASS: output delay -clock_fall -add_delay
|
||||
PASS: source latency early/late rise/fall
|
||||
PASS: source latency on clk2
|
||||
PASS: network latency all rf/minmax
|
||||
PASS: global derate
|
||||
PASS: rise/fall derate
|
||||
PASS: clock/data derate
|
||||
PASS: cell_delay derate
|
||||
PASS: net_delay derate
|
||||
PASS: lib cell derate
|
||||
PASS: instance derate
|
||||
PASS: instance derate inv1
|
||||
PASS: disable buf1
|
||||
PASS: disable pin inv1/A
|
||||
PASS: disable lib cell arc
|
||||
PASS: disable lib cell NAND2
|
||||
PASS: data_check -setup
|
||||
PASS: data_check -hold
|
||||
PASS: case_analysis 0
|
||||
PASS: logic_one
|
||||
PASS: logic_zero
|
||||
PASS: max_time_borrow on clock
|
||||
PASS: max_time_borrow on pin
|
||||
PASS: min pulse width
|
||||
Warning: sdc_port_delay_advanced.tcl line 1, object 'sdc_test2' not found.
|
||||
Warning: sdc_port_delay_advanced.tcl line 1, object 'sdc_test2' not found.
|
||||
PASS: clock gating check
|
||||
PASS: driving cells
|
||||
PASS: set_drive
|
||||
PASS: loads
|
||||
PASS: input transitions
|
||||
PASS: port fanout number
|
||||
PASS: net resistance
|
||||
PASS: design limits
|
||||
PASS: operating conditions and wire load
|
||||
PASS: set_voltage
|
||||
PASS: write_sdc native
|
||||
PASS: write_sdc -compatible
|
||||
PASS: write_sdc -digits 8
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.95 0.95 clock network delay (ideal)
|
||||
0.00 0.95 ^ reg2/CK (DFF_X1)
|
||||
0.09 1.04 ^ reg2/Q (DFF_X1)
|
||||
0.00 1.04 ^ out1 (out)
|
||||
1.04 data arrival time
|
||||
|
||||
5.00 5.00 clock clk1 (fall edge)
|
||||
0.35 5.35 clock network delay (ideal)
|
||||
0.00 5.35 clock reconvergence pessimism
|
||||
-2.50 2.85 output external delay
|
||||
2.85 data required time
|
||||
---------------------------------------------------------
|
||||
2.85 data required time
|
||||
-1.04 data arrival time
|
||||
---------------------------------------------------------
|
||||
1.81 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.95 10.95 clock network delay (ideal)
|
||||
0.00 10.95 ^ reg1/CK (DFF_X1)
|
||||
0.08 11.03 v reg1/Q (DFF_X1)
|
||||
0.00 11.03 v reg3/D (DFF_X1)
|
||||
11.03 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.20 20.20 clock network delay (ideal)
|
||||
0.00 20.20 clock reconvergence pessimism
|
||||
20.20 ^ reg3/CK (DFF_X1)
|
||||
-0.04 20.16 library setup time
|
||||
20.16 data required time
|
||||
---------------------------------------------------------
|
||||
20.16 data required time
|
||||
-11.03 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.13 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.45 0.45 clock network delay (ideal)
|
||||
0.00 0.45 ^ reg2/CK (DFF_X1)
|
||||
0.07 0.52 v reg2/Q (DFF_X1)
|
||||
0.00 0.52 v out1 (out)
|
||||
0.52 data arrival time
|
||||
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.95 0.95 clock network delay (ideal)
|
||||
0.00 0.95 clock reconvergence pessimism
|
||||
-3.00 -2.05 output external delay
|
||||
-2.05 data required time
|
||||
---------------------------------------------------------
|
||||
-2.05 data required time
|
||||
-0.52 data arrival time
|
||||
---------------------------------------------------------
|
||||
2.57 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.45 0.45 clock network delay (ideal)
|
||||
0.00 0.45 ^ reg1/CK (DFF_X1)
|
||||
0.07 0.52 v reg1/Q (DFF_X1)
|
||||
0.00 0.52 v reg3/D (DFF_X1)
|
||||
0.52 data arrival time
|
||||
|
||||
0.00 0.00 clock clk2 (rise edge)
|
||||
0.40 0.40 clock network delay (ideal)
|
||||
0.00 0.40 clock reconvergence pessimism
|
||||
0.40 ^ reg3/CK (DFF_X1)
|
||||
0.00 0.40 library hold time
|
||||
0.40 data required time
|
||||
---------------------------------------------------------
|
||||
0.40 data required time
|
||||
-0.52 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.12 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks -path_delay min
|
||||
max slew
|
||||
|
||||
Pin Limit Slew Slack
|
||||
------------------------------------------------------------
|
||||
reg1/QN 0.20 0.01 0.19 (MET)
|
||||
|
||||
max fanout
|
||||
|
||||
Pin Limit Fanout Slack
|
||||
---------------------------------------------------------
|
||||
reg1/Q 20 1 19 (MET)
|
||||
|
||||
max capacitance
|
||||
|
||||
Pin Limit Cap Slack
|
||||
------------------------------------------------------------
|
||||
reg1/Q 0.20 1.45 -1.25 (VIOLATED)
|
||||
|
||||
PASS: report_check_types
|
||||
PASS: unset_timing_derate
|
||||
PASS: unset disable
|
||||
PASS: unset case analysis
|
||||
PASS: unset clock latencies
|
||||
Startpoint: in3 (input port clocked by clk1)
|
||||
Endpoint: reg2 (falling edge-triggered data to data check clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
5.00 5.00 clock clk1 (fall edge)
|
||||
0.00 5.00 clock network delay (ideal)
|
||||
2.80 7.80 ^ input external delay
|
||||
0.00 7.80 ^ in3 (in)
|
||||
0.03 7.83 ^ or1/ZN (OR2_X1)
|
||||
0.01 7.84 v nor1/ZN (NOR2_X1)
|
||||
0.00 7.84 v reg2/D (DFF_X1)
|
||||
7.84 data arrival time
|
||||
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 v reg1/Q (DFF_X1)
|
||||
-0.50 -0.42 data check setup time
|
||||
-0.42 data required time
|
||||
---------------------------------------------------------
|
||||
-0.42 data required time
|
||||
-7.84 data arrival time
|
||||
---------------------------------------------------------
|
||||
-8.26 slack (VIOLATED)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: final report_checks
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,350 @@
|
||||
# Test advanced port delay, derating, data check, and misc SDC features
|
||||
# Targets: PortDelay.cc, DeratingFactors.cc, DataCheck.cc, Clock.cc,
|
||||
# ClockInsertion.cc, ClockLatency.cc, DisabledPorts.cc,
|
||||
# WriteSdc.cc (writePortDelay, writeDeratingFactors, writeDataCheck,
|
||||
# writeConstants, writeDisabled*, writeClockInsertion)
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
############################################################
|
||||
# Setup clocks
|
||||
############################################################
|
||||
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 -waveform {0 10} [get_ports clk2]
|
||||
create_clock -name vclk -period 8
|
||||
puts "PASS: clocks created"
|
||||
|
||||
############################################################
|
||||
# Input delays with comprehensive min/max/rise/fall options
|
||||
############################################################
|
||||
|
||||
# Basic input delay
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
puts "PASS: basic input delay"
|
||||
|
||||
# Rise/fall max/min on same port
|
||||
set_input_delay -clock clk1 -rise -max 2.5 [get_ports in2]
|
||||
set_input_delay -clock clk1 -rise -min 1.2 [get_ports in2]
|
||||
set_input_delay -clock clk1 -fall -max 2.3 [get_ports in2]
|
||||
set_input_delay -clock clk1 -fall -min 1.0 [get_ports in2]
|
||||
puts "PASS: input delay rise/fall min/max"
|
||||
|
||||
# Input delay with clock_fall
|
||||
set_input_delay -clock clk1 -clock_fall 1.5 [get_ports in3]
|
||||
puts "PASS: input delay -clock_fall"
|
||||
|
||||
# Additional delay on same port
|
||||
set_input_delay -clock clk2 1.8 [get_ports in3] -add_delay
|
||||
puts "PASS: input delay -add_delay"
|
||||
|
||||
# Rise/fall with clock_fall + add_delay
|
||||
set_input_delay -clock clk1 -clock_fall -rise -max 2.8 [get_ports in3] -add_delay
|
||||
set_input_delay -clock clk1 -clock_fall -fall -min 0.8 [get_ports in3] -add_delay
|
||||
puts "PASS: input delay -clock_fall -rise/-fall -add_delay"
|
||||
|
||||
############################################################
|
||||
# Output delays with comprehensive options
|
||||
############################################################
|
||||
|
||||
# Basic output delay
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
puts "PASS: basic output delay"
|
||||
|
||||
# Rise/fall max/min on same port
|
||||
set_output_delay -clock clk2 -rise -max 3.5 [get_ports out2]
|
||||
set_output_delay -clock clk2 -rise -min 1.5 [get_ports out2]
|
||||
set_output_delay -clock clk2 -fall -max 3.2 [get_ports out2]
|
||||
set_output_delay -clock clk2 -fall -min 1.2 [get_ports out2]
|
||||
puts "PASS: output delay rise/fall min/max"
|
||||
|
||||
# Output delay with clock_fall
|
||||
set_output_delay -clock clk1 -clock_fall 2.5 [get_ports out1] -add_delay
|
||||
puts "PASS: output delay -clock_fall -add_delay"
|
||||
|
||||
############################################################
|
||||
# Source latency with early/late (ClockInsertion.cc)
|
||||
############################################################
|
||||
|
||||
set_clock_latency -source -early 0.3 [get_clocks clk1]
|
||||
set_clock_latency -source -late 0.5 [get_clocks clk1]
|
||||
set_clock_latency -source -early -rise 0.25 [get_clocks clk1]
|
||||
set_clock_latency -source -late -rise 0.55 [get_clocks clk1]
|
||||
set_clock_latency -source -early -fall 0.20 [get_clocks clk1]
|
||||
set_clock_latency -source -late -fall 0.45 [get_clocks clk1]
|
||||
puts "PASS: source latency early/late rise/fall"
|
||||
|
||||
set_clock_latency -source -early 0.2 [get_clocks clk2]
|
||||
set_clock_latency -source -late 0.4 [get_clocks clk2]
|
||||
puts "PASS: source latency on clk2"
|
||||
|
||||
# Network latency with all corners
|
||||
set_clock_latency 0.3 [get_clocks clk1]
|
||||
set_clock_latency -rise -max 0.4 [get_clocks clk1]
|
||||
set_clock_latency -rise -min 0.2 [get_clocks clk1]
|
||||
set_clock_latency -fall -max 0.35 [get_clocks clk1]
|
||||
set_clock_latency -fall -min 0.15 [get_clocks clk1]
|
||||
puts "PASS: network latency all rf/minmax"
|
||||
|
||||
############################################################
|
||||
# Timing derate with cell/net type specifics (DeratingFactors.cc)
|
||||
############################################################
|
||||
|
||||
# Global derate
|
||||
set_timing_derate -early 0.95
|
||||
set_timing_derate -late 1.05
|
||||
puts "PASS: global derate"
|
||||
|
||||
# Rise/fall derate
|
||||
set_timing_derate -early -rise 0.96
|
||||
set_timing_derate -late -fall 1.04
|
||||
puts "PASS: rise/fall derate"
|
||||
|
||||
# Clock/data path derate
|
||||
set_timing_derate -early -clock 0.97
|
||||
set_timing_derate -late -clock 1.03
|
||||
set_timing_derate -early -data 0.94
|
||||
set_timing_derate -late -data 1.06
|
||||
puts "PASS: clock/data derate"
|
||||
|
||||
# Cell delay derate
|
||||
set_timing_derate -early -cell_delay 0.93
|
||||
set_timing_derate -late -cell_delay 1.07
|
||||
puts "PASS: cell_delay derate"
|
||||
|
||||
# Net delay derate
|
||||
set_timing_derate -early -net_delay 0.92
|
||||
set_timing_derate -late -net_delay 1.08
|
||||
puts "PASS: net_delay derate"
|
||||
|
||||
# Cell-specific derate (on lib cell)
|
||||
set_timing_derate -early -cell_delay 0.91 [get_lib_cells NangateOpenCellLibrary/INV_X1]
|
||||
set_timing_derate -late -cell_delay 1.09 [get_lib_cells NangateOpenCellLibrary/INV_X1]
|
||||
puts "PASS: lib cell derate"
|
||||
|
||||
# Instance-specific derate
|
||||
set_timing_derate -early -cell_delay 0.90 [get_cells buf1]
|
||||
set_timing_derate -late -cell_delay 1.10 [get_cells buf1]
|
||||
puts "PASS: instance derate"
|
||||
|
||||
set_timing_derate -early -cell_delay 0.89 [get_cells inv1]
|
||||
set_timing_derate -late -cell_delay 1.11 [get_cells inv1]
|
||||
puts "PASS: instance derate inv1"
|
||||
|
||||
############################################################
|
||||
# Disable timing - various forms (DisabledPorts.cc)
|
||||
############################################################
|
||||
|
||||
# Disable instance
|
||||
set_disable_timing [get_cells buf1]
|
||||
puts "PASS: disable buf1"
|
||||
|
||||
# Disable pin
|
||||
set_disable_timing [get_pins inv1/A]
|
||||
puts "PASS: disable pin inv1/A"
|
||||
|
||||
# Disable lib cell arc
|
||||
set_disable_timing [get_lib_cells NangateOpenCellLibrary/BUF_X1] -from A -to Z
|
||||
puts "PASS: disable lib cell arc"
|
||||
|
||||
# Disable lib cell (all arcs)
|
||||
set_disable_timing [get_lib_cells NangateOpenCellLibrary/NAND2_X1]
|
||||
puts "PASS: disable lib cell NAND2"
|
||||
|
||||
############################################################
|
||||
# Data check (DataCheck.cc)
|
||||
############################################################
|
||||
|
||||
catch {
|
||||
set_data_check -from [get_pins reg1/Q] -to [get_pins reg2/D] -setup 0.5
|
||||
puts "PASS: data_check -setup"
|
||||
}
|
||||
|
||||
catch {
|
||||
set_data_check -from [get_pins reg1/Q] -to [get_pins reg2/D] -hold 0.3
|
||||
puts "PASS: data_check -hold"
|
||||
}
|
||||
|
||||
catch {
|
||||
set_data_check -from [get_pins reg1/Q] -to [get_pins reg2/D] -setup 0.6 -clock_fall
|
||||
puts "PASS: data_check -setup -clock_fall"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Case analysis and logic values (Constants)
|
||||
############################################################
|
||||
|
||||
set_case_analysis 0 [get_ports in3]
|
||||
puts "PASS: case_analysis 0"
|
||||
|
||||
set_logic_one [get_ports in2]
|
||||
puts "PASS: logic_one"
|
||||
|
||||
set_logic_zero [get_ports in1]
|
||||
puts "PASS: logic_zero"
|
||||
|
||||
############################################################
|
||||
# Latch borrow limits
|
||||
############################################################
|
||||
|
||||
set_max_time_borrow 2.0 [get_clocks clk1]
|
||||
puts "PASS: max_time_borrow on clock"
|
||||
|
||||
set_max_time_borrow 1.5 [get_pins reg1/D]
|
||||
puts "PASS: max_time_borrow on pin"
|
||||
|
||||
############################################################
|
||||
# Min pulse width (all options)
|
||||
############################################################
|
||||
|
||||
set_min_pulse_width 1.0 [get_clocks clk1]
|
||||
set_min_pulse_width -high 0.6 [get_clocks clk1]
|
||||
set_min_pulse_width -low 0.4 [get_clocks clk1]
|
||||
set_min_pulse_width 0.8 [get_clocks clk2]
|
||||
puts "PASS: min pulse width"
|
||||
|
||||
############################################################
|
||||
# Clock gating check
|
||||
############################################################
|
||||
|
||||
set_clock_gating_check -setup 0.5 [get_clocks clk1]
|
||||
set_clock_gating_check -hold 0.3 [get_clocks clk1]
|
||||
set_clock_gating_check -setup 0.4 [current_design]
|
||||
set_clock_gating_check -hold 0.2 [current_design]
|
||||
puts "PASS: clock gating check"
|
||||
|
||||
############################################################
|
||||
# Driving cells with various options
|
||||
############################################################
|
||||
|
||||
set_driving_cell -lib_cell BUF_X1 [get_ports in1]
|
||||
set_driving_cell -lib_cell INV_X1 -pin ZN [get_ports in2]
|
||||
set_driving_cell -lib_cell BUF_X4 -rise [get_ports in3]
|
||||
set_driving_cell -lib_cell BUF_X2 -fall [get_ports in3]
|
||||
puts "PASS: driving cells"
|
||||
|
||||
# set_drive
|
||||
set_drive 100 [get_ports in1]
|
||||
set_drive -rise 80 [get_ports in2]
|
||||
set_drive -fall 120 [get_ports in2]
|
||||
puts "PASS: set_drive"
|
||||
|
||||
# Loads
|
||||
set_load 0.05 [get_ports out1]
|
||||
set_load -pin_load 0.03 [get_ports out2]
|
||||
set_load -wire_load 0.02 [get_ports out1]
|
||||
set_load -min 0.01 [get_ports out1]
|
||||
set_load -max 0.06 [get_ports out1]
|
||||
puts "PASS: loads"
|
||||
|
||||
# Input transition
|
||||
set_input_transition 0.15 [get_ports in1]
|
||||
set_input_transition -rise -max 0.12 [get_ports in2]
|
||||
set_input_transition -fall -min 0.08 [get_ports in2]
|
||||
set_input_transition -rise -min 0.06 [get_ports in3]
|
||||
set_input_transition -fall -max 0.18 [get_ports in3]
|
||||
puts "PASS: input transitions"
|
||||
|
||||
############################################################
|
||||
# Port fanout number
|
||||
############################################################
|
||||
|
||||
set_port_fanout_number 4 [get_ports out1]
|
||||
set_port_fanout_number 8 [get_ports out2]
|
||||
puts "PASS: port fanout number"
|
||||
|
||||
############################################################
|
||||
# Net resistance
|
||||
############################################################
|
||||
|
||||
set_resistance -min 10.0 [get_nets n1]
|
||||
set_resistance -max 20.0 [get_nets n1]
|
||||
puts "PASS: net resistance"
|
||||
|
||||
############################################################
|
||||
# Design limits
|
||||
############################################################
|
||||
|
||||
set_max_transition 0.5 [current_design]
|
||||
set_max_capacitance 0.2 [current_design]
|
||||
set_max_fanout 20 [current_design]
|
||||
set_max_area 100.0
|
||||
puts "PASS: design limits"
|
||||
|
||||
############################################################
|
||||
# Operating conditions and wire load
|
||||
############################################################
|
||||
|
||||
set_operating_conditions typical
|
||||
set_wire_load_model -name "5K_hvratio_1_1"
|
||||
set_wire_load_mode enclosed
|
||||
puts "PASS: operating conditions and wire load"
|
||||
|
||||
############################################################
|
||||
# Voltage setting
|
||||
############################################################
|
||||
|
||||
catch {set_voltage 1.1 -min 0.9}
|
||||
puts "PASS: set_voltage"
|
||||
|
||||
############################################################
|
||||
# Write SDC with all the constraints
|
||||
############################################################
|
||||
|
||||
set sdc_file1 [make_result_file sdc_port_delay_adv1.sdc]
|
||||
write_sdc -no_timestamp $sdc_file1
|
||||
puts "PASS: write_sdc native"
|
||||
|
||||
set sdc_file2 [make_result_file sdc_port_delay_adv2.sdc]
|
||||
write_sdc -no_timestamp -compatible $sdc_file2
|
||||
puts "PASS: write_sdc -compatible"
|
||||
|
||||
set sdc_file3 [make_result_file sdc_port_delay_adv3.sdc]
|
||||
write_sdc -no_timestamp -digits 8 $sdc_file3
|
||||
puts "PASS: write_sdc -digits 8"
|
||||
|
||||
############################################################
|
||||
# Report checks to verify
|
||||
############################################################
|
||||
|
||||
report_checks
|
||||
puts "PASS: report_checks"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: report_checks -path_delay min"
|
||||
|
||||
report_check_types -max_slew -max_capacitance -max_fanout
|
||||
puts "PASS: report_check_types"
|
||||
|
||||
############################################################
|
||||
# Unset derating and verify
|
||||
############################################################
|
||||
|
||||
unset_timing_derate
|
||||
puts "PASS: unset_timing_derate"
|
||||
|
||||
# Unset disable
|
||||
unset_disable_timing [get_cells buf1]
|
||||
unset_disable_timing [get_pins inv1/A]
|
||||
unset_disable_timing [get_lib_cells NangateOpenCellLibrary/BUF_X1] -from A -to Z
|
||||
unset_disable_timing [get_lib_cells NangateOpenCellLibrary/NAND2_X1]
|
||||
puts "PASS: unset disable"
|
||||
|
||||
# Unset case analysis
|
||||
unset_case_analysis [get_ports in3]
|
||||
puts "PASS: unset case analysis"
|
||||
|
||||
# Unset clock latencies
|
||||
unset_clock_latency [get_clocks clk1]
|
||||
unset_clock_latency -source [get_clocks clk1]
|
||||
unset_clock_latency [get_clocks clk2]
|
||||
unset_clock_latency -source [get_clocks clk2]
|
||||
puts "PASS: unset clock latencies"
|
||||
|
||||
report_checks
|
||||
puts "PASS: final report_checks"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,315 @@
|
||||
PASS: Phase 1 - clocks
|
||||
PASS: Phase 1 - generated clocks
|
||||
PASS: Phase 1 - IO delays
|
||||
PASS: Phase 1 - clock latency
|
||||
PASS: Phase 1 - clock uncertainty
|
||||
PASS: Phase 1 - clock transition
|
||||
PASS: Phase 1 - source latency early/late
|
||||
PASS: Phase 1 - min pulse width
|
||||
PASS: Phase 1 - latch borrow
|
||||
PASS: Phase 1 - clock groups
|
||||
PASS: Phase 1 - exception paths
|
||||
PASS: Phase 1 - timing derate
|
||||
PASS: Phase 1 - disable timing
|
||||
PASS: Phase 1 - case analysis
|
||||
PASS: Phase 1 - design limits
|
||||
PASS: Phase 1 - write_sdc
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.50 0.50 clock network delay (ideal)
|
||||
0.00 0.50 ^ reg2/CK (DFF_X1)
|
||||
0.11 0.61 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.61 ^ out1 (out)
|
||||
0.61 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.30 10.30 clock network delay (ideal)
|
||||
-0.20 10.10 clock uncertainty
|
||||
0.00 10.10 clock reconvergence pessimism
|
||||
-3.00 7.10 output external delay
|
||||
7.10 data required time
|
||||
---------------------------------------------------------
|
||||
7.10 data required time
|
||||
-0.61 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.49 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3/Q (clock source 'gclk2')
|
||||
Endpoint: out2 (output port clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
15.00 15.00 clock gclk2 (fall edge)
|
||||
0.00 15.00 clock network delay
|
||||
15.00 v out2 (out)
|
||||
15.00 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.20 20.20 clock network delay (ideal)
|
||||
0.00 20.20 clock reconvergence pessimism
|
||||
-3.50 16.70 output external delay
|
||||
16.70 data required time
|
||||
---------------------------------------------------------
|
||||
16.70 data required time
|
||||
-15.00 data arrival time
|
||||
---------------------------------------------------------
|
||||
1.70 slack (MET)
|
||||
|
||||
|
||||
PASS: Phase 1 - report_checks
|
||||
PASS: Phase 2 - remove false path
|
||||
PASS: Phase 2 - remove multicycle
|
||||
PASS: Phase 2 - remove timing derate
|
||||
PASS: Phase 2 - remove disable timing
|
||||
PASS: Phase 2 - remove case analysis
|
||||
PASS: Phase 2 - remove clock groups
|
||||
PASS: Phase 2 - remove clock latency
|
||||
PASS: Phase 2 - remove inter-clock uncertainty
|
||||
PASS: Phase 2 - remove propagated clock
|
||||
PASS: Phase 2 - write_sdc
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.10 0.10 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.10 ^ out1 (out)
|
||||
0.10 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
-0.20 9.80 clock uncertainty
|
||||
0.00 9.80 clock reconvergence pessimism
|
||||
-3.00 6.80 output external delay
|
||||
6.80 data required time
|
||||
---------------------------------------------------------
|
||||
6.80 data required time
|
||||
-0.10 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.70 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3/Q (clock source 'gclk2')
|
||||
Endpoint: out2 (output port clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
15.00 15.00 clock gclk2 (fall edge)
|
||||
0.00 15.00 clock network delay
|
||||
15.00 v out2 (out)
|
||||
15.00 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
-3.50 16.50 output external delay
|
||||
16.50 data required time
|
||||
---------------------------------------------------------
|
||||
16.50 data required time
|
||||
-15.00 data arrival time
|
||||
---------------------------------------------------------
|
||||
1.50 slack (MET)
|
||||
|
||||
|
||||
PASS: Phase 2 - report_checks
|
||||
PASS: Phase 3 - delete gclk1
|
||||
PASS: Phase 3 - delete gclk2
|
||||
PASS: Phase 3 - delete vclk
|
||||
Clock Period Waveform
|
||||
----------------------------------------------------
|
||||
clk1 10.00 0.00 5.00
|
||||
clk2 20.00 0.00 10.00
|
||||
PASS: Phase 3 - report after clock deletions
|
||||
PASS: Phase 3a - write_sdc
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.10 0.10 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.10 ^ out1 (out)
|
||||
0.10 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
-0.20 9.80 clock uncertainty
|
||||
0.00 9.80 clock reconvergence pessimism
|
||||
-3.00 6.80 output external delay
|
||||
6.80 data required time
|
||||
---------------------------------------------------------
|
||||
6.80 data required time
|
||||
-0.10 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.70 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.10 10.10 ^ reg1/Q (DFF_X1)
|
||||
0.00 10.10 ^ reg3/D (DFF_X1)
|
||||
10.10 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.03 19.97 library setup time
|
||||
19.97 data required time
|
||||
---------------------------------------------------------
|
||||
19.97 data required time
|
||||
-10.10 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.86 slack (MET)
|
||||
|
||||
|
||||
PASS: Phase 3a - report_checks
|
||||
PASS: Phase 4 - new virtual clock
|
||||
PASS: Phase 4 - new generated clock
|
||||
PASS: Phase 4 - new clock groups
|
||||
PASS: Phase 4 - new exceptions
|
||||
PASS: Phase 4 - new latency
|
||||
PASS: Phase 4 - new uncertainty
|
||||
PASS: Phase 4 - new derate
|
||||
PASS: Phase 4 - new disable
|
||||
PASS: Phase 4 - write_sdc
|
||||
PASS: Phase 4 - write_sdc compatible
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.40 0.40 clock network delay (ideal)
|
||||
0.00 0.40 ^ reg2/CK (DFF_X1)
|
||||
0.10 0.50 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.50 ^ out1 (out)
|
||||
0.50 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.40 10.40 clock network delay (ideal)
|
||||
-0.25 10.15 clock uncertainty
|
||||
0.00 10.15 clock reconvergence pessimism
|
||||
-3.00 7.15 output external delay
|
||||
7.15 data required time
|
||||
---------------------------------------------------------
|
||||
7.15 data required time
|
||||
-0.50 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.65 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Endpoint: out2 (output port clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk2 (rise edge)
|
||||
0.15 0.15 clock network delay (ideal)
|
||||
0.00 0.15 ^ reg3/CK (DFF_X1)
|
||||
0.11 0.26 ^ reg3/Q (DFF_X1)
|
||||
0.00 0.26 ^ out2 (out)
|
||||
0.26 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.15 20.15 clock network delay (ideal)
|
||||
0.00 20.15 clock reconvergence pessimism
|
||||
-3.50 16.65 output external delay
|
||||
16.65 data required time
|
||||
---------------------------------------------------------
|
||||
16.65 data required time
|
||||
-0.26 data arrival time
|
||||
---------------------------------------------------------
|
||||
16.39 slack (MET)
|
||||
|
||||
|
||||
PASS: Phase 4 - report_checks
|
||||
PASS: Phase 5 - read_sdc
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.40 0.40 clock network delay (ideal)
|
||||
0.00 0.40 ^ reg2/CK (DFF_X1)
|
||||
0.10 0.50 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.50 ^ out1 (out)
|
||||
0.50 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.40 10.40 clock network delay (ideal)
|
||||
-0.25 10.15 clock uncertainty
|
||||
0.00 10.15 clock reconvergence pessimism
|
||||
-3.00 7.15 output external delay
|
||||
7.15 data required time
|
||||
---------------------------------------------------------
|
||||
7.15 data required time
|
||||
-0.50 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.65 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Endpoint: out2 (output port clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk2 (rise edge)
|
||||
0.15 0.15 clock network delay (ideal)
|
||||
0.00 0.15 ^ reg3/CK (DFF_X1)
|
||||
0.11 0.26 ^ reg3/Q (DFF_X1)
|
||||
0.00 0.26 ^ out2 (out)
|
||||
0.26 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.15 20.15 clock network delay (ideal)
|
||||
0.00 20.15 clock reconvergence pessimism
|
||||
-3.50 16.65 output external delay
|
||||
16.65 data required time
|
||||
---------------------------------------------------------
|
||||
16.65 data required time
|
||||
-0.26 data arrival time
|
||||
---------------------------------------------------------
|
||||
16.39 slack (MET)
|
||||
|
||||
|
||||
PASS: Phase 5 - report_checks after read
|
||||
PASS: Phase 5 - write_sdc after read
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,265 @@
|
||||
# Test SDC constraint creation, removal, and re-creation
|
||||
# Targets: Sdc.cc (removeClock, deleteMasterClkRefs, removeInputDelay, removeOutputDelay,
|
||||
# deleteInputDelaysReferencing, deleteOutputDelaysReferencing,
|
||||
# deleteClockLatency, deleteClockInsertion, deleteInterClockUncertainty,
|
||||
# deleteClockInsertionsReferencing, deleteMinPulseWidthReferencing,
|
||||
# deleteLatchBorrowLimitsReferencing, clockGroupsDeleteClkRefs),
|
||||
# ExceptionPath.cc (exception removal, priority comparison),
|
||||
# Clock.cc (initClk, deletion, re-creation),
|
||||
# WriteSdc.cc (writing after removals),
|
||||
# CycleAccting.cc (cycle accounting with different clock configs)
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
############################################################
|
||||
# Phase 1: Create comprehensive constraints
|
||||
############################################################
|
||||
|
||||
# Clocks
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 -waveform {0 10} [get_ports clk2]
|
||||
create_clock -name vclk -period 8
|
||||
puts "PASS: Phase 1 - clocks"
|
||||
|
||||
# Generated clocks
|
||||
create_generated_clock -name gclk1 -source [get_ports clk1] -divide_by 2 [get_pins reg1/Q]
|
||||
create_generated_clock -name gclk2 -source [get_ports clk2] -multiply_by 2 [get_pins reg3/Q]
|
||||
puts "PASS: Phase 1 - generated clocks"
|
||||
|
||||
# IO delays
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 -rise -max 2.5 [get_ports in2]
|
||||
set_input_delay -clock clk1 -fall -min 1.0 [get_ports in2]
|
||||
set_input_delay -clock clk2 1.8 [get_ports in3]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 3.5 [get_ports out2]
|
||||
puts "PASS: Phase 1 - IO delays"
|
||||
|
||||
# Clock latency
|
||||
set_clock_latency -source 0.5 [get_clocks clk1]
|
||||
set_clock_latency -source -rise -max 0.6 [get_clocks clk1]
|
||||
set_clock_latency 0.2 [get_clocks clk2]
|
||||
puts "PASS: Phase 1 - clock latency"
|
||||
|
||||
# Clock uncertainty
|
||||
set_clock_uncertainty -setup 0.2 [get_clocks clk1]
|
||||
set_clock_uncertainty -hold 0.1 [get_clocks clk1]
|
||||
set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -setup 0.3
|
||||
set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -hold 0.15
|
||||
puts "PASS: Phase 1 - clock uncertainty"
|
||||
|
||||
# Clock transition
|
||||
set_clock_transition 0.1 [get_clocks clk1]
|
||||
set_clock_transition 0.15 [get_clocks clk2]
|
||||
puts "PASS: Phase 1 - clock transition"
|
||||
|
||||
# Source latency with early/late
|
||||
set_clock_latency -source -early 0.3 [get_clocks clk1]
|
||||
set_clock_latency -source -late 0.5 [get_clocks clk1]
|
||||
puts "PASS: Phase 1 - source latency early/late"
|
||||
|
||||
# Min pulse width
|
||||
set_min_pulse_width 1.0 [get_clocks clk1]
|
||||
set_min_pulse_width -high 0.6 [get_clocks clk2]
|
||||
puts "PASS: Phase 1 - min pulse width"
|
||||
|
||||
# Latch borrow limit
|
||||
set_max_time_borrow 2.0 [get_clocks clk1]
|
||||
set_max_time_borrow 1.5 [get_pins reg1/D]
|
||||
puts "PASS: Phase 1 - latch borrow"
|
||||
|
||||
# Clock groups
|
||||
set_clock_groups -asynchronous -name grp1 \
|
||||
-group {clk1 gclk1} \
|
||||
-group {clk2 gclk2}
|
||||
puts "PASS: Phase 1 - clock groups"
|
||||
|
||||
# Exception paths
|
||||
set_false_path -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
set_multicycle_path -setup 2 -from [get_ports in1] -to [get_ports out1]
|
||||
set_multicycle_path -hold 1 -from [get_ports in1] -to [get_ports out1]
|
||||
set_max_delay -from [get_ports in2] -to [get_ports out1] 8.0
|
||||
set_min_delay -from [get_ports in2] -to [get_ports out1] 1.0
|
||||
group_path -name grp_io -from [get_ports {in1 in2}] -to [get_ports out1]
|
||||
puts "PASS: Phase 1 - exception paths"
|
||||
|
||||
# Timing derate
|
||||
set_timing_derate -early 0.95
|
||||
set_timing_derate -late 1.05
|
||||
puts "PASS: Phase 1 - timing derate"
|
||||
|
||||
# Disable timing
|
||||
set_disable_timing [get_cells buf1]
|
||||
puts "PASS: Phase 1 - disable timing"
|
||||
|
||||
# Case analysis
|
||||
set_case_analysis 0 [get_ports in3]
|
||||
puts "PASS: Phase 1 - case analysis"
|
||||
|
||||
# Design limits
|
||||
set_max_transition 0.5 [current_design]
|
||||
set_max_capacitance 0.2 [current_design]
|
||||
set_max_fanout 20 [current_design]
|
||||
set_max_area 100.0
|
||||
puts "PASS: Phase 1 - design limits"
|
||||
|
||||
# Write Phase 1
|
||||
set sdc_phase1 [make_result_file sdc_removal_phase1.sdc]
|
||||
write_sdc -no_timestamp $sdc_phase1
|
||||
puts "PASS: Phase 1 - write_sdc"
|
||||
|
||||
report_checks
|
||||
puts "PASS: Phase 1 - report_checks"
|
||||
|
||||
############################################################
|
||||
# Phase 2: Remove constraints systematically
|
||||
############################################################
|
||||
|
||||
# Remove exceptions
|
||||
unset_path_exceptions -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
puts "PASS: Phase 2 - remove false path"
|
||||
|
||||
unset_path_exceptions -setup -from [get_ports in1] -to [get_ports out1]
|
||||
unset_path_exceptions -hold -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: Phase 2 - remove multicycle"
|
||||
|
||||
# Remove timing derate
|
||||
unset_timing_derate
|
||||
puts "PASS: Phase 2 - remove timing derate"
|
||||
|
||||
# Remove disable timing
|
||||
unset_disable_timing [get_cells buf1]
|
||||
puts "PASS: Phase 2 - remove disable timing"
|
||||
|
||||
# Remove case analysis
|
||||
unset_case_analysis [get_ports in3]
|
||||
puts "PASS: Phase 2 - remove case analysis"
|
||||
|
||||
# Remove clock groups
|
||||
unset_clock_groups -asynchronous -name grp1
|
||||
puts "PASS: Phase 2 - remove clock groups"
|
||||
|
||||
# Remove clock latency
|
||||
unset_clock_latency [get_clocks clk1]
|
||||
unset_clock_latency -source [get_clocks clk1]
|
||||
unset_clock_latency [get_clocks clk2]
|
||||
puts "PASS: Phase 2 - remove clock latency"
|
||||
|
||||
# Remove inter-clock uncertainty
|
||||
unset_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -setup
|
||||
unset_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -hold
|
||||
puts "PASS: Phase 2 - remove inter-clock uncertainty"
|
||||
|
||||
# Remove propagated clock
|
||||
set_propagated_clock [get_clocks clk1]
|
||||
unset_propagated_clock [get_clocks clk1]
|
||||
puts "PASS: Phase 2 - remove propagated clock"
|
||||
|
||||
# Write Phase 2 (many constraints removed)
|
||||
set sdc_phase2 [make_result_file sdc_removal_phase2.sdc]
|
||||
write_sdc -no_timestamp $sdc_phase2
|
||||
puts "PASS: Phase 2 - write_sdc"
|
||||
|
||||
report_checks
|
||||
puts "PASS: Phase 2 - report_checks"
|
||||
|
||||
############################################################
|
||||
# Phase 3: Delete and re-create clocks
|
||||
# (this is the key test - deleting clocks should remove
|
||||
# all referencing constraints)
|
||||
############################################################
|
||||
|
||||
# Delete generated clocks first
|
||||
delete_generated_clock [get_clocks gclk1]
|
||||
puts "PASS: Phase 3 - delete gclk1"
|
||||
|
||||
delete_generated_clock [get_clocks gclk2]
|
||||
puts "PASS: Phase 3 - delete gclk2"
|
||||
|
||||
# Delete virtual clock
|
||||
delete_clock [get_clocks vclk]
|
||||
puts "PASS: Phase 3 - delete vclk"
|
||||
|
||||
report_clock_properties
|
||||
puts "PASS: Phase 3 - report after clock deletions"
|
||||
|
||||
# Write after clock deletions
|
||||
set sdc_phase3a [make_result_file sdc_removal_phase3a.sdc]
|
||||
write_sdc -no_timestamp $sdc_phase3a
|
||||
puts "PASS: Phase 3a - write_sdc"
|
||||
|
||||
report_checks
|
||||
puts "PASS: Phase 3a - report_checks"
|
||||
|
||||
############################################################
|
||||
# Phase 4: Re-create everything fresh
|
||||
############################################################
|
||||
|
||||
# Re-create virtual clock with different period
|
||||
create_clock -name vclk_new -period 12
|
||||
puts "PASS: Phase 4 - new virtual clock"
|
||||
|
||||
# Re-create generated clocks on new sources
|
||||
create_generated_clock -name gclk_new1 -source [get_ports clk1] -divide_by 4 [get_pins reg1/Q]
|
||||
puts "PASS: Phase 4 - new generated clock"
|
||||
|
||||
# New clock groups
|
||||
set_clock_groups -asynchronous -name new_grp \
|
||||
-group {clk1 gclk_new1} \
|
||||
-group {clk2}
|
||||
puts "PASS: Phase 4 - new clock groups"
|
||||
|
||||
# New exceptions
|
||||
set_false_path -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
set_multicycle_path -setup 3 -from [get_ports in2] -to [get_ports out2]
|
||||
puts "PASS: Phase 4 - new exceptions"
|
||||
|
||||
# New latency
|
||||
set_clock_latency -source 0.4 [get_clocks clk1]
|
||||
set_clock_latency 0.15 [get_clocks clk2]
|
||||
puts "PASS: Phase 4 - new latency"
|
||||
|
||||
# New uncertainty
|
||||
set_clock_uncertainty -setup 0.25 [get_clocks clk1]
|
||||
set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -setup 0.35
|
||||
puts "PASS: Phase 4 - new uncertainty"
|
||||
|
||||
# New derate
|
||||
set_timing_derate -early 0.96
|
||||
set_timing_derate -late 1.04
|
||||
puts "PASS: Phase 4 - new derate"
|
||||
|
||||
# New disable
|
||||
set_disable_timing [get_cells inv1]
|
||||
puts "PASS: Phase 4 - new disable"
|
||||
|
||||
# Write Phase 4
|
||||
set sdc_phase4 [make_result_file sdc_removal_phase4.sdc]
|
||||
write_sdc -no_timestamp $sdc_phase4
|
||||
puts "PASS: Phase 4 - write_sdc"
|
||||
|
||||
set sdc_phase4_compat [make_result_file sdc_removal_phase4_compat.sdc]
|
||||
write_sdc -no_timestamp -compatible $sdc_phase4_compat
|
||||
puts "PASS: Phase 4 - write_sdc compatible"
|
||||
|
||||
report_checks
|
||||
puts "PASS: Phase 4 - report_checks"
|
||||
|
||||
############################################################
|
||||
# Phase 5: Read back SDC and verify
|
||||
############################################################
|
||||
|
||||
read_sdc $sdc_phase4
|
||||
puts "PASS: Phase 5 - read_sdc"
|
||||
|
||||
report_checks
|
||||
puts "PASS: Phase 5 - report_checks after read"
|
||||
|
||||
set sdc_phase5 [make_result_file sdc_removal_phase5.sdc]
|
||||
write_sdc -no_timestamp $sdc_phase5
|
||||
puts "PASS: Phase 5 - write_sdc after read"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,175 @@
|
||||
PASS: clocks created
|
||||
PASS: generated clocks
|
||||
PASS: IO delays
|
||||
PASS: clock latency
|
||||
PASS: clock insertion
|
||||
PASS: clock uncertainty
|
||||
PASS: latch borrow
|
||||
PASS: min pulse width
|
||||
PASS: clock groups
|
||||
PASS: exception paths
|
||||
PASS: write_sdc phase 1
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.60 0.60 clock network delay (ideal)
|
||||
0.00 0.60 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.68 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.68 ^ out1 (out)
|
||||
0.68 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.25 10.25 clock network delay (ideal)
|
||||
-0.20 10.05 clock uncertainty
|
||||
0.00 10.05 clock reconvergence pessimism
|
||||
-3.00 7.05 output external delay
|
||||
7.05 data required time
|
||||
---------------------------------------------------------
|
||||
7.05 data required time
|
||||
-0.68 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.37 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3/Q (clock source 'gclk2')
|
||||
Endpoint: out2 (output port clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
16.67 16.67 clock gclk2 (fall edge)
|
||||
0.00 16.67 clock network delay
|
||||
16.67 v out2 (out)
|
||||
16.67 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.20 20.20 clock network delay (ideal)
|
||||
0.00 20.20 clock reconvergence pessimism
|
||||
-3.50 16.70 output external delay
|
||||
16.70 data required time
|
||||
---------------------------------------------------------
|
||||
16.70 data required time
|
||||
-16.67 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.03 slack (MET)
|
||||
|
||||
|
||||
PASS: report phase 1
|
||||
Warning: sdc_remove_clock_gating.tcl line 1, object 'sdc_test2' not found.
|
||||
Warning: sdc_remove_clock_gating.tcl line 1, object 'sdc_test2' not found.
|
||||
PASS: clock_gating_check design
|
||||
PASS: clock_gating_check clock
|
||||
PASS: clock_gating_check instance
|
||||
PASS: clock_gating_check pin
|
||||
PASS: write_sdc with clock gating
|
||||
PASS: max_capacitance ports
|
||||
PASS: min_capacitance port
|
||||
PASS: max_capacitance pin
|
||||
PASS: max_capacitance design
|
||||
PASS: set_load pin and wire
|
||||
PASS: set_load rise/fall
|
||||
PASS: set_load min/max
|
||||
PASS: port fanout
|
||||
PASS: write_sdc with loads
|
||||
PASS: write_sdc compatible with loads
|
||||
PASS: delete gclk1
|
||||
PASS: delete gclk2
|
||||
PASS: delete vclk
|
||||
PASS: delete clk2
|
||||
Clock Period Waveform
|
||||
----------------------------------------------------
|
||||
clk1 10.00 0.00 5.00
|
||||
PASS: report after clock deletions
|
||||
PASS: write_sdc after clock deletions
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.60 0.60 clock network delay (ideal)
|
||||
0.00 0.60 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.68 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.68 ^ out1 (out)
|
||||
0.68 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.25 10.25 clock network delay (ideal)
|
||||
-0.20 10.05 clock uncertainty
|
||||
0.00 10.05 clock reconvergence pessimism
|
||||
-3.00 7.05 output external delay
|
||||
7.05 data required time
|
||||
---------------------------------------------------------
|
||||
7.05 data required time
|
||||
-0.68 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.37 slack (MET)
|
||||
|
||||
|
||||
PASS: report after deletions
|
||||
PASS: recreated clk2
|
||||
PASS: new inter-clock uncertainty
|
||||
PASS: write_sdc final
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.60 0.60 clock network delay (ideal)
|
||||
0.00 0.60 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.68 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.68 ^ out1 (out)
|
||||
0.68 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.25 10.25 clock network delay (ideal)
|
||||
-0.20 10.05 clock uncertainty
|
||||
0.00 10.05 clock reconvergence pessimism
|
||||
-3.00 7.05 output external delay
|
||||
7.05 data required time
|
||||
---------------------------------------------------------
|
||||
7.05 data required time
|
||||
-0.68 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.37 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2_new)
|
||||
Endpoint: out2 (output port clocked by clk2_new)
|
||||
Path Group: clk2_new
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk2_new (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg3/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg3/Q (DFF_X1)
|
||||
0.00 0.08 ^ out2 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
15.00 15.00 clock clk2_new (rise edge)
|
||||
0.00 15.00 clock network delay (ideal)
|
||||
0.00 15.00 clock reconvergence pessimism
|
||||
-2.50 12.50 output external delay
|
||||
12.50 data required time
|
||||
---------------------------------------------------------
|
||||
12.50 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
12.42 slack (MET)
|
||||
|
||||
|
||||
PASS: read_sdc + report
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,238 @@
|
||||
# Test remove_clock, disable/remove clock gating check, capacitance limits
|
||||
# on cell/port/pin targets, and set_load with -corner variants.
|
||||
# Targets:
|
||||
# Sdc.cc: removeClock (full cascade: deleteExceptionsReferencing,
|
||||
# deleteInputDelaysReferencing, deleteOutputDelaysReferencing,
|
||||
# deleteClockLatenciesReferencing, deleteClockInsertionsReferencing,
|
||||
# deleteInterClockUncertaintiesReferencing, deleteLatchBorrowLimitsReferencing,
|
||||
# deleteMinPulseWidthReferencing, deleteMasterClkRefs, clockGroupsDeleteClkRefs),
|
||||
# disableClockGatingCheck(Instance), disableClockGatingCheck(Pin),
|
||||
# removeDisableClockGatingCheck(Instance), removeDisableClockGatingCheck(Pin),
|
||||
# isDisableClockGatingCheck(Instance), isDisableClockGatingCheck(Pin),
|
||||
# setCapacitanceLimit(Cell/Port/Pin), capacitanceLimit(Port/Pin),
|
||||
# isLeafPinClock, portExtCap (various overloads),
|
||||
# hasPortExtCap, portExtFanout, ensurePortExtPinCap
|
||||
# WriteSdc.cc: writePortLoads, writePortExtCap, writeClockGatingCheck,
|
||||
# writeMinPulseWidths, writeInterClockUncertainty
|
||||
# Clock.cc: removeClock triggers clock deletion and re-creation
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
############################################################
|
||||
# Phase 1: Build full constraint environment referencing clocks
|
||||
############################################################
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 -waveform {0 10} [get_ports clk2]
|
||||
create_clock -name vclk -period 5
|
||||
puts "PASS: clocks created"
|
||||
|
||||
# Generated clocks referencing master clocks
|
||||
create_generated_clock -name gclk1 -source [get_ports clk1] -divide_by 2 [get_pins reg1/Q]
|
||||
create_generated_clock -name gclk2 -source [get_ports clk2] -multiply_by 3 [get_pins reg3/Q]
|
||||
puts "PASS: generated clocks"
|
||||
|
||||
# IO delays referencing clk1 and clk2
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 2.5 [get_ports in2]
|
||||
set_input_delay -clock clk2 1.8 [get_ports in3]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 3.5 [get_ports out2]
|
||||
puts "PASS: IO delays"
|
||||
|
||||
# Clock latency referencing clk1
|
||||
set_clock_latency -source 0.5 [get_clocks clk1]
|
||||
set_clock_latency -source -early 0.3 [get_clocks clk1]
|
||||
set_clock_latency -source -late 0.6 [get_clocks clk1]
|
||||
set_clock_latency 0.2 [get_clocks clk2]
|
||||
puts "PASS: clock latency"
|
||||
|
||||
# Clock insertion
|
||||
set_clock_latency -source -rise -early 0.25 [get_clocks clk1]
|
||||
set_clock_latency -source -fall -late 0.55 [get_clocks clk1]
|
||||
puts "PASS: clock insertion"
|
||||
|
||||
# Inter-clock uncertainty referencing clk1-clk2
|
||||
set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -setup 0.3
|
||||
set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -hold 0.15
|
||||
set_clock_uncertainty -from [get_clocks clk2] -to [get_clocks clk1] -setup 0.28
|
||||
set_clock_uncertainty -from [get_clocks clk2] -to [get_clocks clk1] -hold 0.12
|
||||
set_clock_uncertainty -setup 0.2 [get_clocks clk1]
|
||||
set_clock_uncertainty -hold 0.1 [get_clocks clk1]
|
||||
puts "PASS: clock uncertainty"
|
||||
|
||||
# Latch borrow limits referencing clk1
|
||||
set_max_time_borrow 2.0 [get_clocks clk1]
|
||||
set_max_time_borrow 1.5 [get_clocks clk2]
|
||||
set_max_time_borrow 1.0 [get_pins reg1/D]
|
||||
puts "PASS: latch borrow"
|
||||
|
||||
# Min pulse width referencing clk1
|
||||
set_min_pulse_width -high 0.6 [get_clocks clk1]
|
||||
set_min_pulse_width -low 0.4 [get_clocks clk1]
|
||||
set_min_pulse_width 0.8 [get_clocks clk2]
|
||||
puts "PASS: min pulse width"
|
||||
|
||||
# Clock groups referencing clk1
|
||||
set_clock_groups -asynchronous -name async1 \
|
||||
-group {clk1 gclk1} \
|
||||
-group {clk2 gclk2}
|
||||
puts "PASS: clock groups"
|
||||
|
||||
# Exception paths referencing clk1
|
||||
set_false_path -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
set_multicycle_path -setup 2 -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: exception paths"
|
||||
|
||||
# Write before deletion
|
||||
set sdc1 [make_result_file sdc_rmclk1.sdc]
|
||||
write_sdc -no_timestamp $sdc1
|
||||
puts "PASS: write_sdc phase 1"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report phase 1"
|
||||
|
||||
############################################################
|
||||
# Phase 2: Clock gating check - disable on instance and pin
|
||||
############################################################
|
||||
|
||||
# Design-level clock gating check
|
||||
set_clock_gating_check -setup 0.5 [current_design]
|
||||
set_clock_gating_check -hold 0.3 [current_design]
|
||||
puts "PASS: clock_gating_check design"
|
||||
|
||||
# Clock-level
|
||||
set_clock_gating_check -setup 0.4 [get_clocks clk1]
|
||||
set_clock_gating_check -hold 0.2 [get_clocks clk1]
|
||||
puts "PASS: clock_gating_check clock"
|
||||
|
||||
# Instance-level
|
||||
catch {
|
||||
set_clock_gating_check -setup 0.3 [get_cells reg1]
|
||||
set_clock_gating_check -hold 0.1 [get_cells reg1]
|
||||
puts "PASS: clock_gating_check instance"
|
||||
}
|
||||
|
||||
# Pin-level
|
||||
catch {
|
||||
set_clock_gating_check -setup 0.25 [get_pins reg1/CK]
|
||||
set_clock_gating_check -hold 0.08 [get_pins reg1/CK]
|
||||
puts "PASS: clock_gating_check pin"
|
||||
}
|
||||
|
||||
# Write with clock gating
|
||||
set sdc2 [make_result_file sdc_rmclk2.sdc]
|
||||
write_sdc -no_timestamp $sdc2
|
||||
puts "PASS: write_sdc with clock gating"
|
||||
|
||||
############################################################
|
||||
# Phase 3: Capacitance limits on cell, port, pin
|
||||
############################################################
|
||||
|
||||
# Port capacitance limit
|
||||
set_max_capacitance 0.15 [get_ports out1]
|
||||
set_max_capacitance 0.20 [get_ports out2]
|
||||
puts "PASS: max_capacitance ports"
|
||||
|
||||
catch {
|
||||
set_min_capacitance 0.01 [get_ports out1]
|
||||
puts "PASS: min_capacitance port"
|
||||
}
|
||||
|
||||
# Pin capacitance limit
|
||||
catch {
|
||||
set_max_capacitance 0.10 [get_pins reg1/D]
|
||||
puts "PASS: max_capacitance pin"
|
||||
}
|
||||
|
||||
# Cell capacitance limit (via design)
|
||||
set_max_capacitance 0.25 [current_design]
|
||||
puts "PASS: max_capacitance design"
|
||||
|
||||
############################################################
|
||||
# Phase 4: set_load with various options for portExtCap
|
||||
############################################################
|
||||
|
||||
# Basic pin load
|
||||
set_load -pin_load 0.05 [get_ports out1]
|
||||
set_load -wire_load 0.02 [get_ports out1]
|
||||
puts "PASS: set_load pin and wire"
|
||||
|
||||
# Rise/fall loads
|
||||
set_load -pin_load -rise 0.04 [get_ports out2]
|
||||
set_load -pin_load -fall 0.045 [get_ports out2]
|
||||
puts "PASS: set_load rise/fall"
|
||||
|
||||
# Min/max loads
|
||||
set_load -min 0.01 [get_ports out1]
|
||||
set_load -max 0.06 [get_ports out1]
|
||||
puts "PASS: set_load min/max"
|
||||
|
||||
# Port fanout
|
||||
set_port_fanout_number 4 [get_ports out1]
|
||||
set_port_fanout_number 8 [get_ports out2]
|
||||
puts "PASS: port fanout"
|
||||
|
||||
# Write with loads
|
||||
set sdc3 [make_result_file sdc_rmclk3.sdc]
|
||||
write_sdc -no_timestamp $sdc3
|
||||
puts "PASS: write_sdc with loads"
|
||||
|
||||
set sdc3c [make_result_file sdc_rmclk3_compat.sdc]
|
||||
write_sdc -no_timestamp -compatible $sdc3c
|
||||
puts "PASS: write_sdc compatible with loads"
|
||||
|
||||
############################################################
|
||||
# Phase 5: Delete clocks (exercises removeClock cascade)
|
||||
############################################################
|
||||
|
||||
# Delete generated clocks first (dependent on masters)
|
||||
delete_generated_clock [get_clocks gclk1]
|
||||
puts "PASS: delete gclk1"
|
||||
|
||||
delete_generated_clock [get_clocks gclk2]
|
||||
puts "PASS: delete gclk2"
|
||||
|
||||
# Delete virtual clock
|
||||
delete_clock [get_clocks vclk]
|
||||
puts "PASS: delete vclk"
|
||||
|
||||
# Delete master clock clk2 (removes IO delays, uncertainty, etc.)
|
||||
delete_clock [get_clocks clk2]
|
||||
puts "PASS: delete clk2"
|
||||
|
||||
report_clock_properties
|
||||
puts "PASS: report after clock deletions"
|
||||
|
||||
# Write after deletions - exercises writing with reduced constraints
|
||||
set sdc4 [make_result_file sdc_rmclk4.sdc]
|
||||
write_sdc -no_timestamp $sdc4
|
||||
puts "PASS: write_sdc after clock deletions"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report after deletions"
|
||||
|
||||
############################################################
|
||||
# Phase 6: Re-create clocks and verify
|
||||
############################################################
|
||||
create_clock -name clk2_new -period 15 [get_ports clk2]
|
||||
set_input_delay -clock clk2_new 1.5 [get_ports in3]
|
||||
set_output_delay -clock clk2_new 2.5 [get_ports out2]
|
||||
puts "PASS: recreated clk2"
|
||||
|
||||
set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2_new] -setup 0.25
|
||||
puts "PASS: new inter-clock uncertainty"
|
||||
|
||||
# Write final
|
||||
set sdc5 [make_result_file sdc_rmclk5.sdc]
|
||||
write_sdc -no_timestamp $sdc5
|
||||
puts "PASS: write_sdc final"
|
||||
|
||||
# Read back and verify
|
||||
read_sdc $sdc5
|
||||
report_checks
|
||||
puts "PASS: read_sdc + report"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,318 @@
|
||||
PASS: setup
|
||||
Warning: sdc_sense_unset_override.tcl line 1, set_clock_sense is deprecated as of SDC 2.1. Use set_sense -type clock.
|
||||
PASS: clock_sense positive with clock
|
||||
Warning: sdc_sense_unset_override.tcl line 1, set_clock_sense is deprecated as of SDC 2.1. Use set_sense -type clock.
|
||||
PASS: clock_sense negative with clock
|
||||
Warning: sdc_sense_unset_override.tcl line 1, set_clock_sense is deprecated as of SDC 2.1. Use set_sense -type clock.
|
||||
PASS: clock_sense stop with clock
|
||||
Warning: sdc_sense_unset_override.tcl line 1, set_clock_sense is deprecated as of SDC 2.1. Use set_sense -type clock.
|
||||
PASS: clock_sense positive without clock
|
||||
Warning: sdc_sense_unset_override.tcl line 1, set_clock_sense is deprecated as of SDC 2.1. Use set_sense -type clock.
|
||||
PASS: clock_sense negative without clock
|
||||
PASS: write_sdc with clock senses
|
||||
Warning: sdc_sense_unset_override.tcl line 1, set_clock_sense is deprecated as of SDC 2.1. Use set_sense -type clock.
|
||||
PASS: overwrite clock_sense positive with negative
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: report after sense changes
|
||||
PASS: clock uncertainty
|
||||
PASS: inter-clock uncertainty
|
||||
PASS: write_sdc with uncertainties
|
||||
PASS: unset clock uncertainty
|
||||
PASS: unset inter-clock uncertainty
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 10.08 v reg1/Q (DFF_X1)
|
||||
0.00 10.08 v reg3/D (DFF_X1)
|
||||
10.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
-0.30 19.70 clock uncertainty
|
||||
0.00 19.70 clock reconvergence pessimism
|
||||
19.70 ^ reg3/CK (DFF_X1)
|
||||
-0.04 19.66 library setup time
|
||||
19.66 data required time
|
||||
---------------------------------------------------------
|
||||
19.66 data required time
|
||||
-10.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.58 slack (MET)
|
||||
|
||||
|
||||
PASS: report after uncertainty unset
|
||||
PASS: clock insertion
|
||||
PASS: unset clock insertion
|
||||
PASS: clock_groups asynchronous
|
||||
PASS: unset clock_groups async
|
||||
PASS: clock_groups logically_exclusive
|
||||
PASS: unset clock_groups logically_exclusive
|
||||
PASS: clock_groups physically_exclusive
|
||||
PASS: write_sdc with clock groups
|
||||
PASS: unset clock_groups physically_exclusive
|
||||
PASS: max_delay
|
||||
PASS: false_path overrides max_delay
|
||||
PASS: false_path with rise_to and fall_to
|
||||
PASS: false_path with rise_from and fall_from
|
||||
PASS: multicycle setup + hold same path
|
||||
PASS: multicycle between clocks
|
||||
PASS: max/min delay with through
|
||||
PASS: group_path multi from/to
|
||||
PASS: write_sdc with all exceptions
|
||||
PASS: write_sdc compatible
|
||||
PASS: unset false_path
|
||||
PASS: unset rise/fall false_paths
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: grp_multi
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in3 (input port clocked by clk2)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk2 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
2.00 2.00 v input external delay
|
||||
0.00 2.00 v in3 (in)
|
||||
0.05 2.05 v or1/ZN (OR2_X1)
|
||||
0.03 2.07 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 2.07 ^ reg2/D (DFF_X1)
|
||||
2.07 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
-0.32 9.68 inter-clock uncertainty
|
||||
0.00 9.68 clock reconvergence pessimism
|
||||
9.68 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.65 library setup time
|
||||
9.65 data required time
|
||||
---------------------------------------------------------
|
||||
9.65 data required time
|
||||
-2.07 data arrival time
|
||||
---------------------------------------------------------
|
||||
7.57 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Endpoint: out2 (output port clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk2 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg3/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg3/Q (DFF_X1)
|
||||
0.00 0.08 ^ out2 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
-0.30 19.70 clock uncertainty
|
||||
0.00 19.70 clock reconvergence pessimism
|
||||
-3.00 16.70 output external delay
|
||||
16.70 data required time
|
||||
---------------------------------------------------------
|
||||
16.70 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
16.62 slack (MET)
|
||||
|
||||
|
||||
PASS: final report
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: grp_multi
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in3 (input port clocked by clk2)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk2 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
2.00 2.00 v input external delay
|
||||
0.00 2.00 v in3 (in)
|
||||
0.05 2.05 v or1/ZN (OR2_X1)
|
||||
0.03 2.07 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 2.07 ^ reg2/D (DFF_X1)
|
||||
2.07 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
-0.32 9.68 inter-clock uncertainty
|
||||
0.00 9.68 clock reconvergence pessimism
|
||||
9.68 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.65 library setup time
|
||||
9.65 data required time
|
||||
---------------------------------------------------------
|
||||
9.65 data required time
|
||||
-2.07 data arrival time
|
||||
---------------------------------------------------------
|
||||
7.57 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Endpoint: out2 (output port clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk2 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg3/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg3/Q (DFF_X1)
|
||||
0.00 0.08 ^ out2 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
-0.30 19.70 clock uncertainty
|
||||
0.00 19.70 clock reconvergence pessimism
|
||||
-3.00 16.70 output external delay
|
||||
16.70 data required time
|
||||
---------------------------------------------------------
|
||||
16.70 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
16.62 slack (MET)
|
||||
|
||||
|
||||
PASS: read_sdc + report
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,227 @@
|
||||
# Test clock sense variants (positive, negative, stop), unset_clock_uncertainty,
|
||||
# unset_clock_groups, exception priority and overrides.
|
||||
# Targets:
|
||||
# Sdc.cc: setClockSense (with and without clocks, positive/negative/stop),
|
||||
# clkStopPropagation, clkStopSense, removeClockSense (via unset_clock_sense),
|
||||
# setClockUncertainty, removeClockUncertainty,
|
||||
# unsetInterClockUncertainty, deleteInterClockUncertaintiesReferencing,
|
||||
# removeClockGroups, clockGroupsAreSame, clockGroupMembers,
|
||||
# setClockInsertion/removeClockInsertion,
|
||||
# makeGroupPath (multiple from/to merging)
|
||||
# WriteSdc.cc: writeClockSenses (positive/negative/stop with clocks),
|
||||
# writeClockGroups (logically_exclusive, physically_exclusive, asynchronous),
|
||||
# writeClockUncertainty, writeInterClockUncertainties,
|
||||
# writeClockInsertions, writePropagatedClkPins,
|
||||
# writeExceptions (overriding false_path with multicycle)
|
||||
# ExceptionPath.cc: FalsePath::overrides, MultiCyclePath::overrides,
|
||||
# PathDelay::overrides, intersectsPts, mergeable,
|
||||
# ExceptionFrom::intersectsPts, ExceptionTo::intersectsPts,
|
||||
# ExceptionTo with endTransition (rise/fall)
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
############################################################
|
||||
# Create clocks
|
||||
############################################################
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
create_clock -name vclk -period 5
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in2]
|
||||
set_input_delay -clock clk2 2.0 [get_ports in3]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 3.0 [get_ports out2]
|
||||
puts "PASS: setup"
|
||||
|
||||
############################################################
|
||||
# Clock sense: positive, negative, stop
|
||||
############################################################
|
||||
# Positive sense on a pin with specific clock
|
||||
set_clock_sense -positive -clocks [get_clocks clk1] [get_pins buf1/Z]
|
||||
puts "PASS: clock_sense positive with clock"
|
||||
|
||||
# Negative sense on a pin with specific clock
|
||||
set_clock_sense -negative -clocks [get_clocks clk1] [get_pins inv1/ZN]
|
||||
puts "PASS: clock_sense negative with clock"
|
||||
|
||||
# Stop sense (should prevent clock propagation)
|
||||
set_clock_sense -stop_propagation -clocks [get_clocks clk2] [get_pins or1/ZN]
|
||||
puts "PASS: clock_sense stop with clock"
|
||||
|
||||
# Clock sense without -clocks (applies to all clocks on pin)
|
||||
set_clock_sense -positive [get_pins and1/ZN]
|
||||
puts "PASS: clock_sense positive without clock"
|
||||
|
||||
# Clock sense negative without specific clock
|
||||
set_clock_sense -negative [get_pins nand1/ZN]
|
||||
puts "PASS: clock_sense negative without clock"
|
||||
|
||||
# Write to exercise writeClockSenses
|
||||
set sdc1 [make_result_file sdc_sense1.sdc]
|
||||
write_sdc -no_timestamp $sdc1
|
||||
puts "PASS: write_sdc with clock senses"
|
||||
|
||||
# Overwrite clock sense with a different sense on the same pin
|
||||
# (this exercises the hasKey path in setClockSense)
|
||||
set_clock_sense -negative -clocks [get_clocks clk1] [get_pins buf1/Z]
|
||||
puts "PASS: overwrite clock_sense positive with negative"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report after sense changes"
|
||||
|
||||
############################################################
|
||||
# Clock uncertainty: set and unset
|
||||
############################################################
|
||||
# Simple uncertainty
|
||||
set_clock_uncertainty -setup 0.2 [get_clocks clk1]
|
||||
set_clock_uncertainty -hold 0.1 [get_clocks clk1]
|
||||
set_clock_uncertainty -setup 0.3 [get_clocks clk2]
|
||||
set_clock_uncertainty -hold 0.15 [get_clocks clk2]
|
||||
puts "PASS: clock uncertainty"
|
||||
|
||||
# Inter-clock uncertainty
|
||||
set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -setup 0.35
|
||||
set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -hold 0.18
|
||||
set_clock_uncertainty -from [get_clocks clk2] -to [get_clocks clk1] -setup 0.32
|
||||
set_clock_uncertainty -from [get_clocks clk2] -to [get_clocks clk1] -hold 0.16
|
||||
puts "PASS: inter-clock uncertainty"
|
||||
|
||||
# Write before unset
|
||||
set sdc2 [make_result_file sdc_sense2.sdc]
|
||||
write_sdc -no_timestamp $sdc2
|
||||
puts "PASS: write_sdc with uncertainties"
|
||||
|
||||
# Unset simple uncertainty
|
||||
unset_clock_uncertainty -setup [get_clocks clk1]
|
||||
unset_clock_uncertainty -hold [get_clocks clk1]
|
||||
puts "PASS: unset clock uncertainty"
|
||||
|
||||
# Unset inter-clock uncertainty
|
||||
unset_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -setup
|
||||
unset_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -hold
|
||||
puts "PASS: unset inter-clock uncertainty"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report after uncertainty unset"
|
||||
|
||||
############################################################
|
||||
# Clock insertion (source latency)
|
||||
############################################################
|
||||
set_clock_latency -source -early 0.3 [get_clocks clk1]
|
||||
set_clock_latency -source -late 0.5 [get_clocks clk1]
|
||||
set_clock_latency -source -rise -early 0.25 [get_clocks clk1]
|
||||
set_clock_latency -source -fall -late 0.55 [get_clocks clk1]
|
||||
puts "PASS: clock insertion"
|
||||
|
||||
# Remove clock insertion
|
||||
unset_clock_latency -source [get_clocks clk1]
|
||||
puts "PASS: unset clock insertion"
|
||||
|
||||
############################################################
|
||||
# Clock groups: all three types
|
||||
############################################################
|
||||
# Asynchronous
|
||||
set_clock_groups -asynchronous -name async1 -group {clk1} -group {clk2}
|
||||
puts "PASS: clock_groups asynchronous"
|
||||
|
||||
# Unset clock groups
|
||||
unset_clock_groups -asynchronous -name async1
|
||||
puts "PASS: unset clock_groups async"
|
||||
|
||||
# Logically exclusive
|
||||
set_clock_groups -logically_exclusive -name logic1 -group {clk1} -group {clk2}
|
||||
puts "PASS: clock_groups logically_exclusive"
|
||||
|
||||
# Unset
|
||||
unset_clock_groups -logically_exclusive -name logic1
|
||||
puts "PASS: unset clock_groups logically_exclusive"
|
||||
|
||||
# Physically exclusive
|
||||
set_clock_groups -physically_exclusive -name phys1 -group {clk1} -group {vclk}
|
||||
puts "PASS: clock_groups physically_exclusive"
|
||||
|
||||
# Write to exercise writeClockGroups
|
||||
set sdc3 [make_result_file sdc_sense3.sdc]
|
||||
write_sdc -no_timestamp $sdc3
|
||||
puts "PASS: write_sdc with clock groups"
|
||||
|
||||
# Unset
|
||||
unset_clock_groups -physically_exclusive -name phys1
|
||||
puts "PASS: unset clock_groups physically_exclusive"
|
||||
|
||||
############################################################
|
||||
# Exception overrides: same from/to with different types
|
||||
############################################################
|
||||
|
||||
# First set a max_delay
|
||||
set_max_delay -from [get_ports in1] -to [get_ports out1] 8.0
|
||||
puts "PASS: max_delay"
|
||||
|
||||
# Then override with false_path on same from/to
|
||||
set_false_path -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: false_path overrides max_delay"
|
||||
|
||||
# False path with rise/fall on to endpoint
|
||||
set_false_path -from [get_ports in2] -rise_to [get_ports out1]
|
||||
set_false_path -from [get_ports in2] -fall_to [get_ports out1]
|
||||
puts "PASS: false_path with rise_to and fall_to"
|
||||
|
||||
# False path with rise/fall from
|
||||
set_false_path -rise_from [get_ports in3] -to [get_ports out2]
|
||||
set_false_path -fall_from [get_ports in3] -to [get_ports out2]
|
||||
puts "PASS: false_path with rise_from and fall_from"
|
||||
|
||||
# Multicycle with setup and hold on same path
|
||||
set_multicycle_path -setup 2 -from [get_ports in1] -to [get_ports out2]
|
||||
set_multicycle_path -hold 1 -from [get_ports in1] -to [get_ports out2]
|
||||
puts "PASS: multicycle setup + hold same path"
|
||||
|
||||
# Multicycle between clocks
|
||||
set_multicycle_path -setup 3 -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
set_multicycle_path -hold 2 -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
puts "PASS: multicycle between clocks"
|
||||
|
||||
# Max/min delay with through
|
||||
set_max_delay -from [get_ports in2] -through [get_pins buf1/Z] -to [get_ports out2] 6.0
|
||||
set_min_delay -from [get_ports in2] -through [get_pins buf1/Z] -to [get_ports out2] 0.5
|
||||
puts "PASS: max/min delay with through"
|
||||
|
||||
# Group path with multiple from objects
|
||||
group_path -name grp_multi \
|
||||
-from [list [get_ports in1] [get_ports in2] [get_clocks clk1]] \
|
||||
-to [list [get_ports out1] [get_ports out2]]
|
||||
puts "PASS: group_path multi from/to"
|
||||
|
||||
# Write exceptions with all types
|
||||
set sdc4 [make_result_file sdc_sense4.sdc]
|
||||
write_sdc -no_timestamp $sdc4
|
||||
puts "PASS: write_sdc with all exceptions"
|
||||
|
||||
set sdc5 [make_result_file sdc_sense5.sdc]
|
||||
write_sdc -no_timestamp -compatible $sdc5
|
||||
puts "PASS: write_sdc compatible"
|
||||
|
||||
############################################################
|
||||
# Unset exceptions and re-report
|
||||
############################################################
|
||||
unset_path_exceptions -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: unset false_path"
|
||||
|
||||
unset_path_exceptions -from [get_ports in2] -rise_to [get_ports out1]
|
||||
unset_path_exceptions -from [get_ports in2] -fall_to [get_ports out1]
|
||||
puts "PASS: unset rise/fall false_paths"
|
||||
|
||||
report_checks
|
||||
puts "PASS: final report"
|
||||
|
||||
############################################################
|
||||
# Read back SDC
|
||||
############################################################
|
||||
read_sdc $sdc4
|
||||
report_checks
|
||||
puts "PASS: read_sdc + report"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,8 @@
|
||||
module sdc_test1 (clk, in1, out1);
|
||||
input clk, in1;
|
||||
output out1;
|
||||
wire n1;
|
||||
|
||||
BUF_X1 buf1 (.A(in1), .Z(n1));
|
||||
DFF_X1 reg1 (.D(n1), .CK(clk), .Q(out1));
|
||||
endmodule
|
||||
@@ -0,0 +1,16 @@
|
||||
module sdc_test2 (clk1, clk2, in1, in2, in3, out1, out2);
|
||||
input clk1, clk2, in1, in2, in3;
|
||||
output out1, out2;
|
||||
wire n1, n2, n3, n4, n5, n6, n7;
|
||||
|
||||
BUF_X1 buf1 (.A(in1), .Z(n1));
|
||||
INV_X1 inv1 (.A(in2), .ZN(n2));
|
||||
AND2_X1 and1 (.A1(n1), .A2(n2), .ZN(n3));
|
||||
OR2_X1 or1 (.A1(n1), .A2(in3), .ZN(n4));
|
||||
NAND2_X1 nand1 (.A1(n3), .A2(n4), .ZN(n5));
|
||||
NOR2_X1 nor1 (.A1(n3), .A2(n4), .ZN(n6));
|
||||
|
||||
DFF_X1 reg1 (.D(n5), .CK(clk1), .Q(n7));
|
||||
DFF_X1 reg2 (.D(n6), .CK(clk1), .Q(out1));
|
||||
DFF_X1 reg3 (.D(n7), .CK(clk2), .Q(out2));
|
||||
endmodule
|
||||
@@ -0,0 +1,46 @@
|
||||
PASS: basic setup
|
||||
PASS: sta_crpr_enabled = 1
|
||||
PASS: sta_crpr_enabled = 0
|
||||
PASS: sta_crpr_enabled re-enabled
|
||||
PASS: sta_crpr_mode = same_pin
|
||||
PASS: sta_crpr_mode = same_transition
|
||||
PASS: read sta_crpr_mode = same_transition
|
||||
PASS: sta_cond_default_arcs_enabled = 1
|
||||
PASS: sta_cond_default_arcs_enabled = 0
|
||||
PASS: read sta_cond_default_arcs_enabled = 0
|
||||
PASS: sta_gated_clock_checks_enabled = 1
|
||||
PASS: sta_gated_clock_checks_enabled = 0
|
||||
PASS: read sta_gated_clock_checks_enabled = 0
|
||||
PASS: sta_internal_bidirect_instance_paths_enabled = 1
|
||||
PASS: sta_internal_bidirect_instance_paths_enabled = 0
|
||||
PASS: read sta_internal_bidirect_instance_paths_enabled = 0
|
||||
PASS: sta_bidirect_net_paths_enabled = 1
|
||||
PASS: sta_bidirect_net_paths_enabled = 0
|
||||
PASS: read sta_bidirect_net_paths_enabled = 0
|
||||
PASS: sta_clock_through_tristate_enabled = 1
|
||||
PASS: sta_clock_through_tristate_enabled = 0
|
||||
PASS: read sta_clock_through_tristate_enabled = 0
|
||||
PASS: sta_preset_clear_arcs_enabled = 1
|
||||
PASS: sta_preset_clear_arcs_enabled = 0
|
||||
PASS: read sta_preset_clear_arcs_enabled = 0
|
||||
PASS: sta_recovery_removal_checks_enabled = 1
|
||||
PASS: sta_recovery_removal_checks_enabled = 0
|
||||
PASS: read sta_recovery_removal_checks_enabled = 0
|
||||
PASS: sta_dynamic_loop_breaking = 1
|
||||
PASS: sta_dynamic_loop_breaking = 0
|
||||
PASS: read sta_dynamic_loop_breaking = 0
|
||||
PASS: sta_input_port_default_clock = 1
|
||||
PASS: sta_input_port_default_clock = 0
|
||||
PASS: read sta_input_port_default_clock = 0
|
||||
PASS: sta_propagate_all_clocks = 1
|
||||
PASS: sta_propagate_all_clocks = 0
|
||||
PASS: read sta_propagate_all_clocks = 0
|
||||
PASS: sta_propagate_gated_clock_enable = 1
|
||||
PASS: sta_propagate_gated_clock_enable = 0
|
||||
PASS: read sta_propagate_gated_clock_enable = 0
|
||||
PASS: pocv test completed (may skip if SSTA not compiled)
|
||||
PASS: sta_report_default_digits = 4
|
||||
PASS: sta_report_default_digits = 2 (restored)
|
||||
No paths found.
|
||||
PASS: final report_checks
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,214 @@
|
||||
# Test STA variable settings for Variables.cc code coverage
|
||||
# Targets: Variables.cc, Sdc.cc (variable-related paths)
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
# Setup basic constraints
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
puts "PASS: basic setup"
|
||||
|
||||
############################################################
|
||||
# CRPR variables
|
||||
############################################################
|
||||
|
||||
# Enable/disable CRPR
|
||||
set ::sta_crpr_enabled 1
|
||||
puts "PASS: sta_crpr_enabled = $::sta_crpr_enabled"
|
||||
|
||||
set ::sta_crpr_enabled 0
|
||||
puts "PASS: sta_crpr_enabled = $::sta_crpr_enabled"
|
||||
|
||||
set ::sta_crpr_enabled 1
|
||||
puts "PASS: sta_crpr_enabled re-enabled"
|
||||
|
||||
# CRPR mode
|
||||
set ::sta_crpr_mode "same_pin"
|
||||
puts "PASS: sta_crpr_mode = same_pin"
|
||||
|
||||
set ::sta_crpr_mode "same_transition"
|
||||
puts "PASS: sta_crpr_mode = same_transition"
|
||||
|
||||
# Read back crpr mode
|
||||
set mode $::sta_crpr_mode
|
||||
puts "PASS: read sta_crpr_mode = $mode"
|
||||
|
||||
############################################################
|
||||
# Condition default arcs
|
||||
############################################################
|
||||
|
||||
set ::sta_cond_default_arcs_enabled 1
|
||||
puts "PASS: sta_cond_default_arcs_enabled = 1"
|
||||
|
||||
set ::sta_cond_default_arcs_enabled 0
|
||||
puts "PASS: sta_cond_default_arcs_enabled = 0"
|
||||
|
||||
# Read back
|
||||
set val $::sta_cond_default_arcs_enabled
|
||||
puts "PASS: read sta_cond_default_arcs_enabled = $val"
|
||||
|
||||
############################################################
|
||||
# Gated clock checks
|
||||
############################################################
|
||||
|
||||
set ::sta_gated_clock_checks_enabled 1
|
||||
puts "PASS: sta_gated_clock_checks_enabled = 1"
|
||||
|
||||
set ::sta_gated_clock_checks_enabled 0
|
||||
puts "PASS: sta_gated_clock_checks_enabled = 0"
|
||||
|
||||
set val $::sta_gated_clock_checks_enabled
|
||||
puts "PASS: read sta_gated_clock_checks_enabled = $val"
|
||||
|
||||
############################################################
|
||||
# Bidirectional instance paths
|
||||
############################################################
|
||||
|
||||
set ::sta_internal_bidirect_instance_paths_enabled 1
|
||||
puts "PASS: sta_internal_bidirect_instance_paths_enabled = 1"
|
||||
|
||||
set ::sta_internal_bidirect_instance_paths_enabled 0
|
||||
puts "PASS: sta_internal_bidirect_instance_paths_enabled = 0"
|
||||
|
||||
set val $::sta_internal_bidirect_instance_paths_enabled
|
||||
puts "PASS: read sta_internal_bidirect_instance_paths_enabled = $val"
|
||||
|
||||
############################################################
|
||||
# Bidirectional net paths
|
||||
############################################################
|
||||
|
||||
set ::sta_bidirect_net_paths_enabled 1
|
||||
puts "PASS: sta_bidirect_net_paths_enabled = 1"
|
||||
|
||||
set ::sta_bidirect_net_paths_enabled 0
|
||||
puts "PASS: sta_bidirect_net_paths_enabled = 0"
|
||||
|
||||
set val $::sta_bidirect_net_paths_enabled
|
||||
puts "PASS: read sta_bidirect_net_paths_enabled = $val"
|
||||
|
||||
############################################################
|
||||
# Clock through tristate
|
||||
############################################################
|
||||
|
||||
set ::sta_clock_through_tristate_enabled 1
|
||||
puts "PASS: sta_clock_through_tristate_enabled = 1"
|
||||
|
||||
set ::sta_clock_through_tristate_enabled 0
|
||||
puts "PASS: sta_clock_through_tristate_enabled = 0"
|
||||
|
||||
set val $::sta_clock_through_tristate_enabled
|
||||
puts "PASS: read sta_clock_through_tristate_enabled = $val"
|
||||
|
||||
############################################################
|
||||
# Preset/clear arcs
|
||||
############################################################
|
||||
|
||||
set ::sta_preset_clear_arcs_enabled 1
|
||||
puts "PASS: sta_preset_clear_arcs_enabled = 1"
|
||||
|
||||
set ::sta_preset_clear_arcs_enabled 0
|
||||
puts "PASS: sta_preset_clear_arcs_enabled = 0"
|
||||
|
||||
set val $::sta_preset_clear_arcs_enabled
|
||||
puts "PASS: read sta_preset_clear_arcs_enabled = $val"
|
||||
|
||||
############################################################
|
||||
# Recovery/removal checks
|
||||
############################################################
|
||||
|
||||
set ::sta_recovery_removal_checks_enabled 1
|
||||
puts "PASS: sta_recovery_removal_checks_enabled = 1"
|
||||
|
||||
set ::sta_recovery_removal_checks_enabled 0
|
||||
puts "PASS: sta_recovery_removal_checks_enabled = 0"
|
||||
|
||||
set val $::sta_recovery_removal_checks_enabled
|
||||
puts "PASS: read sta_recovery_removal_checks_enabled = $val"
|
||||
|
||||
############################################################
|
||||
# Dynamic loop breaking
|
||||
############################################################
|
||||
|
||||
set ::sta_dynamic_loop_breaking 1
|
||||
puts "PASS: sta_dynamic_loop_breaking = 1"
|
||||
|
||||
set ::sta_dynamic_loop_breaking 0
|
||||
puts "PASS: sta_dynamic_loop_breaking = 0"
|
||||
|
||||
set val $::sta_dynamic_loop_breaking
|
||||
puts "PASS: read sta_dynamic_loop_breaking = $val"
|
||||
|
||||
############################################################
|
||||
# Input port default clock
|
||||
############################################################
|
||||
|
||||
set ::sta_input_port_default_clock 1
|
||||
puts "PASS: sta_input_port_default_clock = 1"
|
||||
|
||||
set ::sta_input_port_default_clock 0
|
||||
puts "PASS: sta_input_port_default_clock = 0"
|
||||
|
||||
set val $::sta_input_port_default_clock
|
||||
puts "PASS: read sta_input_port_default_clock = $val"
|
||||
|
||||
############################################################
|
||||
# Propagate all clocks
|
||||
############################################################
|
||||
|
||||
set ::sta_propagate_all_clocks 1
|
||||
puts "PASS: sta_propagate_all_clocks = 1"
|
||||
|
||||
set ::sta_propagate_all_clocks 0
|
||||
puts "PASS: sta_propagate_all_clocks = 0"
|
||||
|
||||
set val $::sta_propagate_all_clocks
|
||||
puts "PASS: read sta_propagate_all_clocks = $val"
|
||||
|
||||
############################################################
|
||||
# Propagate gated clock enable
|
||||
############################################################
|
||||
|
||||
set ::sta_propagate_gated_clock_enable 1
|
||||
puts "PASS: sta_propagate_gated_clock_enable = 1"
|
||||
|
||||
set ::sta_propagate_gated_clock_enable 0
|
||||
puts "PASS: sta_propagate_gated_clock_enable = 0"
|
||||
|
||||
set val $::sta_propagate_gated_clock_enable
|
||||
puts "PASS: read sta_propagate_gated_clock_enable = $val"
|
||||
|
||||
############################################################
|
||||
# POCV enabled (may require SSTA compilation, use catch)
|
||||
############################################################
|
||||
|
||||
catch {
|
||||
set ::sta_pocv_enabled 1
|
||||
puts "PASS: sta_pocv_enabled = 1"
|
||||
set ::sta_pocv_enabled 0
|
||||
puts "PASS: sta_pocv_enabled = 0"
|
||||
set val $::sta_pocv_enabled
|
||||
puts "PASS: read sta_pocv_enabled = $val"
|
||||
}
|
||||
puts "PASS: pocv test completed (may skip if SSTA not compiled)"
|
||||
|
||||
############################################################
|
||||
# Report default digits
|
||||
############################################################
|
||||
|
||||
set ::sta_report_default_digits 4
|
||||
puts "PASS: sta_report_default_digits = 4"
|
||||
|
||||
set ::sta_report_default_digits 2
|
||||
puts "PASS: sta_report_default_digits = 2 (restored)"
|
||||
|
||||
############################################################
|
||||
# Final report to verify everything still works
|
||||
############################################################
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: final report_checks"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,113 @@
|
||||
PASS: create_clocks
|
||||
PASS: generated clocks
|
||||
PASS: set_propagated_clock
|
||||
PASS: clock latency
|
||||
PASS: clock uncertainty
|
||||
PASS: clock transition
|
||||
PASS: input delays
|
||||
PASS: output delays
|
||||
PASS: driving cells
|
||||
PASS: set_drive
|
||||
PASS: set_load
|
||||
PASS: input transition
|
||||
PASS: design limits
|
||||
PASS: false paths
|
||||
PASS: multicycle paths
|
||||
PASS: max/min delay
|
||||
PASS: group paths
|
||||
PASS: clock groups
|
||||
Warning: sdc_write_comprehensive.tcl line 1, set_clock_sense is deprecated as of SDC 2.1. Use set_sense -type clock.
|
||||
PASS: clock sense
|
||||
PASS: case analysis
|
||||
PASS: operating conditions
|
||||
PASS: wire load
|
||||
PASS: timing derate
|
||||
PASS: disable timing
|
||||
PASS: min pulse width
|
||||
PASS: port fanout number
|
||||
PASS: resistance
|
||||
PASS: set_max_area
|
||||
PASS: write_sdc basic
|
||||
PASS: write_sdc -digits 6
|
||||
PASS: read_sdc
|
||||
Warning: generated clock gen_div2 pin clk1 is in the fanout of multiple clocks.
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: group_clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.60 0.60 clock network delay (propagated)
|
||||
0.00 0.60 ^ reg2/CK (DFF_X1)
|
||||
0.09 0.69 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.69 ^ out1 (out)
|
||||
0.69 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.50 10.50 clock network delay (propagated)
|
||||
-0.20 10.30 clock uncertainty
|
||||
0.00 10.30 clock reconvergence pessimism
|
||||
-3.00 7.30 output external delay
|
||||
7.30 data required time
|
||||
---------------------------------------------------------
|
||||
7.30 data required time
|
||||
-0.69 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.61 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1_fast)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
5.00 5.00 clock clk1_fast (rise edge)
|
||||
0.00 5.00 clock network delay (ideal)
|
||||
0.00 5.00 ^ reg2/CK (DFF_X1)
|
||||
0.09 5.09 ^ reg2/Q (DFF_X1)
|
||||
0.00 5.09 ^ out1 (out)
|
||||
5.09 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.50 10.50 clock network delay (propagated)
|
||||
-0.20 10.30 clock uncertainty
|
||||
0.00 10.30 clock reconvergence pessimism
|
||||
-3.00 7.30 output external delay
|
||||
7.30 data required time
|
||||
---------------------------------------------------------
|
||||
7.30 data required time
|
||||
-5.09 data arrival time
|
||||
---------------------------------------------------------
|
||||
2.21 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3/Q (clock source 'gen_mul3')
|
||||
Endpoint: out2 (output port clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
13.33 13.33 clock gen_mul3 (rise edge)
|
||||
0.00 13.33 clock network delay
|
||||
13.33 ^ out2 (out)
|
||||
13.33 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.20 20.20 clock network delay (ideal)
|
||||
0.00 20.20 clock reconvergence pessimism
|
||||
-3.50 16.70 output external delay
|
||||
16.70 data required time
|
||||
---------------------------------------------------------
|
||||
16.70 data required time
|
||||
-13.33 data arrival time
|
||||
---------------------------------------------------------
|
||||
3.37 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks after read_sdc
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,238 @@
|
||||
# Test comprehensive write_sdc for WriteSdc.cc code coverage
|
||||
# Also exercises many Sdc.cc, Clock.cc, ExceptionPath.cc paths
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
############################################################
|
||||
# Create multiple clocks with various options
|
||||
############################################################
|
||||
|
||||
# Basic clocks
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 -waveform {0 10} [get_ports clk2]
|
||||
create_clock -name vclk -period 5
|
||||
create_clock -name clk1_fast -period 5 -add [get_ports clk1]
|
||||
puts "PASS: create_clocks"
|
||||
|
||||
# Generated clock
|
||||
create_generated_clock -name gen_div2 -source [get_ports clk1] -divide_by 2 [get_pins reg1/Q]
|
||||
create_generated_clock -name gen_mul3 -source [get_ports clk2] -multiply_by 3 [get_pins reg3/Q]
|
||||
puts "PASS: generated clocks"
|
||||
|
||||
# Propagated clock
|
||||
set_propagated_clock [get_clocks clk1]
|
||||
puts "PASS: set_propagated_clock"
|
||||
|
||||
############################################################
|
||||
# Clock constraints
|
||||
############################################################
|
||||
|
||||
# Clock latency (source and network)
|
||||
set_clock_latency -source 0.5 [get_clocks clk1]
|
||||
set_clock_latency -source -rise -max 0.6 [get_clocks clk1]
|
||||
set_clock_latency -source -fall -min 0.3 [get_clocks clk1]
|
||||
set_clock_latency 0.2 [get_clocks clk2]
|
||||
set_clock_latency -rise -max 0.4 [get_clocks clk2]
|
||||
set_clock_latency -fall -min 0.1 [get_clocks clk2]
|
||||
puts "PASS: clock latency"
|
||||
|
||||
# Clock uncertainty (simple and inter-clock)
|
||||
set_clock_uncertainty -setup 0.2 [get_clocks clk1]
|
||||
set_clock_uncertainty -hold 0.1 [get_clocks clk1]
|
||||
set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -setup 0.3
|
||||
set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -hold 0.15
|
||||
puts "PASS: clock uncertainty"
|
||||
|
||||
# Clock transition
|
||||
set_clock_transition -rise -max 0.15 [get_clocks clk1]
|
||||
set_clock_transition -fall -min 0.08 [get_clocks clk1]
|
||||
set_clock_transition 0.1 [get_clocks clk2]
|
||||
puts "PASS: clock transition"
|
||||
|
||||
############################################################
|
||||
# IO constraints
|
||||
############################################################
|
||||
|
||||
# Input delays with various options
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 -rise -max 2.5 [get_ports in2]
|
||||
set_input_delay -clock clk1 -fall -min 1.0 [get_ports in2]
|
||||
set_input_delay -clock clk2 1.8 [get_ports in3]
|
||||
set_input_delay -clock clk1 -clock_fall 1.5 [get_ports in3] -add_delay
|
||||
puts "PASS: input delays"
|
||||
|
||||
# Output delays with various options
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 -rise -max 3.5 [get_ports out2]
|
||||
set_output_delay -clock clk2 -fall -min 1.5 [get_ports out2] -add_delay
|
||||
puts "PASS: output delays"
|
||||
|
||||
############################################################
|
||||
# Driving cell and load
|
||||
############################################################
|
||||
|
||||
set_driving_cell -lib_cell BUF_X1 [get_ports in1]
|
||||
set_driving_cell -lib_cell INV_X1 -pin ZN [get_ports in2]
|
||||
set_driving_cell -lib_cell BUF_X4 [get_ports in3]
|
||||
puts "PASS: driving cells"
|
||||
|
||||
# set_drive
|
||||
set_drive 100 [get_ports in1]
|
||||
puts "PASS: set_drive"
|
||||
|
||||
set_load 0.05 [get_ports out1]
|
||||
set_load -pin_load 0.03 [get_ports out2]
|
||||
puts "PASS: set_load"
|
||||
|
||||
# Input transition
|
||||
set_input_transition 0.15 [get_ports in1]
|
||||
set_input_transition -rise -max 0.12 [get_ports in2]
|
||||
set_input_transition -fall -min 0.08 [get_ports in2]
|
||||
puts "PASS: input transition"
|
||||
|
||||
############################################################
|
||||
# Design limits
|
||||
############################################################
|
||||
|
||||
set_max_transition 0.5 [current_design]
|
||||
set_max_capacitance 0.2 [current_design]
|
||||
set_max_fanout 20 [current_design]
|
||||
set_max_transition 0.3 [get_ports out1]
|
||||
set_max_capacitance 0.1 [get_ports out1]
|
||||
set_max_transition -clock_path 0.2 [get_clocks clk1]
|
||||
set_max_transition -data_path 0.4 [get_clocks clk1]
|
||||
puts "PASS: design limits"
|
||||
|
||||
############################################################
|
||||
# Exception paths
|
||||
############################################################
|
||||
|
||||
# False path
|
||||
set_false_path -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
set_false_path -from [get_ports in1] -through [get_pins and1/ZN] -to [get_ports out1]
|
||||
set_false_path -rise_from [get_ports in3] -fall_to [get_ports out2]
|
||||
puts "PASS: false paths"
|
||||
|
||||
# Multicycle path
|
||||
set_multicycle_path -setup 2 -from [get_ports in1] -to [get_ports out1]
|
||||
set_multicycle_path -hold 1 -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: multicycle paths"
|
||||
|
||||
# Max/min delay
|
||||
set_max_delay -from [get_ports in2] -to [get_ports out1] 8.0
|
||||
set_min_delay -from [get_ports in2] -to [get_ports out1] 1.0
|
||||
puts "PASS: max/min delay"
|
||||
|
||||
# Group path
|
||||
group_path -name group_clk1 -from [get_clocks clk1]
|
||||
group_path -name group_io -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: group paths"
|
||||
|
||||
############################################################
|
||||
# Clock groups
|
||||
############################################################
|
||||
|
||||
set_clock_groups -asynchronous -group {clk1 clk1_fast} -group {clk2}
|
||||
puts "PASS: clock groups"
|
||||
|
||||
############################################################
|
||||
# Clock sense
|
||||
############################################################
|
||||
|
||||
set_clock_sense -positive -clocks [get_clocks clk1] [get_pins buf1/Z]
|
||||
puts "PASS: clock sense"
|
||||
|
||||
############################################################
|
||||
# Case analysis and logic values
|
||||
############################################################
|
||||
|
||||
set_case_analysis 0 [get_ports in3]
|
||||
puts "PASS: case analysis"
|
||||
|
||||
############################################################
|
||||
# Operating conditions
|
||||
############################################################
|
||||
|
||||
set_operating_conditions typical
|
||||
puts "PASS: operating conditions"
|
||||
|
||||
############################################################
|
||||
# Wire load
|
||||
############################################################
|
||||
|
||||
set_wire_load_model -name "5K_hvratio_1_1"
|
||||
set_wire_load_mode enclosed
|
||||
puts "PASS: wire load"
|
||||
|
||||
############################################################
|
||||
# Timing derate
|
||||
############################################################
|
||||
|
||||
set_timing_derate -early 0.95
|
||||
set_timing_derate -late 1.05
|
||||
puts "PASS: timing derate"
|
||||
|
||||
############################################################
|
||||
# Disable timing
|
||||
############################################################
|
||||
|
||||
set_disable_timing [get_cells buf1]
|
||||
set_disable_timing [get_lib_cells NangateOpenCellLibrary/INV_X1] -from A -to ZN
|
||||
puts "PASS: disable timing"
|
||||
|
||||
############################################################
|
||||
# Min pulse width
|
||||
############################################################
|
||||
|
||||
set_min_pulse_width 1.0 [get_clocks clk1]
|
||||
puts "PASS: min pulse width"
|
||||
|
||||
############################################################
|
||||
# Port external pin cap
|
||||
############################################################
|
||||
|
||||
set_port_fanout_number 4 [get_ports out1]
|
||||
puts "PASS: port fanout number"
|
||||
|
||||
############################################################
|
||||
# Resistance
|
||||
############################################################
|
||||
|
||||
set_resistance -min 10.0 [get_nets n1]
|
||||
set_resistance -max 20.0 [get_nets n1]
|
||||
puts "PASS: resistance"
|
||||
|
||||
############################################################
|
||||
# set_max_area
|
||||
############################################################
|
||||
|
||||
set_max_area 100.0
|
||||
puts "PASS: set_max_area"
|
||||
|
||||
############################################################
|
||||
# Write SDC with various options
|
||||
############################################################
|
||||
|
||||
set sdc_file1 [make_result_file sdc_write_comprehensive1.sdc]
|
||||
write_sdc -no_timestamp $sdc_file1
|
||||
puts "PASS: write_sdc basic"
|
||||
|
||||
set sdc_file2 [make_result_file sdc_write_comprehensive2.sdc]
|
||||
write_sdc -no_timestamp -digits 6 $sdc_file2
|
||||
puts "PASS: write_sdc -digits 6"
|
||||
|
||||
############################################################
|
||||
# Read back SDC
|
||||
############################################################
|
||||
|
||||
# Read the SDC file (re-applying constraints)
|
||||
read_sdc $sdc_file1
|
||||
puts "PASS: read_sdc"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report_checks after read_sdc"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,210 @@
|
||||
PASS: setup
|
||||
PASS: disable ports
|
||||
PASS: disable instances
|
||||
PASS: disable instance from/to
|
||||
PASS: disable lib cells
|
||||
PASS: disable pin
|
||||
PASS: write_sdc with disables
|
||||
PASS: unset all disables
|
||||
PASS: clock_groups async
|
||||
PASS: write with async groups
|
||||
PASS: unset async
|
||||
PASS: clock_groups logically_exclusive
|
||||
PASS: write with logically_exclusive
|
||||
PASS: unset logically_exclusive
|
||||
PASS: clock_groups physically_exclusive
|
||||
PASS: write with physically_exclusive
|
||||
PASS: unset physically_exclusive
|
||||
PASS: group paths
|
||||
PASS: group_path with weight
|
||||
PASS: group_path with multiple through
|
||||
PASS: driving cells
|
||||
PASS: drive resistances
|
||||
PASS: input transitions
|
||||
PASS: inter-clock uncertainty
|
||||
PASS: min_pulse_width global
|
||||
PASS: min_pulse_width clock high/low
|
||||
PASS: min_pulse_width clock same
|
||||
PASS: min_pulse_width pin
|
||||
PASS: min_pulse_width instance
|
||||
PASS: port loads
|
||||
Warning: sdc_write_disabled_groups.tcl line 1, set_clock_sense is deprecated as of SDC 2.1. Use set_sense -type clock.
|
||||
Warning: sdc_write_disabled_groups.tcl line 1, set_clock_sense is deprecated as of SDC 2.1. Use set_sense -type clock.
|
||||
PASS: clock sense
|
||||
PASS: propagated clocks
|
||||
PASS: clock insertion
|
||||
PASS: clock transitions
|
||||
PASS: false paths setup/hold only
|
||||
PASS: write_sdc comprehensive
|
||||
PASS: write_sdc compatible comprehensive
|
||||
PASS: write_sdc digits 8
|
||||
PASS: write_sdc map_hpins
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: grp_reg
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.50 0.50 clock network delay (propagated)
|
||||
0.00 0.50 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.58 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.58 ^ out1 (out)
|
||||
0.58 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.30 10.30 clock network delay (propagated)
|
||||
0.00 10.30 clock reconvergence pessimism
|
||||
-3.00 7.30 output external delay
|
||||
7.30 data required time
|
||||
---------------------------------------------------------
|
||||
7.30 data required time
|
||||
-0.58 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.72 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in3 (input port clocked by clk2)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk2 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
2.00 2.00 v input external delay
|
||||
0.00 2.00 v in3 (in)
|
||||
0.05 2.05 v or1/ZN (OR2_X1)
|
||||
0.03 2.08 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 2.08 ^ reg2/D (DFF_X1)
|
||||
2.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.30 10.30 clock network delay (propagated)
|
||||
-0.28 10.02 inter-clock uncertainty
|
||||
0.00 10.02 clock reconvergence pessimism
|
||||
10.02 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.99 library setup time
|
||||
9.99 data required time
|
||||
---------------------------------------------------------
|
||||
9.99 data required time
|
||||
-2.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
7.91 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Endpoint: out2 (output port clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk2 (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
0.00 0.00 ^ reg3/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg3/Q (DFF_X1)
|
||||
0.00 0.08 ^ out2 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
-3.00 17.00 output external delay
|
||||
17.00 data required time
|
||||
---------------------------------------------------------
|
||||
17.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
16.92 slack (MET)
|
||||
|
||||
|
||||
PASS: report checks
|
||||
PASS: read_sdc
|
||||
PASS: write_sdc roundtrip
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: grp_reg
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.50 0.50 clock network delay (propagated)
|
||||
0.00 0.50 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.58 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.58 ^ out1 (out)
|
||||
0.58 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.30 10.30 clock network delay (propagated)
|
||||
0.00 10.30 clock reconvergence pessimism
|
||||
-3.00 7.30 output external delay
|
||||
7.30 data required time
|
||||
---------------------------------------------------------
|
||||
7.30 data required time
|
||||
-0.58 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.72 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in3 (input port clocked by clk2)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk2 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
2.00 2.00 v input external delay
|
||||
0.00 2.00 v in3 (in)
|
||||
0.05 2.05 v or1/ZN (OR2_X1)
|
||||
0.03 2.08 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 2.08 ^ reg2/D (DFF_X1)
|
||||
2.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.30 10.30 clock network delay (propagated)
|
||||
-0.28 10.02 inter-clock uncertainty
|
||||
0.00 10.02 clock reconvergence pessimism
|
||||
10.02 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.99 library setup time
|
||||
9.99 data required time
|
||||
---------------------------------------------------------
|
||||
9.99 data required time
|
||||
-2.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
7.91 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Endpoint: out2 (output port clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk2 (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
0.00 0.00 ^ reg3/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg3/Q (DFF_X1)
|
||||
0.00 0.08 ^ out2 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
-3.00 17.00 output external delay
|
||||
17.00 data required time
|
||||
---------------------------------------------------------
|
||||
17.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
16.92 slack (MET)
|
||||
|
||||
|
||||
PASS: final report
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,261 @@
|
||||
# Test write_sdc paths for disabled ports, clock groups, group paths,
|
||||
# output drives, inter-clock uncertainty, and min pulse width writing.
|
||||
# Targets:
|
||||
# WriteSdc.cc: writeDisabledPorts (disabled top-level ports),
|
||||
# writeDisabledInstances (disabled instances with from/to),
|
||||
# writeFalsePaths (false_path writing with setup/hold),
|
||||
# writeExceptionThruPins/Nets/Instances,
|
||||
# writeGroupPath (named and default, with weight being ignored),
|
||||
# writeOutputDrives (set_driving_cell, set_drive),
|
||||
# writeMinPulseWidths (on design/clock/pin/instance),
|
||||
# writePortExtCap (pin/wire/fanout writing),
|
||||
# writeInterClockUncertainty (all rise/fall/setup/hold combos),
|
||||
# writeClockGroups (async/logically_excl/physically_excl),
|
||||
# writePropagatedClkPins, writeClockInsertions,
|
||||
# writeClockSenses
|
||||
# Sdc.cc: various getter functions exercised during write
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
create_clock -name vclk -period 8
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in2]
|
||||
set_input_delay -clock clk2 2.0 [get_ports in3]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 3.0 [get_ports out2]
|
||||
puts "PASS: setup"
|
||||
|
||||
############################################################
|
||||
# Disable timing on ports (exercises writeDisabledPorts)
|
||||
############################################################
|
||||
set_disable_timing [get_ports in1]
|
||||
set_disable_timing [get_ports in2]
|
||||
puts "PASS: disable ports"
|
||||
|
||||
# Disable timing on instances with from/to (exercises writeDisabledInstances)
|
||||
set_disable_timing [get_cells buf1]
|
||||
set_disable_timing [get_cells inv1]
|
||||
puts "PASS: disable instances"
|
||||
|
||||
# Disable on instance with from/to pins
|
||||
catch {
|
||||
set_disable_timing -from A -to ZN [get_cells inv1]
|
||||
puts "PASS: disable instance from/to"
|
||||
}
|
||||
|
||||
# Disable on lib cell (exercises writeDisabledCells)
|
||||
set_disable_timing [get_lib_cells NangateOpenCellLibrary/AND2_X1] -from A1 -to ZN
|
||||
set_disable_timing [get_lib_cells NangateOpenCellLibrary/OR2_X1]
|
||||
puts "PASS: disable lib cells"
|
||||
|
||||
# Disable on pins
|
||||
set_disable_timing [get_pins nand1/A1]
|
||||
puts "PASS: disable pin"
|
||||
|
||||
# Write with disables
|
||||
set sdc1 [make_result_file sdc_wdg1.sdc]
|
||||
write_sdc -no_timestamp $sdc1
|
||||
puts "PASS: write_sdc with disables"
|
||||
|
||||
# Unset disables
|
||||
unset_disable_timing [get_ports in1]
|
||||
unset_disable_timing [get_ports in2]
|
||||
unset_disable_timing [get_cells buf1]
|
||||
unset_disable_timing [get_cells inv1]
|
||||
unset_disable_timing [get_lib_cells NangateOpenCellLibrary/AND2_X1] -from A1 -to ZN
|
||||
unset_disable_timing [get_lib_cells NangateOpenCellLibrary/OR2_X1]
|
||||
unset_disable_timing [get_pins nand1/A1]
|
||||
puts "PASS: unset all disables"
|
||||
|
||||
############################################################
|
||||
# Clock groups - all three types (exercises writeClockGroups)
|
||||
############################################################
|
||||
set_clock_groups -asynchronous -name async1 -group {clk1} -group {clk2}
|
||||
puts "PASS: clock_groups async"
|
||||
|
||||
set sdc2 [make_result_file sdc_wdg2.sdc]
|
||||
write_sdc -no_timestamp $sdc2
|
||||
puts "PASS: write with async groups"
|
||||
|
||||
unset_clock_groups -asynchronous -name async1
|
||||
puts "PASS: unset async"
|
||||
|
||||
set_clock_groups -logically_exclusive -name logic1 -group {clk1} -group {clk2}
|
||||
puts "PASS: clock_groups logically_exclusive"
|
||||
|
||||
set sdc3 [make_result_file sdc_wdg3.sdc]
|
||||
write_sdc -no_timestamp $sdc3
|
||||
puts "PASS: write with logically_exclusive"
|
||||
|
||||
unset_clock_groups -logically_exclusive -name logic1
|
||||
puts "PASS: unset logically_exclusive"
|
||||
|
||||
set_clock_groups -physically_exclusive -name phys1 -group {clk1} -group {vclk}
|
||||
puts "PASS: clock_groups physically_exclusive"
|
||||
|
||||
set sdc4 [make_result_file sdc_wdg4.sdc]
|
||||
write_sdc -no_timestamp $sdc4
|
||||
puts "PASS: write with physically_exclusive"
|
||||
|
||||
unset_clock_groups -physically_exclusive -name phys1
|
||||
puts "PASS: unset physically_exclusive"
|
||||
|
||||
############################################################
|
||||
# Group paths - named and default (exercises writeGroupPath)
|
||||
############################################################
|
||||
group_path -name grp_reg -from [get_clocks clk1] -to [get_clocks clk1]
|
||||
group_path -name grp_cross -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
group_path -default -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: group paths"
|
||||
|
||||
# Group path with weight (weight is ignored but syntax is accepted)
|
||||
group_path -name grp_weighted -weight 2.0 \
|
||||
-from [get_ports in2] -to [get_ports out2]
|
||||
puts "PASS: group_path with weight"
|
||||
|
||||
# Group path with through
|
||||
group_path -name grp_thru -from [get_ports in1] \
|
||||
-through [get_pins buf1/Z] \
|
||||
-through [get_pins and1/ZN] \
|
||||
-to [get_ports out1]
|
||||
puts "PASS: group_path with multiple through"
|
||||
|
||||
############################################################
|
||||
# Output drives (exercises writeOutputDrives/writeDriveResistances)
|
||||
############################################################
|
||||
set_driving_cell -lib_cell BUF_X1 [get_ports in1]
|
||||
set_driving_cell -lib_cell INV_X1 -pin ZN [get_ports in2]
|
||||
set_driving_cell -lib_cell BUF_X4 [get_ports in3]
|
||||
puts "PASS: driving cells"
|
||||
|
||||
set_drive 100 [get_ports in1]
|
||||
set_drive -rise 80 [get_ports in2]
|
||||
set_drive -fall 120 [get_ports in2]
|
||||
puts "PASS: drive resistances"
|
||||
|
||||
# Input transition
|
||||
set_input_transition 0.15 [get_ports in1]
|
||||
set_input_transition -rise -max 0.12 [get_ports in2]
|
||||
set_input_transition -fall -min 0.08 [get_ports in2]
|
||||
puts "PASS: input transitions"
|
||||
|
||||
############################################################
|
||||
# Inter-clock uncertainty with all combinations
|
||||
# (exercises writeInterClockUncertainty)
|
||||
############################################################
|
||||
set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -setup 0.3
|
||||
set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -hold 0.15
|
||||
set_clock_uncertainty -from [get_clocks clk2] -to [get_clocks clk1] -setup 0.28
|
||||
set_clock_uncertainty -from [get_clocks clk2] -to [get_clocks clk1] -hold 0.12
|
||||
puts "PASS: inter-clock uncertainty"
|
||||
|
||||
############################################################
|
||||
# Min pulse width on multiple target types
|
||||
# (exercises writeMinPulseWidths)
|
||||
############################################################
|
||||
set_min_pulse_width 0.5
|
||||
puts "PASS: min_pulse_width global"
|
||||
|
||||
set_min_pulse_width -high 0.6 [get_clocks clk1]
|
||||
set_min_pulse_width -low 0.4 [get_clocks clk1]
|
||||
puts "PASS: min_pulse_width clock high/low"
|
||||
|
||||
set_min_pulse_width 0.55 [get_clocks clk2]
|
||||
puts "PASS: min_pulse_width clock same"
|
||||
|
||||
catch {
|
||||
set_min_pulse_width 0.3 [get_pins reg1/CK]
|
||||
puts "PASS: min_pulse_width pin"
|
||||
}
|
||||
|
||||
catch {
|
||||
set_min_pulse_width 0.45 [get_cells reg3]
|
||||
puts "PASS: min_pulse_width instance"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Port loads (exercises writePortLoads/writePortExtCap)
|
||||
############################################################
|
||||
set_load -pin_load 0.05 [get_ports out1]
|
||||
set_load -wire_load 0.02 [get_ports out1]
|
||||
set_load -pin_load -rise 0.04 [get_ports out2]
|
||||
set_load -pin_load -fall 0.045 [get_ports out2]
|
||||
set_port_fanout_number 4 [get_ports out1]
|
||||
puts "PASS: port loads"
|
||||
|
||||
############################################################
|
||||
# Clock sense (exercises writeClockSenses)
|
||||
############################################################
|
||||
set_clock_sense -positive -clocks [get_clocks clk1] [get_pins buf1/Z]
|
||||
set_clock_sense -negative -clocks [get_clocks clk2] [get_pins or1/ZN]
|
||||
puts "PASS: clock sense"
|
||||
|
||||
############################################################
|
||||
# Propagated clocks (exercises writePropagatedClkPins)
|
||||
############################################################
|
||||
set_propagated_clock [get_clocks clk1]
|
||||
set_propagated_clock [get_ports clk2]
|
||||
puts "PASS: propagated clocks"
|
||||
|
||||
# Clock insertion (exercises writeClockInsertions)
|
||||
set_clock_latency -source -early 0.3 [get_clocks clk1]
|
||||
set_clock_latency -source -late 0.5 [get_clocks clk1]
|
||||
puts "PASS: clock insertion"
|
||||
|
||||
############################################################
|
||||
# Clock transition
|
||||
############################################################
|
||||
set_clock_transition -rise -max 0.15 [get_clocks clk1]
|
||||
set_clock_transition -fall -min 0.08 [get_clocks clk1]
|
||||
set_clock_transition 0.1 [get_clocks clk2]
|
||||
puts "PASS: clock transitions"
|
||||
|
||||
############################################################
|
||||
# False paths with -setup/-hold only
|
||||
# (exercises writeFalsePaths branches)
|
||||
############################################################
|
||||
set_false_path -setup -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
set_false_path -hold -from [get_clocks clk2] -to [get_clocks clk1]
|
||||
puts "PASS: false paths setup/hold only"
|
||||
|
||||
############################################################
|
||||
# Comprehensive write with all constraint types
|
||||
############################################################
|
||||
set sdc5 [make_result_file sdc_wdg5.sdc]
|
||||
write_sdc -no_timestamp $sdc5
|
||||
puts "PASS: write_sdc comprehensive"
|
||||
|
||||
set sdc6 [make_result_file sdc_wdg6.sdc]
|
||||
write_sdc -no_timestamp -compatible $sdc6
|
||||
puts "PASS: write_sdc compatible comprehensive"
|
||||
|
||||
set sdc7 [make_result_file sdc_wdg7.sdc]
|
||||
write_sdc -no_timestamp -digits 8 $sdc7
|
||||
puts "PASS: write_sdc digits 8"
|
||||
|
||||
set sdc8 [make_result_file sdc_wdg8.sdc]
|
||||
write_sdc -no_timestamp -map_hpins $sdc8
|
||||
puts "PASS: write_sdc map_hpins"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report checks"
|
||||
|
||||
############################################################
|
||||
# Read back SDC and verify roundtrip
|
||||
############################################################
|
||||
read_sdc $sdc5
|
||||
puts "PASS: read_sdc"
|
||||
|
||||
set sdc9 [make_result_file sdc_wdg9.sdc]
|
||||
write_sdc -no_timestamp $sdc9
|
||||
puts "PASS: write_sdc roundtrip"
|
||||
|
||||
report_checks
|
||||
puts "PASS: final report"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,143 @@
|
||||
PASS: clocks created
|
||||
PASS: generated clocks
|
||||
PASS: clock latency
|
||||
PASS: clock uncertainty
|
||||
PASS: clock transition
|
||||
PASS: propagated clock
|
||||
PASS: clock groups
|
||||
Warning: sdc_write_options.tcl line 1, set_clock_sense is deprecated as of SDC 2.1. Use set_sense -type clock.
|
||||
PASS: clock sense
|
||||
PASS: input delays
|
||||
PASS: output delays
|
||||
PASS: driving cells
|
||||
PASS: set_drive
|
||||
PASS: loads
|
||||
PASS: input transitions
|
||||
PASS: design limits
|
||||
PASS: exception paths
|
||||
PASS: disable timing
|
||||
PASS: case analysis
|
||||
PASS: operating conditions
|
||||
PASS: wire load
|
||||
PASS: timing derate
|
||||
PASS: min pulse width
|
||||
PASS: port fanout
|
||||
PASS: resistance
|
||||
PASS: max area
|
||||
PASS: logic one
|
||||
PASS: max time borrow
|
||||
PASS: clock gating check
|
||||
PASS: voltage
|
||||
PASS: write_sdc basic
|
||||
PASS: write_sdc -compatible
|
||||
PASS: write_sdc -digits 2
|
||||
PASS: write_sdc -digits 8
|
||||
PASS: write_sdc -compatible -digits 6
|
||||
PASS: write_sdc -map_hpins
|
||||
PASS: read_sdc basic
|
||||
Warning: generated clock gen_div2 pin clk1 is in the fanout of multiple clocks.
|
||||
Warning: generated clock gen_edges pin clk1 is in the fanout of multiple clocks.
|
||||
Startpoint: reg2/Q (clock source 'gen_edges')
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
5.00 5.00 clock gen_edges (fall edge)
|
||||
0.00 5.00 clock network delay
|
||||
5.00 v out1 (out)
|
||||
5.00 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.25 10.25 clock network delay (propagated)
|
||||
-0.20 10.05 clock uncertainty
|
||||
0.00 10.05 clock reconvergence pessimism
|
||||
-3.00 7.05 output external delay
|
||||
7.05 data required time
|
||||
---------------------------------------------------------
|
||||
7.05 data required time
|
||||
-5.00 data arrival time
|
||||
---------------------------------------------------------
|
||||
2.05 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3/Q (clock source 'gen_mul3')
|
||||
Endpoint: out2 (output port clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
13.33 13.33 clock gen_mul3 (rise edge)
|
||||
0.00 13.33 clock network delay
|
||||
13.33 ^ out2 (out)
|
||||
13.33 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.20 20.20 clock network delay (ideal)
|
||||
0.00 20.20 clock reconvergence pessimism
|
||||
-3.50 16.70 output external delay
|
||||
16.70 data required time
|
||||
---------------------------------------------------------
|
||||
16.70 data required time
|
||||
-13.33 data arrival time
|
||||
---------------------------------------------------------
|
||||
3.37 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks after read_sdc
|
||||
PASS: read_sdc compatible
|
||||
Warning: generated clock gen_div2 pin clk1 is in the fanout of multiple clocks.
|
||||
Warning: generated clock gen_edges pin clk1 is in the fanout of multiple clocks.
|
||||
Startpoint: reg2/Q (clock source 'gen_edges')
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
5.00 5.00 clock gen_edges (fall edge)
|
||||
0.00 5.00 clock network delay
|
||||
5.00 v out1 (out)
|
||||
5.00 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.25 10.25 clock network delay (propagated)
|
||||
-0.20 10.05 clock uncertainty
|
||||
0.00 10.05 clock reconvergence pessimism
|
||||
-3.00 7.05 output external delay
|
||||
7.05 data required time
|
||||
---------------------------------------------------------
|
||||
7.05 data required time
|
||||
-5.00 data arrival time
|
||||
---------------------------------------------------------
|
||||
2.05 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3/Q (clock source 'gen_mul3')
|
||||
Endpoint: out2 (output port clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
13.33 13.33 clock gen_mul3 (rise edge)
|
||||
0.00 13.33 clock network delay
|
||||
13.33 ^ out2 (out)
|
||||
13.33 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.20 20.20 clock network delay (ideal)
|
||||
0.00 20.20 clock reconvergence pessimism
|
||||
-3.50 16.70 output external delay
|
||||
16.70 data required time
|
||||
---------------------------------------------------------
|
||||
16.70 data required time
|
||||
-13.33 data arrival time
|
||||
---------------------------------------------------------
|
||||
3.37 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks after read_sdc compatible
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,235 @@
|
||||
# Test write_sdc with various option combinations for code coverage
|
||||
# Targets: WriteSdc.cc (multiple write functions, compatible mode, digits,
|
||||
# WriteGetPin, WriteGetPort, WriteGetClock, WriteGetInstance, etc.)
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
############################################################
|
||||
# Create comprehensive constraints to maximize write_sdc coverage
|
||||
############################################################
|
||||
|
||||
# Multiple clocks
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 -waveform {0 10} [get_ports clk2]
|
||||
create_clock -name vclk -period 5
|
||||
create_clock -name clk1_fast -period 5 -add [get_ports clk1]
|
||||
puts "PASS: clocks created"
|
||||
|
||||
# Generated clocks (various options)
|
||||
create_generated_clock -name gen_div2 -source [get_ports clk1] -divide_by 2 [get_pins reg1/Q]
|
||||
create_generated_clock -name gen_mul3 -source [get_ports clk2] -multiply_by 3 [get_pins reg3/Q]
|
||||
create_generated_clock -name gen_edges -source [get_ports clk1] -edges {1 3 5} [get_pins reg2/Q]
|
||||
puts "PASS: generated clocks"
|
||||
|
||||
# Clock latency (source + network, all rf/minmax combos)
|
||||
set_clock_latency -source 0.5 [get_clocks clk1]
|
||||
set_clock_latency -source -rise -max 0.6 [get_clocks clk1]
|
||||
set_clock_latency -source -fall -min 0.3 [get_clocks clk1]
|
||||
set_clock_latency -source -rise -min 0.25 [get_clocks clk1]
|
||||
set_clock_latency -source -fall -max 0.55 [get_clocks clk1]
|
||||
set_clock_latency 0.2 [get_clocks clk2]
|
||||
set_clock_latency -rise -max 0.4 [get_clocks clk2]
|
||||
set_clock_latency -fall -min 0.1 [get_clocks clk2]
|
||||
puts "PASS: clock latency"
|
||||
|
||||
# Clock uncertainty
|
||||
set_clock_uncertainty -setup 0.2 [get_clocks clk1]
|
||||
set_clock_uncertainty -hold 0.1 [get_clocks clk1]
|
||||
set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -setup 0.3
|
||||
set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -hold 0.15
|
||||
puts "PASS: clock uncertainty"
|
||||
|
||||
# Clock transition
|
||||
set_clock_transition -rise -max 0.15 [get_clocks clk1]
|
||||
set_clock_transition -fall -min 0.08 [get_clocks clk1]
|
||||
set_clock_transition 0.1 [get_clocks clk2]
|
||||
puts "PASS: clock transition"
|
||||
|
||||
# Propagated clock
|
||||
set_propagated_clock [get_clocks clk1]
|
||||
puts "PASS: propagated clock"
|
||||
|
||||
# Clock groups
|
||||
set_clock_groups -asynchronous -group {clk1 clk1_fast} -group {clk2}
|
||||
puts "PASS: clock groups"
|
||||
|
||||
# Clock sense
|
||||
set_clock_sense -positive -clocks [get_clocks clk1] [get_pins buf1/Z]
|
||||
puts "PASS: clock sense"
|
||||
|
||||
# Input delays (various options)
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 -rise -max 2.5 [get_ports in2]
|
||||
set_input_delay -clock clk1 -fall -min 1.0 [get_ports in2]
|
||||
set_input_delay -clock clk2 1.8 [get_ports in3]
|
||||
set_input_delay -clock clk1 -clock_fall 1.5 [get_ports in3] -add_delay
|
||||
puts "PASS: input delays"
|
||||
|
||||
# Output delays
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 -rise -max 3.5 [get_ports out2]
|
||||
set_output_delay -clock clk2 -fall -min 1.5 [get_ports out2] -add_delay
|
||||
puts "PASS: output delays"
|
||||
|
||||
# Driving cells
|
||||
set_driving_cell -lib_cell BUF_X1 [get_ports in1]
|
||||
set_driving_cell -lib_cell INV_X1 -pin ZN [get_ports in2]
|
||||
set_driving_cell -lib_cell BUF_X4 [get_ports in3]
|
||||
puts "PASS: driving cells"
|
||||
|
||||
# set_drive
|
||||
set_drive 100 [get_ports in1]
|
||||
puts "PASS: set_drive"
|
||||
|
||||
# Loads
|
||||
set_load 0.05 [get_ports out1]
|
||||
set_load -pin_load 0.03 [get_ports out2]
|
||||
puts "PASS: loads"
|
||||
|
||||
# Input transition
|
||||
set_input_transition 0.15 [get_ports in1]
|
||||
set_input_transition -rise -max 0.12 [get_ports in2]
|
||||
set_input_transition -fall -min 0.08 [get_ports in2]
|
||||
puts "PASS: input transitions"
|
||||
|
||||
# Design limits
|
||||
set_max_transition 0.5 [current_design]
|
||||
set_max_capacitance 0.2 [current_design]
|
||||
set_max_fanout 20 [current_design]
|
||||
set_max_transition 0.3 [get_ports out1]
|
||||
set_max_capacitance 0.1 [get_ports out1]
|
||||
set_max_transition -clock_path 0.2 [get_clocks clk1]
|
||||
set_max_transition -data_path 0.4 [get_clocks clk1]
|
||||
puts "PASS: design limits"
|
||||
|
||||
# Exception paths
|
||||
set_false_path -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
set_false_path -from [get_ports in1] -through [get_pins and1/ZN] -to [get_ports out1]
|
||||
set_false_path -rise_from [get_ports in3] -fall_to [get_ports out2]
|
||||
set_multicycle_path -setup 2 -from [get_ports in1] -to [get_ports out1]
|
||||
set_multicycle_path -hold 1 -from [get_ports in1] -to [get_ports out1]
|
||||
set_max_delay -from [get_ports in2] -to [get_ports out1] 8.0
|
||||
set_min_delay -from [get_ports in2] -to [get_ports out1] 1.0
|
||||
group_path -name group_clk1 -from [get_clocks clk1]
|
||||
group_path -name group_io -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: exception paths"
|
||||
|
||||
# Disable timing
|
||||
set_disable_timing [get_cells buf1]
|
||||
set_disable_timing [get_lib_cells NangateOpenCellLibrary/INV_X1] -from A -to ZN
|
||||
puts "PASS: disable timing"
|
||||
|
||||
# Case analysis
|
||||
set_case_analysis 0 [get_ports in3]
|
||||
puts "PASS: case analysis"
|
||||
|
||||
# Operating conditions
|
||||
set_operating_conditions typical
|
||||
puts "PASS: operating conditions"
|
||||
|
||||
# Wire load
|
||||
set_wire_load_model -name "5K_hvratio_1_1"
|
||||
set_wire_load_mode enclosed
|
||||
puts "PASS: wire load"
|
||||
|
||||
# Timing derate
|
||||
set_timing_derate -early 0.95
|
||||
set_timing_derate -late 1.05
|
||||
set_timing_derate -early -clock 0.97
|
||||
set_timing_derate -late -clock 1.03
|
||||
set_timing_derate -early -data 0.94
|
||||
set_timing_derate -late -data 1.06
|
||||
puts "PASS: timing derate"
|
||||
|
||||
# Min pulse width
|
||||
set_min_pulse_width 1.0 [get_clocks clk1]
|
||||
set_min_pulse_width -high 0.5 [get_clocks clk1]
|
||||
set_min_pulse_width -low 0.4 [get_clocks clk1]
|
||||
puts "PASS: min pulse width"
|
||||
|
||||
# Fanout number
|
||||
set_port_fanout_number 4 [get_ports out1]
|
||||
puts "PASS: port fanout"
|
||||
|
||||
# Net resistance
|
||||
set_resistance -min 10.0 [get_nets n1]
|
||||
set_resistance -max 20.0 [get_nets n1]
|
||||
puts "PASS: resistance"
|
||||
|
||||
# Max area
|
||||
set_max_area 100.0
|
||||
puts "PASS: max area"
|
||||
|
||||
# Logic values
|
||||
set_logic_one [get_ports in2]
|
||||
puts "PASS: logic one"
|
||||
|
||||
# Max time borrow
|
||||
set_max_time_borrow 2.0 [get_clocks clk1]
|
||||
puts "PASS: max time borrow"
|
||||
|
||||
# Clock gating check
|
||||
set_clock_gating_check -setup 0.5 [get_clocks clk1]
|
||||
set_clock_gating_check -hold 0.3 [get_clocks clk1]
|
||||
puts "PASS: clock gating check"
|
||||
|
||||
# set_voltage
|
||||
catch {set_voltage 1.1 -min 0.9}
|
||||
puts "PASS: voltage"
|
||||
|
||||
############################################################
|
||||
# Write SDC with all option combinations
|
||||
############################################################
|
||||
|
||||
# Option 1: basic (native mode, default digits)
|
||||
set sdc_file1 [make_result_file sdc_write_opt_basic.sdc]
|
||||
write_sdc -no_timestamp $sdc_file1
|
||||
puts "PASS: write_sdc basic"
|
||||
|
||||
# Option 2: with -compatible flag
|
||||
set sdc_file2 [make_result_file sdc_write_opt_compat.sdc]
|
||||
write_sdc -no_timestamp -compatible $sdc_file2
|
||||
puts "PASS: write_sdc -compatible"
|
||||
|
||||
# Option 3: with -digits 2
|
||||
set sdc_file3 [make_result_file sdc_write_opt_d2.sdc]
|
||||
write_sdc -no_timestamp -digits 2 $sdc_file3
|
||||
puts "PASS: write_sdc -digits 2"
|
||||
|
||||
# Option 4: with -digits 8
|
||||
set sdc_file4 [make_result_file sdc_write_opt_d8.sdc]
|
||||
write_sdc -no_timestamp -digits 8 $sdc_file4
|
||||
puts "PASS: write_sdc -digits 8"
|
||||
|
||||
# Option 5: -compatible + -digits 6
|
||||
set sdc_file5 [make_result_file sdc_write_opt_compat_d6.sdc]
|
||||
write_sdc -no_timestamp -compatible -digits 6 $sdc_file5
|
||||
puts "PASS: write_sdc -compatible -digits 6"
|
||||
|
||||
# Option 6: -map_hpins
|
||||
set sdc_file6 [make_result_file sdc_write_opt_hpins.sdc]
|
||||
write_sdc -no_timestamp -map_hpins $sdc_file6
|
||||
puts "PASS: write_sdc -map_hpins"
|
||||
|
||||
############################################################
|
||||
# Read back and verify
|
||||
############################################################
|
||||
|
||||
# Read back native SDC
|
||||
read_sdc $sdc_file1
|
||||
puts "PASS: read_sdc basic"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report_checks after read_sdc"
|
||||
|
||||
# Read back compatible SDC
|
||||
read_sdc $sdc_file2
|
||||
puts "PASS: read_sdc compatible"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report_checks after read_sdc compatible"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,28 @@
|
||||
PASS: clocks created
|
||||
PASS: generated clock created
|
||||
PASS: delays set
|
||||
PASS: uncertainty set
|
||||
PASS: latency set
|
||||
PASS: transition set
|
||||
PASS: driving cell set
|
||||
PASS: load set
|
||||
PASS: input transition set
|
||||
PASS: false path set
|
||||
PASS: multicycle set
|
||||
PASS: max delay set
|
||||
PASS: design limits set
|
||||
PASS: case analysis set
|
||||
PASS: operating conditions set
|
||||
PASS: wire load model set
|
||||
PASS: timing derate set
|
||||
PASS: propagated clock set
|
||||
PASS: write_sdc
|
||||
No paths found.
|
||||
PASS: report_checks before clear
|
||||
Clock Period Waveform
|
||||
----------------------------------------------------
|
||||
clk1 10.00 0.00 5.00
|
||||
clk2 20.00 0.00 10.00
|
||||
gen_div2 20.00 0.00 10.00 (generated)
|
||||
PASS: report_clock_properties before clear
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,114 @@
|
||||
# Test SDC write/read roundtrip for code coverage
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
############################################################
|
||||
# Setup various constraints
|
||||
############################################################
|
||||
|
||||
# Clocks
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 -waveform {0 10} [get_ports clk2]
|
||||
puts "PASS: clocks created"
|
||||
|
||||
# Generated clock
|
||||
create_generated_clock -name gen_div2 -source [get_ports clk1] -divide_by 2 [get_pins reg1/Q]
|
||||
puts "PASS: generated clock created"
|
||||
|
||||
# Delays
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 1.5 [get_ports in2]
|
||||
set_input_delay -clock clk1 1.8 [get_ports in3]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 2.5 [get_ports out2]
|
||||
puts "PASS: delays set"
|
||||
|
||||
# Clock uncertainty
|
||||
set_clock_uncertainty -setup 0.2 [get_clocks clk1]
|
||||
set_clock_uncertainty -hold 0.1 [get_clocks clk1]
|
||||
puts "PASS: uncertainty set"
|
||||
|
||||
# Clock latency
|
||||
set_clock_latency -source 0.5 [get_clocks clk1]
|
||||
set_clock_latency 0.3 [get_clocks clk2]
|
||||
puts "PASS: latency set"
|
||||
|
||||
# Clock transition
|
||||
set_clock_transition 0.1 [get_clocks clk1]
|
||||
puts "PASS: transition set"
|
||||
|
||||
# Driving cell
|
||||
set_driving_cell -lib_cell BUF_X1 [get_ports in1]
|
||||
puts "PASS: driving cell set"
|
||||
|
||||
# Load
|
||||
set_load 0.05 [get_ports out1]
|
||||
set_load 0.04 [get_ports out2]
|
||||
puts "PASS: load set"
|
||||
|
||||
# Input transition
|
||||
set_input_transition 0.15 [get_ports in1]
|
||||
puts "PASS: input transition set"
|
||||
|
||||
# False path
|
||||
set_false_path -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
puts "PASS: false path set"
|
||||
|
||||
# Multicycle
|
||||
set_multicycle_path -setup 2 -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: multicycle set"
|
||||
|
||||
# Max/min delay
|
||||
set_max_delay -from [get_ports in2] -to [get_ports out1] 8.0
|
||||
puts "PASS: max delay set"
|
||||
|
||||
# Max transition/capacitance/fanout
|
||||
set_max_transition 0.5 [current_design]
|
||||
set_max_capacitance 0.2 [current_design]
|
||||
set_max_fanout 20 [current_design]
|
||||
puts "PASS: design limits set"
|
||||
|
||||
# Case analysis
|
||||
set_case_analysis 0 [get_ports in3]
|
||||
puts "PASS: case analysis set"
|
||||
|
||||
# Operating conditions
|
||||
set_operating_conditions typical
|
||||
puts "PASS: operating conditions set"
|
||||
|
||||
# Wire load
|
||||
set_wire_load_model -name "5K_hvratio_1_1"
|
||||
puts "PASS: wire load model set"
|
||||
|
||||
# Timing derate
|
||||
set_timing_derate -early 0.95
|
||||
set_timing_derate -late 1.05
|
||||
puts "PASS: timing derate set"
|
||||
|
||||
# Propagated clock
|
||||
set_propagated_clock [get_clocks clk1]
|
||||
puts "PASS: propagated clock set"
|
||||
|
||||
############################################################
|
||||
# Write SDC
|
||||
############################################################
|
||||
|
||||
set sdc_file [make_result_file sdc_write_read.sdc]
|
||||
write_sdc -no_timestamp $sdc_file
|
||||
puts "PASS: write_sdc"
|
||||
|
||||
############################################################
|
||||
# Clear and read back
|
||||
############################################################
|
||||
|
||||
# Report before clear
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: report_checks before clear"
|
||||
|
||||
report_clock_properties
|
||||
puts "PASS: report_clock_properties before clear"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,253 @@
|
||||
PASS: clocks
|
||||
PASS: generated clocks
|
||||
PASS: propagated
|
||||
PASS: clock transition
|
||||
PASS: clock latency
|
||||
PASS: clock uncertainty
|
||||
PASS: IO delays
|
||||
PASS: driving cells
|
||||
PASS: loads
|
||||
PASS: input transitions
|
||||
PASS: design limits
|
||||
PASS: false paths
|
||||
PASS: multicycle paths
|
||||
PASS: max/min delay
|
||||
PASS: group paths
|
||||
PASS: clock groups
|
||||
Warning: sdc_write_roundtrip.tcl line 1, set_clock_sense is deprecated as of SDC 2.1. Use set_sense -type clock.
|
||||
PASS: clock sense
|
||||
PASS: disable timing
|
||||
PASS: case analysis
|
||||
PASS: logic value
|
||||
PASS: operating conditions
|
||||
PASS: wire load
|
||||
PASS: timing derate
|
||||
PASS: min pulse width
|
||||
PASS: latch borrow
|
||||
Warning: sdc_write_roundtrip.tcl line 1, object 'sdc_test2' not found.
|
||||
Warning: sdc_write_roundtrip.tcl line 1, object 'sdc_test2' not found.
|
||||
PASS: clock gating check
|
||||
PASS: port fanout
|
||||
PASS: net resistance
|
||||
PASS: voltage
|
||||
PASS: data check
|
||||
PASS: write_sdc native
|
||||
PASS: write_sdc compatible
|
||||
PASS: write_sdc digits 2
|
||||
PASS: write_sdc digits 8
|
||||
PASS: write_sdc map_hpins
|
||||
PASS: write_sdc compatible digits 6
|
||||
Warning: generated clock gclk_div pin clk1 is in the fanout of multiple clocks.
|
||||
Warning: generated clock gclk_edge pin clk1 is in the fanout of multiple clocks.
|
||||
Startpoint: reg2/Q (clock source 'gclk_edge')
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
5.00 5.00 clock gclk_edge (fall edge)
|
||||
0.00 5.00 clock network delay
|
||||
5.00 v out1 (out)
|
||||
5.00 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.30 10.30 clock network delay (propagated)
|
||||
-0.20 10.10 clock uncertainty
|
||||
0.00 10.10 clock reconvergence pessimism
|
||||
-3.00 7.10 output external delay
|
||||
7.10 data required time
|
||||
---------------------------------------------------------
|
||||
7.10 data required time
|
||||
-5.00 data arrival time
|
||||
---------------------------------------------------------
|
||||
2.10 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3/Q (clock source 'gclk_mul')
|
||||
Endpoint: out2 (output port clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
13.33 13.33 clock gclk_mul (rise edge)
|
||||
0.00 13.33 clock network delay
|
||||
13.33 ^ out2 (out)
|
||||
13.33 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.20 20.20 clock network delay (ideal)
|
||||
0.00 20.20 clock reconvergence pessimism
|
||||
-3.50 16.70 output external delay
|
||||
16.70 data required time
|
||||
---------------------------------------------------------
|
||||
16.70 data required time
|
||||
-13.33 data arrival time
|
||||
---------------------------------------------------------
|
||||
3.37 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks initial
|
||||
PASS: read_sdc native
|
||||
Warning: generated clock gclk_div pin clk1 is in the fanout of multiple clocks.
|
||||
Warning: generated clock gclk_edge pin clk1 is in the fanout of multiple clocks.
|
||||
Startpoint: reg2/Q (clock source 'gclk_edge')
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
5.00 5.00 clock gclk_edge (fall edge)
|
||||
0.00 5.00 clock network delay
|
||||
5.00 v out1 (out)
|
||||
5.00 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.30 10.30 clock network delay (propagated)
|
||||
-0.20 10.10 clock uncertainty
|
||||
0.00 10.10 clock reconvergence pessimism
|
||||
-3.00 7.10 output external delay
|
||||
7.10 data required time
|
||||
---------------------------------------------------------
|
||||
7.10 data required time
|
||||
-5.00 data arrival time
|
||||
---------------------------------------------------------
|
||||
2.10 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3/Q (clock source 'gclk_mul')
|
||||
Endpoint: out2 (output port clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
13.33 13.33 clock gclk_mul (rise edge)
|
||||
0.00 13.33 clock network delay
|
||||
13.33 ^ out2 (out)
|
||||
13.33 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.20 20.20 clock network delay (ideal)
|
||||
0.00 20.20 clock reconvergence pessimism
|
||||
-3.50 16.70 output external delay
|
||||
16.70 data required time
|
||||
---------------------------------------------------------
|
||||
16.70 data required time
|
||||
-13.33 data arrival time
|
||||
---------------------------------------------------------
|
||||
3.37 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks after read native
|
||||
PASS: write_sdc after re-read
|
||||
PASS: read_sdc compatible
|
||||
Warning: generated clock gclk_div pin clk1 is in the fanout of multiple clocks.
|
||||
Warning: generated clock gclk_edge pin clk1 is in the fanout of multiple clocks.
|
||||
Startpoint: reg2/Q (clock source 'gclk_edge')
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
5.00 5.00 clock gclk_edge (fall edge)
|
||||
0.00 5.00 clock network delay
|
||||
5.00 v out1 (out)
|
||||
5.00 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.30 10.30 clock network delay (propagated)
|
||||
-0.20 10.10 clock uncertainty
|
||||
0.00 10.10 clock reconvergence pessimism
|
||||
-3.00 7.10 output external delay
|
||||
7.10 data required time
|
||||
---------------------------------------------------------
|
||||
7.10 data required time
|
||||
-5.00 data arrival time
|
||||
---------------------------------------------------------
|
||||
2.10 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3/Q (clock source 'gclk_mul')
|
||||
Endpoint: out2 (output port clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
13.33 13.33 clock gclk_mul (rise edge)
|
||||
0.00 13.33 clock network delay
|
||||
13.33 ^ out2 (out)
|
||||
13.33 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.20 20.20 clock network delay (ideal)
|
||||
0.00 20.20 clock reconvergence pessimism
|
||||
-3.50 16.70 output external delay
|
||||
16.70 data required time
|
||||
---------------------------------------------------------
|
||||
16.70 data required time
|
||||
-13.33 data arrival time
|
||||
---------------------------------------------------------
|
||||
3.37 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks after read compatible
|
||||
PASS: read_sdc digits 8
|
||||
Warning: generated clock gclk_div pin clk1 is in the fanout of multiple clocks.
|
||||
Warning: generated clock gclk_edge pin clk1 is in the fanout of multiple clocks.
|
||||
Startpoint: reg2/Q (clock source 'gclk_edge')
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
5.00 5.00 clock gclk_edge (fall edge)
|
||||
0.00 5.00 clock network delay
|
||||
5.00 v out1 (out)
|
||||
5.00 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.30 10.30 clock network delay (propagated)
|
||||
-0.20 10.10 clock uncertainty
|
||||
0.00 10.10 clock reconvergence pessimism
|
||||
-3.00 7.10 output external delay
|
||||
7.10 data required time
|
||||
---------------------------------------------------------
|
||||
7.10 data required time
|
||||
-5.00 data arrival time
|
||||
---------------------------------------------------------
|
||||
2.10 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3/Q (clock source 'gclk_mul')
|
||||
Endpoint: out2 (output port clocked by clk2)
|
||||
Path Group: clk2
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
13.33 13.33 clock gclk_mul (rise edge)
|
||||
0.00 13.33 clock network delay
|
||||
13.33 ^ out2 (out)
|
||||
13.33 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.20 20.20 clock network delay (ideal)
|
||||
0.00 20.20 clock reconvergence pessimism
|
||||
-3.50 16.70 output external delay
|
||||
16.70 data required time
|
||||
---------------------------------------------------------
|
||||
16.70 data required time
|
||||
-13.33 data arrival time
|
||||
---------------------------------------------------------
|
||||
3.37 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks after read digits 8
|
||||
PASS: final write_sdc
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,276 @@
|
||||
# Test comprehensive write_sdc / read_sdc / re-write roundtrip
|
||||
# Targets: WriteSdc.cc (all write* functions, WriteGet* classes),
|
||||
# Sdc.cc (reading constraints back in, net load/cap, voltage),
|
||||
# ExceptionPath.cc (exception comparison during merge),
|
||||
# Clock.cc (clock property persistence through roundtrip)
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
############################################################
|
||||
# Create maximum variety of constraints
|
||||
############################################################
|
||||
|
||||
# Clocks with different waveforms
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 -waveform {0 10} [get_ports clk2]
|
||||
create_clock -name vclk -period 8
|
||||
create_clock -name clk1_alt -period 5 -add [get_ports clk1]
|
||||
puts "PASS: clocks"
|
||||
|
||||
# Generated clocks
|
||||
create_generated_clock -name gclk_div -source [get_ports clk1] -divide_by 2 [get_pins reg1/Q]
|
||||
create_generated_clock -name gclk_mul -source [get_ports clk2] -multiply_by 3 [get_pins reg3/Q]
|
||||
create_generated_clock -name gclk_edge -source [get_ports clk1] -edges {1 3 5} [get_pins reg2/Q]
|
||||
puts "PASS: generated clocks"
|
||||
|
||||
# Propagated clock
|
||||
set_propagated_clock [get_clocks clk1]
|
||||
puts "PASS: propagated"
|
||||
|
||||
# Clock slew
|
||||
set_clock_transition -rise -max 0.15 [get_clocks clk1]
|
||||
set_clock_transition -fall -min 0.08 [get_clocks clk1]
|
||||
set_clock_transition 0.1 [get_clocks clk2]
|
||||
puts "PASS: clock transition"
|
||||
|
||||
# Clock latency
|
||||
set_clock_latency -source 0.5 [get_clocks clk1]
|
||||
set_clock_latency -source -early 0.3 [get_clocks clk1]
|
||||
set_clock_latency -source -late 0.6 [get_clocks clk1]
|
||||
set_clock_latency -source -rise -max 0.65 [get_clocks clk1]
|
||||
set_clock_latency -source -fall -min 0.25 [get_clocks clk1]
|
||||
set_clock_latency 0.2 [get_clocks clk2]
|
||||
set_clock_latency -rise -max 0.4 [get_clocks clk2]
|
||||
set_clock_latency -fall -min 0.1 [get_clocks clk2]
|
||||
puts "PASS: clock latency"
|
||||
|
||||
# Clock uncertainty (simple + inter-clock)
|
||||
set_clock_uncertainty -setup 0.2 [get_clocks clk1]
|
||||
set_clock_uncertainty -hold 0.1 [get_clocks clk1]
|
||||
set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -setup 0.3
|
||||
set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -hold 0.15
|
||||
set_clock_uncertainty -from [get_clocks clk2] -to [get_clocks clk1] -setup 0.28
|
||||
set_clock_uncertainty -from [get_clocks clk2] -to [get_clocks clk1] -hold 0.12
|
||||
puts "PASS: clock uncertainty"
|
||||
|
||||
# IO delays (various options)
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 -rise -max 2.5 [get_ports in2]
|
||||
set_input_delay -clock clk1 -fall -min 1.0 [get_ports in2]
|
||||
set_input_delay -clock clk2 1.8 [get_ports in3]
|
||||
set_input_delay -clock clk1 -clock_fall 1.5 [get_ports in3] -add_delay
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 -rise -max 3.5 [get_ports out2]
|
||||
set_output_delay -clock clk2 -fall -min 1.5 [get_ports out2] -add_delay
|
||||
puts "PASS: IO delays"
|
||||
|
||||
# Driving cells / input drive
|
||||
set_driving_cell -lib_cell BUF_X1 [get_ports in1]
|
||||
set_driving_cell -lib_cell INV_X1 -pin ZN [get_ports in2]
|
||||
set_driving_cell -lib_cell BUF_X4 [get_ports in3]
|
||||
set_drive 100 [get_ports in1]
|
||||
set_drive -rise 80 [get_ports in2]
|
||||
set_drive -fall 120 [get_ports in2]
|
||||
puts "PASS: driving cells"
|
||||
|
||||
# Loads
|
||||
set_load 0.05 [get_ports out1]
|
||||
set_load -pin_load 0.03 [get_ports out2]
|
||||
set_load -wire_load 0.02 [get_ports out1]
|
||||
puts "PASS: loads"
|
||||
|
||||
# Input transitions
|
||||
set_input_transition 0.15 [get_ports in1]
|
||||
set_input_transition -rise -max 0.12 [get_ports in2]
|
||||
set_input_transition -fall -min 0.08 [get_ports in2]
|
||||
puts "PASS: input transitions"
|
||||
|
||||
# Design limits
|
||||
set_max_transition 0.5 [current_design]
|
||||
set_max_capacitance 0.2 [current_design]
|
||||
set_max_fanout 20 [current_design]
|
||||
set_max_transition 0.3 [get_ports out1]
|
||||
set_max_capacitance 0.1 [get_ports out1]
|
||||
set_max_transition -clock_path 0.2 [get_clocks clk1]
|
||||
set_max_transition -data_path 0.4 [get_clocks clk1]
|
||||
set_max_area 100.0
|
||||
puts "PASS: design limits"
|
||||
|
||||
# False paths
|
||||
set_false_path -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
set_false_path -from [get_ports in1] -through [get_pins and1/ZN] -to [get_ports out1]
|
||||
set_false_path -rise_from [get_ports in3] -fall_to [get_ports out2]
|
||||
puts "PASS: false paths"
|
||||
|
||||
# Multicycle paths
|
||||
set_multicycle_path -setup 2 -from [get_ports in1] -to [get_ports out1]
|
||||
set_multicycle_path -hold 1 -from [get_ports in1] -to [get_ports out1]
|
||||
set_multicycle_path -setup 3 -from [get_clocks clk1] -to [get_clocks gclk_div]
|
||||
puts "PASS: multicycle paths"
|
||||
|
||||
# Max/min delay
|
||||
set_max_delay -from [get_ports in2] -to [get_ports out1] 8.0
|
||||
set_min_delay -from [get_ports in2] -to [get_ports out1] 1.0
|
||||
puts "PASS: max/min delay"
|
||||
|
||||
# Group paths
|
||||
group_path -name grp_clk1 -from [get_clocks clk1]
|
||||
group_path -name grp_io -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: group paths"
|
||||
|
||||
# Clock groups
|
||||
set_clock_groups -asynchronous -name async1 \
|
||||
-group {clk1 clk1_alt gclk_div gclk_edge} \
|
||||
-group {clk2 gclk_mul}
|
||||
puts "PASS: clock groups"
|
||||
|
||||
# Clock sense
|
||||
set_clock_sense -positive -clocks [get_clocks clk1] [get_pins buf1/Z]
|
||||
puts "PASS: clock sense"
|
||||
|
||||
# Disable timing
|
||||
set_disable_timing [get_cells buf1]
|
||||
set_disable_timing [get_lib_cells NangateOpenCellLibrary/INV_X1] -from A -to ZN
|
||||
puts "PASS: disable timing"
|
||||
|
||||
# Case analysis
|
||||
set_case_analysis 0 [get_ports in3]
|
||||
puts "PASS: case analysis"
|
||||
|
||||
# Logic values
|
||||
set_logic_one [get_ports in2]
|
||||
puts "PASS: logic value"
|
||||
|
||||
# Operating conditions
|
||||
set_operating_conditions typical
|
||||
puts "PASS: operating conditions"
|
||||
|
||||
# Wire load
|
||||
set_wire_load_model -name "5K_hvratio_1_1"
|
||||
set_wire_load_mode enclosed
|
||||
puts "PASS: wire load"
|
||||
|
||||
# Timing derate
|
||||
set_timing_derate -early 0.95
|
||||
set_timing_derate -late 1.05
|
||||
set_timing_derate -early -clock 0.97
|
||||
set_timing_derate -late -clock 1.03
|
||||
set_timing_derate -early -cell_delay 0.91 [get_lib_cells NangateOpenCellLibrary/INV_X1]
|
||||
set_timing_derate -late -cell_delay 1.09 [get_lib_cells NangateOpenCellLibrary/INV_X1]
|
||||
set_timing_derate -early -cell_delay 0.90 [get_cells buf1]
|
||||
set_timing_derate -late -cell_delay 1.10 [get_cells buf1]
|
||||
puts "PASS: timing derate"
|
||||
|
||||
# Min pulse width
|
||||
set_min_pulse_width -high 0.6 [get_clocks clk1]
|
||||
set_min_pulse_width -low 0.4 [get_clocks clk1]
|
||||
puts "PASS: min pulse width"
|
||||
|
||||
# Latch borrow
|
||||
set_max_time_borrow 2.0 [get_clocks clk1]
|
||||
set_max_time_borrow 1.5 [get_pins reg1/D]
|
||||
puts "PASS: latch borrow"
|
||||
|
||||
# Clock gating check
|
||||
set_clock_gating_check -setup 0.5 [get_clocks clk1]
|
||||
set_clock_gating_check -hold 0.3 [get_clocks clk1]
|
||||
set_clock_gating_check -setup 0.4 [current_design]
|
||||
set_clock_gating_check -hold 0.2 [current_design]
|
||||
puts "PASS: clock gating check"
|
||||
|
||||
# Port fanout
|
||||
set_port_fanout_number 4 [get_ports out1]
|
||||
puts "PASS: port fanout"
|
||||
|
||||
# Net resistance
|
||||
set_resistance -min 10.0 [get_nets n1]
|
||||
set_resistance -max 20.0 [get_nets n1]
|
||||
puts "PASS: net resistance"
|
||||
|
||||
# Voltage
|
||||
catch {set_voltage 1.1 -min 0.9}
|
||||
puts "PASS: voltage"
|
||||
|
||||
# Data check
|
||||
catch {
|
||||
set_data_check -from [get_pins reg1/Q] -to [get_pins reg2/D] -setup 0.5
|
||||
set_data_check -from [get_pins reg1/Q] -to [get_pins reg2/D] -hold 0.3
|
||||
puts "PASS: data check"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Write SDC in multiple formats
|
||||
############################################################
|
||||
|
||||
set sdc_native [make_result_file sdc_roundtrip_native.sdc]
|
||||
write_sdc -no_timestamp $sdc_native
|
||||
puts "PASS: write_sdc native"
|
||||
|
||||
set sdc_compat [make_result_file sdc_roundtrip_compat.sdc]
|
||||
write_sdc -no_timestamp -compatible $sdc_compat
|
||||
puts "PASS: write_sdc compatible"
|
||||
|
||||
set sdc_d2 [make_result_file sdc_roundtrip_d2.sdc]
|
||||
write_sdc -no_timestamp -digits 2 $sdc_d2
|
||||
puts "PASS: write_sdc digits 2"
|
||||
|
||||
set sdc_d8 [make_result_file sdc_roundtrip_d8.sdc]
|
||||
write_sdc -no_timestamp -digits 8 $sdc_d8
|
||||
puts "PASS: write_sdc digits 8"
|
||||
|
||||
set sdc_hpins [make_result_file sdc_roundtrip_hpins.sdc]
|
||||
write_sdc -no_timestamp -map_hpins $sdc_hpins
|
||||
puts "PASS: write_sdc map_hpins"
|
||||
|
||||
set sdc_compat_d6 [make_result_file sdc_roundtrip_compat_d6.sdc]
|
||||
write_sdc -no_timestamp -compatible -digits 6 $sdc_compat_d6
|
||||
puts "PASS: write_sdc compatible digits 6"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report_checks initial"
|
||||
|
||||
############################################################
|
||||
# Read back native SDC (exercises read of all constraint types)
|
||||
############################################################
|
||||
|
||||
# Re-read to exercise constraint merging
|
||||
read_sdc $sdc_native
|
||||
puts "PASS: read_sdc native"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report_checks after read native"
|
||||
|
||||
# Write again after re-read
|
||||
set sdc_rewrite [make_result_file sdc_roundtrip_rewrite.sdc]
|
||||
write_sdc -no_timestamp $sdc_rewrite
|
||||
puts "PASS: write_sdc after re-read"
|
||||
|
||||
############################################################
|
||||
# Read compatible SDC
|
||||
############################################################
|
||||
|
||||
read_sdc $sdc_compat
|
||||
puts "PASS: read_sdc compatible"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report_checks after read compatible"
|
||||
|
||||
############################################################
|
||||
# Read high-precision SDC
|
||||
############################################################
|
||||
|
||||
read_sdc $sdc_d8
|
||||
puts "PASS: read_sdc digits 8"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report_checks after read digits 8"
|
||||
|
||||
# Final write
|
||||
set sdc_final [make_result_file sdc_roundtrip_final.sdc]
|
||||
write_sdc -no_timestamp $sdc_final
|
||||
puts "PASS: final write_sdc"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,41 @@
|
||||
PASS: clocks
|
||||
PASS: generated clocks
|
||||
PASS: IO delays
|
||||
PASS: drives
|
||||
PASS: input transitions
|
||||
PASS: loads
|
||||
PASS: net loads
|
||||
PASS: clock latency
|
||||
PASS: clock uncertainty
|
||||
PASS: clock transition
|
||||
PASS: propagated
|
||||
Warning: sdc_write_roundtrip_full.tcl line 1, set_clock_sense is deprecated as of SDC 2.1. Use set_sense -type clock.
|
||||
PASS: clock sense
|
||||
PASS: disable timing
|
||||
PASS: case analysis
|
||||
PASS: logic
|
||||
PASS: design limits
|
||||
PASS: false paths
|
||||
PASS: multicycle paths
|
||||
PASS: max/min delay
|
||||
PASS: group paths
|
||||
PASS: clock groups
|
||||
PASS: clock gating check
|
||||
PASS: min pulse width
|
||||
PASS: latch borrow
|
||||
PASS: net resistance
|
||||
PASS: data checks
|
||||
PASS: operating conditions
|
||||
PASS: wire load
|
||||
PASS: timing derate
|
||||
PASS: constraints set
|
||||
PASS: write native
|
||||
PASS: write compatible
|
||||
PASS: write digits 2
|
||||
PASS: write digits 8
|
||||
PASS: write map_hpins
|
||||
PASS: read native
|
||||
PASS: write after read
|
||||
PASS: read compatible
|
||||
PASS: write final
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,273 @@
|
||||
# Test comprehensive write_sdc roundtrip covering all uncovered
|
||||
# WriteSdc.cc functions: writeDisabledPorts, writeFalsePaths with
|
||||
# all transition variants, writeGroupPath, writeOutputDrives,
|
||||
# writeMinPulseWidth, writeInterClockUncertainty, writeClockGroups.
|
||||
# Also targets Sdc.cc unset/remove operations for maximum coverage.
|
||||
# Targets:
|
||||
# WriteSdc.cc: writeDisabledPorts, writeDisabledInstances,
|
||||
# writeDisabledCells (all/from/to/fromTo paths),
|
||||
# writeFalsePaths (setup/hold, rise/fall from/to),
|
||||
# writeExceptionThruPins with rise/fall_through,
|
||||
# writeGroupPath (named + default + through),
|
||||
# writeOutputDrives / writeDrivingCells,
|
||||
# writeDriveResistances (rise/fall/min/max),
|
||||
# writeMinPulseWidths (all target types, hi!=lo and hi==lo),
|
||||
# writePortExtCap (pin/wire/rise/fall/min/max),
|
||||
# writeInterClockUncertainty,
|
||||
# writeClockGroups (all 3 types),
|
||||
# writeClockSenses,
|
||||
# writeClockInsertions, writePropagatedClkPins,
|
||||
# writeDataChecks, writeClockGatingCheck,
|
||||
# writeCapacitanceLimits, writeResistance
|
||||
# Sdc.cc: all getter functions during write, plus:
|
||||
# removeCaseAnalysis, removePropagatedClock,
|
||||
# removeClockGroups (via unset_clock_groups)
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog sdc_test2.v
|
||||
link_design sdc_test2
|
||||
|
||||
############################################################
|
||||
# Setup complete constraint environment
|
||||
############################################################
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 -waveform {0 10} [get_ports clk2]
|
||||
create_clock -name vclk -period 8
|
||||
puts "PASS: clocks"
|
||||
|
||||
create_generated_clock -name gclk_div -source [get_ports clk1] -divide_by 2 [get_pins reg1/Q]
|
||||
puts "PASS: generated clocks"
|
||||
|
||||
# IO delays with all variants
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 -rise -max 2.5 [get_ports in2]
|
||||
set_input_delay -clock clk1 -fall -min 1.0 [get_ports in2]
|
||||
set_input_delay -clock clk2 1.8 [get_ports in3]
|
||||
set_input_delay -clock clk1 -clock_fall 1.5 [get_ports in3] -add_delay
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 -rise -max 3.5 [get_ports out2]
|
||||
set_output_delay -clock clk2 -fall -min 1.5 [get_ports out2] -add_delay
|
||||
puts "PASS: IO delays"
|
||||
|
||||
# Driving cells and drive resistance
|
||||
set_driving_cell -lib_cell BUF_X1 [get_ports in1]
|
||||
set_driving_cell -lib_cell INV_X1 -pin ZN [get_ports in2]
|
||||
set_driving_cell -lib_cell BUF_X4 [get_ports in3]
|
||||
set_drive 100 [get_ports in1]
|
||||
set_drive -rise 80 [get_ports in2]
|
||||
set_drive -fall 120 [get_ports in2]
|
||||
puts "PASS: drives"
|
||||
|
||||
# Input transitions
|
||||
set_input_transition 0.15 [get_ports in1]
|
||||
set_input_transition -rise -max 0.12 [get_ports in2]
|
||||
set_input_transition -fall -min 0.08 [get_ports in2]
|
||||
puts "PASS: input transitions"
|
||||
|
||||
# Loads with all options
|
||||
set_load -pin_load 0.05 [get_ports out1]
|
||||
set_load -wire_load 0.02 [get_ports out1]
|
||||
set_load -pin_load -rise 0.04 [get_ports out2]
|
||||
set_load -pin_load -fall 0.045 [get_ports out2]
|
||||
set_load -min 0.01 [get_ports out1]
|
||||
set_load -max 0.06 [get_ports out1]
|
||||
set_port_fanout_number 4 [get_ports out1]
|
||||
puts "PASS: loads"
|
||||
|
||||
# Net loads
|
||||
catch {
|
||||
set_load 0.01 [get_nets n1]
|
||||
set_load 0.02 [get_nets n2]
|
||||
}
|
||||
puts "PASS: net loads"
|
||||
|
||||
# Clock latency (source + network)
|
||||
set_clock_latency -source 0.5 [get_clocks clk1]
|
||||
set_clock_latency -source -early 0.3 [get_clocks clk1]
|
||||
set_clock_latency -source -late 0.6 [get_clocks clk1]
|
||||
set_clock_latency -source -rise -max 0.65 [get_clocks clk1]
|
||||
set_clock_latency -source -fall -min 0.25 [get_clocks clk1]
|
||||
set_clock_latency 0.2 [get_clocks clk2]
|
||||
puts "PASS: clock latency"
|
||||
|
||||
# Clock uncertainty (simple + inter-clock)
|
||||
set_clock_uncertainty -setup 0.2 [get_clocks clk1]
|
||||
set_clock_uncertainty -hold 0.1 [get_clocks clk1]
|
||||
set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -setup 0.3
|
||||
set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -hold 0.15
|
||||
set_clock_uncertainty -from [get_clocks clk2] -to [get_clocks clk1] -setup 0.28
|
||||
set_clock_uncertainty -from [get_clocks clk2] -to [get_clocks clk1] -hold 0.12
|
||||
puts "PASS: clock uncertainty"
|
||||
|
||||
# Clock transition
|
||||
set_clock_transition -rise -max 0.15 [get_clocks clk1]
|
||||
set_clock_transition -fall -min 0.08 [get_clocks clk1]
|
||||
set_clock_transition 0.1 [get_clocks clk2]
|
||||
puts "PASS: clock transition"
|
||||
|
||||
# Propagated clock
|
||||
set_propagated_clock [get_clocks clk1]
|
||||
puts "PASS: propagated"
|
||||
|
||||
# Clock sense (using set_clock_sense which triggers the same code)
|
||||
set_clock_sense -positive -clocks [get_clocks clk1] [get_pins buf1/Z]
|
||||
puts "PASS: clock sense"
|
||||
|
||||
# Disable timing - instances, lib cells
|
||||
set_disable_timing [get_cells buf1]
|
||||
set_disable_timing [get_lib_cells NangateOpenCellLibrary/AND2_X1] -from A1 -to ZN
|
||||
set_disable_timing [get_lib_cells NangateOpenCellLibrary/NOR2_X1]
|
||||
puts "PASS: disable timing"
|
||||
|
||||
# Case analysis
|
||||
set_case_analysis 0 [get_ports in3]
|
||||
puts "PASS: case analysis"
|
||||
|
||||
# Logic values
|
||||
set_logic_one [get_ports in2]
|
||||
puts "PASS: logic"
|
||||
|
||||
# Design limits
|
||||
set_max_transition 0.5 [current_design]
|
||||
set_max_capacitance 0.2 [current_design]
|
||||
set_max_fanout 20 [current_design]
|
||||
set_max_transition 0.3 [get_ports out1]
|
||||
set_max_capacitance 0.1 [get_ports out1]
|
||||
set_max_transition -clock_path 0.2 [get_clocks clk1]
|
||||
set_max_transition -data_path 0.4 [get_clocks clk1]
|
||||
set_max_area 100.0
|
||||
puts "PASS: design limits"
|
||||
|
||||
# False paths with all transition combinations
|
||||
set_false_path -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
set_false_path -setup -from [get_clocks clk1] -to [get_clocks vclk]
|
||||
set_false_path -hold -from [get_clocks vclk] -to [get_clocks clk1]
|
||||
set_false_path -rise_from [get_ports in3] -fall_to [get_ports out2]
|
||||
set_false_path -from [get_ports in1] -through [get_pins and1/ZN] -to [get_ports out1]
|
||||
set_false_path -from [get_ports in2] \
|
||||
-rise_through [get_pins buf1/Z] \
|
||||
-fall_through [get_nets n3] \
|
||||
-to [get_ports out1]
|
||||
puts "PASS: false paths"
|
||||
|
||||
# Multicycle paths
|
||||
set_multicycle_path -setup 2 -from [get_ports in1] -to [get_ports out1]
|
||||
set_multicycle_path -hold 1 -from [get_ports in1] -to [get_ports out1]
|
||||
set_multicycle_path -setup -start 3 -from [get_ports in2] -to [get_ports out2]
|
||||
set_multicycle_path -hold -end 1 -from [get_ports in2] -to [get_ports out2]
|
||||
puts "PASS: multicycle paths"
|
||||
|
||||
# Max/min delay
|
||||
set_max_delay -from [get_ports in2] -to [get_ports out1] 8.0
|
||||
set_min_delay -from [get_ports in2] -to [get_ports out1] 1.0
|
||||
set_max_delay -from [get_ports in3] -through [get_cells or1] -to [get_ports out2] 7.0
|
||||
puts "PASS: max/min delay"
|
||||
|
||||
# Group paths
|
||||
group_path -name grp_clk1 -from [get_clocks clk1]
|
||||
group_path -name grp_io -from [get_ports in1] -to [get_ports out1]
|
||||
group_path -name grp_thru -from [get_ports in2] \
|
||||
-through [get_nets n2] -to [get_ports out1]
|
||||
group_path -default -from [get_ports in3] -to [get_ports out2]
|
||||
puts "PASS: group paths"
|
||||
|
||||
# Clock groups
|
||||
set_clock_groups -asynchronous -name async1 \
|
||||
-group {clk1 gclk_div} \
|
||||
-group {clk2}
|
||||
puts "PASS: clock groups"
|
||||
|
||||
# Clock gating check
|
||||
set_clock_gating_check -setup 0.5 [get_clocks clk1]
|
||||
set_clock_gating_check -hold 0.3 [get_clocks clk1]
|
||||
set_clock_gating_check -setup 0.35 [get_clocks clk2]
|
||||
set_clock_gating_check -hold 0.15 [get_clocks clk2]
|
||||
puts "PASS: clock gating check"
|
||||
|
||||
# Min pulse width
|
||||
set_min_pulse_width 0.5
|
||||
set_min_pulse_width -high 0.6 [get_clocks clk1]
|
||||
set_min_pulse_width -low 0.4 [get_clocks clk1]
|
||||
set_min_pulse_width 0.55 [get_clocks clk2]
|
||||
puts "PASS: min pulse width"
|
||||
|
||||
# Latch borrow
|
||||
set_max_time_borrow 2.0 [get_clocks clk1]
|
||||
set_max_time_borrow 1.5 [get_pins reg1/D]
|
||||
puts "PASS: latch borrow"
|
||||
|
||||
# Net resistance
|
||||
set_resistance -min 10.0 [get_nets n1]
|
||||
set_resistance -max 20.0 [get_nets n1]
|
||||
puts "PASS: net resistance"
|
||||
|
||||
# Data checks
|
||||
catch {
|
||||
set_data_check -from [get_pins reg1/Q] -to [get_pins reg2/D] -setup 0.5
|
||||
set_data_check -from [get_pins reg1/Q] -to [get_pins reg2/D] -hold 0.3
|
||||
}
|
||||
puts "PASS: data checks"
|
||||
|
||||
# Operating conditions
|
||||
set_operating_conditions typical
|
||||
puts "PASS: operating conditions"
|
||||
|
||||
# Wire load
|
||||
set_wire_load_model -name "5K_hvratio_1_1"
|
||||
set_wire_load_mode enclosed
|
||||
puts "PASS: wire load"
|
||||
|
||||
# Timing derate
|
||||
set_timing_derate -early 0.95
|
||||
set_timing_derate -late 1.05
|
||||
set_timing_derate -early -clock 0.97
|
||||
set_timing_derate -late -clock 1.03
|
||||
puts "PASS: timing derate"
|
||||
|
||||
puts "PASS: constraints set"
|
||||
|
||||
############################################################
|
||||
# Write in all formats
|
||||
############################################################
|
||||
set sdc_native [make_result_file sdc_wrt_full_native.sdc]
|
||||
write_sdc -no_timestamp $sdc_native
|
||||
puts "PASS: write native"
|
||||
|
||||
set sdc_compat [make_result_file sdc_wrt_full_compat.sdc]
|
||||
write_sdc -no_timestamp -compatible $sdc_compat
|
||||
puts "PASS: write compatible"
|
||||
|
||||
set sdc_d2 [make_result_file sdc_wrt_full_d2.sdc]
|
||||
write_sdc -no_timestamp -digits 2 $sdc_d2
|
||||
puts "PASS: write digits 2"
|
||||
|
||||
set sdc_d8 [make_result_file sdc_wrt_full_d8.sdc]
|
||||
write_sdc -no_timestamp -digits 8 $sdc_d8
|
||||
puts "PASS: write digits 8"
|
||||
|
||||
set sdc_hpins [make_result_file sdc_wrt_full_hpins.sdc]
|
||||
write_sdc -no_timestamp -map_hpins $sdc_hpins
|
||||
puts "PASS: write map_hpins"
|
||||
|
||||
############################################################
|
||||
# Read back native and re-write
|
||||
############################################################
|
||||
read_sdc $sdc_native
|
||||
puts "PASS: read native"
|
||||
|
||||
set sdc_rewrite [make_result_file sdc_wrt_full_rewrite.sdc]
|
||||
write_sdc -no_timestamp $sdc_rewrite
|
||||
puts "PASS: write after read"
|
||||
|
||||
############################################################
|
||||
# Read compatible and verify
|
||||
############################################################
|
||||
read_sdc $sdc_compat
|
||||
puts "PASS: read compatible"
|
||||
|
||||
set sdc_final [make_result_file sdc_wrt_full_final.sdc]
|
||||
write_sdc -no_timestamp $sdc_final
|
||||
puts "PASS: write final"
|
||||
|
||||
puts "ALL PASSED"
|
||||
Reference in New Issue
Block a user