99 lines
3.3 KiB
Plaintext
99 lines
3.3 KiB
Plaintext
PASS: clocks created
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PASS: input delay -source_latency_included
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PASS: input delay -network_latency_included
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PASS: input delay -source_latency_included -network_latency_included
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PASS: input delay -clock_fall -source_latency_included -add_delay
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PASS: input delay rise/fall with latency flags
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PASS: output delay -source_latency_included
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PASS: output delay -network_latency_included
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PASS: output delay -clock_fall -source_latency_included -add_delay
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PASS: output delay -clock_fall -network_latency_included -add_delay
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PASS: output delay 4-way rise/fall min/max
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PASS: set_propagated_clock clk1
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PASS: clock latency (removes propagation)
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PASS: set_propagated_clock on pin clk2
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PASS: clock latency on pin (removes propagation)
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PASS: max_time_borrow on clocks
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PASS: max_time_borrow on pins
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PASS: max_time_borrow on instance
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PASS: max_time_borrow on instance reg3
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PASS: min_pulse_width global
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PASS: min_pulse_width clock high != low
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PASS: min_pulse_width clock same
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PASS: min_pulse_width pin
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PASS: min_pulse_width pin high/low
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PASS: min_pulse_width instance
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PASS: set_max_area
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PASS: group_path -default
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PASS: group_path named with -through
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PASS: group_path named clk-to-clk
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PASS: group_path duplicate
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PASS: clock_groups -logically_exclusive
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PASS: false_path -setup
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PASS: false_path -hold
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PASS: multicycle -setup -start
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PASS: multicycle -hold -end
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PASS: max_delay -ignore_clock_latency
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PASS: min_delay
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PASS: write_sdc
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PASS: write_sdc -compatible
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PASS: write_sdc -digits 8
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PASS: unset_input_delay
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PASS: unset_output_delay
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PASS: unset false paths
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.30 0.30 clock network delay (ideal)
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0.00 0.30 ^ reg2/CK (DFF_X1)
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0.08 0.38 ^ reg2/Q (DFF_X1)
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0.00 0.38 ^ out1 (out)
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0.38 data arrival time
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5.00 5.00 clock clk1 (fall edge)
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0.30 5.30 clock network delay (ideal)
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0.00 5.30 clock reconvergence pessimism
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-3.20 2.10 output external delay
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2.10 data required time
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---------------------------------------------------------
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2.10 data required time
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-0.38 data arrival time
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---------------------------------------------------------
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1.72 slack (MET)
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Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Endpoint: out2 (output port clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk2 (rise edge)
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0.20 0.20 clock network delay (ideal)
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0.00 0.20 ^ reg3/CK (DFF_X1)
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0.08 0.28 ^ reg3/Q (DFF_X1)
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0.00 0.28 ^ out2 (out)
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0.28 data arrival time
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10.00 10.00 clock clk2 (fall edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.80 7.20 output external delay
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7.20 data required time
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---------------------------------------------------------
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7.20 data required time
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-0.28 data arrival time
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---------------------------------------------------------
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6.92 slack (MET)
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PASS: read_sdc + report
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PASS: write_sdc after re-read
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ALL PASSED
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