173 lines
6.8 KiB
Tcl
173 lines
6.8 KiB
Tcl
# Test CycleAccting.cc with generated clocks, odd period ratios,
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# and waveform offsets that stress the cycle accounting convergence loop.
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# Targets: CycleAccting.cc findDelays with non-trivial period ratios,
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# firstCycle with edge times, setSetupAccting, setHoldAccting,
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# setAccting for latchSetup/latchHold/gatedClockSetup/gatedClockHold,
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# findDefaultArrivalSrcDelays, setDefaultSetupAccting, setDefaultHoldAccting,
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# maxCyclesExceeded, reportClkToClkMaxCycleWarnings,
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# CycleAcctingLess, CycleAcctingHash, CycleAcctingEqual,
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# requiredTime, sourceTimeOffset, targetTimeOffset
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source ../../test/helpers.tcl
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog sdc_test2.v
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link_design sdc_test2
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############################################################
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# Phase 1: Generated clock from master clock
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############################################################
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create_clock -name master -period 10 [get_ports clk1]
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create_generated_clock -name gen_div2 -source [get_ports clk1] \
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-divide_by 2 [get_ports clk2]
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set_input_delay -clock master 1.0 [get_ports in1]
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set_input_delay -clock master 1.0 [get_ports in2]
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set_input_delay -clock gen_div2 2.0 [get_ports in3]
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set_output_delay -clock master 2.0 [get_ports out1]
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set_output_delay -clock gen_div2 3.0 [get_ports out2]
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report_checks -path_delay max
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report_checks -path_delay min
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puts "PASS: generated clock div2"
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############################################################
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# Phase 2: Multicycle on generated clock paths
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############################################################
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puts "--- mcp setup 2 master -> gen_div2 ---"
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set_multicycle_path -setup 2 -from [get_clocks master] -to [get_clocks gen_div2]
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report_checks -path_delay max -from [get_ports in1] -to [get_ports out2]
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puts "PASS: mcp master->gen setup 2"
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puts "--- mcp hold 1 master -> gen_div2 ---"
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set_multicycle_path -hold 1 -from [get_clocks master] -to [get_clocks gen_div2]
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report_checks -path_delay min -from [get_ports in1] -to [get_ports out2]
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puts "PASS: mcp master->gen hold 1"
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puts "--- mcp setup 2 gen_div2 -> master ---"
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set_multicycle_path -setup 2 -from [get_clocks gen_div2] -to [get_clocks master]
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report_checks -path_delay max -from [get_ports in3] -to [get_ports out1]
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puts "PASS: mcp gen->master setup 2"
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unset_path_exceptions -setup -from [get_clocks master] -to [get_clocks gen_div2]
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unset_path_exceptions -hold -from [get_clocks master] -to [get_clocks gen_div2]
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unset_path_exceptions -setup -from [get_clocks gen_div2] -to [get_clocks master]
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############################################################
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# Phase 3: Delete and create clocks with odd ratios
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# Exercises findDelays with non-convergent cycles
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############################################################
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puts "--- odd ratio clocks ---"
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delete_clock [get_clocks master]
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delete_clock [get_clocks gen_div2]
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create_clock -name clk_p7 -period 7 [get_ports clk1]
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create_clock -name clk_p13 -period 13 [get_ports clk2]
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set_input_delay -clock clk_p7 1.0 [get_ports in1]
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set_input_delay -clock clk_p7 1.0 [get_ports in2]
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set_input_delay -clock clk_p13 2.0 [get_ports in3]
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set_output_delay -clock clk_p7 2.0 [get_ports out1]
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set_output_delay -clock clk_p13 3.0 [get_ports out2]
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report_checks -path_delay max
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report_checks -path_delay min
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puts "PASS: odd ratio clocks 7:13"
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puts "--- mcp on odd ratio ---"
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set_multicycle_path -setup 3 -from [get_clocks clk_p7] -to [get_clocks clk_p13]
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set_multicycle_path -hold 2 -from [get_clocks clk_p7] -to [get_clocks clk_p13]
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report_checks -path_delay max
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report_checks -path_delay min
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puts "PASS: mcp odd ratio"
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############################################################
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# Phase 4: Waveform with edge offset
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############################################################
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puts "--- waveform edge offset ---"
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delete_clock [get_clocks clk_p7]
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delete_clock [get_clocks clk_p13]
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# Clock with offset waveform (exercises firstCycle edge time handling)
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create_clock -name clk_off -period 10 -waveform {2 7} [get_ports clk1]
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create_clock -name clk_norm -period 10 [get_ports clk2]
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set_input_delay -clock clk_off 1.0 [get_ports in1]
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set_input_delay -clock clk_off 1.0 [get_ports in2]
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set_input_delay -clock clk_norm 1.0 [get_ports in3]
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set_output_delay -clock clk_off 2.0 [get_ports out1]
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set_output_delay -clock clk_norm 2.0 [get_ports out2]
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report_checks -path_delay max
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report_checks -path_delay min
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puts "PASS: waveform edge offset"
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puts "--- mcp waveform edge offset ---"
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set_multicycle_path -setup 2 -from [get_clocks clk_off] -to [get_clocks clk_norm]
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set_multicycle_path -hold 1 -from [get_clocks clk_off] -to [get_clocks clk_norm]
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report_checks -path_delay max
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report_checks -path_delay min
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puts "PASS: mcp waveform edge offset"
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############################################################
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# Phase 5: Generated clock with multiply_by
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############################################################
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puts "--- generated clock multiply_by ---"
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delete_clock [get_clocks clk_off]
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delete_clock [get_clocks clk_norm]
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create_clock -name base -period 20 [get_ports clk1]
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create_generated_clock -name gen_mult -source [get_ports clk1] \
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-multiply_by 2 [get_ports clk2]
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set_input_delay -clock base 2.0 [get_ports in1]
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set_input_delay -clock base 2.0 [get_ports in2]
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set_input_delay -clock gen_mult 1.0 [get_ports in3]
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set_output_delay -clock base 3.0 [get_ports out1]
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set_output_delay -clock gen_mult 2.0 [get_ports out2]
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report_checks -path_delay max
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report_checks -path_delay min
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puts "PASS: generated multiply_by 2"
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puts "--- mcp base -> gen_mult ---"
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set_multicycle_path -setup 2 -from [get_clocks base] -to [get_clocks gen_mult]
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report_checks -path_delay max
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puts "PASS: mcp base->mult"
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############################################################
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# Phase 6: Generated clock with edge list
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############################################################
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puts "--- generated clock edge list ---"
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delete_clock [get_clocks base]
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delete_clock [get_clocks gen_mult]
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create_clock -name mclk -period 10 [get_ports clk1]
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create_generated_clock -name edge_clk -source [get_ports clk1] \
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-edges {1 3 5} [get_ports clk2]
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set_input_delay -clock mclk 1.0 [get_ports in1]
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set_input_delay -clock mclk 1.0 [get_ports in2]
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set_input_delay -clock edge_clk 1.5 [get_ports in3]
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set_output_delay -clock mclk 2.0 [get_ports out1]
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set_output_delay -clock edge_clk 2.5 [get_ports out2]
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report_checks -path_delay max
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report_checks -path_delay min
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puts "PASS: generated clock edge list"
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############################################################
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# Phase 7: report_clock_properties
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############################################################
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puts "--- report_clock_properties ---"
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report_clock_properties
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puts "PASS: clock_properties"
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############################################################
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# Phase 8: Write SDC roundtrip
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############################################################
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set sdc_out [make_result_file sdc_cycle_acct_genclk.sdc]
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write_sdc -no_timestamp $sdc_out
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puts "PASS: write_sdc"
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puts "ALL PASSED"
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