316 lines
10 KiB
Plaintext
316 lines
10 KiB
Plaintext
PASS: Phase 1 - clocks
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PASS: Phase 1 - generated clocks
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PASS: Phase 1 - IO delays
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PASS: Phase 1 - clock latency
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PASS: Phase 1 - clock uncertainty
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PASS: Phase 1 - clock transition
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PASS: Phase 1 - source latency early/late
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PASS: Phase 1 - min pulse width
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PASS: Phase 1 - latch borrow
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PASS: Phase 1 - clock groups
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PASS: Phase 1 - exception paths
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PASS: Phase 1 - timing derate
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PASS: Phase 1 - disable timing
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PASS: Phase 1 - case analysis
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PASS: Phase 1 - design limits
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PASS: Phase 1 - write_sdc
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.50 0.50 clock network delay (ideal)
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0.00 0.50 ^ reg2/CK (DFF_X1)
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0.11 0.61 ^ reg2/Q (DFF_X1)
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0.00 0.61 ^ out1 (out)
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0.61 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.30 10.30 clock network delay (ideal)
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-0.20 10.10 clock uncertainty
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0.00 10.10 clock reconvergence pessimism
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-3.00 7.10 output external delay
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7.10 data required time
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---------------------------------------------------------
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7.10 data required time
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-0.61 data arrival time
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---------------------------------------------------------
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6.49 slack (MET)
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Startpoint: reg3/Q (clock source 'gclk2')
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Endpoint: out2 (output port clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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15.00 15.00 clock gclk2 (fall edge)
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0.00 15.00 clock network delay
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15.00 v out2 (out)
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15.00 data arrival time
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20.00 20.00 clock clk2 (rise edge)
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0.20 20.20 clock network delay (ideal)
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0.00 20.20 clock reconvergence pessimism
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-3.50 16.70 output external delay
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16.70 data required time
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---------------------------------------------------------
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16.70 data required time
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-15.00 data arrival time
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---------------------------------------------------------
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1.70 slack (MET)
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PASS: Phase 1 - report_checks
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PASS: Phase 2 - remove false path
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PASS: Phase 2 - remove multicycle
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PASS: Phase 2 - remove timing derate
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PASS: Phase 2 - remove disable timing
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PASS: Phase 2 - remove case analysis
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PASS: Phase 2 - remove clock groups
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PASS: Phase 2 - remove clock latency
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PASS: Phase 2 - remove inter-clock uncertainty
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PASS: Phase 2 - remove propagated clock
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PASS: Phase 2 - write_sdc
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg2/CK (DFF_X1)
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0.10 0.10 ^ reg2/Q (DFF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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-0.20 9.80 clock uncertainty
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0.00 9.80 clock reconvergence pessimism
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-3.00 6.80 output external delay
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6.80 data required time
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---------------------------------------------------------
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6.80 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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6.70 slack (MET)
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Startpoint: reg3/Q (clock source 'gclk2')
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Endpoint: out2 (output port clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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15.00 15.00 clock gclk2 (fall edge)
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0.00 15.00 clock network delay
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15.00 v out2 (out)
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15.00 data arrival time
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20.00 20.00 clock clk2 (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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-3.50 16.50 output external delay
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16.50 data required time
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---------------------------------------------------------
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16.50 data required time
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-15.00 data arrival time
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---------------------------------------------------------
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1.50 slack (MET)
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PASS: Phase 2 - report_checks
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PASS: Phase 3 - delete gclk1
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PASS: Phase 3 - delete gclk2
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PASS: Phase 3 - delete vclk
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Clock Period Waveform
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----------------------------------------------------
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clk1 10.00 0.00 5.00
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clk2 20.00 0.00 10.00
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PASS: Phase 3 - report after clock deletions
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PASS: Phase 3a - write_sdc
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg2/CK (DFF_X1)
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0.10 0.10 ^ reg2/Q (DFF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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-0.20 9.80 clock uncertainty
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0.00 9.80 clock reconvergence pessimism
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-3.00 6.80 output external delay
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6.80 data required time
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---------------------------------------------------------
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6.80 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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6.70 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 ^ reg1/CK (DFF_X1)
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0.10 10.10 ^ reg1/Q (DFF_X1)
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0.00 10.10 ^ reg3/D (DFF_X1)
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10.10 data arrival time
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20.00 20.00 clock clk2 (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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20.00 ^ reg3/CK (DFF_X1)
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-0.03 19.97 library setup time
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19.97 data required time
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---------------------------------------------------------
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19.97 data required time
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-10.10 data arrival time
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---------------------------------------------------------
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9.86 slack (MET)
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PASS: Phase 3a - report_checks
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PASS: Phase 4 - new virtual clock
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PASS: Phase 4 - new generated clock
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PASS: Phase 4 - new clock groups
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PASS: Phase 4 - new exceptions
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PASS: Phase 4 - new latency
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PASS: Phase 4 - new uncertainty
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PASS: Phase 4 - new derate
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PASS: Phase 4 - new disable
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PASS: Phase 4 - write_sdc
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PASS: Phase 4 - write_sdc compatible
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.40 0.40 clock network delay (ideal)
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0.00 0.40 ^ reg2/CK (DFF_X1)
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0.10 0.50 ^ reg2/Q (DFF_X1)
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0.00 0.50 ^ out1 (out)
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0.50 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.40 10.40 clock network delay (ideal)
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-0.25 10.15 clock uncertainty
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0.00 10.15 clock reconvergence pessimism
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-3.00 7.15 output external delay
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7.15 data required time
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---------------------------------------------------------
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7.15 data required time
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-0.50 data arrival time
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---------------------------------------------------------
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6.65 slack (MET)
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Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Endpoint: out2 (output port clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk2 (rise edge)
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0.15 0.15 clock network delay (ideal)
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0.00 0.15 ^ reg3/CK (DFF_X1)
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0.11 0.26 ^ reg3/Q (DFF_X1)
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0.00 0.26 ^ out2 (out)
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0.26 data arrival time
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20.00 20.00 clock clk2 (rise edge)
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0.15 20.15 clock network delay (ideal)
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0.00 20.15 clock reconvergence pessimism
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-3.50 16.65 output external delay
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16.65 data required time
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---------------------------------------------------------
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16.65 data required time
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-0.26 data arrival time
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---------------------------------------------------------
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16.39 slack (MET)
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PASS: Phase 4 - report_checks
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PASS: Phase 5 - read_sdc
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.40 0.40 clock network delay (ideal)
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0.00 0.40 ^ reg2/CK (DFF_X1)
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0.10 0.50 ^ reg2/Q (DFF_X1)
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0.00 0.50 ^ out1 (out)
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0.50 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.40 10.40 clock network delay (ideal)
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-0.25 10.15 clock uncertainty
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0.00 10.15 clock reconvergence pessimism
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-3.00 7.15 output external delay
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7.15 data required time
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---------------------------------------------------------
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7.15 data required time
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-0.50 data arrival time
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---------------------------------------------------------
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6.65 slack (MET)
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Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Endpoint: out2 (output port clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk2 (rise edge)
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0.15 0.15 clock network delay (ideal)
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0.00 0.15 ^ reg3/CK (DFF_X1)
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0.11 0.26 ^ reg3/Q (DFF_X1)
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0.00 0.26 ^ out2 (out)
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0.26 data arrival time
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20.00 20.00 clock clk2 (rise edge)
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0.15 20.15 clock network delay (ideal)
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0.00 20.15 clock reconvergence pessimism
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-3.50 16.65 output external delay
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16.65 data required time
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---------------------------------------------------------
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16.65 data required time
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-0.26 data arrival time
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---------------------------------------------------------
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16.39 slack (MET)
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PASS: Phase 5 - report_checks after read
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PASS: Phase 5 - write_sdc after read
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ALL PASSED
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