319 lines
11 KiB
Plaintext
319 lines
11 KiB
Plaintext
PASS: setup
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Warning: sdc_sense_unset_override.tcl line 1, set_clock_sense is deprecated as of SDC 2.1. Use set_sense -type clock.
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PASS: clock_sense positive with clock
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Warning: sdc_sense_unset_override.tcl line 1, set_clock_sense is deprecated as of SDC 2.1. Use set_sense -type clock.
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PASS: clock_sense negative with clock
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Warning: sdc_sense_unset_override.tcl line 1, set_clock_sense is deprecated as of SDC 2.1. Use set_sense -type clock.
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PASS: clock_sense stop with clock
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Warning: sdc_sense_unset_override.tcl line 1, set_clock_sense is deprecated as of SDC 2.1. Use set_sense -type clock.
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PASS: clock_sense positive without clock
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Warning: sdc_sense_unset_override.tcl line 1, set_clock_sense is deprecated as of SDC 2.1. Use set_sense -type clock.
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PASS: clock_sense negative without clock
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PASS: write_sdc with clock senses
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Warning: sdc_sense_unset_override.tcl line 1, set_clock_sense is deprecated as of SDC 2.1. Use set_sense -type clock.
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PASS: overwrite clock_sense positive with negative
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg2/CK (DFF_X1)
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0.08 0.08 ^ reg2/Q (DFF_X1)
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0.00 0.08 ^ out1 (out)
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0.08 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-3.00 7.00 output external delay
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7.00 data required time
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---------------------------------------------------------
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7.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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6.92 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 ^ reg1/CK (DFF_X1)
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0.08 10.08 v reg1/Q (DFF_X1)
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0.00 10.08 v reg3/D (DFF_X1)
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10.08 data arrival time
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20.00 20.00 clock clk2 (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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20.00 ^ reg3/CK (DFF_X1)
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-0.04 19.96 library setup time
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19.96 data required time
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---------------------------------------------------------
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19.96 data required time
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-10.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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PASS: report after sense changes
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PASS: clock uncertainty
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PASS: inter-clock uncertainty
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PASS: write_sdc with uncertainties
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PASS: unset clock uncertainty
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PASS: unset inter-clock uncertainty
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg2/CK (DFF_X1)
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0.08 0.08 ^ reg2/Q (DFF_X1)
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0.00 0.08 ^ out1 (out)
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0.08 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-3.00 7.00 output external delay
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7.00 data required time
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---------------------------------------------------------
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7.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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6.92 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 ^ reg1/CK (DFF_X1)
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0.08 10.08 v reg1/Q (DFF_X1)
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0.00 10.08 v reg3/D (DFF_X1)
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10.08 data arrival time
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20.00 20.00 clock clk2 (rise edge)
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0.00 20.00 clock network delay (ideal)
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-0.30 19.70 clock uncertainty
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0.00 19.70 clock reconvergence pessimism
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19.70 ^ reg3/CK (DFF_X1)
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-0.04 19.66 library setup time
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19.66 data required time
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---------------------------------------------------------
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19.66 data required time
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-10.08 data arrival time
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---------------------------------------------------------
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9.58 slack (MET)
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PASS: report after uncertainty unset
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PASS: clock insertion
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PASS: unset clock insertion
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PASS: clock_groups asynchronous
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PASS: unset clock_groups async
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PASS: clock_groups logically_exclusive
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PASS: unset clock_groups logically_exclusive
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PASS: clock_groups physically_exclusive
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PASS: write_sdc with clock groups
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PASS: unset clock_groups physically_exclusive
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PASS: max_delay
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PASS: false_path overrides max_delay
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PASS: false_path with rise_to and fall_to
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PASS: false_path with rise_from and fall_from
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PASS: multicycle setup + hold same path
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PASS: multicycle between clocks
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PASS: max/min delay with through
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PASS: group_path multi from/to
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PASS: write_sdc with all exceptions
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PASS: write_sdc compatible
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PASS: unset false_path
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PASS: unset rise/fall false_paths
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: grp_multi
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg2/CK (DFF_X1)
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0.08 0.08 ^ reg2/Q (DFF_X1)
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0.00 0.08 ^ out1 (out)
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0.08 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-3.00 7.00 output external delay
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7.00 data required time
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---------------------------------------------------------
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7.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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6.92 slack (MET)
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Startpoint: in3 (input port clocked by clk2)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk2 (rise edge)
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0.00 0.00 clock network delay (ideal)
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2.00 2.00 v input external delay
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0.00 2.00 v in3 (in)
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0.05 2.05 v or1/ZN (OR2_X1)
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0.03 2.07 ^ nor1/ZN (NOR2_X1)
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0.00 2.07 ^ reg2/D (DFF_X1)
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2.07 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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-0.32 9.68 inter-clock uncertainty
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0.00 9.68 clock reconvergence pessimism
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9.68 ^ reg2/CK (DFF_X1)
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-0.03 9.65 library setup time
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9.65 data required time
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---------------------------------------------------------
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9.65 data required time
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-2.07 data arrival time
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---------------------------------------------------------
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7.57 slack (MET)
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Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Endpoint: out2 (output port clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk2 (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg3/CK (DFF_X1)
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0.08 0.08 ^ reg3/Q (DFF_X1)
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0.00 0.08 ^ out2 (out)
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0.08 data arrival time
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20.00 20.00 clock clk2 (rise edge)
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0.00 20.00 clock network delay (ideal)
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-0.30 19.70 clock uncertainty
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0.00 19.70 clock reconvergence pessimism
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-3.00 16.70 output external delay
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16.70 data required time
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---------------------------------------------------------
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16.70 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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16.62 slack (MET)
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PASS: final report
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: grp_multi
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg2/CK (DFF_X1)
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0.08 0.08 ^ reg2/Q (DFF_X1)
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0.00 0.08 ^ out1 (out)
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0.08 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-3.00 7.00 output external delay
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7.00 data required time
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---------------------------------------------------------
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7.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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6.92 slack (MET)
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Startpoint: in3 (input port clocked by clk2)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk2 (rise edge)
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0.00 0.00 clock network delay (ideal)
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2.00 2.00 v input external delay
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0.00 2.00 v in3 (in)
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0.05 2.05 v or1/ZN (OR2_X1)
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0.03 2.07 ^ nor1/ZN (NOR2_X1)
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0.00 2.07 ^ reg2/D (DFF_X1)
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2.07 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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-0.32 9.68 inter-clock uncertainty
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0.00 9.68 clock reconvergence pessimism
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9.68 ^ reg2/CK (DFF_X1)
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-0.03 9.65 library setup time
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9.65 data required time
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---------------------------------------------------------
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9.65 data required time
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-2.07 data arrival time
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---------------------------------------------------------
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7.57 slack (MET)
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Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Endpoint: out2 (output port clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk2 (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg3/CK (DFF_X1)
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0.08 0.08 ^ reg3/Q (DFF_X1)
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0.00 0.08 ^ out2 (out)
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0.08 data arrival time
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20.00 20.00 clock clk2 (rise edge)
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0.00 20.00 clock network delay (ideal)
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-0.30 19.70 clock uncertainty
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0.00 19.70 clock reconvergence pessimism
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-3.00 16.70 output external delay
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16.70 data required time
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---------------------------------------------------------
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16.70 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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16.62 slack (MET)
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PASS: read_sdc + report
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ALL PASSED
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