254 lines
8.2 KiB
Plaintext
254 lines
8.2 KiB
Plaintext
PASS: clocks
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PASS: generated clocks
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PASS: propagated
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PASS: clock transition
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PASS: clock latency
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PASS: clock uncertainty
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PASS: IO delays
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PASS: driving cells
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PASS: loads
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PASS: input transitions
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PASS: design limits
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PASS: false paths
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PASS: multicycle paths
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PASS: max/min delay
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PASS: group paths
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PASS: clock groups
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Warning: sdc_write_roundtrip.tcl line 1, set_clock_sense is deprecated as of SDC 2.1. Use set_sense -type clock.
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PASS: clock sense
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PASS: disable timing
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PASS: case analysis
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PASS: logic value
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PASS: operating conditions
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PASS: wire load
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PASS: timing derate
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PASS: min pulse width
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PASS: latch borrow
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Warning: sdc_write_roundtrip.tcl line 1, object 'sdc_test2' not found.
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Warning: sdc_write_roundtrip.tcl line 1, object 'sdc_test2' not found.
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PASS: clock gating check
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PASS: port fanout
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PASS: net resistance
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PASS: voltage
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PASS: data check
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PASS: write_sdc native
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PASS: write_sdc compatible
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PASS: write_sdc digits 2
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PASS: write_sdc digits 8
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PASS: write_sdc map_hpins
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PASS: write_sdc compatible digits 6
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Warning: generated clock gclk_div pin clk1 is in the fanout of multiple clocks.
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Warning: generated clock gclk_edge pin clk1 is in the fanout of multiple clocks.
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Startpoint: reg2/Q (clock source 'gclk_edge')
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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5.00 5.00 clock gclk_edge (fall edge)
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0.00 5.00 clock network delay
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5.00 v out1 (out)
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5.00 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.30 10.30 clock network delay (propagated)
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-0.20 10.10 clock uncertainty
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0.00 10.10 clock reconvergence pessimism
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-3.00 7.10 output external delay
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7.10 data required time
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---------------------------------------------------------
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7.10 data required time
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-5.00 data arrival time
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---------------------------------------------------------
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2.10 slack (MET)
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Startpoint: reg3/Q (clock source 'gclk_mul')
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Endpoint: out2 (output port clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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13.33 13.33 clock gclk_mul (rise edge)
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0.00 13.33 clock network delay
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13.33 ^ out2 (out)
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13.33 data arrival time
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20.00 20.00 clock clk2 (rise edge)
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0.20 20.20 clock network delay (ideal)
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0.00 20.20 clock reconvergence pessimism
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-3.50 16.70 output external delay
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16.70 data required time
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---------------------------------------------------------
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16.70 data required time
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-13.33 data arrival time
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---------------------------------------------------------
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3.37 slack (MET)
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PASS: report_checks initial
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PASS: read_sdc native
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Warning: generated clock gclk_div pin clk1 is in the fanout of multiple clocks.
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Warning: generated clock gclk_edge pin clk1 is in the fanout of multiple clocks.
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Startpoint: reg2/Q (clock source 'gclk_edge')
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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5.00 5.00 clock gclk_edge (fall edge)
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0.00 5.00 clock network delay
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5.00 v out1 (out)
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5.00 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.30 10.30 clock network delay (propagated)
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-0.20 10.10 clock uncertainty
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0.00 10.10 clock reconvergence pessimism
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-3.00 7.10 output external delay
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7.10 data required time
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---------------------------------------------------------
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7.10 data required time
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-5.00 data arrival time
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---------------------------------------------------------
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2.10 slack (MET)
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Startpoint: reg3/Q (clock source 'gclk_mul')
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Endpoint: out2 (output port clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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13.33 13.33 clock gclk_mul (rise edge)
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0.00 13.33 clock network delay
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13.33 ^ out2 (out)
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13.33 data arrival time
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20.00 20.00 clock clk2 (rise edge)
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0.20 20.20 clock network delay (ideal)
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0.00 20.20 clock reconvergence pessimism
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-3.50 16.70 output external delay
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16.70 data required time
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---------------------------------------------------------
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16.70 data required time
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-13.33 data arrival time
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---------------------------------------------------------
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3.37 slack (MET)
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PASS: report_checks after read native
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PASS: write_sdc after re-read
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PASS: read_sdc compatible
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Warning: generated clock gclk_div pin clk1 is in the fanout of multiple clocks.
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Warning: generated clock gclk_edge pin clk1 is in the fanout of multiple clocks.
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Startpoint: reg2/Q (clock source 'gclk_edge')
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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5.00 5.00 clock gclk_edge (fall edge)
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0.00 5.00 clock network delay
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5.00 v out1 (out)
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5.00 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.30 10.30 clock network delay (propagated)
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-0.20 10.10 clock uncertainty
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0.00 10.10 clock reconvergence pessimism
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-3.00 7.10 output external delay
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7.10 data required time
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---------------------------------------------------------
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7.10 data required time
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-5.00 data arrival time
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---------------------------------------------------------
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2.10 slack (MET)
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Startpoint: reg3/Q (clock source 'gclk_mul')
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Endpoint: out2 (output port clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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13.33 13.33 clock gclk_mul (rise edge)
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0.00 13.33 clock network delay
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13.33 ^ out2 (out)
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13.33 data arrival time
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20.00 20.00 clock clk2 (rise edge)
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0.20 20.20 clock network delay (ideal)
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0.00 20.20 clock reconvergence pessimism
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-3.50 16.70 output external delay
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16.70 data required time
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---------------------------------------------------------
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16.70 data required time
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-13.33 data arrival time
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---------------------------------------------------------
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3.37 slack (MET)
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PASS: report_checks after read compatible
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PASS: read_sdc digits 8
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Warning: generated clock gclk_div pin clk1 is in the fanout of multiple clocks.
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Warning: generated clock gclk_edge pin clk1 is in the fanout of multiple clocks.
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Startpoint: reg2/Q (clock source 'gclk_edge')
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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5.00 5.00 clock gclk_edge (fall edge)
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0.00 5.00 clock network delay
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5.00 v out1 (out)
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5.00 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.30 10.30 clock network delay (propagated)
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-0.20 10.10 clock uncertainty
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0.00 10.10 clock reconvergence pessimism
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-3.00 7.10 output external delay
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7.10 data required time
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---------------------------------------------------------
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7.10 data required time
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-5.00 data arrival time
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---------------------------------------------------------
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2.10 slack (MET)
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Startpoint: reg3/Q (clock source 'gclk_mul')
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Endpoint: out2 (output port clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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13.33 13.33 clock gclk_mul (rise edge)
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0.00 13.33 clock network delay
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13.33 ^ out2 (out)
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13.33 data arrival time
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20.00 20.00 clock clk2 (rise edge)
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0.20 20.20 clock network delay (ideal)
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0.00 20.20 clock reconvergence pessimism
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-3.50 16.70 output external delay
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16.70 data required time
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---------------------------------------------------------
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16.70 data required time
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-13.33 data arrival time
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---------------------------------------------------------
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3.37 slack (MET)
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PASS: report_checks after read digits 8
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PASS: final write_sdc
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ALL PASSED
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