154 lines
6.2 KiB
Tcl
154 lines
6.2 KiB
Tcl
# Test CycleAccting.cc: cycle accounting with clocks of different periods,
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# multicycle paths (-start/-end), half-period clocks, and clock relationships.
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# Exercises CycleAccting.cc findDelays with various src/tgt clock edge combos,
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# findDefaultArrivalSrcDelays, requiredTime, sourceTimeOffset, targetTimeOffset,
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# maxCycles, reportClkToClkMaxCycleWarnings.
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# Also exercises Sdc.cc multicyclePath, set_multicycle_path -start/-end,
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# Clock.cc edge operations with different period clocks.
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source ../../test/helpers.tcl
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog sdc_test2.v
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link_design sdc_test2
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############################################################
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# Phase 1: Clocks with different periods for cycle accounting
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############################################################
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create_clock -name clk1 -period 10 [get_ports clk1]
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create_clock -name clk2 -period 15 [get_ports clk2]
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set_input_delay -clock clk1 2.0 [get_ports in1]
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set_input_delay -clock clk1 2.0 [get_ports in2]
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set_input_delay -clock clk2 3.0 [get_ports in3]
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set_output_delay -clock clk1 3.0 [get_ports out1]
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set_output_delay -clock clk2 4.0 [get_ports out2]
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puts "PASS: clocks different periods"
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############################################################
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# Phase 2: Multicycle path -setup (default -end)
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############################################################
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puts "--- multicycle -setup 2 ---"
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set_multicycle_path -setup 2 -from [get_clocks clk1] -to [get_clocks clk2]
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report_checks -path_delay max
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puts "PASS: mcp setup 2"
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puts "--- multicycle -hold 1 ---"
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set_multicycle_path -hold 1 -from [get_clocks clk1] -to [get_clocks clk2]
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report_checks -path_delay min
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puts "PASS: mcp hold 1"
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############################################################
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# Phase 3: Multicycle with -start
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############################################################
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puts "--- multicycle -setup 3 -start ---"
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set_multicycle_path -setup 3 -start -from [get_clocks clk1] -to [get_clocks clk2]
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report_checks -path_delay max -from [get_ports in1] -to [get_ports out2]
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puts "PASS: mcp setup 3 start"
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puts "--- multicycle -hold 2 -start ---"
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set_multicycle_path -hold 2 -start -from [get_clocks clk1] -to [get_clocks clk2]
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report_checks -path_delay min -from [get_ports in1] -to [get_ports out2]
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puts "PASS: mcp hold 2 start"
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############################################################
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# Phase 4: Multicycle with -end
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############################################################
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puts "--- multicycle -setup 4 -end ---"
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set_multicycle_path -setup 4 -end -from [get_clocks clk2] -to [get_clocks clk1]
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report_checks -path_delay max -from [get_ports in3] -to [get_ports out1]
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puts "PASS: mcp setup 4 end"
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puts "--- multicycle -hold 3 -end ---"
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set_multicycle_path -hold 3 -end -from [get_clocks clk2] -to [get_clocks clk1]
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report_checks -path_delay min -from [get_ports in3] -to [get_ports out1]
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puts "PASS: mcp hold 3 end"
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############################################################
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# Phase 5: Unset and re-do multicycle
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############################################################
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puts "--- unset_path_exceptions ---"
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unset_path_exceptions -setup -from [get_clocks clk1] -to [get_clocks clk2]
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unset_path_exceptions -hold -from [get_clocks clk1] -to [get_clocks clk2]
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unset_path_exceptions -setup -from [get_clocks clk2] -to [get_clocks clk1]
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unset_path_exceptions -hold -from [get_clocks clk2] -to [get_clocks clk1]
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report_checks -path_delay max
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puts "PASS: unset multicycle"
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############################################################
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# Phase 6: Same clock domain multicycle
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############################################################
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puts "--- same domain multicycle ---"
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set_multicycle_path -setup 2 -from [get_clocks clk1] -to [get_clocks clk1]
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set_multicycle_path -hold 1 -from [get_clocks clk1] -to [get_clocks clk1]
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report_checks -path_delay max
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report_checks -path_delay min
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puts "PASS: same domain mcp"
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############################################################
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# Phase 7: Re-create clocks with non-integer ratio periods
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############################################################
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puts "--- reclk with non-integer ratio ---"
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delete_clock [get_clocks clk1]
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delete_clock [get_clocks clk2]
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create_clock -name clk_a -period 7 [get_ports clk1]
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create_clock -name clk_b -period 11 [get_ports clk2]
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set_input_delay -clock clk_a 1.0 [get_ports in1]
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set_input_delay -clock clk_a 1.0 [get_ports in2]
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set_input_delay -clock clk_b 2.0 [get_ports in3]
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set_output_delay -clock clk_a 2.0 [get_ports out1]
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set_output_delay -clock clk_b 3.0 [get_ports out2]
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report_checks -path_delay max
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report_checks -path_delay min
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puts "PASS: non-integer ratio clocks"
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puts "--- multicycle on non-integer ratio ---"
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set_multicycle_path -setup 2 -from [get_clocks clk_a] -to [get_clocks clk_b]
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report_checks -path_delay max
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puts "PASS: mcp non-integer ratio"
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############################################################
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# Phase 8: Half-period clock (waveform test)
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############################################################
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puts "--- half-period waveform ---"
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delete_clock [get_clocks clk_a]
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delete_clock [get_clocks clk_b]
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create_clock -name clk_half -period 10 -waveform {0 3} [get_ports clk1]
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create_clock -name clk_norm -period 10 [get_ports clk2]
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set_input_delay -clock clk_half 1.0 [get_ports in1]
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set_input_delay -clock clk_half 1.0 [get_ports in2]
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set_input_delay -clock clk_norm 1.0 [get_ports in3]
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set_output_delay -clock clk_half 2.0 [get_ports out1]
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set_output_delay -clock clk_norm 2.0 [get_ports out2]
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report_checks -path_delay max
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report_checks -path_delay min
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puts "PASS: half-period waveform"
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puts "--- multicycle half-period ---"
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set_multicycle_path -setup 2 -from [get_clocks clk_half] -to [get_clocks clk_norm]
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set_multicycle_path -hold 1 -from [get_clocks clk_half] -to [get_clocks clk_norm]
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report_checks -path_delay max
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report_checks -path_delay min
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puts "PASS: mcp half-period"
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############################################################
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# Phase 9: Write SDC
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############################################################
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set sdc_out [make_result_file sdc_cycle_acct.sdc]
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write_sdc -no_timestamp $sdc_out
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puts "PASS: write_sdc"
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############################################################
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# Phase 10: report_clock_properties
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############################################################
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puts "--- report_clock_properties ---"
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report_clock_properties
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puts "PASS: clock_properties"
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puts "ALL PASSED"
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