252 lines
8.8 KiB
Tcl
252 lines
8.8 KiB
Tcl
# Test clock operations: removeClock, clock properties,
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# generated clock edge/invert, clock uncertainty inter-clock,
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# clock insertion, clock latency source variants,
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# findClock, clock waveform edge handling.
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# Targets: Sdc.cc removeClock, makeClockAfter, findClock,
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# clkFindLeafPins, makeGeneratedClock edge/multiply/divide/invert,
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# setClockInsertion, removeClockInsertion,
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# setClockLatency various source/nonsource/early/late,
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# removeClockLatency,
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# Clock.cc generated clock operations, waveform edge handling,
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# addToPins, clkEdgeTimes, clkEdge,
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# WriteSdc.cc writeClocks, writeGeneratedClock, writeClock,
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# writeClockSlews, writeClockUncertainty, writeClockLatencies,
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# writeClockInsertions, writeInterClockUncertainties,
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# writePropagatedClkPins
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source ../../test/helpers.tcl
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog sdc_test2.v
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link_design sdc_test2
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set_input_delay -clock [create_clock -name clk1 -period 10 [get_ports clk1]] 2.0 [get_ports in1]
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set_input_delay -clock clk1 2.0 [get_ports in2]
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set_output_delay -clock clk1 3.0 [get_ports out1]
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############################################################
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# Create clocks with different waveforms
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############################################################
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puts "--- clock with custom waveform ---"
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create_clock -name clk2 -period 20 -waveform {5 15} [get_ports clk2]
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set_input_delay -clock clk2 2.0 [get_ports in3]
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set_output_delay -clock clk2 3.0 [get_ports out2]
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report_checks
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puts "PASS: custom waveform clock"
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puts "--- clock with asymmetric waveform ---"
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create_clock -name vclk1 -period 8 -waveform {0 3}
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puts "PASS: asymmetric waveform"
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puts "--- clock with -add ---"
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create_clock -name clk1_alt -period 5 -add [get_ports clk1]
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report_checks
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puts "PASS: clock -add"
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############################################################
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# Generated clocks with various options
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############################################################
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puts "--- generated clock divide_by ---"
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create_generated_clock -name gclk_div2 -source [get_ports clk1] -divide_by 2 [get_pins reg1/Q]
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report_checks
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puts "PASS: genclk divide_by 2"
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puts "--- generated clock multiply_by ---"
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create_generated_clock -name gclk_mul3 -source [get_ports clk2] -multiply_by 3 [get_pins reg3/Q]
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report_checks
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puts "PASS: genclk multiply_by 3"
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puts "--- generated clock edges ---"
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create_generated_clock -name gclk_edge -source [get_ports clk1] -edges {1 3 5} [get_pins reg2/Q]
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report_checks
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puts "PASS: genclk edges"
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puts "--- generated clock invert ---"
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catch {
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create_generated_clock -name gclk_inv -source [get_ports clk1] -divide_by 1 -invert [get_pins reg1/Q] -add
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report_checks
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}
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puts "PASS: genclk invert"
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############################################################
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# Propagated clock
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############################################################
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puts "--- set_propagated_clock ---"
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set_propagated_clock [get_clocks clk1]
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set_propagated_clock [get_clocks clk2]
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report_checks
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puts "PASS: propagated clocks"
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puts "--- set_propagated_clock on pin ---"
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catch {
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set_propagated_clock [get_ports clk1]
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}
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puts "PASS: propagated clock pin"
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############################################################
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# Clock slew/transition
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############################################################
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puts "--- clock transition ---"
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set_clock_transition -rise -max 0.15 [get_clocks clk1]
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set_clock_transition -fall -min 0.08 [get_clocks clk1]
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set_clock_transition 0.1 [get_clocks clk2]
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set_clock_transition -rise 0.12 [get_clocks clk1]
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set_clock_transition -fall 0.09 [get_clocks clk1]
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report_checks
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puts "PASS: clock transition"
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############################################################
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# Clock latency - source and non-source
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############################################################
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puts "--- clock latency source ---"
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set_clock_latency -source 0.5 [get_clocks clk1]
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set_clock_latency -source -early 0.3 [get_clocks clk1]
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set_clock_latency -source -late 0.6 [get_clocks clk1]
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set_clock_latency -source -rise -max 0.65 [get_clocks clk1]
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set_clock_latency -source -fall -min 0.25 [get_clocks clk1]
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report_checks
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puts "PASS: clock latency source"
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puts "--- clock latency non-source ---"
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set_clock_latency 0.2 [get_clocks clk2]
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set_clock_latency -rise -max 0.4 [get_clocks clk2]
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set_clock_latency -fall -min 0.1 [get_clocks clk2]
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report_checks
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puts "PASS: clock latency non-source"
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############################################################
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# Clock insertion
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############################################################
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puts "--- clock insertion ---"
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catch {
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set_clock_latency -source -rise -early 0.1 [get_clocks clk1]
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set_clock_latency -source -rise -late 0.3 [get_clocks clk1]
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set_clock_latency -source -fall -early 0.15 [get_clocks clk1]
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set_clock_latency -source -fall -late 0.35 [get_clocks clk1]
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}
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report_checks
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puts "PASS: clock insertion"
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############################################################
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# Clock uncertainty - simple
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############################################################
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puts "--- clock uncertainty ---"
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set_clock_uncertainty -setup 0.2 [get_clocks clk1]
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set_clock_uncertainty -hold 0.1 [get_clocks clk1]
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set_clock_uncertainty 0.15 [get_clocks clk2]
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report_checks
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puts "PASS: clock uncertainty"
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############################################################
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# Inter-clock uncertainty
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############################################################
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puts "--- inter-clock uncertainty ---"
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set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -setup 0.3
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set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -hold 0.15
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set_clock_uncertainty -from [get_clocks clk2] -to [get_clocks clk1] -setup 0.28
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set_clock_uncertainty -from [get_clocks clk2] -to [get_clocks clk1] -hold 0.12
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report_checks
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puts "PASS: inter-clock uncertainty"
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############################################################
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# Clock uncertainty on pin
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############################################################
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puts "--- clock uncertainty on pin ---"
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catch {
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set_clock_uncertainty -setup 0.25 [get_ports clk1]
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set_clock_uncertainty -hold 0.08 [get_ports clk1]
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}
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report_checks
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puts "PASS: clock uncertainty pin"
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############################################################
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# Write SDC
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############################################################
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puts "--- write_sdc ---"
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set sdc1 [make_result_file sdc_clock_ops1.sdc]
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write_sdc -no_timestamp $sdc1
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puts "PASS: write_sdc"
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puts "--- write_sdc compatible ---"
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set sdc2 [make_result_file sdc_clock_ops2.sdc]
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write_sdc -no_timestamp -compatible $sdc2
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puts "PASS: write_sdc compatible"
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############################################################
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# Remove clock and re-create
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############################################################
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puts "--- remove_clock ---"
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catch {
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remove_clock vclk1
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report_checks
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}
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puts "PASS: remove_clock"
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############################################################
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# Clock properties reporting
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############################################################
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puts "--- report_clock_properties ---"
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report_clock_properties
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report_clock_properties clk1
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report_clock_properties clk2
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puts "PASS: clock properties"
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############################################################
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# Read SDC back
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############################################################
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puts "--- read_sdc ---"
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read_sdc $sdc1
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report_checks
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puts "PASS: read_sdc"
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############################################################
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# Remove clock latency
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############################################################
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puts "--- unset_clock_latency ---"
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catch {
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unset_clock_latency -source [get_clocks clk1]
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report_checks
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}
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puts "PASS: unset clock latency"
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############################################################
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# Remove clock uncertainty
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############################################################
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puts "--- unset_clock_uncertainty ---"
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catch {
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unset_clock_uncertainty -setup [get_clocks clk1]
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unset_clock_uncertainty -hold [get_clocks clk1]
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report_checks
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}
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puts "PASS: unset clock uncertainty"
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############################################################
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# Remove inter-clock uncertainty
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############################################################
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puts "--- unset inter-clock uncertainty ---"
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catch {
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unset_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -setup
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unset_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -hold
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report_checks
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}
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puts "PASS: unset inter-clock uncertainty"
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############################################################
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# Remove propagated clock
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############################################################
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puts "--- unset_propagated_clock ---"
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catch {
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unset_propagated_clock [get_clocks clk1]
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unset_propagated_clock [get_clocks clk2]
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report_checks
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}
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puts "PASS: unset propagated clock"
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############################################################
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# Final write
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############################################################
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set sdc3 [make_result_file sdc_clock_ops3.sdc]
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write_sdc -no_timestamp $sdc3
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puts "PASS: final write_sdc"
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puts "ALL PASSED"
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