238 lines
7.6 KiB
Plaintext
238 lines
7.6 KiB
Plaintext
PASS: clocks created
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PASS: basic input delay
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PASS: input delay rise/fall min/max
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PASS: input delay -clock_fall
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PASS: input delay -add_delay
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PASS: input delay -clock_fall -rise/-fall -add_delay
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PASS: basic output delay
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PASS: output delay rise/fall min/max
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PASS: output delay -clock_fall -add_delay
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PASS: source latency early/late rise/fall
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PASS: source latency on clk2
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PASS: network latency all rf/minmax
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PASS: global derate
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PASS: rise/fall derate
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PASS: clock/data derate
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PASS: cell_delay derate
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PASS: net_delay derate
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PASS: lib cell derate
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PASS: instance derate
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PASS: instance derate inv1
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PASS: disable buf1
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PASS: disable pin inv1/A
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PASS: disable lib cell arc
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PASS: disable lib cell NAND2
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PASS: data_check -setup
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PASS: data_check -hold
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PASS: case_analysis 0
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PASS: logic_one
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PASS: logic_zero
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PASS: max_time_borrow on clock
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PASS: max_time_borrow on pin
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PASS: min pulse width
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Warning: sdc_port_delay_advanced.tcl line 1, object 'sdc_test2' not found.
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Warning: sdc_port_delay_advanced.tcl line 1, object 'sdc_test2' not found.
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PASS: clock gating check
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PASS: driving cells
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PASS: set_drive
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PASS: loads
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PASS: input transitions
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PASS: port fanout number
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PASS: net resistance
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PASS: design limits
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PASS: operating conditions and wire load
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PASS: set_voltage
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PASS: write_sdc native
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PASS: write_sdc -compatible
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PASS: write_sdc -digits 8
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.95 0.95 clock network delay (ideal)
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0.00 0.95 ^ reg2/CK (DFF_X1)
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0.09 1.04 ^ reg2/Q (DFF_X1)
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0.00 1.04 ^ out1 (out)
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1.04 data arrival time
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5.00 5.00 clock clk1 (fall edge)
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0.35 5.35 clock network delay (ideal)
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0.00 5.35 clock reconvergence pessimism
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-2.50 2.85 output external delay
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2.85 data required time
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---------------------------------------------------------
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2.85 data required time
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-1.04 data arrival time
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---------------------------------------------------------
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1.81 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock clk1 (rise edge)
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0.95 10.95 clock network delay (ideal)
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0.00 10.95 ^ reg1/CK (DFF_X1)
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0.08 11.03 v reg1/Q (DFF_X1)
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0.00 11.03 v reg3/D (DFF_X1)
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11.03 data arrival time
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20.00 20.00 clock clk2 (rise edge)
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0.20 20.20 clock network delay (ideal)
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0.00 20.20 clock reconvergence pessimism
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20.20 ^ reg3/CK (DFF_X1)
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-0.04 20.16 library setup time
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20.16 data required time
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---------------------------------------------------------
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20.16 data required time
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-11.03 data arrival time
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---------------------------------------------------------
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9.13 slack (MET)
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PASS: report_checks
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.45 0.45 clock network delay (ideal)
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0.00 0.45 ^ reg2/CK (DFF_X1)
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0.07 0.52 v reg2/Q (DFF_X1)
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0.00 0.52 v out1 (out)
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0.52 data arrival time
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0.00 0.00 clock clk1 (rise edge)
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0.95 0.95 clock network delay (ideal)
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0.00 0.95 clock reconvergence pessimism
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-3.00 -2.05 output external delay
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-2.05 data required time
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---------------------------------------------------------
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-2.05 data required time
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-0.52 data arrival time
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---------------------------------------------------------
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2.57 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Path Group: clk2
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.45 0.45 clock network delay (ideal)
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0.00 0.45 ^ reg1/CK (DFF_X1)
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0.07 0.52 v reg1/Q (DFF_X1)
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0.00 0.52 v reg3/D (DFF_X1)
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0.52 data arrival time
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0.00 0.00 clock clk2 (rise edge)
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0.40 0.40 clock network delay (ideal)
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0.00 0.40 clock reconvergence pessimism
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0.40 ^ reg3/CK (DFF_X1)
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0.00 0.40 library hold time
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0.40 data required time
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---------------------------------------------------------
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0.40 data required time
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-0.52 data arrival time
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---------------------------------------------------------
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0.12 slack (MET)
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PASS: report_checks -path_delay min
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max slew
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Pin Limit Slew Slack
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------------------------------------------------------------
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reg1/QN 0.20 0.01 0.19 (MET)
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max fanout
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Pin Limit Fanout Slack
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---------------------------------------------------------
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reg1/Q 20 1 19 (MET)
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max capacitance
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Pin Limit Cap Slack
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------------------------------------------------------------
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reg1/Q 0.20 1.45 -1.25 (VIOLATED)
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PASS: report_check_types
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PASS: unset_timing_derate
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PASS: unset disable
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PASS: unset case analysis
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PASS: unset clock latencies
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Startpoint: in3 (input port clocked by clk1)
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Endpoint: reg2 (falling edge-triggered data to data check clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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5.00 5.00 clock clk1 (fall edge)
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0.00 5.00 clock network delay (ideal)
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2.80 7.80 ^ input external delay
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0.00 7.80 ^ in3 (in)
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0.03 7.83 ^ or1/ZN (OR2_X1)
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0.01 7.84 v nor1/ZN (NOR2_X1)
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0.00 7.84 v reg2/D (DFF_X1)
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7.84 data arrival time
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock network delay (propagated)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 v reg1/Q (DFF_X1)
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-0.50 -0.42 data check setup time
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-0.42 data required time
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---------------------------------------------------------
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-0.42 data required time
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-7.84 data arrival time
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---------------------------------------------------------
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-8.26 slack (VIOLATED)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 ^ reg1/CK (DFF_X1)
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0.08 10.08 v reg1/Q (DFF_X1)
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0.00 10.08 v reg3/D (DFF_X1)
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10.08 data arrival time
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20.00 20.00 clock clk2 (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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20.00 ^ reg3/CK (DFF_X1)
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-0.04 19.96 library setup time
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19.96 data required time
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---------------------------------------------------------
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19.96 data required time
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-10.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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PASS: final report_checks
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ALL PASSED
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